JP5834200B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a junction field effect transistor and a manufacturing method thereof.

  Junction filed effect transistors (hereinafter referred to as JFETs) are devices having good noise characteristics, and are often used in the construction of low noise circuits.

  In order to stably operate the JFET, it is important to suppress variations in the pinch-off voltage, and various proposals have been made so far for the realization thereof. For example, Patent Document 1 discloses a configuration in which high-concentration gate regions are provided above and below a channel region.

  FIG. 18 is a cross-sectional view of a conventional semiconductor device disclosed in Patent Document 1. In FIG. As shown in FIG. 18, an epitaxial layer 3 is formed on a P-type semiconductor substrate 1 via an N-type buried layer 2. An insulating region 4 is formed on the semiconductor substrate 1 so as to surround the buried layer 2 and the epitaxial layer 3, and an insulating film 6 is formed on the surface of the epitaxial layer 3. In the epitaxial layer 3, a P-type channel region 8 is buried, and an N-type upper gate region 9 and a lower gate region 9a are formed so as to sandwich the P-type channel region 8 from above and below.

  With the configuration shown in FIG. 18, since the spread of the depletion layer can be controlled, a JFET having a low channel resistance and a low pinch-off voltage can be realized.

Japanese Patent Laid-Open No. 6-84948 (particularly, the first embodiment, FIGS. 3 and 4)

  However, the above-described conventional semiconductor device has a problem that it is difficult to control the pinch-off voltage with high accuracy as the power supply voltage is lowered.

  In view of the above, an object of the present invention is to realize a JFET that enables highly accurate pinch-off voltage control even at a low power supply voltage.

  In order to achieve the above object, the inventors of the present invention investigated the cause of the difficulty in controlling the pinch-off voltage with high accuracy as the power supply voltage is lowered in the above-described conventional semiconductor device. The following knowledge was obtained.

  In the conventional semiconductor device disclosed in Patent Document 1, two gate regions are formed above and below the channel region, and the side surfaces of the channel region are also covered by the two gate regions. Therefore, the width of the channel region and the impurity concentration distribution on the side of the channel region are affected by fluctuations (variations) in triple ion implantation for forming the channel region and the two gate regions, respectively. In the conventional semiconductor device disclosed in Patent Document 1, in order to form the channel region, it is necessary to make the impurity concentration of the gate region near the side surface of the channel region lower than the impurity concentration of the channel region. It becomes difficult to control the spread of the depletion layer in the direction.

  For the reasons described above, in the conventional semiconductor device disclosed in Patent Document 1, it is difficult to control pinch-off voltage with high accuracy as the power supply voltage is lowered.

  The present invention has been made on the basis of the above knowledge, and a first semiconductor device according to the present invention includes a channel region of a first conductivity type provided on a surface portion of a semiconductor substrate, and the above-described semiconductor substrate. A second conductivity type first semiconductor region provided below the channel region; a second conductivity type gate region provided on a surface portion of the channel region; and the gate region on the surface portion of the channel region. First conductivity type source / drain regions provided on both sides in the channel length direction, and having a higher impurity concentration on both sides in the channel width direction of the channel region in the semiconductor substrate than in the first semiconductor region. A second conductivity type second semiconductor region is further provided.

  According to the first semiconductor device of the present invention, the second conductivity type second semiconductor having a higher impurity concentration than the second conductivity type first semiconductor region provided below the first conductivity type channel region. Regions are separately provided on both sides of the channel region in the channel width direction. That is, both side surfaces of the channel region are delimited by the second semiconductor region of the opposite conductivity type having a high impurity concentration. For this reason, the situation where the width of the channel region and the impurity concentration distribution on the side of the channel region are affected by fluctuation (variation) in ion implantation for forming the first semiconductor region and the gate region sandwiching the channel region from above and below is avoided. can do. In addition, since the impurity concentration of the first semiconductor region under the channel region can be set low, it is not necessary to increase the impurity concentration of the channel region itself. As a result, it is possible to prevent a decrease in the impurity concentration of the second semiconductor region near the side surface of the channel region, so that the spread of the depletion layer in the horizontal direction can be controlled with high accuracy.

  Accordingly, since the depletion layer surely spreads from the top, bottom, left, and right in the channel region even at a low power supply voltage, a JFET that enables highly accurate pinch-off voltage control can be realized. In addition, since the impurity concentration of the channel region itself can be set low, the channel region can be depleted with a low gate voltage, so that the pinch-off voltage can be reduced.

  In the first semiconductor device according to the present invention, when the second semiconductor region is formed deeper than the channel region, the above-described effects can be reliably obtained. In this case, if the second semiconductor region is formed shallower than the first semiconductor region, the breakdown voltage of the JFET can be improved.

  In the first semiconductor device according to the present invention, the gate region and the source / drain region may be separated from each other. In this case, by appropriately setting the separation distance between the gate region and the source / drain region, the breakdown voltage can be improved while suppressing an increase in on-resistance. In this case, a part of the channel region may be interposed between the gate region and the source / drain region.

  In the first semiconductor device according to the present invention, when the second semiconductor region and the source / drain region are separated from each other, the breakdown voltage of the JFET can be improved.

  In the first semiconductor device according to the present invention, if the dimension of the source / drain region in the channel width direction is larger than the dimension of the gate region in the channel width direction, the breakdown voltage of the JFET can be improved. .

  In the first semiconductor device according to the present invention, the impurity concentration of the gate region may be higher than the impurity concentration of the first semiconductor region. In this case, when the peak value of the impurity concentration of the gate region and the peak value of the impurity concentration of the second semiconductor region are substantially the same, the spread of the depletion layer can be reliably controlled.

  The first semiconductor device according to the present invention may further include a bipolar transistor provided on the semiconductor substrate. In this case, if the channel region and the base region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. Further, when the second semiconductor region and the collector region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. Further, when the gate region and the emitter region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. If the source / drain region and the base contact region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes.

  A second semiconductor device according to the present invention includes a first conductivity type channel region provided on a surface portion of a semiconductor substrate, a second conductivity type gate region provided on the surface portion of the channel region, A source / drain region of a first conductivity type provided on both sides in the channel length direction of the gate region in the surface portion of the channel region, and the channel on both sides in the channel width direction of the channel region in the semiconductor substrate. A second conductivity type semiconductor region having an impurity concentration higher than that of the region is provided, and a second conductivity type buried region having an impurity concentration higher than that of the channel region is provided below the channel region in the semiconductor substrate. An area is provided.

  According to the second semiconductor device of the present invention, the second conductivity type semiconductor region having an impurity concentration higher than that of the first conductivity type channel region is separately provided on both sides of the channel region in the channel width direction. A second conductivity type buried region having an impurity concentration higher than that of the first conductivity type channel region is separately provided below the channel region. That is, the upper surface of the channel region is delimited by an opposite conductivity type gate region having a high impurity concentration, and both side surfaces of the channel region are delimited by an opposite conductivity type semiconductor region having a high impurity concentration. The bottom surface of the region is delimited by a buried region of opposite conductivity type having a high impurity concentration. Therefore, it is possible to avoid a situation in which the width of the channel region and the impurity concentration distribution on the side of the channel region are affected by fluctuations (variations) in ion implantation for forming the buried region and the gate region sandwiching the channel region from above and below. Can do. In addition, since the channel region can be surrounded by opposite conductivity type regions having a higher impurity concentration than the channel region, the depletion layer can be surely spread from the top, bottom, left and right of the channel region even at a low power supply voltage. Highly accurate pinch-off voltage control is possible. Furthermore, the channel region can be depleted with a low gate voltage by surrounding the upper, lower, left, and right sides of the channel region with regions of opposite conductivity type having a high impurity concentration, so that the pinch-off voltage can be reduced.

  In particular, in the case of a JFET structure with a shallow channel depth and a wide channel width, the spread of the depletion layer at the bottom of the channel region has a great influence on the variation of the pinch-off voltage, and therefore, as in the second semiconductor device according to the present invention. By using a structure in which high-concentration impurity regions of the opposite conductivity type are arranged on the bottom surface of the channel region in addition to the both side surfaces of the channel region, the above-described effects are remarkably exhibited.

  In the second semiconductor device according to the present invention, when the semiconductor region is formed deeper than the channel region, the above-described effects can be obtained with certainty. In this case, the semiconductor region may be formed shallower than the buried region, or the semiconductor region may be formed deeper than the buried region.

  In the second semiconductor device according to the present invention, the gate region and the source / drain region may be separated from each other. In this case, by appropriately setting the separation distance between the gate region and the source / drain region, the breakdown voltage can be improved while suppressing an increase in on-resistance. In this case, a part of the channel region may be interposed between the gate region and the source / drain region.

  In the second semiconductor device according to the present invention, when the semiconductor region and the source / drain region are separated from each other, the breakdown voltage of the JFET can be improved.

  In the second semiconductor device according to the present invention, if the dimension of the source / drain region in the channel width direction is larger than the dimension of the gate region in the channel width direction, the breakdown voltage of the JFET can be improved. .

  In the second semiconductor device according to the present invention, when the impurity concentration of the gate region is higher than the impurity concentration of the channel region, the above-described effects can be reliably obtained. In this case, if the peak value of the impurity concentration in the gate region and the peak value of the impurity concentration in the semiconductor region are substantially the same, the spread of the depletion layer can be reliably controlled.

  The second semiconductor device according to the present invention may further comprise a bipolar transistor provided on the semiconductor substrate. In this case, if the buried region and the buried region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. If the channel region and the base region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. Here, the channel region and the base region may be formed in a semiconductor layer epitaxially grown on the semiconductor substrate. In addition, when the semiconductor region and the collector region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. Further, when the gate region and the emitter region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes. If the source / drain region and the base contact region of the bipolar transistor are formed in the same process, a semiconductor device provided with the JFET and the bipolar transistor of the present invention can be obtained without increasing the number of processes.

  According to the present invention, since the depletion layer surely spreads from the top, bottom, left, and right in the channel region, a JFET that enables highly accurate pinch-off voltage control can be realized. In addition, since the channel region can be depleted with a low gate voltage, the pinch-off voltage can be reduced.

FIG. 1 is a plan view of the semiconductor device according to the first embodiment. 2A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB in FIG. FIG. 3 is a diagram showing an impurity concentration distribution in the depth direction of each impurity region in the semiconductor device according to the first embodiment. FIG. 4 is a plan view of a semiconductor device according to a modification of the first embodiment. FIG. 5 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. 7A to 7F are cross-sectional views illustrating respective steps of the semiconductor device manufacturing method according to the first embodiment. 8A to 8F are cross-sectional views illustrating the respective steps of the semiconductor device manufacturing method according to the first embodiment. FIG. 9 is a plan view of the semiconductor device according to the second embodiment. 10A is a cross-sectional view taken along line AA in FIG. 9, and FIG. 10B is a cross-sectional view taken along line BB in FIG. FIG. 11 is a diagram showing an impurity concentration distribution in the depth direction of each impurity region in the semiconductor device according to the second embodiment. FIG. 12 is a plan view of a semiconductor device according to a modification of the second embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment. FIG. 14 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment. FIGS. 15A to 15F are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment. FIGS. 16A to 16F are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the second embodiment. FIGS. 17A and 17B are cross-sectional views illustrating one step of the method of manufacturing the semiconductor device according to the second embodiment. FIG. 18 is a cross-sectional view of a conventional semiconductor device.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

  FIG. 1 is a plan view of a semiconductor device according to the present embodiment, specifically, a semiconductor device having a JFET. FIG. 2A is a cross-sectional view taken along line AA in FIG. (B) is sectional drawing of the BB line of FIG.

  As shown in FIGS. 1, 2 (a), and 2 (b), in the semiconductor device according to the present embodiment, a p-type channel region 105 is formed on the surface portion of a p-type semiconductor substrate 101. A first n-type semiconductor region 104 is formed below the p-type channel region 105 in the p-type semiconductor substrate 101. An n-type gate region 107 is formed on the surface portion of the p-type channel region 105. A p-type source / drain region 108 is formed on both sides of the n-type gate region 107 in the channel length direction on the surface portion of the p-type channel region 105.

  Further, as a feature of the present embodiment, a second n-type semiconductor having a higher impurity concentration than the first n-type semiconductor region 104 on both sides in the channel width direction of the p-type channel region 105 in the p-type semiconductor substrate 101. Region 106 is formed.

  The p-type semiconductor substrate 101 includes a p-type channel region 105, a second n-type semiconductor region 106 (excluding the bottom), an n-type gate region 107, and a p-type source / drain region 108 surrounded by the surface portion. The insulating film 102 is embedded. Further, below the insulating film 102 in the p-type semiconductor substrate 101, for example, from a low-concentration p-type semiconductor region so as to surround the bottoms of the first n-type semiconductor region 104 and the second n-type semiconductor region 106. An isolation region 103 is provided.

In the present embodiment, the p-type semiconductor substrate 101 is, for example, a P-type silicon substrate, and the impurity concentration is about 4 × 10 ¹⁵ cm ⁻³ . The first n-type semiconductor region 104 is, for example, an n-type layer provided by ion-implanting n-type impurities into the surface portion of the p-type semiconductor substrate 101 and diffusing the impurities, and the impurity concentration is 1 × 10 ¹⁶ cm ^-3 or so. Here, the first n-type semiconductor region 104 is partitioned in an island shape by the isolation region 103 reaching the inside of the p-type semiconductor substrate 101. The p-type channel region 105 is a p-type layer provided by implanting p-type impurities into the surface portion of the first n-type semiconductor region 104, and has an impurity concentration of about 1 × 10 ¹⁸ cm ^−3. . The second n-type semiconductor region 106 is, for example, an n-type layer provided by implanting an n-type impurity on both sides in the channel width direction of the p-type channel region 105 in the p-type semiconductor substrate 101, and has an impurity concentration. Is about 1 × 10 ¹⁹ cm ⁻³ and is formed deeper than the p-type channel region 105. The n-type gate region 107 is, for example, an n-type layer provided by injecting an n-type impurity into the surface portion of the p-type channel region 105, and has an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ . The p-type source / drain region 108 is, for example, a p-type layer provided by implanting p-type impurities on both sides of the n-type gate region 107 in the channel length direction on the surface portion of the p-type channel region 105. The impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ .

  3 shows the impurity concentration distribution in the depth direction of the first n-type semiconductor region 104, the second n-type semiconductor region 106, the p-type channel region 105, and the n-type gate region 107 in the semiconductor device according to the present embodiment. Is shown. As shown in FIG. 3, in this embodiment, the impurity concentration of the second n-type semiconductor region 106 is higher than the impurity concentration of the first n-type semiconductor region 104.

  According to the present embodiment described above, the second n-type semiconductor region 106 having an impurity concentration higher than that of the first n-type semiconductor region 104 provided below the p-type channel region 105 is changed to the p-type channel. It is provided on both sides of the region 105 in the channel width direction. That is, both side surfaces of the p-type channel region 105 are delimited by the second n-type semiconductor region 106 of the opposite conductivity type having a high impurity concentration. Therefore, the width of the p-type channel region 105 and the impurity concentration distribution on the side of the p-type channel region 105 form the first n-type semiconductor region 104 and the n-type gate region 107 sandwiching the p-type channel region 105 from above and below. Therefore, it is possible to avoid a situation that is affected by fluctuations (variations) in ion implantation. In addition, since the impurity concentration of the first n-type semiconductor region 104 under the p-type channel region 105 can be set low, it is not necessary to increase the impurity concentration of the p-type channel region 105 itself. As a result, a decrease in the impurity concentration of the second n-type semiconductor region 106 in the vicinity of the side surface of the p-type channel region 105 can be prevented, so that the spread of the depletion layer in the horizontal direction can be controlled with high accuracy.

  Therefore, according to the present embodiment, the depletion layer surely spreads from the top, bottom, left, and right in the p-type channel region 105 even at a low power supply voltage, so that a JFET capable of highly accurate pinch-off voltage control can be realized. Further, since the impurity concentration of the p-type channel region 105 itself can be set low, the p-type channel region 105 can be depleted with a low gate voltage, so that the pinch-off voltage can be reduced.

  In the present embodiment, the second n-type semiconductor region 106 and the p-type source / drain region 108 may be separated from each other. In this way, the breakdown voltage of the JFET can be improved. Further, the dimension of the p-type source / drain region 108 in the channel width direction may be larger than the dimension of the n-type gate region 107 in the channel width direction. In this way, the breakdown voltage of the JFET can be improved. However, if there is no problem with the withstand voltage, the second n-type semiconductor region 106 and the p-type source / drain region 108 are in contact with each other as shown in FIG. 4 (modified example of the planar configuration shown in FIG. 1). Alternatively, the dimension of the n-type gate region 107 in the channel width direction and the dimension of the p-type source / drain region 108 in the channel width direction may be approximately the same.

  In the present embodiment, the n-type gate region 107 and the p-type source / drain region 108 may be separated from each other. In this way, by properly setting the separation distance between the n-type gate region 107 and the p-type source / drain region 108, the breakdown voltage can be improved while suppressing an increase in on-resistance. In this case, a part of the p-type channel region 105 may be interposed between the n-type gate region 107 and the p-type source / drain region 108 as in this embodiment.

  In the present embodiment, the second n-type semiconductor region 106 may be formed deeper than the p-type channel region 105. In this way, the above-described effects can be reliably obtained. In this case, if the second n-type semiconductor region 106 is formed shallower than the first n-type semiconductor region 104, the breakdown voltage of the JFET can be improved. However, if there is no problem with the withstand voltage, the second n-type semiconductor region 106 is replaced by the first n-type semiconductor region 104 as shown in FIG. 5 (modified example of the cross-sectional configuration shown in FIG. 2A). May be formed deeply.

  In the present embodiment, as shown in FIG. 2B, the p-type channel region 105 is interposed between the p-type source / drain region 108 and the first n-type semiconductor region 104. Instead, a part of the p-type source / drain region 108 may be in contact with the first n-type semiconductor region 104 as shown in FIG. 6 (modified example of the cross-sectional configuration shown in FIG. 2B). .

  In this embodiment, the insulating film 102 is buried in the surface portion of the p-type semiconductor substrate 101 to a depth similar to the depth of the p-type channel region 105. Instead, the insulating film 102 is replaced with the p-type channel region. It may be embedded deeper or shallower than 105.

  In the present embodiment, the isolation region 103 made of the low-concentration p-type semiconductor region is provided below the insulating film 102 in the p-type semiconductor substrate 101. Instead, for example, it is covered with a silicon oxide film. An isolation region composed of a non-doped polysilicon region may be provided.

  In the present embodiment, for example, as shown in FIG. 3, the impurity concentration of the n-type gate region 107 may be higher than the impurity concentration of the first n-type semiconductor region 104. In this case, as shown in FIG. 3, for example, the peak value of the impurity concentration of the n-type gate region 107 and the peak value of the impurity concentration of the second n-type semiconductor region 106 are substantially the same. Good. In this way, the spread of the depletion layer can be reliably controlled.

  In the present embodiment, the p-type semiconductor substrate 101 is used. Instead, an intrinsic semiconductor substrate or an insulating substrate having a p-type semiconductor region formed on the surface may be used.

  In this embodiment, the conductivity type of the channel region and the source / drain region is p-type, and the conductivity type of the gate region and the semiconductor region below and on the side of the channel region is n-type. Even if the conductivity type of the channel region and the source / drain region is n-type, and the conductivity type of the semiconductor region below and on the side of the gate region and the channel region is p-type, the same effect as this embodiment can be obtained.

  Further, in the present embodiment, it is needless to say that the detailed conditions such as the presence / absence of the surface protective film at the time of ion implantation, the film type and film thickness of the mask material, and the film type and film thickness of the interlayer insulating film are not particularly limited.

  Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings, taking as an example a case where an NPN bipolar transistor is provided on the same substrate together with the above-described JFET of the present embodiment.

  The manufacturing method of the semiconductor device according to the present embodiment includes the second n located on both sides in the channel width direction of the p-type channel region 105 in the JFET of the present embodiment shown in FIGS. 1 and 2A, 2B. The n-type semiconductor region 106 is formed by n-type impurity implantation at the same time as the collector region of the NPN bipolar transistor, whereby the JFET of this embodiment can be formed simultaneously with the NPN bipolar transistor without a new additional process. There is an effect.

  FIGS. 7A to 7F and FIGS. 8A to 8F are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the present embodiment, and FIGS. , (E) and FIGS. 8 (a), (c), and (e) show the cross-sectional configuration of the JFET in the channel width direction along with the cross-sectional configuration of the NPN bipolar transistor, and FIGS. (F) and FIGS. 8B, 8D, and 8F show cross-sectional configurations of the JFET in the channel length direction. 7 (a) to (f) and FIGS. 8 (a) to (f), the same components as those of the semiconductor device of this embodiment shown in FIGS. 1 and 2 (a) and 2 (b) are the same. The code is attached.

  In the present embodiment, first, as a first step, as shown in FIGS. 7A and 7B, the surface of a predetermined region of the p-type semiconductor substrate 101 is formed using a processing technique such as trench etching, for example. The insulating film 102 is embedded and an isolation region 103 is formed below the insulating film 102 in the p-type semiconductor substrate 101. As a result, the JFET formation region and the NPN bipolar transistor formation region are electrically separated.

Next, as a second step, as shown in FIGS. 7C and 7D, an n-type impurity is applied to the entire surface of the p-type semiconductor substrate 101, for example, with a dose of 1 × 10 ¹² cm ⁻² and an implantation energy of 300 keV. After ion implantation under conditions, the implanted impurities are diffused by, for example, heat treatment at 1000 ° C. for 60 minutes. As a result, the first n-type semiconductor region 104 is formed on the surface portion of the p-type semiconductor substrate 101 in the JFET formation region, and the n-type semiconductor region 114 is formed on the surface portion of the p-type semiconductor substrate 101 in the NPN bipolar transistor formation region. Is formed.

Next, as a third step, as shown in FIGS. 7E and 7F, the surfaces of the first n-type semiconductor region 104 in the JFET formation region and the n-type semiconductor region 114 in the NPN bipolar transistor formation region, respectively. A p-type impurity is selectively ion-implanted into the part under conditions of a dose amount of 2 × 10 ¹² cm ⁻² and an implantation energy of 40 keV, for example. As a result, the p-type channel region 105 is formed on the surface portion of the first n-type semiconductor region 104 in the JFET formation region, and the p-type base region 115 is formed on the surface portion of the n-type semiconductor region 114 in the NPN bipolar transistor formation region. Is formed.

Next, as a fourth step, as shown in FIGS. 8A and 8B, both end portions in the channel width direction of the first n-type semiconductor region 104 and the p-type channel region 105 in the JFET formation region, and the NPN An n-type impurity is selectively ion-implanted into a portion of the n-type semiconductor region 114 in the bipolar transistor formation region where the p-type base region 115 is not formed, for example, with a dose amount of 5 × 10 ¹⁵ cm ⁻² and an implantation energy of 80 keV. To do. As a result, the second n-type semiconductor region 106 is formed deeper than the p-type channel region 105 at both ends in the channel width direction of the p-type channel region 105 in the JFET formation region, and the n-type in the NPN bipolar transistor formation region. An n-type collector region 116 is formed in a portion of the semiconductor region 114 where the p-type base region 115 is not formed.

Next, as a fifth step, as shown in FIGS. 8C and 8D, the surface portion of the p-type channel region 105 in the JFET formation region, the p-type base region 115 in the NPN bipolar transistor formation region, and the n-type An n-type impurity is selectively ion-implanted into each surface portion of the collector region 116 under the conditions of a dose amount of 4 × 10 ¹⁵ cm ⁻² and an implantation energy of 50 keV, for example. As a result, an n-type gate region 107 is formed on the surface portion of the p-type channel region 105 in the JFET formation region, and at the surface portions of the p-type base region 115 and the n-type collector region 116 in the NPN bipolar transistor formation region. An n-type emitter region 117 and an n-type collector contact region 127 are formed.

Next, as a sixth step, as shown in FIGS. 8E and 8F, both sides of the n-type gate region 107 in the channel length direction on the surface portion of the p-type channel region 105 of the JFET formation region, and the NPN bipolar A p-type impurity is selectively applied to a portion where the n-type emitter region 117 is not formed in the surface portion of the p-type base region 115 of the transistor formation region, for example, under a condition of a dose amount of 4 × 10 ¹⁵ cm ⁻² and an implantation energy of 3 keV. Ion implantation. Thus, p-type source / drain regions 108 are formed on both sides of the n-type gate region 107 in the channel length direction on the surface portion of the p-type channel region 105 in the JFET formation region, and the p-type base in the NPN bipolar transistor formation region. A p-type base contact region 118 is formed in a portion of the surface portion of the region 115 where the n-type emitter region 117 is not formed.

  Through the steps described above, the n-type semiconductor region 114, the p-type base region 115 formed on the p-type semiconductor substrate 101 together with the JFET of this embodiment shown in FIGS. 1 and 2A and 2B, An NPN bipolar transistor including an n-type collector region 116, an n-type emitter region 117, an n-type collector contact region 127, and a p-type base contact region 118 is formed.

  As described above, according to the manufacturing method of the present embodiment, the second n-type semiconductor region 106 having a high impurity concentration located on both sides in the channel width direction of the p-type channel region 105 in the JFET of the present embodiment is converted into an NPN bipolar transistor. Since the n-type collector region 116 can be formed at the same time, a semiconductor device in which the JFET and the bipolar transistor of this embodiment are provided on the same substrate can be obtained without any additional process.

  In the manufacturing method of the present embodiment, the conductivity type of the channel region and source / drain region of the JFET and the base region and base contact region of the bipolar transistor are p-type, and the lower side and side of the gate region and channel region of the JFET. The conductivity type of the semiconductor region and the collector region, emitter region, and collector contact region of the bipolar transistor are n-type. Instead, the channel region and source / drain region of the JFET, and the base region and base contact region of the bipolar transistor As in the present embodiment, the conductivity type of n is the n type, and the conductivity type of the gate region of the JFET, the semiconductor region below and on the side of the channel region, and the collector region, emitter region, and collector contact region of the bipolar transistor is p type. Effect of It is obtained. That is, a PNP bipolar transistor may be provided together with the JFET instead of the NPN bipolar transistor.

  Further, in the manufacturing method of the present embodiment, there are no particular limitations on the detailed conditions such as the presence / absence of a surface protective film during ion implantation, the film type and film thickness of the mask material, and the film type and film thickness of the interlayer insulating film. Needless to say.

(Second Embodiment)
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

  9 is a plan view of the semiconductor device according to the present embodiment, specifically, a semiconductor device having a JFET. FIG. 10A is a cross-sectional view taken along the line AA in FIG. (B) is sectional drawing of the BB line of FIG.

  As shown in FIGS. 9, 10 (a), and 10 (b), in the semiconductor device according to the present embodiment, a p-type channel region 206 is formed on the surface portion of a p-type semiconductor substrate 201. An n-type gate region 208 is formed on the surface portion of the p-type channel region 206. A p-type source / drain region 209 is formed on both sides of the n-type gate region 208 in the channel length direction on the surface portion of the p-type channel region 206.

  Further, as a feature of the present embodiment, n-type semiconductor regions 207 having an impurity concentration higher than that of the channel region 206 are formed on both sides of the p-type channel region 206 in the channel width direction of the p-type semiconductor substrate 201. An n-type buried region 202 having an impurity concentration higher than that of the channel region 206 is formed below the p-type channel region 206 in the p-type semiconductor substrate 201.

  Note that an insulating film is formed on the surface portion of the p-type semiconductor substrate 201 so as to surround the p-type channel region 206, the n-type semiconductor region 207 (excluding the bottom), the n-type gate region 208, and the p-type source / drain region 209. 204 is embedded. An isolation region 205 made of, for example, a low concentration p-type semiconductor region is provided below the insulating film 204 in the p-type semiconductor substrate 201 so as to surround the bottom of the n-type buried region 202 and the n-type semiconductor region 207. It has been.

In the present embodiment, the p-type semiconductor substrate 201 is, for example, a P-type silicon substrate, and the impurity concentration is about 4 × 10 ¹⁵ cm ⁻³ . The n-type buried region 202 is, for example, an n-type layer provided by epitaxially growing a silicon layer on the p-type semiconductor substrate 201 after ion-implanting n-type impurities into the surface portion of the p-type semiconductor substrate 201. The impurity concentration is about 2 × 10 ¹⁹ cm ⁻³ . Here, the n-type buried region 202 is partitioned in an island shape by an isolation region 205 reaching the inside of the p-type semiconductor substrate 201. The p-type channel region 206 is, for example, a p-type layer provided by implanting p-type impurities into a silicon layer (epitaxial layer) epitaxially grown on the n-type buried region 202, and the impurity concentration is 1 × 10. It is about ¹⁸ cm ^-3 . The n-type semiconductor region 207 is, for example, an n-type layer provided by implanting an n-type impurity on both sides in the channel width direction of the p-type channel region 206 in the p-type semiconductor substrate 201 including the epitaxial layer, The impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ and is formed deeper than the p-type channel region 206. The n-type gate region 208 is, for example, an n-type layer provided by injecting an n-type impurity into the surface portion of the p-type channel region 206 and has an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ . The p-type source / drain region 209 is, for example, a p-type layer provided by implanting p-type impurities on both sides of the n-type gate region 208 in the channel length direction on the surface portion of the p-type channel region 206. The impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ .

  FIG. 11 shows the impurity concentration distribution in the depth direction of the n-type buried region 202, the n-type semiconductor region 207, the p-type channel region 206, and the n-type gate region 208 in the semiconductor device according to the present embodiment. As shown in FIG. 11, in this embodiment, the impurity concentration of each of the n-type buried region 202, the n-type semiconductor region 207, and the n-type gate region 208 is higher than the impurity concentration of the p-type channel region 206.

  According to the present embodiment described above, the n-type semiconductor region 207 having an impurity concentration higher than that of the p-type channel region 206 is separately provided on both sides of the p-type channel region 206 in the channel width direction, and the p-type channel. An n-type buried region 202 having a higher impurity concentration than the region 206 is separately provided below the p-type channel region 206. That is, the upper surface of the p-type channel region 206 is delimited by an n-type gate region 208 of an opposite conductivity type having a high impurity concentration, and both side surfaces of the p-type channel region 206 are of an opposite conductivity type having a high impurity concentration. The bottom surface of the p-type channel region 206 is partitioned by the n-type buried region 202 of the opposite conductivity type having a high impurity concentration. For this reason, the width of the p-type channel region 206 and the impurity concentration distribution on the side of the p-type channel region 206 indicate that ions for forming the n-type buried region 202 and the n-type gate region 208 sandwiching the p-type channel region 206 from above and below. It is possible to avoid a situation that is affected by fluctuation (variation) in injection. In addition, since the upper, lower, left, and right sides of the p-type channel region 206 can be surrounded by regions of opposite conductivity type having a higher impurity concentration than the p-type channel region 206, the p-type channel region 206 is depleted from the upper, lower, left and right sides even at low power supply voltage. Since the layer is surely spread, the pinch-off voltage can be controlled with high accuracy. Furthermore, the p-type channel region 206 can be depleted with a low gate voltage by surrounding the upper, lower, left, and right sides of the p-type channel region 206 with regions of opposite conductivity type having a high impurity concentration, so that the pinch-off voltage can be reduced. it can.

  In particular, in the case of a JFET structure in which the channel depth is shallow and the channel width is wide, the spread of the depletion layer on the bottom surface of the p-type channel region 206 greatly affects the variation in pinch-off voltage. By using a structure in which opposite conductivity type high-concentration impurity regions are arranged on the bottom surface of the p-type channel region 206 in addition to the both side surfaces of the p-type channel region 206, the above-described effects are remarkably exhibited.

  In the present embodiment, the n-type semiconductor region 207 and the p-type source / drain region 209 may be separated from each other. In this way, the breakdown voltage of the JFET can be improved. In addition, the dimension of the p-type source / drain region 209 in the channel width direction may be larger than the dimension of the n-type gate region 208 in the channel width direction. In this way, the breakdown voltage of the JFET can be improved. However, if there is no problem with the withstand voltage, the n-type semiconductor region 207 and the p-type source / drain region 209 may be in contact with each other as shown in FIG. 12 (modified example of the planar configuration shown in FIG. 9). The dimension of the n-type gate region 208 in the channel width direction and the dimension of the p-type source / drain region 209 in the channel width direction may be approximately the same.

  In the present embodiment, the n-type gate region 208 and the p-type source / drain region 209 may be separated from each other. In this way, by appropriately setting the separation distance between the n-type gate region 208 and the p-type source / drain region 209, the breakdown voltage can be improved while suppressing an increase in on-resistance. In this case, a part of the p-type channel region 206 may be interposed between the n-type gate region 208 and the p-type source / drain region 209 as in this embodiment.

  In the present embodiment, the n-type semiconductor region 207 may be formed deeper than the p-type channel region 206. In this way, the above-described effects can be reliably obtained. In this case, if the n-type semiconductor region 207 is formed shallower than the n-type buried region 202, the breakdown voltage of the JFET can be improved. However, if there is no problem with the withstand voltage, the n-type semiconductor region 207 is formed deeper than the n-type buried region 202 as shown in FIG. 13 (modified example of the cross-sectional configuration shown in FIG. 10A). Also good.

  Further, in this embodiment, as shown in FIG. 10B, the p-type channel region 206 is interposed between the p-type source / drain region 209 and the n-type buried region 202. As shown in FIG. 14 (modified example of the cross-sectional configuration shown in FIG. 10B), part of the p-type source / drain region 209 may be in contact with the n-type buried region 202.

  In the present embodiment, the n-type buried region 202 below the p-type channel region 206 is formed by epitaxial growth of a silicon layer. Instead, a p-type channel is formed by using selective ion implantation. An n-type buried region 202 of an opposite conductivity type having an impurity concentration higher than that of the region 206 may be formed.

  In the present embodiment, the insulating film 204 is a surface portion of the p-type semiconductor substrate 201 (more precisely, a silicon layer epitaxially grown on the p-type semiconductor substrate 201) to the same depth as that of the p-type channel region 206. However, instead of this, the insulating film 204 may be buried deeper or shallower than the p-type channel region 206.

  In the present embodiment, the isolation region 205 made of the low-concentration p-type semiconductor region is provided below the insulating film 204 in the p-type semiconductor substrate 201. Instead, for example, it is covered with a silicon oxide film. An isolation region composed of a non-doped polysilicon region may be provided.

  In the present embodiment, as shown in FIG. 11, for example, the impurity concentration of the n-type gate region 208 may be higher than the impurity concentration of the p-type channel region 206. In this way, the above-described effects can be reliably obtained. In this case, for example, as shown in FIG. 11, the impurity concentration of the n-type gate region 208 may be higher than the impurity concentration of the n-type semiconductor region 207. Alternatively, the peak value of the impurity concentration of the n-type gate region 208 and the peak value of the impurity concentration of the n-type semiconductor region 207 may be substantially the same. In this way, the spread of the depletion layer can be reliably controlled.

  In this embodiment, the p-type semiconductor substrate 201 is used. Instead, an intrinsic semiconductor substrate or an insulating substrate having a p-type semiconductor region formed on the surface may be used.

  In this embodiment, the conductivity type of the channel region and the source / drain region is p-type, and the conductivity type of the gate region and the semiconductor region below and on the side of the channel region is n-type. Even if the conductivity type of the channel region and the source / drain region is n-type, and the conductivity type of the semiconductor region below and on the side of the gate region and the channel region is p-type, the same effect as this embodiment can be obtained.

  Further, in the present embodiment, it is needless to say that the detailed conditions such as the presence / absence of the surface protective film at the time of ion implantation, the film type and film thickness of the mask material, and the film type and film thickness of the interlayer insulating film are not particularly limited.

  Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings, taking as an example a case where an NPN bipolar transistor is provided on the same substrate together with the above-described JFET of the present embodiment.

  The manufacturing method of the semiconductor device according to this embodiment includes an n-type semiconductor region located on both sides in the channel width direction of the p-type channel region 206 in the JFET of this embodiment shown in FIGS. 9 and 10A, 10B. 207 is formed simultaneously with the collector region of the NPN bipolar transistor by n-type impurity implantation, and the n-type buried region 202 located below the p-type channel region 206 in the JFET is defined as a buried region of the NPN bipolar transistor. At the same time, it is characterized in that it is formed by epitaxial growth of a silicon layer. This provides an effect that the JFET of this embodiment can be formed simultaneously with the NPN bipolar transistor without a new additional process.

  FIGS. 15A to 15F, FIGS. 16A to 16F, and FIGS. 17A and 17B are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the present embodiment. 15 (a), 15 (c), 15 (e), 16 (a), 16 (c), 17 (e), and 17 (a) show the cross-sectional configuration of the JFET in the channel width direction. FIGS. 15 (b), (d), (f), FIGS. 16 (b), (d), (f), and FIG. 17 show the cross-sectional configuration of the JFET in the channel length direction. . 15 (a) to 15 (f), FIGS. 16 (a) to (f) and FIGS. 17 (a) and 17 (b), this embodiment shown in FIGS. 9 and 10 (a) and 10 (b). The same components as those of the semiconductor device are denoted by the same reference numerals.

In this embodiment, first, as a first step, as shown in FIGS. 15A and 15B, n-type impurities are respectively added to the JFET formation region and the NPN bipolar transistor formation region in the p-type semiconductor substrate 201. For example, the n-type buried region 202 and the n-type buried region 212 are formed by selective ion implantation under conditions of a dose amount of 5 × 10 ¹⁵ cm ⁻² and an implantation energy of 30 keV.

  Next, as a second step, as shown in FIGS. 15C and 15D, an n-type silicon layer is epitaxially grown on the p-type semiconductor substrate 201 at a temperature of about 1100 ° C., for example, thereby forming a JFET formation region. An n-type epitaxial layer 203 is formed on the surface portion of the p-type semiconductor substrate 201, and an n-type epitaxial layer 213 is formed on the surface portion of the p-type semiconductor substrate 201 in the NPN bipolar transistor formation region. Here, the thickness of each of the n-type epitaxial layer 203 and the n-type epitaxial layer 213 is, for example, about 0.4 μm. In addition, when the n-type epitaxial layer 203 and the n-type epitaxial layer 213 are formed, the n-type buried region 202 in the JFET formation region and the n-type buried region 212 in the NPN bipolar transistor formation region are also the n-type epitaxial layer 203 and the n-type epitaxial layer, respectively. For example, the thickness of the n-type buried region 202 and the n-type buried region 212 is about 0.5 μm.

  Next, as a third step, as shown in FIGS. 15E and 15F, an insulating film 204 is embedded in the surface portion of a predetermined region of the p-type semiconductor substrate 201 using a processing technique such as trench etching, for example. At the same time, an isolation region 205 is formed below the insulating film 204 in the p-type semiconductor substrate 201. As a result, the JFET formation region and the NPN bipolar transistor formation region are electrically separated.

Next, as a fourth step, as shown in FIGS. 16A and 16B, the surface portions of the n-type epitaxial layer 203 in the JFET formation region and the n-type epitaxial layer 213 in the NPN bipolar transistor formation region are selected. For example, p-type impurities are ion-implanted under the conditions of a dose amount of 2 × 10 ¹² cm ⁻² and an implantation energy of 40 keV. As a result, the p-type channel region 206 is formed in the n-type epitaxial layer 203 in the JFET formation region so as to reach the n-type buried region 202, and the p-type base region 216 is formed in the n-type epitaxial layer 213 in the NPN bipolar transistor formation region. Is formed to reach the n-type buried region 212. Here, each thickness of the p-type channel region 206 and the p-type base region 216 is, for example, about 0.3 μm.

Next, as a fifth step, as shown in FIGS. 16C and 16D, both ends of the n-type epitaxial layer 203 including the p-type channel region 206 of the JFET formation region in the channel width direction, and the NPN bipolar transistor An n-type impurity is selectively ion-implanted into the formation region of the n-type epitaxial layer 213 where the p-type base region 216 is not formed, for example, under the conditions of a dose of 5 × 10 ¹⁵ cm ⁻² and an implantation energy of 80 keV. As a result, the n-type semiconductor region 207 is formed deeper than the p-type channel region 206 at both ends in the channel width direction of the p-type channel region 206 in the JFET formation region, and the n-type epitaxial layer 213 in the NPN bipolar transistor formation region. An n-type collector region 217 is formed in a portion where the p-type base region 216 is not formed. Here, the n-type semiconductor region 207 and the n-type collector region 217 are formed, for example, about 0.4 μm deeper than the n-type epitaxial layer 203 and the n-type epitaxial layer 213, respectively.

Next, as a sixth step, as shown in FIGS. 16E and 16F, the surface portion of the p-type channel region 206 in the JFET formation region, the p-type base region 216 and the n-type in the NPN bipolar transistor formation region. An n-type impurity is selectively ion-implanted into each surface portion of the collector region 217 under the conditions of a dose amount of 4 × 10 ¹⁵ cm ⁻² and an implantation energy of 50 keV, for example. As a result, an n-type gate region 208 is formed on the surface portion of the p-type channel region 206 in the JFET formation region, and at the surface portions of the p-type base region 216 and the n-type collector region 217 in the NPN bipolar transistor formation region. An n-type emitter region 218 and an n-type collector contact region 228 are formed. Here, the thickness of each of the n-type gate region 208, the n-type emitter region 218, and the n-type collector contact region 228 is, for example, about 0.15 μm.

Next, as a seventh step, as shown in FIGS. 17A and 17B, both sides of the n-type gate region 208 in the channel length direction on the surface portion of the p-type channel region 206 of the JFET formation region, and the NPN bipolar A p-type impurity is selectively applied to a portion where the n-type emitter region 218 is not formed in the surface portion of the p-type base region 216 in the transistor formation region, for example, under a condition of a dose amount of 4 × 10 ¹⁵ cm ⁻² and an implantation energy of 3 keV. Ion implantation. As a result, p-type source / drain regions 209 are formed on both sides of the n-type gate region 208 in the channel length direction on the surface portion of the p-type channel region 206 in the JFET formation region, and the p-type base in the NPN bipolar transistor formation region. A p-type base contact region 219 is formed in a portion of the surface portion of the region 216 where the n-type emitter region 218 is not formed. Here, the thickness of each of the p-type source / drain region 209 and the p-type base contact region 219 is, for example, about 0.2 μm.

  Through the steps described above, the N-type buried region 212, the p-type base region 216, and the J-type base region 216 formed on the p-type semiconductor substrate 201 together with the JFET of this embodiment shown in FIGS. 9 and 10A and 10B. An NPN bipolar transistor including an n-type collector region 217, an n-type emitter region 218, an n-type collector contact region 228, and a p-type base contact region 219 is formed.

  As described above, according to the manufacturing method of the present embodiment, the high impurity concentration n-type semiconductor regions 207 located on both sides in the channel width direction of the p-type channel region 206 in the JFET of the present embodiment are replaced with the n-type of the NPN bipolar transistor. Since the n-type buried region 202 positioned below the p-type channel region 206 in the JFET of the present embodiment can be formed simultaneously with the buried region 212 of the NPN bipolar transistor, it can be formed at the same time as the collector region 216. In addition, a semiconductor device in which the JFET and the bipolar transistor of this embodiment are provided on the same substrate can be obtained.

  In the manufacturing method of the present embodiment, the n-type buried region 202 of the JFET and the n-type buried region 212 of the NPN bipolar transistor are formed by epitaxial growth of the silicon layer. Implantation may be used to form the JFET n-type buried region 202 and the NPN bipolar transistor n-type buried region 212.

  In the manufacturing method of the present embodiment, the conductivity type of the channel region and source / drain region of the JFET and the base region and base contact region of the bipolar transistor are p-type, and the lower side and side of the gate region and channel region of the JFET. The conductivity type of the semiconductor region and the collector region, emitter region, and collector contact region of the bipolar transistor are n-type. Instead, the channel region and source / drain region of the JFET, and the base region and base contact region of the bipolar transistor As in the present embodiment, the conductivity type of n is the n type, and the conductivity type of the gate region of the JFET, the semiconductor region below and on the side of the channel region, and the collector region, emitter region, and collector contact region of the bipolar transistor is p type. of Results can be obtained. That is, a PNP bipolar transistor may be provided together with the JFET instead of the NPN bipolar transistor.

  Further, in the manufacturing method of the present embodiment, there are no particular limitations on the detailed conditions such as the presence / absence of a surface protective film during ion implantation, the film type and film thickness of the mask material, and the film type and film thickness of the interlayer insulating film. Needless to say.

  As described above, the present invention has the effect of realizing a JFET that enables high-precision pinch-off voltage control and low pinch-off voltage, and is useful in low-noise semiconductor devices and manufacturing methods thereof. .

101 p-type semiconductor substrate 102 insulating film 103 isolation region 104 first n-type semiconductor region 105 p-type channel region 106 second n-type semiconductor region 107 n-type gate region 108 p-type source / drain region 114 n-type semiconductor region 115 p-type base region 116 n-type collector region 117 n-type emitter region 118 p-type base contact region 127 n-type collector contact region 201 p-type semiconductor substrate 202 n-type buried region 203 n-type epitaxial layer 204 insulating film 205 isolation region 206 p-type Channel region 207 n-type semiconductor region 208 n-type gate region 209 p-type source / drain region 212 n-type buried region 213 n-type epitaxial layer 216 p-type base region 217 n-type collector region 218 n-type emitter region 219 p-type Over scan the contact region 228 n-type collector contact region

Claims (17)

A channel region of a first conductivity type provided on the surface portion of the semiconductor substrate;
A first semiconductor region of a second conductivity type provided below the channel region in the semiconductor substrate;
A gate region of a second conductivity type provided on the surface of the channel region;
A source / drain region of a first conductivity type provided on both sides of the channel region in the channel length direction on the surface portion of the channel region;
A second conductivity type second semiconductor region having an impurity concentration higher than that of the first semiconductor region is further provided on both sides of the channel region in the channel width direction of the semiconductor substrate;
The second semiconductor region is formed shallower than the first semiconductor region ;
2. The semiconductor device according to claim 1, wherein the second semiconductor region is formed only in the source / drain region and a region between them in the channel length direction of the gate region . The semiconductor device according to claim 1,
The semiconductor device, wherein the second semiconductor region is formed deeper than the channel region. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the gate region and the source / drain region are separated from each other. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the second semiconductor region and the source / drain region are separated from each other. The semiconductor device according to any one of claims 1 to 4,
2. The semiconductor device according to claim 1, wherein a dimension of the source / drain region in the channel width direction is larger than a dimension of the gate region in the channel width direction. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein an impurity concentration of the gate region is higher than an impurity concentration of the first semiconductor region. The semiconductor device according to claim 6.
The semiconductor device characterized in that the peak value of the impurity concentration of the gate region and the peak value of the impurity concentration of the second semiconductor region are substantially the same. In the semiconductor device according to claim 1,
A semiconductor device further comprising a bipolar transistor provided on the semiconductor substrate. A channel region of a first conductivity type provided on the surface portion of the semiconductor substrate;
A gate region of a second conductivity type provided on the surface of the channel region;
A source / drain region of a first conductivity type provided on both sides of the channel region in the channel length direction on the surface portion of the channel region;
A second conductivity type semiconductor region having a higher impurity concentration than the channel region is provided on both sides of the channel region in the semiconductor substrate in the channel width direction, and below the channel region in the semiconductor substrate. A buried region of a second conductivity type having a higher impurity concentration than the channel region is provided ;
The semiconductor device is characterized in that the semiconductor region is formed only in the source / drain region and the region between them in the channel length direction of the gate region . The semiconductor device according to claim 9.
The semiconductor device is characterized in that the semiconductor region is formed deeper than the channel region. The semiconductor device according to claim 10.
The semiconductor device is characterized in that the semiconductor region is formed shallower than the buried region. The semiconductor device according to any one of claims 9 to 11,
The semiconductor device, wherein the gate region and the source / drain region are separated from each other. The semiconductor device according to any one of claims 9 to 12,
The semiconductor device, wherein the semiconductor region and the source / drain region are separated from each other. The semiconductor device according to any one of claims 9 to 13,
2. The semiconductor device according to claim 1, wherein a dimension of the source / drain region in the channel width direction is larger than a dimension of the gate region in the channel width direction. The semiconductor device according to any one of claims 9 to 14,
The semiconductor device, wherein an impurity concentration of the gate region is higher than an impurity concentration of the channel region. The semiconductor device according to claim 15,
The semiconductor device characterized in that the peak value of the impurity concentration of the gate region and the peak value of the impurity concentration of the semiconductor region are substantially the same. The semiconductor device according to any one of claims 9 to 16,
A semiconductor device further comprising a bipolar transistor provided on the semiconductor substrate.

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