JP5807597B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, a power MOSFET having a trench gate structure has been proposed as a power semiconductor device corresponding to a large current. In such a power MOSFET, when a high voltage is applied to the drain layer, the depletion layer extends to the channel region, punch-through occurs between the source layer and the drain layer, and the semiconductor device is destroyed. There is a problem. Therefore, as a technique for suppressing punch-through in a power MOSFET, for example, those shown in Patent Documents 1 and 2 below are known.

Patent Document 1 describes a trench gate type power MISFET in which a gate electrode (10) is formed inside a groove (7). A p-type semiconductor region (14) having a higher impurity concentration than the p ⁻ -type semiconductor region (13) is located below the n ⁺ -type semiconductor region (15) serving as the source region of the trench gate type power MISFET. It is formed as. In Patent Document 1, punch-through is suppressed by suppressing the depletion of the channel region by the p-type semiconductor region (14).

Patent Document 2 discloses a drift as an n-type second semiconductor layer having an impurity concentration lower than that of the drain layer (1) on the main surface of the n ⁺ -type drain layer (1) as the first semiconductor layer. A layer (2), a base layer (3) as a p-type third semiconductor layer, and a source layer (4) as an n ⁺ -type fourth semiconductor layer having a higher impurity concentration than the drift layer (2). A trench gate type vertical MOSFET is described in which a trench gate structure is provided on the surface side of the semiconductor layers provided in order. The contact groove (38) is provided so as to penetrate the source layer (4) so that the width gradually decreases as the contact groove (38) becomes deeper from the surface side to the base layer 3 side, and below the contact groove (38). A corresponding portion is provided with a p-type pillar layer (buried diffusion layer) (25) as a fifth semiconductor layer. The p-type pillar layer (25) is formed into a p-type using the source layer (4) in which the contact groove (38) is selectively formed and the trench gate structure as a mask before forming the source electrode (11). It is formed by injecting impurities (for example, boron) and performing heat treatment.

JP 2005-57050 A JP 2009-141243 A

  However, in the configuration of Patent Document 1, since a punch-through stopper layer having an impurity concentration higher than that of the channel region is formed, there is a problem that a threshold voltage and an on-resistance increase. Further, since the profile of the impurity concentration in the lateral direction (in-plane direction) of the channel region and the body region is flat, breakdown occurs at the end of the trench gate, and the generated carriers enter the insulating film and be charged. There was a problem.

  On the other hand, in the configuration of Patent Document 2, p-type impurities are implanted from the multi-stage trench contact groove for the purpose of increasing the breakdown voltage and reducing the on-resistance. However, the wiring is performed directly from the multi-stage trench contact. In addition, there is a risk of reaching through from the lower part of the trench contact, and there is a concern that the L load withstand capability is lowered.

  The present invention has been made to solve the above-described problems, and can suppress punch-through while suppressing an increase in threshold voltage and on-resistance, and a semiconductor device and a semiconductor capable of preventing a decrease in L load withstand capability It is to provide a method for manufacturing an apparatus.

The present invention is formed by digging down from a front surface side of the semiconductor substrate, a semiconductor substrate having a predetermined surface and a back surface, a first semiconductor layer of a first conductivity type provided in the semiconductor substrate, and the semiconductor substrate. A plurality of trenches, a gate insulating film formed on the bottom and side surfaces of the trench, a gate electrode formed inside the gate insulating film in the trench, and between the trenches in the plurality of trenches. A second semiconductor layer of a second conductivity type formed on one semiconductor layer, and a third semiconductor layer of a first conductivity type provided adjacent to the trench on the surface side, the trench comprising: A predetermined region in the depth direction is adjacent to the second semiconductor layer, and a bottom provided at a position deeper than the adjacent position is adjacent to the first semiconductor layer. The semiconductor substrate is configured to be adjacent to the third semiconductor layer on the surface side, and the semiconductor substrate has a groove so that a bottom portion is deeper than an upper end portion of the trench in a predetermined region in the width direction between the trenches. A step portion formed in a shape, and on the surface side of the second semiconductor layer, at an intermediate position away from each trench and at an intermediate position in the width direction of the step portion, from the bottom portion of the step portion to the back surface A concave groove formed on the side is formed, an insulating layer is embedded in the groove, the third semiconductor layer is formed adjacent to the upper end of the step, and the step The second semiconductor layer is formed adjacent to the bottom portion, and a punch-through stopper extending to a position deeper than the predetermined region in the depth direction in the lower region of the groove portion in the second semiconductor layer Characterized in that it is constructed as a.

According to a second aspect of the present invention, a step of forming a first semiconductor layer of a first conductivity type in a semiconductor substrate having a predetermined surface and a back surface, and a plurality of trenches are dug down from the surface side of the semiconductor substrate. A step of forming, a step of forming a gate insulating film on the bottom and side surfaces of the trench, a step of forming a gate electrode inside the gate insulating film in the trench, and between the trenches in the plurality of trenches, Forming a second conductive type second semiconductor layer on the first semiconductor layer, and forming a first conductive type third semiconductor layer adjacent to the trench on the surface side. A predetermined region in the depth direction of the trench is adjacent to the second semiconductor layer, and a bottom portion of the trench provided at a position deeper than the adjacent position is adjacent to the first semiconductor layer. And the trench is formed adjacent to the third semiconductor layer on the surface side of the predetermined region in the depth direction, and the upper end of the trench in the predetermined region in the width direction between the trenches of the semiconductor substrate. Forming a stepped portion in a groove shape so that the bottom is deeper than the bottom, and on the surface side of the second semiconductor layer, at an intermediate position away from each trench and at an intermediate position in the width direction of the stepped portion. A step of forming a groove that is recessed from the bottom of the stepped portion toward the back surface, and an impurity is implanted into a lower region of the groove in the second semiconductor layer and a position deeper than the predetermined region in the depth direction. Forming a punch-through stopper layer and embedding the impurity and then embedding an insulating layer in the groove.

In the semiconductor device according to the first aspect, a plurality of trenches are formed by digging down from the surface side of the semiconductor substrate. The trench is configured such that a predetermined region in the depth direction is adjacent to the second semiconductor layer, and a bottom provided at a position deeper than the adjacent position is adjacent to the first semiconductor layer. Further, it is configured to be adjacent to the third semiconductor layer on the surface side. Further, the semiconductor substrate is provided with a step portion formed in a groove shape so that the bottom portion is deeper than the upper end portion of the trench in a predetermined region in the width direction between the trenches. Further, on the surface side of the second semiconductor layer, a groove formed in a concave shape recessed from the bottom of the step portion to the back side is formed at an intermediate position away from each trench and in the intermediate position in the width direction of the step portion. An insulating layer is embedded inside. In this configuration, a path for carrier extraction during switching is performed from both sides of the lower portion of the step portion while avoiding the lower region of the groove portion. Thereby, generation | occurrence | production of the reach through in the lower part area | region of a groove part is suppressed, and the fall of L load tolerance can be prevented.

  The lower region of the groove in the second semiconductor layer is configured as a punch-through stopper layer that extends to a position deeper than the predetermined region in the depth direction. Thus, by providing the second semiconductor layer functioning as a punch-through stopper layer so as to extend to a position deeper than the predetermined region in the depth direction, the center portion (body portion) where the breakdown point is separated from the trench Therefore, it is possible to avoid the problem that the generated carriers enter the gate insulating film and are charged due to breakdown at the end of the trench gate. Also, by providing a step portion on the semiconductor substrate and forming a groove portion at the intermediate position in the width direction of the step portion, the punch-through stopper layer can be easily formed at a desired position (a central portion away from the trench). Furthermore, by forming the groove in this manner, impurities can be implanted into a deep region without enlarging energy so that the impurities are prevented from spreading to the channel region at the time of implantation, and the threshold voltage and on-resistance are increased. Can be suppressed.

  In a second aspect of the present invention, a contact layer whose impurity concentration is set higher than other portions of the second semiconductor layer is formed in a region adjacent to the bottom of the stepped portion. The punch-through stopper layer is set to have an impurity concentration lower than that of the contact layer. Thus, by setting the impurity concentration, the occurrence of reach through from the lower region of the groove portion can be suppressed when the carrier is pulled out, and the L load resistance can be increased.

  In a third aspect of the invention, a part of the side wall surface of the third semiconductor layer is provided adjacent to the stepped portion, and the side wall surface of the stepped portion is formed in a reverse taper shape. According to this configuration, when impurities are implanted into the second semiconductor layer, it is possible to prevent impurities from entering the third semiconductor layer unnecessarily, and an increase in contact resistance and an increase in on-resistance in the third semiconductor layer. Can be suppressed.

  In the invention of claim 4, the width of the groove is set to be less than 24% of the distance between the trenches. Thus, by setting the width of the groove, punch-through can be effectively suppressed while suppressing an increase in on-resistance.

In the method of manufacturing a semiconductor device according to claim 5, the plurality of trenches are adjacent to the second semiconductor layer in a predetermined region in the depth direction and adjacent to the first semiconductor layer at a bottom portion provided at a position deeper than the adjacent position. And formed so as to be adjacent to the third semiconductor layer on the surface side of the predetermined region in the depth direction. Further, a step portion is formed in a groove shape in a predetermined region in the width direction between the trenches of the semiconductor substrate so that the bottom portion is deeper than the upper end portion of the trench, and is separated from each trench on the surface side of the second semiconductor layer. In addition, a groove portion recessed in a concave shape from the bottom portion of the step portion to the back surface side is formed at the intermediate position in the width direction of the step portion . Then, an impurity is implanted into a lower region of the groove in the second semiconductor layer and a position deeper than the predetermined region in the depth direction to form a punch-through stopper layer. After the impurity is implanted, the insulating layer is embedded in the groove. I have to.
As described above, since the impurity is implanted after forming the groove portion in the vicinity of the central portion between the trenches, the impurity can be implanted into a deep region without increasing the energy so much that the impurity is channeled into the channel region at the time of implantation. And the increase in threshold voltage and on-resistance can be suppressed.

  According to the sixth aspect of the invention, a part of the side wall surface of the third semiconductor layer is formed so as to be adjacent to the stepped portion, and the side wall surface of the stepped portion is formed in an inversely tapered shape. By forming in this way, it is possible to suppress the impurities from entering the third semiconductor layer unnecessarily during the implantation of the impurities into the second semiconductor layer, and increase in contact resistance and on-resistance in the third semiconductor layer. Can be suppressed.

FIG. 1 is an explanatory cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 2 is an enlarged view of a region indicated by α in FIG. FIG. 3 is a diagram showing the relationship between the ratio of the width of the groove to the distance between the trenches and the on-resistance. FIG. 4 is a diagram illustrating the relationship between the depth of the groove and the on-resistance. FIG. 5 is a cross-sectional explanatory view showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional explanatory view showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional explanatory view showing the manufacturing process of the semiconductor device according to the first embodiment.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described in detail.

  In the present invention, for example, the semiconductor device 1 having a trench gate structure is formed on the surface (main surface) of the semiconductor substrate 3 made of silicon. The semiconductor substrate 3 has an N-type conductivity type, and an N-type drift layer 15 is provided in the semiconductor substrate 3. A drain electrode 11 composed of an N + type drain layer 13 and an aluminum film is sequentially formed on the back side of the semiconductor substrate 3. The N-type drift layer 15 corresponds to an example of “a first semiconductor layer of a first conductivity type”.

A P-type channel layer 17 is formed on the surface side of the semiconductor substrate 3. Then, a plurality of trenches 19 (only two trenches are shown in FIG. 1 and FIG. 2 for the sake of space) are formed by being dug down from the surface of the P-type channel layer 17 to the N-type drift layer 15. . That is, the P-type channel layer 17 is disposed on the N-type drift layer 15 between the trenches in the plurality of trenches 19. A gate insulating film 21 made of an oxide film such as SiO ₂ is formed on the inner wall surface including the bottom and side surfaces of the trench 19. Further, a gate electrode 23 is formed inside the trench 19 inside the gate insulating film 21. The P-type channel layer 17 corresponds to an example of a “second conductive type second semiconductor layer”.

  An N + type source layer 25 is formed in a region adjacent to the upper end portion of the trench 19 on the P type channel layer 17. A part of the side wall surface of the N + type source layer 25 is provided adjacent to a stepped portion 40 described later together with the P type channel layer 17 formed on the lower layer side. Further, the side wall surface of the N + type source layer 25 is configured to have an inversely tapered shape (that is, the side wall surface of the N + type source layer 25 increases from the width direction intermediate position W1 side to the trench 19 side as it becomes deeper from the surface layer side. It is configured in an inclined shape toward the top.) In the trench 19, the predetermined region R in the depth direction is adjacent to the P-type channel layer 17, and a bottom portion 19 a provided at a position deeper than the adjacent position is adjacent to the N-type drift layer 15. It is adjacent to the N + type source layer 25 on the surface side of the predetermined region R in the vertical direction. Here, the predetermined region R in the depth direction is, as shown in FIG. 1, a lower end portion P1 of the N + type source layer 25 adjacent to the trench 19 and a lower end portion P2 of the P type channel layer 17 adjacent to the trench 19. The area between. This depth direction predetermined region R is a channel region. The N + type source layer 25 corresponds to an example of a “first conductivity type third semiconductor layer”.

  The semiconductor substrate 3 is provided with a step portion 40 formed in a groove shape so that the bottom portion 40a is deeper than the upper end portion of the trench 19 in the predetermined width direction region d3 between the trenches 19 (d2). ing. Further, the P-type channel layer 17 is disposed adjacent to the bottom 40 a of the stepped portion 40. A groove 27 is formed at the intermediate position W1 in the width direction of the stepped portion 40 at an intermediate position away from each trench on the surface side of the P-type channel layer 17. The groove 27 is formed in a concave shape that is recessed on the back side of the semiconductor substrate 3.

  The width d1 of the groove portion 27 is configured to be less than 24% with respect to the distance (cell pitch) d2 between the trenches 19, and more preferably less than 20%. In this way, by setting the width d1 of the groove 27, as shown in FIG. 3, an increase in on-resistance can be suppressed. More specifically, for example, when the distance d2 between the trenches is 2.5 μm, the width d1 of the groove 27 is preferably about 0.4 to 0.6 μm. At this time, the interval d3 between the N + type source layers 25 is preferably about 1.4 μm.

Further, the depth T1 of the groove 27 is preferably less than 0.5 μm as can be seen from FIG. In FIG. 4, black circles are values when the width d1 of the groove 27 is 0.4 μm, black squares are values when the width is 0.5 μm, and black diamonds are values when the width is 0.6 μm. . At this time, the depth T2 from the upper end of the N + type source layer 25 to the surface layer of the P type channel layer 17 is preferably about 0.5 μm. Further, in order to cause breakdown in the vicinity of the center of the P-type channel layer 17 (region deeper than the channel region (predetermined region R in the depth direction)), the groove 27 needs to have a certain depth. The lower limit of the depth T1 of the groove 27 is preferably about 0.2 μm. The depth T1 of the groove 27 can be changed as appropriate according to the energy at the time of ion implantation. An insulating layer 29 is formed in the groove 27. The insulating layer 29 can be made of, for example, SiO ₂ , Si ₃ N ₄ , non-doped polycrystalline silicon, SiN, or the like.

Further, the lower region of the groove 27 in the P-type channel layer 17 is configured as a punch-through stopper layer 31 extending to a position deeper than the predetermined region R in the depth direction (a position deeper than the P2 position). In the region adjacent to the bottom 40 a of the stepped portion 40, the RCP layer 32 is formed in which the impurity concentration is set higher than other portions of the P-type channel layer 17. By providing the RCP layer 32, the contact resistance can be lowered. The punch-through stopper layer 31 is set to have a lower impurity concentration than the RCP layer 32. That is, the punch-through stopper layer 31 is configured as a part of the P-type channel layer 17, and the P-type channel layer 17 is a lower region of the groove portion 27 than the impurity concentration of the region adjacent to the bottom portion 40 a of the stepped portion 40. The impurity concentration of is set lower. For example, when boron is used as the impurity, the impurity concentration of the punch-through stopper layer 31 is about 1.9 × 10 ¹⁷ cm ⁻³ , and the impurity concentration on the surface layer side (RCP layer 32) of the P-type channel layer 17 is 7.0 ×. It is good to be about 10 ¹⁹ cm ⁻³ . The RCP layer 32 corresponds to an example of a “contact layer”.

  As shown in FIGS. 1 and 2, the lowermost end 31a of the punch-through stopper layer 31 is disposed at a position deeper than at least the P2 position. Preferably, the lowermost end portion 31 a is disposed at a position deeper than the bottom portion 23 a of the gate electrode 23. More preferably, the lowermost end portion 31 a may be disposed at a position deeper than the bottom portion 19 a of the trench 19. The N + type source layer 25 is disposed on the upper side of the bottom 40a of the stepped portion 40. In particular, P1 may be arranged on the upper side of the bottom 40a.

  The groove 27 may be formed at least at the center position W1 of the d2 between the trenches 19, and at least at the center of the d2 between the trenches 19, the lowermost end 31a may be disposed in a region deeper than the bottom 19a of the trench 19. More preferably, the lowermost end 31a may be formed in a lower region of the region d1 of the groove 27 (width d1 of the groove 27).

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
In the manufacturing method of the semiconductor device 1 of the present invention, first, a trench gate structure and a trench 19 are formed on a silicon substrate (semiconductor substrate 3) on which the N + type drain layer 13 and the N type drift layer 15 are formed. Next, a gate insulating film 21 is formed in the trench 19 so as to cover at least the bottom and side surfaces of the trench 19. Then, the gate electrode 23 is embedded in the trench 19 and further covered with an insulating film.

Next, boron is ion-implanted over the entire surface at a dose of 1.0 × 10 ¹³ / cm ² and 120 KeV, and is activated by heat treatment at 1050 ° C. for 120 minutes to form a P-type channel layer 17 (FIG. 5). (A)). Then, arsenic is ion-implanted into the P-type channel layer 17 at a dose of 1.5 × 10 ¹⁵ / cm ² and 135 KeV, and activated by heat treatment at 1050 ° C. for 75 minutes to form the N + type source layer 25. (FIG. 5B). The height from the lower end of the trench 19 to the upper end of the N + type source layer 25 is formed to be about 1.5 μm. The impurity concentration of the N + type source layer 25 is formed to be about 6.4 × 10 ¹⁹ cm ⁻³ .

  Next, a PSG film (Phosphorus-Silicate Glass) 38 is formed to about 3000 mm (FIG. 5C). Then, a trench contact 33 is formed (FIG. 6A). The trench contact 33 is formed by shaving the N + source layer (silicon film) 25 by about 0.4 μm by isotropic etching and further shaving the N + type source layer 25 by about 0.1 μm by anisotropic etching. Thereby, the N + type source layer 25 can be formed in an inclined shape (tapered shape) from the width direction intermediate position side toward the trench 19 side. Further, by forming the trench contact 33, the step portion 40 is provided.

Next, the vicinity of the central portion of the P-type channel layer 17 (silicon film) is selectively anisotropically etched using a mask or the like, and is cut by about 0.5 μm to form a groove 27 that is recessed in a concave shape. Then, in order to form the punch-through stopper layer 31, boron is ion-implanted over the entire surface of the P-type channel layer 17 at a dose of 5.0 × 10 ¹² / cm ² and 120 KeV. (Fig. 6 (B))

  Next, an oxide film 39 is formed to 1.1 μm. Thereby, an insulating layer 29 is formed in the groove 27. Then, the surface layer of the oxide film 39 is polished and planarized by CMP (Chemical Mechanical Polishing) (FIG. 6C).

Next, an Ox etching mask 41 is formed so as to exclude a portion where the step portion 40 and the groove portion 27 are formed (FIG. 7A). Then, anisotropic etching using this Ox etching mask 41 is performed, and the oxide film 30 is shaved by about 1.0 μm so as to leave the insulating layer 29 in the groove 27, thereby exposing the bottom 40 a of the step 40. At this time, the upper surface of the insulating layer 29 provided in the groove 27 and the bottom 20a of the stepped portion 40 are substantially flush. Thereafter, the Ox etching mask 41 is removed. Then, boron is ion-implanted at a dose of 3.0 × 10 ¹⁵ / cm ² and 20 KeV to form the RCP layer 32 on the surface layer of the P-type channel layer 17 (FIG. 7B). Next, heat treatment is performed at 900 ° C. for 10 minutes to activate the surface layer of the P-type channel layer 17 and the punch-through stopper layer 31. The channel surface is formed to have an impurity concentration of about 1.1 × 10 ¹⁷ cm ⁻³ and a channel length of about 0.45 μm. Then, the source electrode 37 and the drain electrode 11 made of an Al film are formed, and the semiconductor device 1 can be manufactured (FIG. 7C).

  As described above, according to the semiconductor device 1 according to the first embodiment, a plurality of trenches 19 are formed by being dug down from the surface side of the semiconductor substrate 3. The trench 19 is configured such that a predetermined region in the depth direction is adjacent to the P-type channel layer 17, and a bottom portion 19 a provided at a position deeper than the adjacent position is adjacent to the N-type drift layer 15. It is configured to be adjacent to the N + type source layer 25 on the surface side of the predetermined region in the vertical direction. Further, the semiconductor substrate 3 is provided with a stepped portion 40 formed in a groove shape so that the bottom portion 40 a is deeper than the upper end portion of the trench 19 in a predetermined region in the width direction between the trenches 19. Further, on the front surface side of the P-type channel layer 17, a groove portion 27 formed in a concave shape recessed on the back surface side is formed at an intermediate position away from each trench 19 and at an intermediate position in the width direction of the stepped portion 40. An insulating layer 29 is embedded inside. In this configuration, a path for carrier extraction during switching is performed from both sides of the lower portion of the step portion 40 while avoiding the lower region of the groove portion 27. Thereby, generation | occurrence | production of the reach through in the lower area | region of the groove part 27 is suppressed, and the fall of L load tolerance can be prevented.

  The lower region of the groove 27 in the P-type channel layer 17 is configured as a punch-through stopper layer that extends to a position deeper than the predetermined region in the depth direction. In this way, by providing the P-type channel layer 17 that functions as the punch-through stopper layer 31 so as to extend to a position deeper than the predetermined region in the depth direction, the breakdown point is separated from the central portion ( The body portion) can be shifted, and a problem that a breakdown occurs at the end of the trench gate and the generated carriers enter the gate insulating film 21 to be charged can be avoided. Further, the step portion 40 is provided in the semiconductor substrate 3 and the groove portion 27 is formed at the intermediate position in the width direction of the step portion 40, so that the punch-through stopper layer 31 is formed at a desired position (a central portion away from the trench 19). It becomes easy to do. Furthermore, by forming the groove in this manner, impurities can be implanted into a deep region without enlarging energy so that the impurities are prevented from spreading to the channel region at the time of implantation, and the threshold voltage and on-resistance are increased. Can be suppressed.

  In the region adjacent to the bottom 40a of the stepped portion 40, an RCP layer 32 (contact layer) is formed in which the impurity concentration is set higher than other portions of the P-type channel layer 17. The punch-through stopper layer 31 is set to have a lower impurity concentration than the RCP layer 32. Thus, by setting the impurity concentration, the occurrence of reach-through from the lower region of the groove 27 can be suppressed when the carrier is extracted, and the L load withstand capability can be increased.

  Further, a part of the side wall surface of the N + type source layer 25 is provided adjacent to the stepped portion 40, and the side wall surface of the stepped portion 40 is formed in a reverse taper shape. According to this configuration, when impurities are implanted into the P-type channel layer 17, it is possible to prevent impurities from entering the N + -type source layer 25 unnecessarily, increasing the contact resistance in the N + -type source layer 25 and turning it on. An increase in resistance can be suppressed.

  Further, the width of the groove 27 is set to be less than 24% of the distance between the trenches 19. Thus, by setting the width of the groove 27, it is possible to effectively suppress punch-through while further suppressing an increase in on-resistance.

In the method for manufacturing the semiconductor device 1 according to the present embodiment, the plurality of trenches 19 are formed such that the predetermined region in the depth direction is adjacent to the P-type channel layer 17 and the bottom 19a provided at a position deeper than the adjacent position is N. It is formed so as to be adjacent to the type drift layer 15 and so as to be adjacent to the N + type source layer 25 on the surface side of the predetermined region in the depth direction. Further, in the predetermined region in the width direction between the trenches 19 of the semiconductor substrate 3, a step 40 is formed in a groove shape so that the bottom 40 a is deeper than the upper end of the trench 19, and the surface side of the P-type channel layer 17 In FIG. 8, a groove 27 that is recessed in the back surface is formed at an intermediate position away from each trench 19 and at an intermediate position in the width direction of the stepped portion 40. Then, an impurity is implanted into a region below the groove 27 in the P-type channel layer 17 and a position deeper than a predetermined region in the depth direction to form a punch-through stopper layer 31. After the impurity is implanted, insulation is provided in the groove 27. The layer 29 is embedded.
As described above, since the impurity is implanted after the groove 27 is formed near the central portion between the trenches 19, the impurity can be implanted into a deep region without energizing the energy so much. Expansion to the channel region can be suppressed, and an increase in threshold voltage and on-resistance can be suppressed.

  Further, a part of the side wall surface of the N + type source layer 25 is formed so as to be adjacent to the stepped portion 40, and the side wall surface of the stepped portion 40 is formed in a reverse taper shape. By forming in this way, it is possible to prevent impurities from entering the N + type source layer 25 unnecessarily during the implantation of impurities into the P type channel layer 17, and increase in contact resistance in the N + type source layer 25. And increase in on-resistance can be suppressed.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  In the above embodiment, an example is shown in which a part of the side wall surface of the N + type source layer 25 is provided adjacent to the stepped portion 40, and the side wall surface of the stepped portion 40 is configured in an inversely tapered shape. However, it is not particularly limited to this.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 3 ... Semiconductor substrate 11 ... Drain electrode 13 ... N + type drain layer 15 ... N type drift layer (1st conductivity type 1st semiconductor layer)
17 P-type channel layer (second conductivity type second semiconductor layer)
DESCRIPTION OF SYMBOLS 19 ... Trench 21 ... Gate insulating film 23 ... Gate electrode 25 ... N + type source layer (3rd semiconductor layer of 1st conductivity type)
27 ... Groove 29 ... Insulating layer 31 ... Punch-through stopper layer 32 ... RCP layer (contact layer)
33 ... trench contact 35 ... PSG film 37 ... source electrode 38 ... PSG film 39 ... oxide film 40 ... stepped portion 40a ... bottom of stepped portion 41 ... Ox etching mask

Claims (6)

A semiconductor substrate having a predetermined surface and a back surface;
A first semiconductor layer of a first conductivity type provided in the semiconductor substrate;
A plurality of trenches formed by being dug from the surface side of the semiconductor substrate;
A gate insulating film formed on the bottom and side surfaces of the trench;
A gate electrode formed inside the gate insulating film in the trench;
A second semiconductor layer of a second conductivity type formed on the first semiconductor layer between the trenches of the plurality of trenches;
A third semiconductor layer of a first conductivity type provided adjacent to the trench on the surface side;
With
The trench is configured such that a predetermined region in the depth direction is adjacent to the second semiconductor layer, and a bottom provided at a position deeper than the adjacent position is adjacent to the first semiconductor layer, Configured to be adjacent to the third semiconductor layer on the surface side of the region,
The semiconductor substrate is provided with a step portion formed in a groove shape so that the bottom portion is deeper than the upper end portion of the trench in a predetermined region in the width direction between the trenches,
On the front surface side of the second semiconductor layer, a groove portion formed in a concave shape recessed from the bottom portion of the step portion to the back surface side is formed at an intermediate position away from each trench and at an intermediate position in the width direction of the step portion. And
An insulating layer is embedded in the groove,
The third semiconductor layer is formed adjacent to the upper end of the stepped portion;
The second semiconductor layer is formed adjacent to the bottom of the stepped portion;
The semiconductor device according to claim 1, wherein a lower region of the groove portion in the second semiconductor layer is configured as a punch-through stopper layer extending to a position deeper than the predetermined region in the depth direction. A region adjacent to the bottom of the stepped portion is formed with a contact layer whose impurity concentration is set higher than other portions of the second semiconductor layer,
The semiconductor device according to claim 1, wherein the punch-through stopper layer is set to have an impurity concentration lower than that of the contact layer.   A part of the side wall surface of the third semiconductor layer is provided adjacent to the stepped portion, and the side wall surface of the stepped portion is configured in an inversely tapered shape. Item 3. The semiconductor device according to Item 2.   4. The semiconductor device according to claim 1, wherein a width of the groove is less than 24% of a distance between the trenches. 5. Forming a first semiconductor layer of a first conductivity type in a semiconductor substrate having a predetermined surface and a back surface;
Digging from the surface side of the semiconductor substrate to form a plurality of trenches;
Forming a gate insulating film on the bottom and side surfaces of the trench;
Forming a gate electrode inside the gate insulating film in the trench;
Forming a second conductivity type second semiconductor layer on the first semiconductor layer between the trenches of the plurality of trenches;
Forming a third semiconductor layer of a first conductivity type so as to be adjacent to the trench on the surface side,
A predetermined region in the depth direction of the trench is adjacent to the second semiconductor layer, and a bottom portion of the trench provided at a position deeper than the adjacent position is formed adjacent to the first semiconductor layer; and Forming a trench so as to be adjacent to the third semiconductor layer on the surface side of the predetermined region in the depth direction;
Forming a stepped portion in a groove shape so that the bottom portion is deeper than the upper end portion of the trench in a predetermined region in the width direction between the trenches of the semiconductor substrate;
Forming a groove portion recessed in a concave shape from the bottom portion of the step portion to the back surface side at an intermediate position away from each trench and in a width direction intermediate position of the step portion on the front surface side of the second semiconductor layer; ,
Forming a punch-through stopper layer by injecting impurities into a lower region of the groove in the second semiconductor layer and a position deeper than the predetermined region in the depth direction;
And a step of embedding an insulating layer in the groove after the impurity is implanted.   6. The semiconductor according to claim 5, wherein a part of the side wall surface of the third semiconductor layer is formed so as to be adjacent to the stepped portion, and the side wall surface of the stepped portion is formed in a reverse taper shape. Device manufacturing method.

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