JP5893371B2 - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Description

  The present invention has a structure in which a plurality of internal electrode layers are stacked via ceramic dielectric layers, and the vias extend in the stacking direction of the ceramic dielectric layers and the internal electrode layers and are connected to the plurality of internal electrode layers. The present invention relates to a multilayer ceramic capacitor in which electrodes are arranged in an array as a whole and a method for manufacturing the same.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, a wiring board in which a capacitor is embedded in a resin core board (for example, see Patent Document 1) has been proposed.

  Patent Document 1 discloses a via array type multilayer ceramic capacitor as a capacitor built in a wiring board. This multilayer ceramic capacitor has a structure in which a plurality of ceramic dielectric layers and a plurality of internal electrode layers are alternately stacked. In this ceramic capacitor, a plurality of via electrodes that are electrically connected to the internal electrode layers through the ceramic dielectric layers are arranged in an array. These via electrodes are arranged so as to cancel out magnetic fields induced by currents flowing through the internal electrode layers, and the inductance of the multilayer ceramic capacitor can be kept low. For this reason, the multilayer ceramic capacitor is connected to the vicinity of the power supply terminal of the IC chip for high frequency and is used as a decoupling capacitor for reducing power supply noise.

  When manufacturing a via array type multilayer ceramic capacitor, first, the unfired conductor part to be an internal electrode layer and the unfired ceramic part to be a ceramic dielectric layer are laminated, and then unfired by pressing them in the laminating direction. A ceramic laminate is prepared. Furthermore, after forming the unsintered via conductor portion that penetrates the unsintered ceramic laminate in the stacking direction, a multi-layer ceramic capacitor is manufactured by performing a firing step.

JP-A-2005-39243

  By the way, in the above-mentioned via array type multilayer ceramic capacitor, clearance holes are provided in every other region in the plurality of internal electrode layers through which the via electrodes penetrate. For this reason, the number of internal electrode layers is halved around the via electrode provided with the clearance hole. In the conventional multilayer ceramic capacitor, the diameters of the plurality of clearance holes are formed to be equal, and the end portions of the clearance holes are aligned in the stacking direction. Therefore, when manufacturing a multilayer ceramic capacitor, the clearance hole portion has less overlap between the unfired conductors in the unfired ceramic laminate, so the pressure applied during pressing is not uniform and the density is low. Prone. For this reason, a density difference occurs in the vicinity of the clearance hole. Further, when firing the unfired ceramic laminate, in addition to the difference in density in the clearance hole, there is a possibility that the ceramic capacitor warps due to a difference in shrinkage behavior between the unfired conductor part and the unfired ceramic part. is there. In particular, a via array type multilayer ceramic capacitor has a plurality of locations (clearance holes) where the difference in shrinkage behavior described above exists in an array, and the planar size is larger than that of a chip capacitor, so that warpage is likely to occur.

  Further, in the ceramic capacitor, the region outside the end portion of the internal electrode layer is constituted only by the ceramic dielectric layer. Therefore, at the end portion of the internal electrode layer (the boundary between the internal electrode layer forming region and the outer region), the ratio between the ceramic and the conductor changes abruptly, which causes a difference in shrinkage behavior. It is conceivable that warpage occurs in the multilayer ceramic capacitor due to this difference in shrinkage behavior.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a multilayer ceramic capacitor capable of reducing warpage in the multilayer ceramic capacitor. Another object is to provide a multilayer ceramic capacitor with less warpage and excellent connection reliability.

As means for solving the above problems (means 1A ), the ceramic dielectric layer has a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via the ceramic dielectric layer. A first via electrode extending in the stacking direction of the body layer and the internal electrode layer and connected to the plurality of first internal electrode layers; and a first via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers. 2 via electrodes are arranged in an array as a whole, a first clearance hole is provided in the plurality of first internal electrode layers, and the first clearance hole allows the first internal electrode layer, the second via electrode, Are electrically insulated, and a plurality of second internal electrode layers are provided with second clearance holes, and the second clearance holes provide electrical connection between the second internal electrode layer and the first via electrode. A method of manufacturing a multilayer ceramic capacitor that is insulated from each other (hereinafter, simply referred to as “a method of manufacturing a multilayer ceramic capacitor having the above-described basic configuration”) , which includes the first internal electrode layer and the second internal electrode layer; An unfired ceramic laminate in which the unfired conductor portion and the unfired ceramic portion are integrated by laminating the unfired conductor portion and the unfired ceramic portion to be the ceramic dielectric layer and pressing in the laminating direction And a green body via which the first via electrode and the second via electrode are formed in the through hole, and a through hole penetrating the green ceramic laminated body in the laminating direction is formed. A via forming step for forming a conductor part, and sintering the green ceramic laminate to form the ceramic dielectric layer, the internal electrode layer, and the via electrode In the laminated body preparation step, two or more types of clearances having different diameters with respect to the unfired conductor portion serving as at least one internal electrode layer of the first internal electrode layer and the second internal electrode layer are included. A pattern is formed so that holes are arranged in the stacking direction, and an average value of the diameters of the clearance holes is made equal in the upper layer and the lower layer in the stacking direction of the green ceramic laminate. There is a method for manufacturing a multilayer ceramic capacitor .
Another means (means 1B, 1C) for solving the above-described problem is a method for manufacturing a multilayer ceramic capacitor having the above-described basic structure, which is not yet used as the first internal electrode layer and the second internal electrode layer. An unfired ceramic laminate in which the unfired conductor portion and the unfired ceramic portion are integrated by laminating the fired conductor portion and the unfired ceramic portion serving as the ceramic dielectric layer and pressing in the laminating direction. A laminate preparation step to be prepared, and an unfired via conductor portion that forms a through-hole penetrating the unfired ceramic laminate in the laminating direction and serves as the first via electrode and the second via electrode in the through-hole Forming a via, and sintering the green ceramic laminate to form the ceramic dielectric layer, the internal electrode layer, and the via electrode. In the laminate preparation step, two or more types of clearance holes having different diameters are arranged in the stacking direction for the unfired conductor portion serving as at least one of the first internal electrode layer and the second internal electrode layer. A pattern was formed so as to be provided, and clearance holes having different diameters were regularly repeated in the laminating direction in the unfired conductor portions to be the first internal electrode layer and the second internal electrode layer ( Alternatively, there is a method for manufacturing a multilayer ceramic capacitor characterized in that the diameter of the clearance hole provided in the outer peripheral portion is formed larger than the diameter of the clearance hole provided in the central portion.

According to the invention described in the means 1A to 1C , since the unfired conductor portion is formed in a pattern so that two or more types of clearance holes having different diameters are arranged in the laminating direction, the position of the end portion is in the laminating direction. Each clearance hole is formed in a different state. For this reason, compared with the case where the positions of the end portions of the clearance holes are aligned in the stacking direction as in the prior art, the number of layers where the unfired conductor portions overlap at the end portions of the clearance holes changes stepwise. Accordingly, when the green ceramic laminate is pressed, a rapid change in density difference near the end of the clearance hole is alleviated. As a result, at the time of firing the unsintered ceramic laminate, the difference in shrinkage behavior according to the density is reduced, and the warp of the multilayer ceramic capacitor can be reduced.

  In the laminate preparation step, it is preferable that the average value of the diameters of the clearance holes is made equal in the upper layer and the lower layer in the stacking direction of the unfired ceramic laminate. In the laminate preparation step, it is more preferable to form clearance holes having different diameters so that the number of layers is the same in the stacking direction in the unfired conductor portions serving as the first internal electrode layer and the second internal electrode layer. Furthermore, in the laminated body preparation step, it is more preferable to form clearance holes having different diameters regularly in the stacking direction in the unfired conductor portions serving as the first internal electrode layer and the second internal electrode layer. In this case, since clearance holes having different diameters are arranged without deviation in the laminating direction, a density difference hardly occurs in the laminating direction, and the warpage of the multilayer ceramic capacitor can be reduced.

  In the laminated body preparation step, the diameter of the clearance hole provided in the outer peripheral portion is formed larger than the diameter of the clearance hole provided in the central portion in the unfired conductor portion to be the first internal electrode layer and the second internal electrode layer. May be. In this case, in the multilayer ceramic capacitor, the ratio of the ceramic dielectric layer gradually increases from the central portion toward the outer peripheral portion. For this reason, in the vicinity of the end portion of the internal electrode layer, the difference in the rapid contraction behavior according to the presence or absence of the electrode layer between the ceramic dielectric layers is alleviated, and the warpage of the multilayer ceramic capacitor can be reduced.

Further, as another means (means 2) for solving the above-described problem, the first internal electrode layer and the second internal electrode layer are alternately stacked via a ceramic dielectric layer, A first via electrode extending in the stacking direction of the ceramic dielectric layer and the internal electrode layer and connected to the plurality of first internal electrode layers; and connected to the plurality of second internal electrode layers extending in the stacking direction. The second via electrodes are arranged in an array as a whole, and a plurality of first internal electrode layers are provided with first clearance holes, and the first clearance holes provide the first internal electrode layers and the second internal electrodes. A plurality of second internal electrode layers are electrically insulated from via electrodes, and second clearance holes are provided in the plurality of second internal electrode layers, and the second clearance holes allow the second internal electrode layers and the first via electrodes to be separated from each other. Electrical The at least one internal electrode layer of the first internal electrode layer and the second internal electrode layer is provided with two or more types of clearance holes having different diameters in the stacking direction. Tei Rutotomoni, in an upper layer and a lower layer of the stacking direction, there is a multilayer ceramic capacitor is characterized in that equal the mean value of the diameters of the clearance hole.

  According to the invention described in means 2, since two or more types of clearance holes having different diameters are arranged in the stacking direction in the internal electrode layer, the positions of the end portions of the clearance holes differ in the stacking direction. In this case, the rapid change in the density difference near the end of the clearance hole is alleviated, and the difference in shrinkage behavior according to the density is reduced at the time of firing the ceramic, so that the warpage of the ceramic capacitor can be reduced. When a DC voltage is applied, the ceramic dielectric layers expand and contract due to electrostriction. At this time, since the position of the end portion of the clearance hole is different in the stacking direction, the stress in the vicinity of the end portion of the clearance hole, which is a boundary without displacement, is dispersed. Therefore, cracks and delamination hardly occur when a DC voltage is applied, and the product reliability of the multilayer ceramic capacitor is improved.

  The multilayer ceramic capacitor preferably has a rectangular shape including sides with a length of 8 mm or more and a warp amount of 30 μm or less. In particular, the warp amount is preferably 20 μm or less, and more preferably 15 μm or less. Thus, by suppressing the amount of warpage in a multilayer ceramic capacitor having a relatively large size, it is possible to sufficiently ensure the connection reliability of the multilayer ceramic capacitor when the wiring board is built in.

  As the ceramic dielectric layer, a dielectric composed of one or more of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium zirconate, calcium zirconate, titanium oxide, lead niobate, etc. It is preferable to use a sintered body of a body ceramic. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized. Further, as the ceramic dielectric layer, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride or the like may be used, or alumina may be used for borosilicate glass or lead borosilicate glass. A sintered body of a low-temperature fired ceramic such as a glass ceramic to which an inorganic ceramic filler such as the above is added may be used.

  The internal electrode layer and the via electrode are preferably metallized conductors. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, barium titanate), as the metal powder in the metallized conductor, nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo ), Manganese (Mn), and the like and alloys thereof. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

Sectional drawing which shows schematic structure of the multilayer ceramic capacitor in this Embodiment. The top view which shows the multilayer ceramic capacitor in this Embodiment. Sectional drawing which shows the internal electrode layer for power supplies, and a 1st clearance hole. Sectional drawing which shows the internal electrode layer for power supplies, and a 1st clearance hole. Sectional drawing which shows the internal electrode layer for grounds, and a 2nd clearance hole. Sectional drawing which shows the internal electrode layer for grounds, and a 2nd clearance hole. Sectional drawing which shows the laminated body preparation process in the manufacturing method of a multilayer ceramic capacitor. Sectional drawing which shows the laminated body preparation process in the manufacturing method of a multilayer ceramic capacitor. Sectional drawing which shows the via formation process in the manufacturing method of a multilayer ceramic capacitor. Sectional drawing which shows the surface layer electrode formation process in the manufacturing method of a multilayer ceramic capacitor. Explanatory drawing which shows the measurement point of the curvature amount of a capacitor | condenser. Sectional drawing which shows the laminated body preparation process of Example 3. FIG. Sectional drawing which shows the 1st internal electrode part of Examples 4-8. Sectional drawing which shows the 2nd internal electrode part of Examples 4-8. Sectional drawing which shows the 1st internal electrode part of Examples 4-8. Sectional drawing which shows the 2nd internal electrode part of Examples 4-8.

  Hereinafter, an embodiment in which the present invention is embodied in a multilayer ceramic capacitor will be described in detail with reference to the drawings.

  As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 101 according to the present embodiment is a so-called via array type capacitor. The ceramic sintered body 104 constituting the multilayer ceramic capacitor 101 has one capacitor main surface 102 (upper surface in FIG. 1), one capacitor back surface 103 (lower surface in FIG. 1), and four capacitor side surfaces 106. Yes. The size is, for example, about 10 mm long × 10 mm wide × 0.8 mm thick.

  The ceramic sintered body 104 includes an electrode laminated portion 107 and a cover layer portion 108. The electrode laminated portion 107 alternately laminates power supply internal electrode layers 141A and 141B (first internal electrode layers) and ground internal electrode layers 142A and 142B (second internal electrode layers) via the ceramic dielectric layer 105. Has the structure. In the electrode laminate portion 107, the number of power supply internal electrode layers 141A and 141B and the number of ground internal electrode layers 142A and 142B are 50 layers, respectively. The cover layer portion 108 is provided so as to cover the outer surface of the electrode stack portion 107 in the stacking direction. The cover layer portion 108 has a structure in which a plurality of ceramic insulating layers 150 are stacked. The ceramic insulating layer 150 of the cover layer portion 108 is formed using the same material as the ceramic dielectric layer 105 in the electrode laminate portion 107.

  The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and is a dielectric (insulator) between the internal electrode layers 141A and 141B for power supply and the internal electrode layers 142A and 142B for ground. Function as. That is, the power supply internal electrode layers 141A and 141B and the ground internal electrode layers 142A and 142B are electrically insulated via the ceramic dielectric layer 105. The power supply internal electrode layers 141A and 141B and the ground internal electrode layers 142A and 142B are both metallized conductors formed mainly of nickel. In the present embodiment, the thickness of each ceramic dielectric layer 105 is about 5 μm, and the thickness of each internal electrode layer 141A, 141B, 142A, 142B is 1.5 μm to 1.8 μm.

  A large number of vias 130 are formed in the ceramic sintered body 104. These vias 130 penetrate the ceramic sintered body 104 in the thickness direction (stacking direction) and are arranged in an array over the entire surface of the ceramic sintered body 104. In each via 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. In the present embodiment, since the diameter of the via 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 is also set to about 100 μm. The via conductors 131 and 132 have an aspect ratio of about 8. Further, the pitch between the via conductors 131 and 132 is about 400 μm.

  Each power supply capacitor internal via conductor 131 (first via electrode) extends in the laminating direction of the ceramic sintered body 104 and penetrates each power supply internal electrode layer 141A, 141B, and is electrically connected to each other. doing. Each ground-capacitor via conductor 132 (second via electrode) extends in the stacking direction of the ceramic sintered body 104 and penetrates each ground internal electrode layer 142A, 142B, and is electrically connected to each other. doing. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. In FIG. 1 and FIG. 2, for convenience of explanation, the via conductors 131 and 132 in the capacitor are shown in 4 rows × 4 rows, but actually more rows (in this embodiment, for example, 20 rows × 20 rows). Column) exists.

  A plurality of main surface side power surface electrodes 111 and a plurality of main surface side ground surface electrodes 112 are provided on the upper surface of the cover layer portion 108 to be the capacitor main surface 102 of the ceramic sintered body 104. The main surface side power surface layer electrode 111 is directly connected to the end surface of the power source capacitor inner via conductor 131 on the capacitor main surface 102 side, and the main surface side ground surface electrode 112 is connected to the ground inner capacitor via conductor. The capacitor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  On the lower surface of the cover layer portion 108 to be the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power surface electrodes 121 and a plurality of back surface ground surface electrodes 122 are provided. The back surface side power surface layer electrode 121 is directly connected to the end surface of the power source capacitor via conductor 131 on the capacitor back surface 103 side, and the back surface ground surface electrode 122 is a capacitor in the ground capacitor internal via conductor 132. It is directly connected to the end surface on the back surface 103 side. Therefore, the power surface layer electrodes 111 and 121 are electrically connected to the power source capacitor via conductor 131 and the power source internal electrode layers 141A and 141B, and the ground surface layer electrodes 112 and 122 are connected to the ground capacitor inner via conductor 132 and the ground. The internal electrode layers 142A and 142B are electrically connected.

  Each surface layer electrode 111, 112, 121, 122 is a circular island electrode formed with nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). In the present embodiment, the diameter of each surface layer electrode 111, 112, 121, 122 is set to about 300 μm.

  Further, in the plurality of internal electrode layers 141A, 141B, 142A, 142B in the electrode laminated portion 107, clearance holes 133, 134 are provided in every other area in the region through which the via conductors 131, 132 penetrate. Specifically, as shown in FIGS. 1, 3, and 4, a first clearance hole 133 is formed in a region through which the via-capacitor via conductor 132 penetrates in the power supply internal electrode layers 141 </ b> A and 141 </ b> B. The first clearance hole 133 electrically insulates the power internal electrode layers 141A and 141B from the ground capacitor internal via conductor 132. As shown in FIGS. 1, 5 and 6, the ground internal electrode layers 142A and 142B are formed with a second clearance hole 134 in a region through which the power-source capacitor via conductor 131 passes, and the second clearance hole 134 is formed. The holes 134 electrically insulate the ground internal electrode layers 142A, 142B from the power supply capacitor via conductors 131. The ceramic dielectric layer 105 is interposed between the internal electrode layers 141A, 141B, 142A, 142B and the via conductors 131, 132 in the clearance holes 133, 134.

  FIG. 3 shows the internal electrode layers 141A arranged at positions that are odd layers counted from above in the plurality of power supply internal electrode layers 141A and 141B, and FIG. 4 shows even layers counted from above. The internal electrode layer 141 </ b> B disposed at the position is shown. FIG. 5 shows the internal electrode layers 142A arranged at positions that are odd layers counted from above in the plurality of ground internal electrode layers 142A and 142B, and FIG. 6 shows even layers counted from above. The internal electrode layer 142 </ b> B disposed at the position is shown. It should be noted that in the stacking order of all the internal electrode layers including the power supply internal electrode layer and the ground internal electrode layer, they are repeatedly stacked in the order of 141A / 142A / 141B / 142B.

  As shown in FIGS. 1 and 3 to 6, in the multilayer ceramic capacitor 101 of the present embodiment, two types of clearance holes 133, having different diameters in the power supply internal electrode layer and the ground internal electrode layer, respectively. 134 are alternately arranged in the stacking direction. Moreover, the diameters of the clearance holes 133 and 134 provided in the outer peripheral portion are larger than the diameters of the clearance holes 133 and 134 provided in the central portion.

  Specifically, for example, in each of the power supply internal electrode layers 141A of the odd-numbered layers, the clearance hole 133 provided in the outer peripheral portion has a diameter of 350 μm, and the clearance hole 133 provided in the central portion has a diameter of 300 μm (see FIG. 3). Further, in each power supply internal electrode layer 141B of the even layer, the diameter of the clearance hole 133 provided in the outer peripheral portion is 300 μm, and the diameter of the clearance hole 133 provided in the central portion is 250 μm (see FIG. 4). On the other hand, in each odd-numbered ground internal electrode layer 142A, the clearance hole 134 provided in the outer peripheral portion has a diameter of 350 μm, and the clearance hole 134 provided in the central portion has a diameter of 300 μm (see FIG. 5). Further, in each ground internal electrode layer 142B of even layers, the diameter of the clearance hole 134 provided in the outer peripheral portion is 300 μm, and the diameter of the clearance hole 134 provided in the central portion is 250 μm (see FIG. 6).

  As described above, in the multilayer ceramic capacitor 101 of the present embodiment, the clearance holes 133 and 134 having large diameters and the clearance holes 133 and 134 having small diameters are regularly arranged alternately in the stacking direction. Therefore, the clearance holes 133 and 134 having a large diameter and the clearance holes 133 and 134 having a small diameter are equal in number in the stacking direction.

  The ceramic capacitor 101 of the present embodiment is manufactured as follows.

A slurry containing barium titanate (BaTiO ₃ ) powder is applied onto a carrier film and dried to obtain an unfired ceramic green sheet disposed in a peelable state on the carrier film. The unfired ceramic green sheet is a sheet having a thickness of about 8 μm (about 5 μm after firing), and is later cut into a desired shape to form an unfired ceramic part.

  A screen mask is disposed on the unfired ceramic green sheet, and the internal electrode paste is screen-printed and dried to pattern the internal electrode portion having a thickness of 2 μm to 3 μm. The internal electrode paste includes nickel powder as conductive particles, barium titanate powder as a common material, and the like.

  Specifically, as shown in FIG. 7, the first internal electrode portion 161A of the pattern 1-A that forms a clearance hole 133 having a large diameter is unfired as an unfired conductor portion that becomes the internal electrode layer 141A for power supply. It is formed on the ceramic green sheet 160. Further, a first internal electrode portion 161B having a pattern 1-B that forms a clearance hole 133 having a small diameter is formed on the unfired ceramic green sheet 160 as an unfired conductor portion that becomes the power source internal electrode layer 141B. Further, a second internal electrode portion 162A having a pattern 2-A that forms a clearance hole 134 having a large diameter is formed on the unfired ceramic green sheet 160 as an unfired conductor portion to be the ground internal electrode layer 142A. Further, a second internal electrode portion 162B having a pattern 2-B that forms a clearance hole 134 having a small diameter is formed on the green ceramic green sheet 160 as a green conductor portion to be the ground internal electrode layer 142B. In the present embodiment, the patterns of the first internal electrode portions 161A and 161B of the pattern 1-A and the pattern 1-B, and the second internal electrode portions 162A and 162B of the pattern 2-A and the pattern 2-B, respectively. Twenty-five unfired ceramic green sheets 160 are formed, that is, a total of 100 unfired ceramic green sheets 160 are prepared.

  The clearance holes 133, 134 formed in the internal electrode portions 161A, 161B, 162A, 162B contract during ceramic firing. Therefore, here, considering the shrinkage at the time of firing, the clearance holes 133 and 134 that are about 1.18 times larger in diameter (350 μm to 250 μm) of the clearance holes 133 and 134 in the ceramic capacitor 101 are formed in the internal electrode portions 161A and 161B. , 162A, 162B.

  Then, at the portion corresponding to the electrode stacking portion 107, 100 green sheets 160 on which the internal electrode portions 161A, 161B, 162A, 162B are formed are stacked. In the present embodiment, the green sheet 160 on which the first internal electrode portion 161A of the pattern 1-A is formed, the green sheet 160 on which the second internal electrode portion 162A of the pattern 2-A is formed, and the first of the pattern 1-B. The green sheets 160 on which the first internal electrode portions 161B are formed and the green sheets 160 on which the second internal electrode portions 162B of the pattern 2-B are formed are stacked in order (see FIG. 7). In addition, at a portion corresponding to the cover layer portion 108 (front and back portions of the laminate), three green sheets 160 in which the internal electrode portions 161A, 161B, 162A, and 162B are not formed are laminated.

Next, each green sheet 160 is integrated by applying a pressing force of 300 kgf / cm ^{2 to} 1000 kgf / cm ^{2 in} the sheet stacking direction using a laminating apparatus under a temperature condition of 60 ° C. to 80 ° C. As a result, a green sheet laminate 165 (unfired ceramic laminate) as shown in FIG. 8 is formed (laminate preparation step). In addition, the thickness of the green sheet laminated body 165 is about 1 mm.

  Further, using a laser processing machine (not shown), vias 130 (through holes) having a diameter of about 120 μm that penetrate the green sheet laminate 165 in the laminating direction are regularly drilled. Thereafter, as shown in FIG. 9, each via 130 is press-filled with a paste for via conductor at a pressure of 2.0 MPa to 7.5 MPa using a paste press-fitting and filling device (not shown), and the unfired via conductor is filled. A portion 166 is formed (via formation step). The via conductor paste includes nickel powder as conductive particles and barium titanate powder as a common material.

  Next, the green sheet laminate 165 is set in a screen printing apparatus (not shown), a screen mask is arranged on the upper surface of the green sheet laminate 165, and the surface electrode paste is printed and applied by screen printing and dried. Let As a result, an unfired surface layer electrode portion 168 to be the main surface side power source surface electrode 111 and the main surface side ground surface layer electrode 112 is formed on the upper surface side of the green sheet laminate 165 (see FIG. 10). Similarly, a screen mask is disposed on the lower surface of the green sheet laminate 165, and the surface electrode paste is printed and applied by screen printing and dried. As a result, an unfired surface layer electrode portion 168 to be the back surface side power supply surface electrode 121 and the back surface side ground surface layer electrode 122 is patterned on the lower surface side of the green sheet laminate 165 (see FIG. 10). The surface electrode paste includes nickel powder as conductive particles, barium titanate powder as a common material, and the like.

  Then, for example, break grooves are formed in a lattice shape in the green sheet laminate 165 by laser processing. Thereafter, the green sheet laminate 165 is degreased at a temperature of 250 ° C. to 300 ° C. for 10 hours to 20 hours in the air, and further fired for a predetermined time at a temperature of 1280 ° C. in a reducing atmosphere containing water vapor (firing step). . As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104. Specifically, in this firing step, each internal electrode portion 161A, 161B, 162A, 162B, each green sheet 160, the unfired via conductor portion 166, and the unfired surface layer electrode portion 168 in the green sheet laminate 165 are fired. The internal electrode layers 141A, 141B, 142A, 142B, the ceramic dielectric layer 105, the via conductors 131, 132, and the surface layer electrodes 111, 112, 121, 122 are formed.

  Next, electroless plating (thickness 1 μm to 50 μm) is performed on each surface layer electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each surface electrode 111, 112, 121, 122. The product in this state is a multi-piece ceramic sintered body 104 (panel-shaped ceramic sintered body) in which a plurality of product regions to be the ceramic capacitor 101 are arranged vertically and horizontally along the plane direction. A plurality of ceramic capacitors 101 can be obtained at the same time by dividing the panel-shaped ceramic sintered body 104 along the break grooves.

  For the ceramic capacitor 101 (Example 1) manufactured by the above manufacturing method, the present inventors have formed formation patterns 1-A, 2- of the internal electrode portions 161A, 161B, 162A, 162B in the multilayer body preparation step. Example 2 to Example as shown in Table 1 and Table 2 by changing the lamination method of A, 1-B, 2-B and each pattern 1-A, 2-A, 1-B, 2-B, etc. 8 and the conventional multilayer ceramic capacitor 101 were produced. And the curvature amount in the multilayer ceramic capacitor 101 of Examples 1 to 8 and the conventional example was measured. The results are shown in Table 3.

  In addition, the clearance hole diameter in Table 1 shows a numerical value in the ceramic capacitor 101 after ceramic firing. Table 3 shows that in the multilayer ceramic capacitor 101, the average diameter CH1 (average diameter) of the clearance holes 133 and 134 in the upper layer and the lower layer, and the average diameter of the clearance holes 133 and 134 in the outer peripheral portion and the central portion. CH2 (average diameter) is shown. Here, the upper layer in the multilayer ceramic capacitor 101 is a half portion from the top in the stacking direction (50 layers from the top in the electrode stacking portion 107), and the lower layer is a half portion from the bottom in the stacking direction (electrode stacking). 50 layers from the bottom in the portion 107). With respect to all the clearance holes 133 and 134 formed in the internal electrode portions 161A, 161B, 162A, and 162B in the upper layer and the lower layer, average values of the diameters of the upper layer and the lower layer are obtained. In the multilayer ceramic capacitor 101, 20 × 20 = 400 via conductors 131 and 132 are formed. Accordingly, the number of via conductors 131 and 132 in the outer peripheral portion is 76, and the number of via conductors 131 and 132 in the central portion (inside) is 324. Then, the average value of the diameters of all the clearance holes 133 and 134 formed around the peripheral via conductors 131 and 132, and all the clearance holes 133 formed around the central via conductors 131 and 132, respectively. The average value of 134 diameters was determined, and the average value is shown in Table 3.

The amount of warpage was measured by the following method. Specifically, as shown in FIG. 11, the height of each of 25 measurement points P1 set at a pitch of 2.25 mm on the capacitor main surface 102 of the multilayer ceramic capacitor 101 is measured with a laser. . Each measurement point P1 is set at a position other than the region where the clearance holes 133 and 134 are formed. Then, the least square plane was calculated from the measured height, and the height from the lowest position to the highest position on the plane was calculated as the amount of warpage. In each of Examples 1 to 8 and the conventional example, measurement was performed on 100 ceramic capacitors 101, and the average value was obtained as the amount of warpage.

  As shown in Tables 1 and 2, in the green sheet laminate 165 of Example 1, the first internal electrode parts 161A and 161B each have a clearance hole 133 having a large diameter (outer peripheral part 350 μm, central part 300 μm). The first internal electrode portions 161A of the pattern 1-A and the first internal electrode portions 161B of the pattern 1-B having clearance holes 133 having a small diameter (an outer peripheral portion of 300 μm and a central portion of 250 μm) are alternately arranged. Further, for each of the second internal electrode portions 162A and 162B, the second internal electrode portion 162A of the pattern 2-A having a clearance hole 134 having a large diameter (outer peripheral portion 350 μm, central portion 300 μm), and a clearance hole 134 having a small diameter ( The second internal electrode portions 162B of the pattern 2-B having an outer peripheral portion of 300 μm and a central portion of 250 μm are alternately arranged. In addition, in the lamination | stacking order of all the internal electrode parts which combined the 1st internal electrode part and the 2nd internal electrode part, it is repeatedly laminated | stacked in order of 161A / 162A / 161B / 162B. In the green sheet laminate 165 of Example 1, the first internal electrode portion 161A of pattern 1-A, the first internal electrode portion 161B of pattern 1-B, the second internal electrode portion 162A of pattern 2-A, and the pattern 2 25 layers are arranged for each pattern of the -B second internal electrode portion 162B.

  In the green sheet laminate 165 of Example 2, all the clearance holes 134 in the second internal electrode part 162A of the pattern 2-A and the second internal electrode part 162B of the pattern 2-B are 300 μm in comparison with the example 1. The diameter has been changed. That is, clearance holes 133 having different diameters are provided in the first internal electrode portions 161A and 161B.

  In the green sheet laminate 165 of Example 3, the internal electrode portions 161A and 162A of the patterns 1-A and 2-A having the clearance holes 133 and 134 having a large diameter are arranged in the upper layer 165A, and the clearance hole 133 having a small diameter is formed. , 134 and the internal electrode portions 161B, 162B of the patterns 1-B, 2-B are arranged in the lower layer 165B (see FIG. 12). In addition, clearance holes 133 and 134 having the same diameter as in the first embodiment are formed in the internal electrode portions 161A, 161B, 162A, and 162B of the patterns 1-A, 1-B, 2-A, and 2-B, respectively. ing.

  In the green sheet laminate 165 of Example 4, the diameters of the clearance holes 133 and 134 provided in the central portions of the patterns 1-A, 1-B, 2-A, and 2-B are compared with those of Example 1. It is made equal to the diameter of the clearance holes 133 and 134 in the outer peripheral portion. That is, in each of the internal electrode portions 161A and 162A of the patterns 1-A and 2-A, clearance holes 133 and 134 (see FIGS. 13 and 14) having a diameter of 350 μm are formed, and the patterns 1-B and 2-B. Each internal electrode portion 161B, 162B has a clearance hole (see FIGS. 15 and 16) having a diameter of 300 μm. In this case, as in the green sheet laminate 165 of Example 1, the internal electrode portions 161A, 162A, 161B, 162B of the patterns 1-A, 2-A and the patterns 1-B, 2-B are alternately arranged. Are arranged in layers.

  In the green sheet laminate 165 of Examples 5 to 8, the clearance holes 133, formed in the internal electrode portions 161A, 161B, 162A, 162B of the patterns 1-A, 1-B, 2-A, 2-B. 134 (see FIGS. 13 to 16) is the same as in the case of the fourth embodiment, but the lamination method of the patterns 1-A, 1-B, 2-A, and 2-B is the same as that in the fourth embodiment. Is different.

  Specifically, in the case of Example 5, in the upper layer 165A of the green sheet laminate 165, the internal electrode portions 161A and 162A (see FIGS. 13 and 14) of the patterns 1-A and 2-A are 40 layers from the top. The internal electrode portions 161B and 162B (see FIGS. 15 and 16) of the patterns 1-B and 2-B are stacked and arranged for 10 layers from the bottom. Similarly, in the lower layer 165B of the green sheet laminate 165, the internal electrode portions 161A and 162A of the patterns 1-A and 2-A are stacked and disposed for 40 layers from the top, and the patterns 1-B and 2-B are also arranged. The internal electrode portions 161B and 162B are stacked and arranged for 10 layers from the bottom.

  In the case of Example 6, in the upper layer 165A of the green sheet laminate 165, the internal electrode portions 161A and 162A (see FIGS. 13 and 14) of the patterns 1-A and 2-A are stacked by 25 layers from the top. At the same time, the internal electrode portions 162B and 161B (see FIGS. 15 and 16) of the patterns 2-B and 1-B are stacked and arranged for 25 layers from the bottom. Similarly, in the lower layer 165B of the green sheet laminated body 165, the internal electrode portions 161A and 162A of the patterns 1-A and 2-A are stacked and disposed for 25 layers from the top, and the patterns 2-B and 1-B are arranged. The internal electrode portions 162B and 161B are stacked and arranged for 25 layers from the bottom.

  In the case of Example 7, in the upper layer 165A of the green sheet laminate 165, the internal electrode portions 161A and 162A (see FIGS. 13 and 14) of the patterns 1-A and 2-A are laminated and the lower layer In 165B, the internal electrode portions 161B and 162B (see FIGS. 15 and 16) of the patterns 1-B and 2-B are stacked.

  In the case of Example 8, in the upper layer 165A of the green sheet laminate 165, the internal electrode portions 161B and 162B (see FIGS. 15 and 16) of the patterns 1-B and 2-B are stacked and the lower layer In 165B, the internal electrode portions 161A and 162A (see FIGS. 13 and 14) of the patterns 1-A and 2-A are stacked.

  In the conventional example, clearance holes 133 and 134 having the same diameter (300 μm) are formed in the first internal electrode portions 161A and 161B and the second internal electrode portions 162A and 162B.

  In the first to eighth embodiments, the internal electrode portions 161A, 161B, 162A, and 162B are patterned so that clearance holes 133 and 134 having different diameters are arranged in the stacking direction. The amount of warpage was smaller compared to the case where the diameters were uniform. In particular, in Examples 1, 2, and 4 in which the patterns 1-A and 2-A and the patterns 1-B and 2-B are alternately and regularly arranged, the amount of warpage can be reduced.

  In the case of Examples 1, 2, 4, 5, and 6 in which the diameters of the clearance holes 133 and 134 are not biased in the upper layer 165A and the lower layer 165B of the green sheet laminate 165 (the average diameter is the same). The amount of warpage was smaller than in other Examples 3, 7, and 8 in which the diameters of the clearance holes 133 and 134 were biased.

  Further, when the diameters of the clearance holes 133 and 134 in the outer peripheral portion were made larger than the diameters of the clearance holes 133 and 134 in the central portion, the amount of warpage could be suppressed low. Specifically, when comparing Example 1 and Example 4, the ceramic capacitor 101 of Example 1 is formed such that the clearance holes 133 and 134 in the outer peripheral portion are larger in diameter than the clearance holes 133 and 134 in the central portion. As a result, the amount of warpage could be kept lower than that in Example 4.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the laminate preparation process of the present embodiment, since the two types of clearance holes 133 and 134 having different diameters are formed so as to be arranged in the stacking direction, the positions of the end portions are different in the stacking direction. In this state, the clearance holes 133 and 134 are formed. For this reason, compared with the case where the positions of the end portions of the clearance holes 133, 134 are aligned in the stacking direction as in the conventional example, the internal electrode portions 161A, 161B, The number of layers where 162A and 162B overlap changes stepwise. Therefore, when the green sheet laminate 165 is pressed, a sudden change in density difference near the end portions of the clearance holes 133 and 134 is alleviated. As a result, when the green sheet laminate 165 is fired, the difference in shrinkage behavior according to the density is reduced, and the warpage of the multilayer ceramic capacitor 101 can be reduced.

  (2) In the green sheet laminate 165 of Examples 1, 2, 4, 5, and 6, the clearance holes 133 of the internal electrode portions 161A, 161B, 162A, and 162B are formed in the upper layer 165A and the lower layer 165B in the stacking direction. , 134 are equal in average value. In this way, since the clearance holes 133 and 134 having different diameters are arranged without deviation in the stacking direction, it is difficult for the density difference to occur in the stacking direction, and the warpage of the multilayer ceramic capacitor 101 can be reduced.

  (3) In the green sheet laminates 165 of Examples 1 to 4 and 6 to 8, the clearance holes 133 and 134 having different diameters in the internal electrode portions 161A, 161B, 162A, and 162B have the same number of layers in the lamination direction. It is formed to become. By doing so, the change in the number of layers where the internal electrodes overlap at the end of the clearance hole becomes gentle, so that a sudden change in the density difference near the end is alleviated. Therefore, the difference in shrinkage behavior according to the density during firing is reduced, and the warpage of the multilayer ceramic capacitor 101 can be reduced.

  (4) In the green sheet laminate 165 of Examples 1, 2, and 4, the clearance holes 133 and 134 having different diameters are formed in the internal electrode portions 161A, 161B, 162A, and 162B so as to be regularly repeated in the lamination direction. doing. In this way, since the clearance holes 133 and 134 having different diameters are arranged without deviation in the stacking direction, it is difficult for the density difference to occur in the stacking direction, and the warpage of the multilayer ceramic capacitor 101 can be reduced.

  (5) In the green sheet laminated body 165 of Examples 1 to 3, the diameters of the clearance holes 133 and 134 provided in the outer peripheral portion are formed larger than the diameters of the clearance holes 133 and 134 provided in the central portion. In the green sheet laminated body 165, the internal electrode portions 161A, 161B, 162A, 162B are not provided at the outer peripheral end portions of the respective green sheets 160, and the green sheet stack 165 is formed only of a ceramic material (see FIG. 10 and the like). For this reason, in the vicinity of the outer peripheral ends of the internal electrode portions 161A, 161B, 162A, and 162B, the ratio of the ceramic material and the conductor material changes abruptly. Accordingly, as in the first to third embodiments, by increasing the diameter of the clearance holes 133 and 134 in the outer peripheral portion rather than the central portion, in the multilayer ceramic capacitor 101, the ceramic dielectric is gradually increased from the central portion toward the outer peripheral portion. The proportion of layer 105 increases. For this reason, in the vicinity of the end portions of the internal electrode layers 141A, 141B, 142A, 142B, the difference in abrupt contraction behavior depending on the presence or absence of the electrode layers 141A, 141B, 142A, 142B between the ceramic dielectric layers 105 is alleviated. The warpage of the multilayer ceramic capacitor 101 can be reduced.

  (6) In the multilayer ceramic capacitor 101 of the present embodiment, the amount of warpage can be kept low, so that the connection reliability of the multilayer ceramic capacitor 101 when the wiring board is built-in can be sufficiently ensured. Further, when a DC voltage is applied to the multilayer ceramic capacitor 101, the ceramic dielectric layers 105 expand and contract due to electrostriction. At this time, since the positions of the end portions of the clearance holes 133 and 134 are different in the stacking direction, the stress in the vicinity of the end portions of the clearance holes 133 and 134 that are boundaries without displacement is dispersed. Therefore, cracks and delamination are less likely to occur when a DC voltage is applied, and the product reliability of the multilayer ceramic capacitor 101 can be improved.

  (7) In the multilayer ceramic capacitor 101 of the present embodiment, a copper plating layer is applied to the surface of each surface layer electrode 111, 112, 121, 122. If it does in this way, the ceramic of the common base material contained in the metallized conductor of each surface layer electrode 111,112,121,122 will not be exposed to the electrode surface. As a result, the wettability of the surface layer electrodes 111, 112, 121, 122 can be improved, and the connection reliability of the multilayer ceramic capacitor 101 can be sufficiently ensured.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiment, the internal electrode portions 161A, 161B, 162A, 162B are patterned so that two types of clearance holes 133, 134 having different diameters are arranged in the stacking direction. A pattern may be formed so that the above clearance holes are arranged in the stacking direction. For example, when the internal electrode portions of the three types of patterns A, B, and C having different diameters of the clearance holes 133 and 134 are stacked, they are regularly (A, B, C,... A, B, The green electrode laminate 165 is formed by stacking and arranging the internal electrode portions so as to repeat in the order of C). In this way, since the clearance holes 133 and 134 having different diameters are arranged without deviation in the stacking direction, it is difficult for the density difference to occur in the stacking direction, and the warpage of the multilayer ceramic capacitor 101 can be reduced.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiments described above are listed below.

  (1) It has a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via ceramic dielectric layers, and extends in the stacking direction of the ceramic dielectric layers and the internal electrode layers. A first via electrode connected to the plurality of first internal electrode layers and a second via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers are arranged in an array as a whole, A first clearance hole is provided in the plurality of first internal electrode layers, and the first clearance electrode is electrically insulated from the first internal electrode layer and the second via electrode, and the plurality of first internal electrode layers are electrically insulated from each other. A multilayer ceramic capacitor in which a second clearance hole is provided in the two internal electrode layers, and the second internal electrode layer and the first via electrode are electrically insulated by the second clearance hole; The capacitor has a rectangular shape including sides with a length of 8 mm or more and a warp amount of 30 μm or less, and at least one of the first internal electrode layer and the second internal electrode layer has two or more different diameters. The multilayer ceramic capacitor is characterized in that the clearance holes are arranged in the stacking direction.

DESCRIPTION OF SYMBOLS 101 ... Multilayer ceramic capacitor 105 ... Ceramic dielectric layer 130 ... Via as a through hole 131 ... Via conductor in capacitor for power supply as first via electrode 132 ... Via conductor in capacitor for ground as second via electrode 133 ... First Clearance hole 134 ... second clearance hole 141A, 141B ... internal electrode layer for power supply as first internal electrode layer 142A, 142B ... internal electrode layer for ground as second internal electrode layer 160 ... unfired as unfired ceramic part Ceramic green sheets 161A, 161B... First internal electrode portions as unfired conductor portions 162A, 162B... Second internal electrode portions as unfired conductor portions 165... Green sheet laminate as unfired ceramic laminate 165A. 165B ... Lower layer 166 ... Unfired via guide Part

Claims (11)

The first internal electrode layer and the second internal electrode layer are alternately stacked via a ceramic dielectric layer, and extend in the stacking direction of the ceramic dielectric layer and the internal electrode layer. A first via electrode connected to the first internal electrode layer and a second via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers are arranged in an array as a whole, and A first clearance hole is provided in the first internal electrode layer, and the first internal electrode layer and the second via electrode are electrically insulated by the first clearance hole, and the plurality of second internal electrodes A method of manufacturing a multilayer ceramic capacitor in which a second clearance hole is provided in a layer, and the second internal electrode layer and the first via electrode are electrically insulated by the second clearance hole,
The unfired conductor part to be the first internal electrode layer and the second internal electrode layer and the unfired ceramic part to be the ceramic dielectric layer are laminated and pressed in the laminating direction to A laminate preparation step of preparing an unfired ceramic laminate integrated with the unfired ceramic part;
Forming a through hole penetrating the unfired ceramic laminate in the laminating direction and forming an unfired via conductor portion serving as the first via electrode and the second via electrode in the through hole; and
Sintering the unfired ceramic laminate to form the ceramic dielectric layer, the internal electrode layer, and the via electrode,
In the laminate preparation step, two or more types of clearance holes having different diameters are arranged in the stacking direction for the unfired conductor portion serving as at least one of the first internal electrode layer and the second internal electrode layer. While forming the pattern to be installed ,
The method for manufacturing a multilayer ceramic capacitor , wherein an average value of the diameters of the clearance holes is made equal in an upper layer and a lower layer in the stacking direction of the green ceramic multilayer body . In the laminated body preparing step, clearance holes having different diameters are formed in the unfired conductor portions to be the first internal electrode layer and the second internal electrode layer so as to have the same number of layers in the laminating direction. The method for producing a multilayer ceramic capacitor according to claim 1 , wherein: In the laminated body preparing step, clearance holes having different diameters are formed so as to regularly repeat in the laminating direction in the unfired conductor portions to be the first internal electrode layer and the second internal electrode layer. The method for producing a multilayer ceramic capacitor according to claim 1 or 2 . In the laminate preparation step, the diameter of the clearance hole provided in the outer peripheral portion of the unfired conductor portion serving as the first internal electrode layer and the second internal electrode layer is greater than the diameter of the clearance hole provided in the central portion. method of manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, characterized in that also the larger.   The first internal electrode layer and the second internal electrode layer are alternately stacked via a ceramic dielectric layer, and extend in the stacking direction of the ceramic dielectric layer and the internal electrode layer. A first via electrode connected to the first internal electrode layer and a second via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers are arranged in an array as a whole, and A first clearance hole is provided in the first internal electrode layer, and the first internal electrode layer and the second via electrode are electrically insulated by the first clearance hole, and the plurality of second internal electrodes A method of manufacturing a multilayer ceramic capacitor in which a second clearance hole is provided in a layer, and the second internal electrode layer and the first via electrode are electrically insulated by the second clearance hole,
  The unfired conductor part to be the first internal electrode layer and the second internal electrode layer and the unfired ceramic part to be the ceramic dielectric layer are laminated and pressed in the laminating direction to A laminate preparation step of preparing an unfired ceramic laminate integrated with the unfired ceramic part;
  Forming a through hole penetrating the unfired ceramic laminate in the laminating direction and forming an unfired via conductor portion serving as the first via electrode and the second via electrode in the through hole; and
  A firing step of sintering the green ceramic laminate to form the ceramic dielectric layer, the internal electrode layer, and the via electrode;
Including
  In the laminate preparation step, two or more types of clearance holes having different diameters are arranged in the stacking direction for the unfired conductor portion serving as at least one of the first internal electrode layer and the second internal electrode layer. While forming the pattern to be installed,
  In the unsintered conductor portions to be the first internal electrode layer and the second internal electrode layer, clearance holes having different diameters are formed to repeat regularly in the stacking direction.
A method for producing a monolithic ceramic capacitor.   In the laminated body preparing step, clearance holes having different diameters are formed in the unfired conductor portions to be the first internal electrode layer and the second internal electrode layer so as to have the same number of layers in the laminating direction. The method for producing a multilayer ceramic capacitor according to claim 5, wherein:   In the laminate preparation step, the diameter of the clearance hole provided in the outer peripheral portion of the unfired conductor portion serving as the first internal electrode layer and the second internal electrode layer is greater than the diameter of the clearance hole provided in the central portion. The method for manufacturing a multilayer ceramic capacitor according to claim 5, wherein the multilayer ceramic capacitor is formed in a large size.   The first internal electrode layer and the second internal electrode layer are alternately stacked via a ceramic dielectric layer, and extend in the stacking direction of the ceramic dielectric layer and the internal electrode layer. A first via electrode connected to the first internal electrode layer and a second via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers are arranged in an array as a whole, and A first clearance hole is provided in the first internal electrode layer, and the first internal electrode layer and the second via electrode are electrically insulated by the first clearance hole, and the plurality of second internal electrodes A method of manufacturing a multilayer ceramic capacitor in which a second clearance hole is provided in a layer, and the second internal electrode layer and the first via electrode are electrically insulated by the second clearance hole,
  The unfired conductor part to be the first internal electrode layer and the second internal electrode layer and the unfired ceramic part to be the ceramic dielectric layer are laminated and pressed in the laminating direction to A laminate preparation step of preparing an unfired ceramic laminate integrated with the unfired ceramic part;
  Forming a through hole penetrating the unfired ceramic laminate in the laminating direction and forming an unfired via conductor portion serving as the first via electrode and the second via electrode in the through hole; and
  A firing step of sintering the green ceramic laminate to form the ceramic dielectric layer, the internal electrode layer, and the via electrode;
Including
  In the laminate preparation step, two or more types of clearance holes having different diameters are arranged in the stacking direction for the unfired conductor portion serving as at least one of the first internal electrode layer and the second internal electrode layer. While forming the pattern to be installed,
  In the unfired conductor portion that becomes the first internal electrode layer and the second internal electrode layer, the diameter of the clearance hole provided in the outer peripheral portion is formed larger than the diameter of the clearance hole provided in the central portion.
A method for producing a monolithic ceramic capacitor.   In the laminated body preparing step, clearance holes having different diameters are formed in the unfired conductor portions to be the first internal electrode layer and the second internal electrode layer so as to have the same number of layers in the laminating direction. The method for producing a multilayer ceramic capacitor according to claim 8. The first internal electrode layer and the second internal electrode layer are alternately stacked via a ceramic dielectric layer, and extend in the stacking direction of the ceramic dielectric layer and the internal electrode layer. A first via electrode connected to the first internal electrode layer and a second via electrode extending in the stacking direction and connected to the plurality of second internal electrode layers are arranged in an array as a whole, and A first clearance hole is provided in the first internal electrode layer, and the first internal electrode layer and the second via electrode are electrically insulated by the first clearance hole, and the plurality of second internal electrodes A multilayer ceramic capacitor in which a second clearance hole is provided in the layer, and the second internal electrode layer and the first via electrode are electrically insulated by the second clearance hole;
Wherein the first inner electrode layer and at least one of the inner electrode layer of the second inner electrode layer, two or more of said clearance holes with different diameters are arranged in the stacking direction Rutotomoni,
The average value of the diameter of the clearance hole is made equal in the upper layer and the lower layer in the stacking direction.
A multilayer ceramic capacitor characterized by that.   11. The multilayer ceramic capacitor according to claim 10, wherein clearance holes having different diameters are regularly formed in the stacking direction in the first internal electrode layer and the second internal electrode layer.

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