JP5879852B2 - Circuit device and electronic device - Google Patents

Description

  The present invention relates to a circuit device, an electronic device, and the like.

  In recent years, contactless power transmission (non-contact power transmission) that uses electromagnetic induction and enables power transmission even without a contact of a metal part has been in the spotlight. As an application example of this contactless power transmission, a non-contact IC card or the like that can receive power and transmit / receive information by simply holding it over a terminal device has been proposed. According to this non-contact IC card, it is possible to realize a card having functions such as electronic money, a public transportation prepaid card, and an ID card for entrance / exit management.

  As a conventional technique of a charging circuit for a secondary battery in such a non-contact IC card, there is a technique disclosed in Patent Document 1, for example. The charging circuit of Patent Document 1 has a circuit configuration in which the secondary battery is charged with a constant current having a constant current value, and the charging is finished after confirming that the charging voltage has reached a specified voltage.

  However, in a conventional charging circuit, a charge storage unit with a slightly larger capacity is provided without accurately knowing how much charge is required for the operation of the IC card after charging, and the charging voltage is a specified voltage. The method of charging until it reached was adopted. For this reason, there is a problem that a mounting space is wasted in mounting a charge storage unit having a large capacity. Further, conventionally, since a method for optimally controlling the charging current according to the charging voltage is not employed, there is a problem that power storage in the charge storage unit is wasted and charging efficiency is low.

  Further, in the non-contact IC card, the power reception time from the charger is extremely short. Therefore, when the charge storage unit is charged with the power received in this extremely short power reception time, if the charging efficiency is low, sufficient charge cannot be stored in the charge storage unit. For this reason, for example, when an EPD (Electrophoretic Display), which is an electrophoretic display, is provided as a display device for displaying the usage amount, balance, etc. for an IC card, this EPD display rewriting process cannot be completed. Such a problem also occurs.

JP 2006-323683 A

  According to some aspects of the present invention, it is possible to provide a circuit device, an electronic device, and the like that enable efficient charging of a charge storage unit in a device using electromagnetic induction.

  One embodiment of the present invention controls a current control unit that receives power from a power receiving unit that receives power by electromagnetic induction and controls a flow of a variable charging current to a charge storage unit, and the current control unit. A control unit that controls the charging current, and the control unit relates to a circuit device that performs control to reduce the charging current as a charging voltage of the charge storage unit increases.

  In one embodiment of the present invention, control is performed to charge a charge storage unit by supplying a variable charging current with power from a power receiving unit that receives power by electromagnetic induction. In this case, the charging current is controlled so that the charging current decreases as the charging voltage of the charge storage unit increases. In this way, in a system that receives power by electromagnetic induction, when there is a characteristic that the current that can be extracted becomes low when the voltage is high, the characteristics of the charging voltage and the charging current are matched with this characteristic. Is possible. Therefore, efficient charging of the charge storage unit can be realized in a device using electromagnetic induction.

  In one aspect of the present invention, the control unit may control the charging current based on operation lower limit voltage information of a power supply destination device.

  In this way, it is possible to realize charge control that can ensure the operation lower limit voltage of the power supply destination device, and it is possible to prevent malfunction of the power supply destination device.

  In the aspect of the invention, the control unit may control the charging current based on the operation lower limit voltage information and power usage information of the power supply destination device.

  In this way, it is possible to achieve charge control that accumulates necessary and sufficient charges in accordance with the power usage information of the power supply destination device in the charge storage unit, preventing situations such as unnecessary storage of electricity. it can.

  In the aspect of the invention, the control unit may perform control so that the charge current flows through the charge accumulation unit until the accumulated charge amount of the charge accumulation unit reaches at least a target charge amount.

  In this way, it is possible to prevent a situation in which unnecessary charges exceeding the target charge amount are accumulated in the charge accumulation unit, and thus it is possible to prevent a situation in which unnecessary power storage is performed.

  In the aspect of the invention, the control unit may set the target charge amount based on operation lower limit voltage information of a power supply destination device.

  In this way, it is possible to control the charge by setting the target charge amount according to the operation lower limit voltage of the power supply destination device, so it is not necessary to secure the operation lower limit voltage of the power supply destination device. It is possible to prevent a situation in which a simple power storage is performed.

  In the aspect of the invention, the control unit may set the target charge amount based on the operation lower limit voltage information and power usage information of the power supply destination device.

  In this way, it is possible to prevent a situation where wasteful power storage is performed while accumulating necessary and sufficient charges in accordance with the power usage information in the charge storage unit.

  In the aspect of the invention, the control unit may measure voltage information that specifies a charging voltage of the charge storage unit, and may control the charging current based on the measured voltage information.

  In this way, charge control can be performed by measuring and grasping the amount of charge that has already been stored, so that the charge storage unit can be efficiently charged.

  In one aspect of the present invention, the control unit obtains an accumulated charge amount of the charge accumulation unit based on the measured voltage information, and is necessary for operating the accumulated charge amount and a power supply destination device. The target charge amount may be obtained based on the total charge amount, and the charge current may be controlled to flow through the charge accumulation unit until the accumulated charge amount of the charge accumulation unit reaches at least the target charge amount. .

  In this way, the accumulated charge amount is obtained from the measured voltage information, the target charge amount is obtained based on the accumulated charge amount and the total charge amount, and the charge accumulation unit is charged until the target charge amount is reached. Control becomes possible. Therefore, more accurate and efficient charge control can be realized.

  In one aspect of the present invention, the control unit is necessary to operate the power supply destination device based on the operation lower limit voltage information of the power supply destination device and the power usage information of the power supply destination device. The total charge amount may be set.

  In this way, it is possible to realize charge control for accumulating necessary and sufficient charges in the charge accumulating unit according to the power usage information while ensuring the operation lower limit voltage of the power supply destination device.

  In one aspect of the present invention, the control unit measures the storage capacity of the charge storage unit by performing a control to flow a capacitance measurement current to the charge storage unit, and the measured storage capacity, The total charge amount may be set based on the operation lower limit voltage information and the power usage information.

  In this way, it is possible to cope with the case where the storage capacity is not known.

  According to another aspect of the present invention, the first control unit includes the current control unit, receives electric power from the power reception unit, and performs control for accumulating charges in the first charge accumulation unit that is the charge accumulation unit. Storage control unit, a second storage control unit that receives electric power from the power receiving unit, and performs control to store charges in the second charge storage unit, the first charge storage unit, the first charge storage unit, A power supply unit that supplies power to the system device based on the charge accumulated in the second charge accumulation unit, wherein the second charge accumulation unit is more charged than the first charge accumulation unit. A charge storage unit for starting the system having a small storage capacity, and the power supply unit supplies a power source based on the stored charge of the second charge storage unit at the time of system startup after power reception by the power receiving unit. You may supply with respect to a device.

  In this way, even when the storage capacity of the first charge storage unit is large, power based on the stored charge of the second charge storage unit for system startup can be supplied to the system device at an early stage. Become. Therefore, it is possible to provide a circuit device or the like that enables the system to be activated in a short power reception period in a device using electromagnetic induction.

  In the aspect of the invention, the power supply unit supplies power to the system device based on the accumulated charge of the first charge accumulation unit in a period after the end of power reception by the power reception unit. Also good.

  In this way, in the period after the end of the power reception by the power receiving unit, the power based on the accumulated charge of the first charge accumulation unit having a large accumulation capacity can be supplied to the system device.

  In one aspect of the present invention, the system device performs display control processing of an electrophoretic display unit that displays an image, and the first accumulation control unit performs at least one display rewrite of the electrophoretic display unit. Control for accumulating necessary electric charge in the first electric charge accumulating unit may be performed.

  Thus, if the amount of charge stored in the first charge storage unit is limited to the charge required for at least one display rewrite of the electrophoretic display unit, the storage capacity of the first charge storage unit is reduced. You don't have to make it big. As a result, charge accumulation in the first charge accumulation unit can be completed in a short time, and it is possible to cope with a case where a short power reception period is required.

  In the aspect of the invention, the power supply unit is provided between the first storage node and the connection node of the first charge storage unit, and travels from the first storage node to the connection node. A first diode whose direction is a forward direction and a direction from the second storage node to the connection node provided between the second storage node and the connection node of the second charge storage unit; The power supply unit may supply power to the system device based on a voltage of the connection node.

  In this way, the rectifying function of the first and second diodes can be effectively used to supply the power supply voltage based on the accumulated charges of the first and second charge accumulation units to the system device. . In addition, if the first and second diodes are used in this way, a control signal for switching operation can be made unnecessary, so even if it is difficult to generate such a control signal before starting the system, It becomes possible to respond.

  Another aspect of the invention relates to an electronic device including any one of the circuit devices described above.

1 is a basic configuration example of a circuit device according to an embodiment. 1 is a configuration example of an electronic apparatus to which a circuit device according to an embodiment is applied. Application example to a non-contact IC card which is one of electronic devices. FIGS. 4A and 4B are explanatory diagrams of problems relating to charging of a charge storage unit in a device using electromagnetic induction. FIG. 5A and FIG. 5B are explanatory diagrams of the charging method of this embodiment. 6A to 6C are detailed examples of the charging method of the present embodiment. The operation | movement flowchart of the detailed example of the charging method of this embodiment. FIG. 8A is an explanatory diagram of the method of the comparative example, and FIG. 8B is an explanatory diagram of the method of the present embodiment. FIG. 9A and FIG. 9B are explanatory diagrams of the method of this embodiment. 3 is a detailed configuration example of a circuit device according to the present embodiment. FIG. 11A and FIG. 11B are operation explanatory views of a detailed configuration example of the present embodiment. The detailed structural example of a current control part. A configuration example of a system device. 14A to 14C are explanatory diagrams of an electrophoretic display unit.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Basic Configuration of Circuit Device and Electronic Device FIG. 1 shows a basic configuration example of a circuit device according to this embodiment. This circuit device includes a current control unit 32 and a control unit 70. The configuration of the circuit device is not limited to the configuration of FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The power receiving unit 10 receives power from a power transmission device (partner device, terminal device, charger) by electromagnetic induction. For example, power is received by non-contact power transmission (non-contact power transmission) that enables power transmission even without a metal part contact.

  The current control unit 32 receives electric power from the power receiving unit 10 that receives electric power by electromagnetic induction, and controls the charging current (ICH) to flow through the capacitor C (charge storage unit in a broad sense). That is, the capacitor C is charged by controlling the charging current having a variable current value to flow through the capacitor C.

  Specifically, current control unit 32 is provided between power input node NI from power reception unit 10 and current output node NCQ. Between the current output node NCQ of the current control unit 32 and the charge storage node NA of the capacitor C, a backflow prevention diode DI3 is provided. In addition, one end of a capacitor CC for stabilizing the potential is connected to the power input node NI.

  The control unit 70 controls the current control unit 32 to control the charging current. For example, the control unit 70 outputs a charging current control signal ICT to the current control unit 32 to control the magnitude (current value) of the charging current. Specifically, the control unit 70 measures the charging voltage (VCH) of the charge storage node NA, and sets the signal level of each bit of the n-bit control signal ICT based on the measurement result, whereby the current control unit 32 controls the magnitude of the charging current. The control unit 70 can be realized by a digital circuit for performing arithmetic processing, an analog circuit for measuring voltage information, or the like.

  In this embodiment, the control unit 70 performs control to decrease the charging current (ICH) as the charging voltage (VCH) of the capacitor C (charge storage unit in a broad sense) increases. For example, the control unit 70 controls the current control unit 32 so that the capacitor C is charged with a charging current having a large first current value at the start of charging. Then, when the charging voltage exceeds the first voltage value, the current control unit 32 is controlled so as to charge the capacitor C with a charging current having a second current value smaller than the first current value. Further, when the charging voltage exceeds a second voltage value that is larger than the first voltage value, the capacitor C is charged with a charging current having a third current value smaller than the second current value. The current controller 32 is controlled. As described above, the control unit 70 performs control to reduce the charging current of the capacitor C, for example, in a stepwise manner as the charging voltage of the capacitor C (voltage of the node NA) increases. Such control of the charging current can be realized by setting the charging current value by the n-bit control signal ICT output from the control unit 70 to the current control unit 32.

  In the present embodiment, the control unit 70 controls the charging current based on the operation lower limit voltage information of the power supply destination device. Here, the power supply destination device is a device to which power is supplied based on the accumulated charge of the capacitor C, and is, for example, a system device or a display unit (EPD) described later. The operation lower limit voltage information is information for specifying the operation lower limit voltage of the power supply destination device, and the operation lower limit voltage is a voltage for which the power supply destination device is guaranteed to perform a normal operation.

  Furthermore, the control unit 70 controls the charging current based on the operation lower limit voltage information and the power usage information (usage charge amount information) of the power supply destination device. In other words, the current control unit 32 is controlled using both the operation lower limit voltage information and the used power information to control the charging current.

  Here, the used power information (used charge amount information) is information for specifying the power (charge amount) used by a device that operates by being supplied with power based on the accumulated charge of the capacitor C. For example, when the power supply destination device performs a predetermined operation (for example, a display rewriting operation to be described later) based on the stored power of the capacitor C after the power reception is completed, the used power information includes the power (charge amount) necessary for the operation. It is information for specifying

  Further, in the present embodiment, the control unit 70 controls the charging current to flow through the capacitor C until the accumulated charge amount of the capacitor C reaches at least the target charge amount. For example, the current control unit 32 is controlled so that the charging current flows until the accumulated charge amount reaches at least the target charge amount. Here, the target charge amount is a charge amount that is an accumulation target of the accumulated charge amount of the capacitor C. In order to provide a margin, the current control unit 32 may be controlled so that the charging current flows through the capacitor C until the accumulated charge amount slightly exceeds the target charge amount.

  Further, the control unit 70 sets the target charge amount based on the operation lower limit voltage information of the power supply destination device. More specifically, the target charge amount is set based on the operation lower limit voltage information and the power usage information of the power supply destination device. For example, the target charge amount increases as the operation lower limit voltage increases. In addition, the target charge amount increases as the power consumption (use charge amount) of the power supply destination device increases.

  In addition, the control unit 70 measures voltage information that specifies the charging voltage of the capacitor C, and controls the charging current based on the measured voltage information.

  For example, as shown in FIG. 1, the control unit 70 includes an A / D conversion unit 72, a timer 74, and an arithmetic processing unit 76. The A / D converter 72 (voltage information acquisition unit) measures (acquires) the voltage information of the charging voltage by A / D converting the charging voltage (VCH) of the capacitor C. The arithmetic processing unit 76 performs arithmetic processing for determining the value of the charging current based on the measured voltage information and the time information set by the timer 74, and outputs a charging current control signal ICT to the current control unit 32. To do.

  More specifically, the control unit 70 (arithmetic processing unit 76) obtains the accumulated charge amount of the capacitor C (charge accumulation unit) based on the measured voltage information. Then, the target charge amount is obtained based on the obtained accumulated charge amount and the total charge amount necessary for operating the power supply destination device. Then, control is performed so that the charging current flows to the capacitor C until the accumulated charge amount of the capacitor C reaches at least the target charge amount. In this case, the control unit 70 sets (calculates) a total charge amount necessary for operating the power supply destination device based on the operation lower limit voltage information and the power usage information of the power supply destination device. Further, the control unit 70 controls the flow of the capacitance measurement current to the capacitor C, thereby measuring the storage capacity of the capacitor C, and based on the measured storage capacity, the operating lower limit voltage information, and the used power information. The total charge amount may be set (calculated). The arithmetic processing of these control units 70 will be described in detail with reference to FIGS.

  In FIG. 1, the voltage information specifying the charging voltage is the charging voltage itself of the charge storage node NA of the capacitor C, but the present embodiment is not limited to this. For example, the voltage information for specifying the charging voltage is sufficient as long as it can specify the magnitude of the charging voltage of the capacitor C. For example, the voltage information for the nodes NCQ and NI in FIG.

  In the circuit device of the present embodiment having the above configuration, control is performed such that the charging current is reduced as the charging voltage of the capacitor serving as the charge storage unit increases. As a result, as will be described in detail later, in a device that receives power using electromagnetic induction, it is possible to efficiently charge a capacitor that is a charge storage unit. Accordingly, it is possible to charge the capacitor with a necessary amount of charge in a short time, and it is possible to provide a circuit device that can perform charging suitable for a non-contact IC card or the like. In addition, a capacitor having a small storage capacity can be adopted as the capacitor, and space saving or the like can be achieved.

  Further, in the circuit device according to the present embodiment, the target charge amount to be stored in the capacitor is obtained based on the operation lower limit voltage information and power usage information of the power supply destination device, and the charging current is controlled. In addition, voltage information on the charging voltage of the capacitor is measured to control the charging current. Therefore, since the charge current can be controlled by accurately grasping the amount of charge to be stored, it is possible to efficiently store the necessary amount of charge in the capacitor in a short time. Thereby, waste of stored electric power can be prevented, and the capacitor can be reduced in capacity to save space.

  FIG. 2 shows a configuration example of an electronic apparatus to which the circuit device of this embodiment is applied. 2 includes a power receiving unit 10 that receives power by electromagnetic induction, a circuit device 90 according to the present embodiment, a system device 100, and a display unit 150 (such as an electrophoretic display unit). Here, the circuit device 90 includes a power management unit 20 and a control unit 70. Further, the electronic device can include a host I / F 18, a secondary coil L2 (a power receiving coil, a secondary inductor), a capacitor CB, capacitors C1, C2, and the like. The secondary coil L2 and the capacitor CB constitute a power receiving side resonance circuit.

  Note that the configuration of the electronic device is not limited to the configuration shown in FIG. 2, and various modifications such as omitting some of the components or adding other components are possible. Further, as an electronic device to which the present embodiment is applied, various devices such as an IC card, an electronic shelf label, and an IC tag can be assumed.

  The power receiving unit 10 receives power transmitted from the power transmission device 200 (terminal device, charger, counterpart device) by electromagnetic induction. Specifically, a primary coil L1 (power transmission coil, primary inductor) provided on the power transmission side and a secondary coil L2 provided on the power reception side are electromagnetically coupled to form a power transmission transformer. Thus, non-contact power transmission (contactless power transmission) is realized. The power receiving unit 10 converts the AC induced voltage of the secondary coil L2 into a DC voltage. This conversion can be realized by a rectifier circuit included in the power receiving unit 10 or the like.

  As the primary coil L1 and the secondary coil L2, for example, a planar coil can be adopted, but this embodiment is not limited to this, and the primary coil L1 and the secondary coil L2 are electromagnetically coupled to generate power. As long as it can transmit, the shape, structure, etc. are not limited.

  The host I / F (interface) 18 is an interface for host communication. By this interface, data communication between the power transmission device 200 and the power receiving unit 10 is realized. Data communication between the power transmission device 200 and the power receiving unit 10 may be realized using the primary coil L1 and the secondary coil L2 for electromagnetic induction, or may be realized by providing another coil for communication. May be.

  The power management unit 20 includes first and second accumulation control units 30 and 40 and a power supply unit 50, and the first accumulation control unit 30 includes the current control unit 32 of FIG. The power management unit 20 can be realized by an analog circuit or a digital circuit. Details of the first and second accumulation control units 30 and 40 and the power supply unit 50 will be described later.

  The control unit 70 controls the charging current, performs various controls of the circuit device 90 of the present embodiment, and performs communication control processing.

  The system device 100 is a device that executes processing as a system of an electronic device, and can be realized by, for example, a microcomputer. The system device 100 includes a host I / F 110 and a processing unit 120.

  The display unit 150 is for displaying various images. The processing unit 120 (processor) performs display control processing for the display unit 150. As the display unit 150, for example, an electrophoretic display unit (hereinafter, appropriately referred to as EPD) can be employed, and the processing unit 120 performs display control processing of the EPD. The processing unit 120 performs various control processes necessary for system operation.

  Examples of display information on the display unit 150 include information on received data by communication, sensor detection information (information such as pressure, temperature, humidity, etc.), unique information / personal information in a memory built in the IC card, and the like.

  The host I / F 110 is communicatively connected to the host I / F 18 on the power receiving unit 10 side via the control unit 70, for example. As a result, the system device 100 can perform data communication with the power transmission apparatus 200.

  FIG. 3 shows an application example when the electronic device is an IC card 190. The IC card 190 is provided with a display unit 150 realized by EPD or the like so that various types of information can be displayed. The IC card 190 has a power receiving unit 10, a circuit device 90 (IC), capacitors C1 and C2, which will be described later, and the like mounted therein.

  When the user holds the IC card 190 over the terminal device 202 (power transmission device), the IC card 190 operates by receiving power from the terminal device 202 by electromagnetic induction and performs data communication with the terminal device 202. Then, images such as numbers and characters corresponding to the communication result are displayed on the display unit 150. Taking electronic money or a prepaid card as an example, the amount used, balance, etc. are displayed on the display unit 150. Various types of information are also displayed on the display unit 210 of the terminal device 202.

2. Next, the charging method of this embodiment will be described in detail. FIG. 4A is a diagram illustrating the relationship between voltage and current in contactless power transmission. 4A is the output voltage of the power receiving unit 10 in FIG. 1, and II is the output current. This voltage VI is a voltage (DC voltage) obtained by rectifying the coil end voltage of the secondary coil L2 by, for example, a rectifier circuit included in the power receiving unit 10.

  As shown in FIG. 4A, in a system that receives power by electromagnetic induction, a high voltage VI can be secured if the current II is small. However, if a large current II is extracted, the voltage VI decreases. is there.

  On the other hand, an operating lower limit voltage is defined for the system device 100 of FIG. 2 which is one of the power supply destination devices. Here, the operation lower limit voltage is a voltage for which the system device 100 is guaranteed to perform a normal operation. For example, when the system device 100 is a microcomputer, the operation lower limit voltage is defined by the specification of the microcomputer. For example, when a power supply voltage lower than the operation lower limit voltage is supplied to the system device 100, there is a possibility that a malfunction such as a through current flows in a transistor constituting the system device 100 may occur. Therefore, when the power source based on the electric charge accumulated in the capacitor C in FIG. 1 (C1 in FIG. 2) is supplied to the system device 100, it is necessary that the supplied power source voltage does not fall below the lower limit operating voltage. .

  Therefore, in this embodiment, when the system device 100 or the like is operated with a power source based on the accumulated charge of the capacitor C (C1) after the power reception unit 10 has finished receiving power, the charging voltage of the capacitor C does not fall below the lower limit operating voltage. A method of charging the capacitor C with an amount of charge is employed.

  However, when such a method is employed, it has been found that if the capacity of the capacitor C for power storage is large, a situation where wasteful power storage is performed occurs.

  For example, in FIG. 4B, when the capacitance of the capacitor C is large, the charge amount QA1 is necessary to secure the charging voltage of the operation lower limit voltage. Then, if the charge amount QA2 necessary for the operation of the power supply destination device after receiving power is stored in the capacitor C, the charging voltage of the capacitor C can be ensured to be equal to or higher than the operation lower limit voltage during the operation period of the power supply destination device. it can. As a result, the power supply destination device can be operated safely based on the charge accumulated in the capacitor C during the operation period after the end of power reception.

  In FIG. 4B, when the capacitance of the capacitor C is small, the charge amount QB1 is necessary to secure the charge voltage of the operation lower limit voltage. Then, if the amount of charge QB2 necessary for the operation of the power supply destination device after receiving power is stored in the capacitor C, the power supply destination device can be safely operated based on the accumulated charge of the capacitor C during the operation period after the end of power reception. It becomes possible to operate.

  Here, as shown in FIG. 4B, the relationship of QA1> QB1 is established for the amount of charge for securing the operation lower limit voltage. Regarding the amount of charge necessary for the operation after receiving power, the relationship of QA2 = QB2 is established. The charge amounts QA1 and QB1 necessary for securing the operation lower limit voltage become surplus power that is not used during operation. Therefore, if this charge amount is large, the stored power is wasted. Therefore, in order to reduce such waste and increase the efficiency of power storage, it is desirable that the capacity of the capacitor C be as small as possible.

  On the other hand, as is clear from FIG. 4B, when the capacitance of the capacitor C is reduced, the charge voltage needs to be increased in order to store the charge amount QB2 necessary for the operation after power reception. That is, in order to reduce wasteful stored power and increase the efficiency of storage, it is desirable to reduce the capacity of the capacitor C and increase the charging voltage.

  However, in a system that receives power by electromagnetic induction, the relationship of FIG. 4A is established between the voltage VI and the current II. Therefore, when the capacity of the capacitor C is reduced, the charging voltage of the capacitor C cannot be increased, and there is a problem that it is difficult to store the charge amount QB2 necessary for the operation after receiving power in the capacitor C.

  In order to solve such a problem, in the present embodiment, as shown in FIG. 5A, a charging method is adopted in which the charging current is reduced as the charging voltage of the capacitor C increases. In other words, the charging current is increased as the charging voltage of the capacitor C is lower. Specifically, in the initial period when power reception by the power reception unit 10 is started, the charging voltage (VCH) of the capacitor C is also low, so that the current control unit 32 is charged greatly under the control of the control unit 70 in FIG. Control is performed so that a current (ICH) flows through the capacitor C.

  On the other hand, as the charging voltage of the capacitor C increases with time after the start of power reception, the charging current is reduced accordingly. That is, under the control of the control unit 70, the current control unit 32 performs control to flow a small charging current to the capacitor C.

  In this way, as shown in FIG. 5B, the voltage-current characteristic (VI-II characteristic) on the power receiving unit side (coil side) and the charging voltage-charge current characteristic (VCH-ICH characteristic) on the capacitor side. Can be matched. Therefore, as shown in FIG. 4B, the capacity of the capacitor C can be reduced, so that both the efficiency of power storage and the securing of the operation lower limit voltage can be achieved. Further, by reducing the capacitance of the capacitor C, it is possible to reduce the mounting space for the capacitors (C1, C2) of the IC card 190 of FIG. 3, which can contribute to downsizing of the device.

  Next, further detailed examples of the charging method of the present embodiment will be described with reference to FIGS. In FIG. 6A, QTL is the total charge amount required. QEP is a charge amount necessary for display on the display unit 150 (EPD) (a charge amount necessary for at least one display rewrite). This charge amount QEP corresponds to, for example, QA2 and QB2 in FIG. QBA is the amount of charge necessary to ensure the lower limit operating voltage. This charge amount QBA corresponds to QA1 and QB1 in FIG. QTG is a target charge amount to be stored in the capacitor C. QCH is a charge amount for an arbitrary time due to a variable current from the current control unit 32.

  As shown in FIG. 6A, the charge amount necessary for display is expressed as QEP = TEP × IEP. TEP represents the operating time of the power supply destination device (system device, display unit), and IEP represents the operating current. When the magnitude of the operating current IEP at each operation timing is different, the charge amount QEP is obtained by integrating IEP with the operating time.

  Further, the amount of charge necessary for securing the operation lower limit voltage is expressed as QBA = C × VOL. VOL is an operation lower limit voltage. Note that the name of the capacitor C and its capacitance are represented by the same symbol C.

  The total charge amount is expressed as QTL = QEP + QBA = TEP × IEP + C × VOL. That is, the total amount of charge required is the sum of the amount of charge QEP required for display and the amount of charge QBA required for securing the operating lower limit voltage.

  For example, as shown in FIG. 6B, when the target charge amount is QTG, QTL = QTG + C × V1, and therefore QTG = QTL−C × V1. V1 is the current charging voltage measured. Then, as shown in FIG. 6C, if the charge amount for an arbitrary time of the variable current from the current control unit 32 is QCH, the charge amount QCH is accumulated. Then, charging with a variable current is performed until the accumulated charge amount reaches the target charge amount QTG, and when the accumulated charge amount reaches the target charge amount QTG, the charging ends. In order to provide a margin, the charging operation may be continued until the accumulated charge amount slightly exceeds the target charge amount QTG.

  FIG. 7 is an operation flow of a detailed example of the charging method of this embodiment. First, the initial voltage V0 is measured (step S1). For example, there is a case where the charge due to the previous charge is accumulated in the capacitor C and remains, and the initial voltage V0 is measured by the A / D conversion unit 72 in FIG. Then, the capacitor C is charged with the current IM for capacitance measurement during the TM period (step S2). In other words, the current control unit 32 charges the capacitor C by performing a control to flow the capacitance measurement current IM through the capacitor C during the period TM. The period TM in this case is set by the timer 74 in FIG.

  Next, the charging voltage VCH = V1 is measured (step S3). That is, the A / D converter 72 measures the charging voltage VCH = V1 by the capacity measurement current IM. Then, the capacity C = (IM × TM) / (V1−V0) is obtained based on the initial voltage V0, the charging voltage VCH = V1, and the like (step S4). That is, when the capacity C is not known, the capacity C is obtained by effectively utilizing the hardware of the current control unit 32.

  Next, the total charge amount QTL is calculated (step S5). As described with reference to FIG. 6A, the total charge amount can be obtained by an arithmetic expression of QTL = QEP + QBA = TEP × IEP + C × VOL. Further, the current accumulated charge amount Q0 = C × V1 is calculated (step S6), and the target charge amount QTG is calculated (step S7). As described with reference to FIG. 6B, the target charge amount can be obtained by an arithmetic expression of QTG = QTL−Q0 = QTL−C × V1. Note that the arithmetic processing such as steps S4, S5, S6, and S7 in FIG. 7 is executed by the arithmetic processing unit 76 in FIG.

  Then, as described in FIG. 6C, charging is performed during the TCH period with the variable charging current ICH (step S8). That is, the current control unit 32 charges the capacitor C by performing a control that causes the charging current ICM to flow through the capacitor C during the period TCH. Thereby, the accumulated charge amount is updated to QCH (n) = QCH (n−1) + ICH × TCH. The period TCH in this case is set by the timer 74 in FIG. The magnitude of the charging current ICH is variably set using the control signal ICT in FIG.

  Then, it is determined whether or not the current accumulated charge amount QCH has reached the target charge amount QTG (step S9). If not, the process returns to step S8, and the variable charge current ICH is used for the TCH period. Charge again. On the other hand, if the QCH reaches QTG, it is determined that charging is complete (step S10). In step S9 in FIG. 7, it is determined whether or not QCH ≧ QTG. However, it may be determined whether or not QCH ≧ QTG + ΔQ in order to provide some margin.

  As described above, in the present embodiment, the charging current is controlled based on the operation lower limit voltage information and power usage information of the power supply destination device. Specifically, control is performed so that the charging current flows through the capacitor C until the accumulated charge amount reaches at least the target charge amount QTG. In this case, the target charge amount QTG is set based on the operation lower limit voltage information and power usage information of the power supply destination device.

  For example, in step S5 of FIG. 7 and FIG. 6A, the total charge amount QTL is the charge amount QBA specified by the operation lower limit voltage of the power supply destination device and the charge amount specified by the used power (used charge amount). Required by QEP. Then, as shown in step S7, the target charge amount QTG is obtained based on the total charge amount QTL. That is, the target charge amount QTG is obtained based on information on the lower limit operating voltage of the power supply destination device and the power used. Then, as shown in steps S8 and S9, in the present embodiment, control is performed so that the charging current flows through the capacitor C until the accumulated charge amount QCH of the capacitor C reaches the target charge amount QTG. That is, control is performed so that the charge current flows until the accumulated charge amount QCH reaches the target charge amount QTG obtained based on the information about the operation lower limit voltage and power consumption.

  In this way, the target target charge amount QTG can be obtained based on the information about the operation lower limit voltage and power consumption of the power supply destination device, and the capacitor C can be charged with a lean charging operation. That is, it is possible to efficiently store a necessary amount of charge in the capacitor C even in a short time.

  In the present embodiment, voltage information specifying the charging voltage of the capacitor C is measured, and the charging current is controlled based on the measured voltage information. For example, in step S3 of FIG. 7, the charging voltage VCH is measured, and the charging current is controlled based on the measurement result.

  Specifically, as shown in step S6, the accumulated charge amount Q0 of the capacitor C is obtained based on the measured voltage information. Then, as shown in step S7, the target charge amount QTG is obtained based on the accumulated charge amount Q0 and the total charge amount QTL necessary for operating the power supply destination device. Then, as shown in steps S8 and S9, control is performed so that the charging current flows through the capacitor C until the accumulated charge amount QCH in the capacitor C reaches at least the target charge amount QTG.

  In this way, since the charge of the capacitor C is controlled by accurately measuring and grasping the amount of charge already stored and the amount of charge to be stored, it is possible to realize accurate and wasteful charge control.

  In this case, as described above, in this embodiment, the total charge amount QTL necessary for operating the power supply destination device is set based on the information about the operation lower limit voltage of the power supply destination device and the power consumption. In this way, it is possible to realize further charge control that is not wasted.

  Further, as shown in step S2, the storage capacitor C is measured by controlling the flow of the capacitance measuring current IM through the capacitor C. Then, the total charge amount QTL is set based on the measured storage capacity C and information on the operation lower limit voltage and power consumption. In this way, even when the storage capacity C is not known, it is possible to cope with this, and convenience and the like can be improved. For example, it is possible to cope with a case where the capacitance value differs for each IC card product. In addition, it is possible to cope with a case where the capacity value is variable, such as the capacity value changing depending on the card area. Furthermore, it is possible to cope with the case where there is a manufacturing variation in the capacitance value.

3. Starting Capacitor Next, a detailed configuration example of the power management unit 20 of the circuit device according to the present embodiment will be described with reference to FIG. As shown in FIG. 2, the power management unit 20 includes first and second accumulation control units 30 and 40 and a power supply unit 50. The first accumulation control unit 30 includes the current control unit 32 of FIG. The capacitor C in FIG. 1 corresponds to, for example, the capacitor C1 in FIG.

  The first accumulation control unit 30 (first accumulation operation unit) receives power from the power receiving unit 10 that receives power by electromagnetic induction, and stores a capacitor C1 (first charge accumulation unit in a broad sense). Control (operation) for accumulating charges is performed. The second accumulation control unit 40 (second accumulation operation unit) receives electric power from the power receiving unit 10 and accumulates charges in the starting capacitor C2 (second charge accumulation unit in a broad sense). Perform control (operation).

  Specifically, the first accumulation control unit 30 is provided between the power input node NI from the power receiving unit 10 and the first accumulation node NA1. Then, the current and voltage for charging the main capacitor C1 for power storage are controlled to control charging to the capacitor C1.

  For example, it is assumed that the system device 100 performs display control processing of an electrophoretic display unit (EPD) that displays an image. In this case, the first accumulation control unit 30 performs control to accumulate charges necessary for display rewriting for at least one time in the electrophoretic display unit (nonvolatile display element) in the capacitor C1. By doing so, it is possible to rewrite the display unit of the system device 100 at least once after receiving power by electromagnetic dielectric. Thus, for example, when applied to a prepaid card or an IC card of electronic money, it is possible to display the usage amount, balance, etc. on the display unit of the IC card after the IC card is held over the terminal device.

  Here, the charge necessary for at least one display rewrite is, for example, a charge necessary for rewriting image data for one screen when performing display rewrite of an image for one screen after receiving power. Alternatively, when display rewriting of a part of one screen image is performed after power reception, the charge is necessary for rewriting part of the image data. The amount of these charges can be known in advance by design or actual measurement. Therefore, for example, the first accumulation control unit 30 may perform control for accumulating the charge corresponding to the worst case data in the design value or actual measurement value of the charge amount in the capacitor C1.

  On the other hand, the second accumulation control unit 40 is provided between the power input node NI from the power receiving unit 10 and the second accumulation node NA2. Then, the charging control to the capacitor C2 is performed by controlling the current and voltage for charging the starting sub capacitor C2.

  The power supply unit 50 supplies power from electromagnetic induction power to the system device 100 (and the control unit 70). For example, the power supply unit 50 supplies power to the system device 100 based on the charges accumulated in the capacitors C1 and C2 (first and second charge accumulation units). Specifically, a power supply voltage based on the voltages of the storage nodes NA1 and NA2 is output to the output node NQ of the power supply to the system device 100.

  In this case, the power supply unit 50 supplies power to the system device 100 after the power supply voltage obtained by the accumulated charge of the capacitor C2 (second charge storage unit) exceeds the operation lower limit voltage of the system device 100. It is desirable to do. Here, as described above, the operation lower limit voltage is a voltage for which the system device 100 is guaranteed to perform a normal operation. For example, when a power supply voltage lower than the operation lower limit voltage is supplied to the system device 100, there is a possibility that a malfunction such as a through current flows in a transistor constituting the system device 100 may occur. In this respect, such a problem can be prevented by preventing the power supply unit 50 from supplying power to the system device 100 until the operating lower limit voltage is exceeded.

  The system device 100 (power supply target device in a broad sense) is a device to which power is supplied by electromagnetic induction. The system device 100 performs, for example, display control processing of a display unit that displays an image. The system device 100 can be realized by a microcomputer with a built-in display controller, for example.

  In this embodiment, the capacitor C2 (second charge storage unit) includes a system startup charge storage unit having a charge storage capacity (capacitance) smaller than that of the storage capacitor C1 (first charge storage unit). It has become. As an example, the capacity of the capacitor C1 for storing electricity is several tens of μF to several hundreds of μF (for example, about 100 μF), and the capacity of the starting capacitor C2 is 1 μF or less (for example, about 0.1 μF). A capacitor such as a spar capacitor can be used as the capacitor C1 or the like serving as the storage element. Accordingly, since the power storage element can be configured to be thin, it can be easily built in an IC card or the like.

  One end of the capacitor C1 is connected to the storage node NA1, which is an output node of the first storage control unit 30, and the other end is connected to, for example, a GND node. One end of the capacitor C2 is connected to the storage node NA2 that is an output node of the second storage control unit 40, and the other end is connected to, for example, a GND node. Note that one end of a capacitor CC for stabilizing the potential is connected to the power input node NI.

  The power supply unit 50 supplies power to the system device 100 based on the charge stored in the capacitor C2 (second charge storage unit) when the system is started after the power reception unit 10 starts receiving power. That is, at the time of system startup, a power supply (power supply voltage based on the voltage of the node NA2) based on the accumulated charge of the small capacity capacitor C2 for system startup is supplied to the system device 100.

  On the other hand, the power supply unit 50 supplies power to the system device 100 based on the accumulated charge of the capacitor C1 (first charge accumulation unit) in a period after the end of power reception by the power reception unit 10. That is, in a period after the end of power reception when the system is activated and the capacitor is sufficiently charged, a power supply (power supply voltage based on the voltage of the node NA1) based on the accumulated charge of the large-capacity capacitor C1 for power storage is supplied to the system device. 100.

  Note that the power supplied to the system device 100 in the period after the end of power reception is preferably a power supply based on the accumulated charges of both the capacitors C1 and C2. In addition, it is sufficient that the power source based on the accumulated charge of the capacitor C2 is supplied to the system device 100 at the time of system start-up (first half of the power receiving period) during the power receiving period. Power may be supplied to the system device 100.

  In the circuit device of the present embodiment shown in FIG. 2 described above, the power supply voltage is quickly applied to the system device 100 because the small-capacitance capacitor C2 for activation is charged in a short time after power reception by the power reception unit 10 is started. It becomes possible to supply and start up the system. After that, the capacitor C1 for power storage having a larger capacity than the capacitor C2 is charged, and the system device 100 is operated by supplying power to the system device 100 based on the charge charged in the capacitor C1 even after the end of the power receiving period. It becomes possible.

  For example, when the circuit device according to the present embodiment is applied to a non-contact IC card, it is necessary to communicate with the terminal device in a short time to store electricity. However, the stored capacitor has a large capacity, and the rising of the charging voltage is slow, and there is a problem that communication cannot be started without releasing the reset of the system (system device).

  In this regard, in this embodiment, as shown in FIG. 2, in addition to the large-capacity capacitor C1 for power storage, a small-capacitance capacitor C2 for activation is provided. As a result, immediately after the start of power reception, the system device 100 can be operated with the charging voltage of the capacitor C2 to perform communication or the like. Accordingly, the system can be started up without depending on the capacity of the capacitor C1 for power storage, and the power storage and communication time can be shortened by starting up the communication system at an early stage.

  For example, an EPD that is a non-volatile display element is a suitable display device as the display unit 150 of the IC card 190 as shown in FIG.

  However, EPD has a problem that it takes a long time (for example, 1 second) to rewrite display information as compared with a liquid crystal display device. For this reason, as shown in FIG. 3, it is difficult to receive power and rewrite the display of the EPD by touch & go operation of holding the IC card 190 over the terminal device 202. .

  For example, in the method of the comparative example of FIG. 8A, the length T1 of the power reception period TR due to electromagnetic induction is lengthened, and the data from the terminal device 202 (reader / writer) in the first half of the power reception period TR as indicated by A1. Receive. Then, as shown by A2, the display rewriting of the EPD is performed in the display rewriting period TC in the latter half of the power receiving period TR. In this case, the length T2 of the display rewriting period TC is shorter than the length T1 of the power reception period TR.

  However, in the method of the comparative example of FIG. 8A, since the length T1 of the power receiving period TR becomes long, the touch and go operation as shown in FIG. ) Cannot be realized.

  Therefore, in the present embodiment, as shown in FIG. 8B, the length T1 of the power reception period TR is shortened. Then, data reception from the terminal device 202 is performed during the power receiving period TR as shown in A3, and display rewriting of the EPD is performed in the subsequent display rewriting period TC as shown in A4. In this case, when the length of the power receiving period TR is T1 and the length of the display rewriting period TC is T2, the relationship of T2> T1 is established.

  In this way, by shortening the length T1 of the power reception period TR, the IC card 190 can operate while receiving power by a touch-and-go operation as shown in FIG. In addition, by increasing the length T2 of the display rewriting period TC, the display information can be rewritten even when EPD is used as the display unit 150. That is, EPD requires a long time (1 second) to rewrite display information as compared with a liquid crystal display device. However, when T2 is long, at least one EPD display can be rewritten.

  In this case, if the length T1 of the power reception period TR is short, there is a possibility that sufficient electric charge necessary for EPD display rewriting cannot be accumulated.

  Therefore, in FIG. 2, a large-capacity capacitor is provided as the capacitor C1 for power storage. For example, by using a capacitor such as a spar capacitor as the capacitor C1, it is possible to accumulate sufficient electric charge necessary for display rewriting of the EPD.

  Specifically, the first accumulation control unit 30 performs control for accumulating charges necessary for at least one display rewriting of the EPD (electrophoretic display unit) in the capacitor C1 (charge accumulation unit).

  The system device 100 is supplied with power based on the charge stored in the capacitor C1 (charge storage unit) in the power reception period TR of the power reception unit 10, and performs display rewrite processing of the EPD in the display rewrite period TC after power reception. . For example, an EPD display rewriting process is performed based on data received from the terminal device 202 in the power reception period TR. In this case, as described above, a relationship of T2> T1 is established between the length T1 of the power reception period TR and the length T2 of the display rewriting period TC.

  That is, in the present embodiment, as shown in FIG. 8B, charges are accumulated in the large-capacity storage capacitor C1 in the short power receiving period TR, and the EPD display information is rewritten in the long display rewriting period TC thereafter. Do.

  In this way, it becomes possible to incorporate an EPD that can hold display information in a non-powered state with respect to an IC card that requires touch & go operation, and an IC card that can display various types of information by EPD. Can be realized.

  In this case, if the power reception period TR is shortened as shown in FIG. 8B, it becomes difficult to operate the system device 100 over the long display rewriting period TC thereafter.

  In this regard, in the present embodiment, a large-capacity storage capacitor C1 is provided, and the charging control in the first accumulation control unit 30 is devised, so that a long display rewriting period even in a short power receiving period TR. It has been successful in accumulating enough charge to operate the system device 100 over TC. In particular, by limiting the amount of charge accumulated in the capacitor C1 for power storage to the amount of charge required for one display rewriting of EPD, for example, even if the power receiving period TR is shortened, the system is extended over a long display rewriting period TC. It becomes possible to operate the device 100 and rewrite the display of the EPD.

  However, when the capacitor C1 for power storage has a large capacity as described above, there is a problem that the power supply voltage supplied to the system device 100 does not rise easily and the system cannot be started up at an early stage.

  Therefore, in the present embodiment, a startup capacitor C2 is provided separately from the storage capacitor C1. As shown in B1 and B2 of FIG. 9A, these capacitors C1 and C2 are charged via the first and second accumulation control units 30 and 40 based on the output voltage from the power receiving unit 10. The

  Then, as indicated by B <b> 3 in FIG. 9A, when the system is started after power reception by the power receiving unit 10, power based on the accumulated charge of the startup capacitor C <b> 2 is supplied to the system device 100. That is, since the capacitance of the start-up capacitor C2 is small, the voltage of the charge storage node NA2 of C2 rises quickly, and this voltage is supplied to the system device 100 as a power supply voltage as indicated by B3.

  On the other hand, as shown in FIG. 9B, power is supplied to the system device 100 based on the accumulated charge of the capacitor C <b> 1 for power storage in the period after the end of power reception by the power receiving unit 10. That is, since the capacitor C1 for power storage is large, the rise of the voltage at the charge storage node NA1 of C1 is slow. However, when time elapses after the start of power reception, this voltage exceeds the operating lower limit voltage of the system device 100, and can be supplied to the system device 100 as a power supply voltage as indicated by B4.

  By doing so, it becomes possible to operate the system device 100 by turning on the system power at an early stage as indicated by A5 in FIG. 8B. As a result, the data reception process shown in A3 can be completed at an early stage, and a short power reception period for realizing a touch-and-go operation can be dealt with.

  That is, in order to realize the touch & go operation, it is necessary to complete data reception between the IC card 190 and the terminal device 202 during a short power reception period. However, if the large-capacity capacitor C1 is used, the rise of the power supply voltage is delayed, and if the rise of the system is also delayed, the start of data reception is delayed only by that amount, and the system device 100 is received during a short power reception period. Will not be able to complete the data reception process.

  In this regard, in the present embodiment, the system device 100 starts up and operates at an early stage by the power source based on the small-capacitance start-up capacitor C2, so that the system device 100 completes the data reception process even in a short power reception period. It becomes possible to respond to the touch & go operation of the IC card 190. As described above, the power supply method according to the present embodiment is a method suitable for a non-contact IC card or the like that includes an EPD display unit and requires a touch & go operation.

4). Detailed Configuration Example of Circuit Device Next, a detailed configuration example of the circuit device according to the present embodiment will be described with reference to FIG. In FIG. 10, the first accumulation control unit 30 in FIGS. 1 and 2 is realized by the current control unit 32, and the second accumulation control unit 40 is realized by the startup regulator 42.

  The current control unit 32 receives the voltage VIN from the rectifier circuit 12 constituting the power receiving unit 10 and outputs a charging current to the storage node NA1 via the backflow preventing diode I3.

  The startup regulator 42 receives the voltage VIN from the rectifier circuit 12, and outputs the voltage VA2 after voltage adjustment to the storage node NA2. For example, the constant voltage VA2 is output by voltage adjustment. Specifically, for example, a maximum voltage of about 15 V is stepped down to a constant voltage VA2 of, for example, about 4.5 V by the regulator 42, and charge is stored in the starting capacitor C2.

  In FIG. 10, the power supply unit 50 includes first and second diodes DI1 and DI2. Here, DI1 is a diode provided between the storage node NA1 of the power storage regulator 32 (first charge storage unit 30) and the connection node NC, and having a forward direction from the storage node NA1 to the connection node NC. It is. DI2 is a diode provided between the storage node NA2 of the activation regulator 42 (second charge storage unit 40) and the connection node NC and having a forward direction from the storage node NA2 to the connection node NC. It is. The power supply unit 50 supplies power to the system device 100 based on the voltage of the connection node NC.

  By configuring the power supply unit 50 with such diodes DI1 and DI2, it is possible to prevent backflow of current from the connection node NC to the storage nodes NA1 and NA2, and to supply the voltages VA1 and VA2 of the storage nodes NA1 and NA2 to the power supply. The voltage VC can be output to the connection node NC.

  FIG. 11A is a voltage waveform diagram for explaining the operation of the circuit device of FIG.

  When power reception is started and the voltage VIN from the power receiving unit 10 is supplied, the capacity VA2 of the capacitor C2 for activation is small, so that the voltage VA2 of the storage node NA2 of the capacitor C2 rises early as indicated by D1. As will be described in detail later, when the threshold voltage VTH corresponding to the operation lower limit voltage of the system device 100 is exceeded as indicated by D2, the voltage corresponding to the voltage VA2 is supplied to the system device 100 as the power supply voltage VC. Is done. Specifically, a voltage dropped from VA2 by the amount corresponding to the forward voltage of diode DI1 is supplied as VC.

  On the other hand, since the capacity of the storage capacitor C1 is large, the voltage VA1 of the storage node NA1 of the capacitor C1 gradually rises as indicated by D3. When the voltage VA1 rises, a voltage corresponding to the voltage VA1 is supplied to the system device 100 as the power supply voltage VC. Specifically, a voltage dropped from VA1 by the amount corresponding to the forward voltage of diode DI1 is supplied as VC.

  When the power reception period ends after the start of power reception, the charges of the capacitors C1 and C2 are discharged, so that the power supply voltage VC gradually decreases as indicated by D4. In this case, since the capacitance of the capacitor C1 is sufficiently large in this embodiment, the display rewriting period of a long time (for example, 1 second) is set as shown by A4 in FIG. 8B or D5 in FIG. It becomes possible to secure.

  FIG. 11B is a diagram showing the relationship between the accumulated current and the discharge current. For example, during the power reception period, charges are accumulated in the capacitor as indicated by E1. Further, as indicated by E2, electric charge is discharged from the capacitor for system startup or the like. In the display rewriting period, the charge is discharged from the capacitor as indicated by E3, and the EPD display rewriting process by the system device 100 is performed based on the discharged charge.

  The configuration of the circuit device according to the present embodiment is not limited to that shown in FIG. 10, and various modifications can be made. For example, a switch / transistor circuit or the like may be provided in place of the diodes DI1, DI2, and DI3. If such a switch transistor circuit is used, since there is no voltage drop due to the forward voltage of the diode, there is an advantage that the power supply efficiency can be improved only by that amount. On the other hand, in FIG. 10, since the voltage switch operation is realized by the diodes DI1 and DI2, there is an advantage that a control signal for the switch operation is unnecessary. For example, it is difficult to generate such a control signal before the system is started. However, according to the configuration example of FIG. 10, it is possible to cope with such a situation.

5. Current Control Unit FIG. 12 shows a detailed configuration example of the current control unit 32 of FIG. The current control unit 32 includes operational amplifiers OP1 and OP2, transistors TB1 to TB5, resistors RB1 to RB7, and RCH. Note that the configuration of the current control unit 32 is not limited to the configuration of FIG. 12, and various modifications such as omitting some of the components or adding other components are possible. Further, a current control unit having a circuit system different from that in FIG. 12 may be employed.

  The transistors TB1, TB2, and TB3 are ON / OFF controlled by a control signal ICT from the control unit 70 in FIG. For example, when the control signal ICT is composed of 3-bit signals ICT1, ICT2, and ICT3, each of the transistors TB1, TB2, and TB3 is ON / OFF controlled by each of these signals ICT1, ICT2, and ICT3. One end of each of the resistors RB1, RB2, and RB3 is connected to each of the transistors TB1, TB2, and TB3. The other ends of the resistors RB1, RB2, and RB3 are commonly connected to the node NB1.

  The reference voltage VR is input to the inverting input terminal of the operational amplifier OP1, and the node NB1 is connected to the non-inverting input terminal. The output of the operational amplifier OP1 is connected to the gate of a transistor TB4 provided between the nodes NB2 and NB1. As a result, the operational amplifier OP1 operates so that the voltage VB1 of the node NB1 is set to the reference voltage VR. Then, when the node NB1 is set to a constant voltage VR (for example, 1.25 V), which is a constant voltage, the transistors TB1, TB2, and TB3 are controlled to be turned on / off by the control of the control unit 70. The current IB flowing through RB4 and RB5 can be variably controlled.

  In FIG. 12, the non-inverting input terminal of the operational amplifier OP2 is connected to the node NB2, and the inverting input terminal is set to the node NB3. The output of the operational amplifier OP2 is connected to the gate of the transistor TB5 provided between the nodes NI and NB4. As a result, the operational amplifier OP2 operates so that the voltage VB2 of the node NB2 and the voltage VB3 of the node NB3 are equal. That is, the operational amplifier OP2 operates so that VB2 = VB3.

  RB6 and RB7 are dummy resistors, and no current flows from the nodes NB5 to NB3. For this reason, the voltages at both ends of the resistors RB6 and RB7 are equal, and VB5 = VB3 = VB2.

  If the resistance values of the resistors RB4 and RB5 are expressed by the same symbols RB4 and RB5, VB4 = VB2 + IB × (RB4 + RB5).

  Therefore, a voltage difference of VB4−VB5 = VB2 + IB × (RB4 + RB5) −VB5 = VB2 + IB × (RB4 + RB5) −VB2 = IB × (RB4 + RB5) is applied to both ends of the resistor RCH. Therefore, the current ICH flowing through the resistor RCH is ICH = IB × {(RB4 + RB5) / RCH}, and this current ICH flows as a charging current to the capacitor C1 to perform a charging operation.

  As described above, the current IB is variably controlled by the control signal ICT (ICT1 to ICT3) from the control unit 70. Therefore, the charging current ICH = IB × {(RB4 + RB5) / RCH} is also variably controlled by the control signal ICT.

  For example, in FIG. 12, resistors RB1, RB2, and RB3 have different resistance values such as 5KΩ, 10KΩ, and 20KΩ, respectively. For example, assume that the control unit 70 outputs a control signal ICT that turns off the transistors TB1 and TB3 and turns on the transistor TB2. Then, since the voltage of the node NB1 becomes VB1 = VR = 1.25V, IB = 125 μA. When RCH = RB4 + RB5, a charging current of ICH = 125 μA flows to the capacitor C.

  As described above, according to the current control unit 32 having the configuration shown in FIG. 12, the charging current ICH can be variably controlled by controlling on / off of the transistors TB1 to TB3 by the control signal ICT from the control unit 70. . As a result, the charging method of the present embodiment as described with reference to FIGS. 5A and 5B can be realized. According to the configuration of FIG. 12, the voltage difference between both ends of the resistor RCH can be set to a small voltage difference, so that the charging current ICH can be variably controlled with a small voltage drop, and the charging efficiency can be improved.

6). Next, a configuration example of the system device 100 will be described. FIG. 13 shows a detailed configuration example of the system device 100. The system device 100 includes a host I / F 110, a processing unit 120, a register unit 130, a waveform information memory 140, an image memory 142, and a work memory 144. Note that the configuration of the system device 100 is not limited to the configuration of FIG. 13, and various modifications such as omitting some of the components or adding other components are possible. For example, the memories 140, 142, and 144 may be external memories.

  The host I / F 110 is an interface for transmitting / receiving information to / from a counterpart device (power transmission device, terminal device, charger) serving as a host. The host I / F 110 is connected to the host I / F 18 on the power receiving unit 10 side via the control unit 70 as shown in FIG. As a result, transmission / reception of information to / from the power transmission device 200 (partner device) becomes possible. Transmission / reception of this information can be realized by, for example, amplitude modulation processing (frequency modulation processing) or load modulation processing using the coils L1 and L2.

  The processing unit 120 performs display control processing of the display unit 150 and various control processes of the system. The processing unit 120 can be realized by a processor, a gate array circuit, or the like, for example.

  The display unit 150 whose display is controlled by the processing unit 120 includes a display panel 152 (electro-optical panel) and a driver circuit 154 that is a circuit for driving the display panel 152. The driver circuit 154 drives data lines (segment electrodes) and scanning lines (common electrodes) of the display panel 152. The display panel 152 is realized by a display element such as an electrophoretic element.

The register unit 130 includes various registers such as a control register and a status register. The register unit 130 can be realized by a RAM such as an SRAM or a flip-flop circuit. The waveform information memory 140 stores waveform information, instruction code information, and the like for driving the EPD. The waveform information memory 140 can be realized by, for example, a nonvolatile memory (for example, a flash memory) that can rewrite / erase data.

  The image memory 142 (VRAM) stores, for example, image data for one screen displayed on the display panel 152. The work memory 144 is a memory serving as a work area for the processing unit 120 and the like. The image memory 142 and the work memory 144 can be realized by a RAM such as an SRAM.

  FIG. 14A illustrates a configuration example of the display panel 152. The display panel 152 includes an element substrate 300, a counter substrate 310, and an electrophoretic layer 320 provided between the element substrate 300 and the counter substrate 310. The electrophoretic layer 320 (electrophoretic sheet) includes a large number of microcapsules 322 having an electrophoretic substance. The microcapsule 322, for example, disperses positively charged black positively charged particles (electrophoretic substance) and negatively charged white negatively charged particles (electrophoretic substance) in a dispersion liquid. It is realized by enclosing in a simple capsule.

  The element substrate 300 is formed of glass or transparent resin. The element substrate 300 includes a plurality of data lines (segment electrodes), a plurality of scanning lines (common electrodes), and a plurality of pixel electrodes in which each pixel electrode is provided at the intersection of each data line and each scanning line. Is done. In addition, a plurality of switch elements are provided in which each switch element formed by a TFT (Thin Film Transistor) or the like is connected to each pixel electrode. A data driver for driving the data lines and a scanning driver for driving the scanning lines are also provided.

  A common electrode (transparent electrode) is formed on the counter substrate 310, and a common voltage VCOM (counter voltage) is supplied to the common electrode. Note that the electrophoretic sheet may be formed by forming a common electrode with a transparent conductive material on the transparent resin layer, and applying an adhesive or the like on the transparent resin layer to adhere the electrophoretic layer.

  In the display panel 152 in FIG. 14A, when an electric field is applied between the pixel electrode and the common electrode, positively charged particles (black) and negatively charged particles (white) sealed in the microcapsule 322 are Electrostatic force acts in the direction according to the positive and negative charge. For example, positively charged particles (black) move to the common electrode side on the pixel electrode having a higher potential than the common electrode, so that the pixel is displayed in black.

  Next, the waveform information stored in the waveform information memory 140 of FIG. 13 will be described. Here, waveform information of an EPD (electrophoretic display unit) will be described as an example.

  For example, in a liquid crystal display device, as indicated by F1 in FIG. 14B, when changing the gradation of a pixel from the first gradation to the second gradation, data on the data line (source line) is displayed. The voltage also changes in one frame period from the data voltage VG1 corresponding to the first gradation to the data voltage VG2 corresponding to the second gradation.

  On the other hand, in EPD, when the gray level of a pixel is changed from the first gray level to the second gray level, as shown by F2 in FIG. Change over time. For example, when changing from the first gradation close to white to the second gradation close to black, the display of white and black is repeated over a plurality of frames to change the gradation of the pixel to the final second level. Change the key. For example, in the waveform of FIG. 14C, the data voltage changes over a plurality of frames such that the data voltage is set to VA in the first three frames and is set to -VA in the next three frames. Note that the waveform has a different shape depending on the combination of the pixel gradation in the current display state and the pixel gradation in the next display state.

  The waveform information memory 140 stores waveform information as indicated by F2 in FIG. The processing unit 120 determines the driving voltage of the EPD in each frame based on the image data (gradation data of each pixel) stored in the image memory 142 and the waveform information stored in the waveform information memory 140. Then, display control processing of the EPD (display unit 150) is performed.

  As apparent from comparing F1 in FIG. 14B and F2 in FIG. 14C, the EPD requires a longer time to rewrite display information than a liquid crystal display device or the like. For this reason, there is a problem that it is necessary to increase the length T2 of the display rewriting period TC in FIG.

  In this regard, in the present embodiment, as described above, the large-capacity capacitor C1 for power storage is provided, and charges necessary for display rewriting for at least one EPD are stored in the capacitor C1 during the power reception period TR.

  Further, by providing a small-capacitance capacitor C2 for activation, the system power is turned on early as indicated by A5 in FIG. 8B. As a result, the processing unit 120 in FIG. 13 receives data such as display information from the counterpart device (power transmission device, terminal device) that is the host via the host I / F 110, as indicated by A3.

  Then, the processing unit 120 performs an EPD display rewriting process as indicated by A4 in FIG. 8B in the display rewriting period TC after power reception. That is, based on the display information received through the host I / F 110 and written in the image memory 142 and the waveform information stored in the waveform information memory 140, the waveform as shown by F2 in FIG. EPD display rewrite processing is performed on the form.

  Thus, even with an EPD having a long display rewriting period, display information can be rewritten based on the charge received in the short power receiving period TR. Therefore, for example, an EPD display unit 150 that can hold display information in a non-powered state can be incorporated into a non-contact IC card that requires a touch & go operation as shown in FIG. An unprecedented type of IC card can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, at least once, terms (capacitors, capacitors for storage, Starting capacitor etc.) may be replaced by the different terminology anywhere in the specification or drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration and operation of the circuit device and the electronic device, the current control method, the charging method, the power supply method, and the like are not limited to those described in this embodiment, and various modifications can be made.

L1 primary coil, L2 secondary coil, CA, CB, CC, CP capacitor,
C, capacitor, C1 storage capacitor, C2 start-up capacitor,
DI1, DI2, DI3 first, second and third diodes,
OP1, OP2 operational amplifiers, TB1-TB5 transistors,
RB1 to RB7 RCH resistance, VR reference voltage,
10 power receiving unit, 12 rectifier circuit, 18 host I / F, 20 power management unit,
30 first accumulation control unit, 32 current control unit,
40 second storage control unit, 42 regulator for startup, 50 power supply unit,
70 control unit, 72 A / D conversion unit, 74 timer, 76 arithmetic processing unit,
90 circuit device, 100 system device, 110 host I / F,
120 processing units, 130 register units, 140 waveform information memory,
142 image memory, 144 work memory, 150 display unit,
152 display panel, 154 driver circuit, 190 IC card,
200 power transmission device, 202 terminal device, 210 display unit, 300 element substrate,
310 counter substrate, 320 electrophoretic layer, 322 microcapsule

Claims (11)

Including a control unit that receives electric power from a power receiving unit that receives electric power by electromagnetic induction and controls a flow of a variable charging current to the charge storage unit;
In the charge storage unit, charges are accumulated by the charging current during a power reception period of the power reception unit,
A power supply destination device to which power based on the charge accumulated in the charge accumulation unit is supplied operates in an operation period including a period after the power reception period,
The controller is
The charge current decreases as the charge voltage increases until at least the target charge amount, which is a charge amount that prevents the charge voltage of the charge storage unit from falling below the operation lower limit voltage of the power supply destination device during the operation period, is reached. The circuit device is characterized in that the charging current is controlled to flow through the charge storage portion during the power reception period while performing the control . In claim 1,
The controller is
The circuit device characterized in that the target charge amount is set based on the operation lower limit voltage information of the power supply destination device and the power consumption information of the power supply destination device. In claim 1,
  The controller is
  A circuit device characterized in that the target charge amount is obtained based on an accumulated charge amount of the charge accumulation unit and a total charge amount necessary for operating the power supply destination device. In claim 3 ,
The controller is
Measure the voltage information identifying the charging voltage of the charge storage unit, based on said measured voltage information, determine the amount of charges stored in the charge storage part, and the accumulated charge amount, the power supply destination device based on said total amount of charge required to operate, determined the target charge amount, the amount of charges stored in the charge storage unit, until it reaches at least the target charge amount, the charge current to the charge storage unit A circuit device characterized by performing flow control. In claim 4 ,
The controller is
A circuit that sets the total amount of charge required to operate the power supply destination device based on the operation lower limit voltage information of the power supply destination device and the power consumption information of the power supply destination device. apparatus. In claim 5 ,
The controller is
By controlling the flow of a capacitance measurement current to the charge storage unit, the storage capacity of the charge storage unit is measured, and based on the measured storage capacity, the operating lower limit voltage information, and the power usage information The total charge amount is set. In any one of Claims 1 thru | or 6 .
A first accumulation control unit that receives electric power from the power receiving unit and performs control for accumulating charges in the first charge accumulation unit that is the charge accumulation unit;
A second accumulation control unit that receives electric power from the power reception unit and performs control for accumulating charges in the second charge accumulation unit;
A power supply unit that supplies power to a system device based on the charges accumulated in the first charge accumulation unit and the second charge accumulation unit;
Including
The second charge storage unit is a charge storage unit having a charge storage capacity smaller than that of the first charge storage unit,
The power supply unit
A circuit device that supplies power to the system device based on the stored charge of the second charge storage unit when the system is started after power reception by the power reception unit. In claim 7 ,
The power supply unit
After the power reception by the power reception unit is completed, a circuit device is characterized in that power based on the accumulated charge of the first charge accumulation unit is supplied to the system device. In claim 7 or 8 ,
The system device performs display control processing of an electrophoretic display unit that displays an image,
The first accumulation control unit
A circuit device characterized by performing control for accumulating charges necessary for display rewriting at least once in the electrophoretic display section in the first charge accumulating section. In any one of Claims 7 thru | or 9 ,
The power supply unit
A first diode provided between a first storage node and a connection node of the first charge storage unit, the forward direction being a direction from the first storage node to the connection node;
A second diode provided between the second storage node and the connection node of the second charge storage unit and having a forward direction from the second storage node to the connection node. ,
The power supply unit
A circuit device that supplies power to the system device based on a voltage of the connection node. An electronic apparatus comprising the circuit arrangement as claimed in any one of claims 1 to 10.

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