JP5873324B2 - Method for manufacturing semiconductor device - Google Patents

Description

The disclosed invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a technique for manufacturing a transistor using a Zn—O-based oxide or an In—O—Ga—Zn—O-based oxide as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). .

By the way, it has been pointed out that in an oxide semiconductor, a donor is generated in a shallow level from the conduction band and becomes n-type by containing hydrogen. Therefore, it is required to take measures so that hydrogen is not mixed during formation of the oxide semiconductor. In addition, a technique for reducing variation in threshold voltage by reducing hydrogen in a gate insulating film in contact with an oxide semiconductor as well as an oxide semiconductor is disclosed (see Patent Document 3).

JP 2007-123861 A JP 2007-96055 A JP 2009-224479 A

In an oxide semiconductor, oxygen vacancies serve as donors and generate electrons that are carriers in the oxide semiconductor. If there are many oxygen vacancies in the oxide semiconductor including the channel formation region of the transistor, electrons are generated in the channel formation region, which causes the threshold voltage of the transistor to fluctuate in the negative direction.

In view of the above problems, in one embodiment of the present invention, a method for manufacturing a semiconductor device using an oxide semiconductor, which can provide stable electrical characteristics and high reliability can be obtained. One purpose is to provide.

In a semiconductor device having a bottom-gate transistor including an oxide semiconductor layer, the insulating layer is in contact with the oxide semiconductor layer and includes a region containing oxygen in excess of the stoichiometric composition ratio and containing nitrogen Is provided.

Examples of the insulating layer in contact with the oxide semiconductor layer in the bottom-gate transistor include a gate insulating layer provided in contact with the oxide semiconductor layer and an interlayer insulating layer provided in contact with the oxide semiconductor layer. In the invention disclosed in this specification, the gate insulating layer and / or the interlayer insulating layer, which is an insulating layer in contact with the oxide semiconductor layer, is subjected to oxygen doping treatment, so that oxygen exceeds the stoichiometric composition ratio. A region (hereinafter also referred to as an oxygen excess region) is formed. The insulating layer in contact with the oxide semiconductor layer and having an oxygen-excess region is an insulating layer containing nitrogen as its composition.

Since the insulating layer in contact with the oxide semiconductor layer has an oxygen-excess region, oxygen extraction from the oxide semiconductor layer by the insulating layer can be suppressed or prevented; Can be suppressed. In addition, excess oxygen contained in the insulating layer in contact with the oxide semiconductor layer also has an effect of extracting hydrogen in the oxide semiconductor layer. Therefore, the insulating layer can reduce the hydrogen concentration of the oxide semiconductor layer and suppress oxygen vacancies.

In addition, since nitrogen has three bonds, by performing oxygen doping treatment on the insulating layer containing nitrogen as a composition, the nitrogen contained in the film is combined with oxygen into which oxygen is introduced, and the introduced oxygen This has the effect of trapping in the film. Therefore, an oxygen-excess region can be easily formed in the insulating layer in contact with the oxide semiconductor layer, or a larger amount of oxygen can be contained in the film.

The insulating layer in contact with the oxide semiconductor layer is preferably free of impurities such as water and hydrogen as much as possible. This is because when the insulating layer in contact with the oxide semiconductor layer contains hydrogen, the hydrogen may enter the oxide semiconductor layer or the hydrogen may extract oxygen from the oxide semiconductor layer. Therefore, the insulating layer in contact with the oxide semiconductor layer is preferably a film that has been subjected to heat treatment for dehydration or dehydrogenation.

Note that the heat treatment and / or the oxygen doping treatment of the insulating layer in contact with the oxide semiconductor layer may be repeated a plurality of times. Further, after the oxide semiconductor layer is formed, heat treatment for dehydration or dehydrogenation treatment of the oxide semiconductor layer may be performed. The heat treatment of the oxide semiconductor layer is preferably performed before the oxide semiconductor layer is processed into an island shape.

One embodiment of the present invention includes a gate electrode layer, a gate insulating layer provided over the gate electrode layer, an oxide semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween, and the oxide semiconductor layer electrically A source electrode layer and a drain electrode layer which are connected to each other, and an interlayer insulating layer which covers the source electrode layer and the drain electrode layer and is in contact with the oxide semiconductor layer, and one of the gate insulating layer and the interlayer insulating layer has a chemical amount This is a semiconductor device that has a region containing oxygen in excess of the theoretical composition ratio and is an insulating layer containing nitrogen.

One embodiment of the present invention includes a gate electrode layer, a gate insulating layer provided over the gate electrode layer, an oxide semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween, and an oxide semiconductor layer. A source electrode layer and a drain electrode layer which are electrically connected; and an interlayer insulating layer which covers the source electrode layer and the drain electrode layer and is in contact with the oxide semiconductor layer. The gate insulating layer and the interlayer insulating layer have a stoichiometric amount. This is a semiconductor device that has a region containing oxygen in excess of the theoretical composition ratio and is an insulating layer containing nitrogen.

In the above semiconductor device, the gate insulating layer preferably includes a silicon nitride film in contact with the gate electrode layer and a silicon nitride oxide film in contact with the oxide semiconductor layer.

In any one of the above semiconductor devices, the interlayer insulating layer preferably includes a silicon nitride oxide film in contact with the oxide semiconductor layer and an aluminum oxide film provided over the silicon nitride oxide film.

In any one of the above semiconductor devices, the gate insulating layer and / or the interlayer insulating layer preferably includes a film formed by a chemical vapor deposition method.

The above “oxygen doping” means adding oxygen (including at least one of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions) to the bulk. Say to do. The term “bulk” is used for the purpose of clarifying that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. Further, “oxygen doping” includes “oxygen plasma doping” in which oxygen in plasma form is added to a bulk.

A gas containing oxygen can be used for the oxygen doping treatment. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, a rare gas may be added in the oxygen doping process.

One embodiment of the present invention relates to a semiconductor device including a transistor or a circuit including the transistor. For example, the invention relates to a semiconductor device including a transistor or a circuit including a transistor in which a channel formation region is formed using an oxide semiconductor. For example, power devices mounted on LSIs, CPUs, power supply circuits, semiconductor integrated circuits including memories, thyristors, converters, image sensors, etc., light-emitting displays having electro-optical devices and light-emitting elements typified by liquid crystal display panels The present invention relates to an electronic device equipped with a device as a component.

According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor that can provide stable electrical characteristics and high reliability can be provided.

8A and 8B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 10 is a plan view illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 9 illustrates an electronic device. FIG. 9 illustrates an electronic device. The TDS result of the sample produced in the Example.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, when referring to a portion having a similar function, the hatch pattern may be the same, and there may be no particular reference.

It should be noted that ordinal numbers such as “first” and “second” in the present specification are added to avoid confusion between components and are not limited in number.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor layer is described as an example of a semiconductor device.

FIG. 1 illustrates a configuration example of the transistor 420. 1A is a plan view of the transistor 420, FIG. 1B is a cross-sectional view taken along line X1-Y1 of FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. It is sectional drawing in V1-W1. Note that in FIG. 1A, some components (for example, the interlayer insulating layer 417 and the like) are not illustrated in order to avoid complexity.

A transistor 420 illustrated in FIG. 1 overlaps with the gate electrode layer 401 provided over the substrate 400, the gate insulating layer 402 provided over the gate electrode layer 401, and the gate electrode layer 401 with the gate insulating layer 402 interposed therebetween. The oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode layer 405b that are electrically connected to the oxide semiconductor layer 403, and the interlayer insulating film that covers the source electrode layer 405a and the drain electrode layer 405b and is in contact with the oxide semiconductor layer 403 And a layer 417.

A transistor 420 described in this embodiment includes a gate insulating layer 402 in which a gate insulating layer 402a and a gate insulating layer 402b are stacked in this order from the gate electrode layer 401 side, and an interlayer insulating layer 417a in order from the oxide semiconductor layer 403 side. And an interlayer insulating layer 417 in which an interlayer insulating layer 417b is stacked. Note that the embodiment of the present invention is not limited to this, and the gate insulating layer and the interlayer insulating layer may each have a single-layer structure or a stacked structure including three or more layers.

In the transistor 420 described in this embodiment, the interlayer insulating layer 417 in contact with the oxide semiconductor layer 403 is an insulating layer having a region containing oxygen in excess of the stoichiometric composition ratio and containing nitrogen. . More specifically, in the stacked structure in which the interlayer insulating layer 417 is formed, at least the interlayer insulating layer 417a in contact with the oxide semiconductor layer 403 includes a region containing oxygen in excess of the stoichiometric composition ratio. In addition, an insulating layer containing nitrogen is used. In this embodiment, a silicon oxynitride film having an oxygen-excess region is used as the interlayer insulating layer 417a, and an aluminum oxide film is used as the interlayer insulating layer 417b.

Note that in this specification, oxynitride is a substance having a higher oxygen content than nitrogen in the composition, and nitride oxide has a nitrogen content higher than oxygen in the composition. Means a substance.

Nitrogen has three bonds, and has more bonds than oxygen, which has two bonds. Therefore, when oxygen doping is performed to form an oxygen-excess region in the insulating layer in contact with the oxide semiconductor layer, the composition is higher than that in the case where an oxide insulating layer (eg, a silicon oxide film) is used as the insulating layer. By using an insulating layer containing nitrogen (for example, a silicon oxynitride film), the introduced oxygen can be trapped more in the film. Therefore, an oxygen-excess region can be easily formed in the insulating layer in contact with the oxide semiconductor layer, or a larger amount of oxygen can be contained in the film.

The interlayer insulating layer 417b is an insulating layer that functions as a protective film of the transistor 420. The aluminum oxide film has a high blocking effect that prevents the film from permeating both hydrogen, moisture and other impurities, and oxygen. Therefore, by using an aluminum oxide film as the interlayer insulating layer 417b, release of oxygen from the oxide semiconductor layer 403 and the interlayer insulating layer 417a in contact with the oxide semiconductor layer 403 can be prevented, and water and hydrogen can be supplied to the oxide semiconductor layer 403. Mixing can be prevented.

Note that it is more preferable that the aluminum oxide film have a high density (a film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more) because the transistor 420 can be provided with stable electrical characteristics. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray reflectance measurement (XRR: X-Ray Reflection).

In addition, the oxide semiconductor layer 403 is preferably highly purified so as not to contain impurities such as copper, aluminum, and chlorine. In the transistor manufacturing process, it is preferable to appropriately select a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor layer. When the impurity is attached to the surface of the oxide semiconductor layer, oxalic acid or dilute hydrofluoric acid is preferably used. It is preferable to remove impurities on the surface of the oxide semiconductor layer by exposure to the above or by performing plasma treatment (N ₂ O plasma treatment or the like). Specifically, the copper concentration of the oxide semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. In addition, the aluminum concentration of the oxide semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration in the oxide semiconductor layer is 2 × 10 ¹⁸ atoms / cm ³ or less.

The oxide semiconductor layer 403 is preferably formed by removing impurities such as water and hydrogen as much as possible. For example, in the transistor 420, the concentration of hydrogen contained in the oxide semiconductor layer 403 is 2 × 10 ¹⁹ / cm ³ or less, preferably 5 × 10 ¹⁸ / cm ³ or less, more preferably 2 × 10 ¹⁸ / cm ³ or less. It is preferable to do.

Hereinafter, an example of a method for manufacturing the transistor 420 illustrated in FIGS.

First, after the gate electrode layer 401 is formed over the substrate 400 having an insulating surface, the gate insulating layer 402a and the gate insulating layer 402b are sequentially stacked over the gate electrode layer 401 to form the gate insulating layer 402 (FIG. 2). A)).

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance enough to withstand heat treatment performed later. For example, various glass substrates used in the electronic industry such as glass substrates such as barium borosilicate glass and alumino borosilicate glass can be used. The substrate has a thermal expansion coefficient of 25 × 10 ⁻⁷ / ° C. or higher and 50 × 10 ⁻⁷ / ° C. or lower (preferably 30 × 10 ⁻⁷ / ° C. or higher and 40 × 10 ⁻⁷ / ° C. or lower). A substrate having a strain point of 650 ° C. or higher and 750 ° C. or lower (preferably 700 ° C. or higher and 740 ° C. or lower) is preferably used.

5th generation (1000 mm × 1200 mm or 1300 mm × 1500 mm), 6th generation (1500 mm × 1800 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2500 mm), 9th generation (2400 mm × 2800 mm), 1st When a large glass substrate of 10 generations (2880 × 3130 mm) or the like is used, fine processing may be difficult due to shrinkage of the substrate caused by heat treatment in a manufacturing process of a semiconductor device. Therefore, when a large glass substrate as described above is used as the substrate, it is preferable to use a substrate with less shrinkage. For example, a large glass substrate having a shrinkage of 20 ppm or less, preferably 10 ppm or less, more preferably 5 ppm or less after heat treatment at 450 ° C., preferably 500 ° C. for 1 hour, is preferably used as the substrate. Good.

Alternatively, as the substrate 400, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used. You may use what provided the semiconductor element on these board | substrates.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device having flexibility, the transistor 420 including the oxide semiconductor layer 403 may be directly formed over a flexible substrate, or the transistor including the oxide semiconductor layer 403 over another manufacturing substrate. 420 may be manufactured and then peeled off and transferred to a flexible substrate. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor 420 including the oxide semiconductor layer.

A base insulating layer may be provided over the substrate 400. As the base insulating layer, an oxide insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, silicon nitride, silicon nitride oxide, aluminum nitride is formed by a plasma CVD method or a sputtering method. Alternatively, a nitride insulating film such as aluminum nitride oxide, or a mixed material thereof can be used.

Heat treatment may be performed on the substrate 400 (or the substrate 400 and the base insulating layer). For example, the heat treatment may be performed at 650 ° C. for 1 minute to 5 minutes using a GRTA (Gas Rapid Thermal Anneal) apparatus that performs heat treatment using a high-temperature gas. Note that as the high-temperature gas in GRTA, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used. Moreover, you may heat-process with an electric furnace for 500 degreeC and 30 minutes-1 hour.

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

The material of the gate electrode layer 401 is indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, oxide A conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

The gate electrode layer 401 includes a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, or an In—Ga containing nitrogen. An —O film, an In—Zn—O film containing nitrogen, an Sn—O film containing nitrogen, an In—O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

In this embodiment, a tungsten film with a thickness of 100 nm is formed by a sputtering method.

Further, after the gate electrode layer 401 is formed, heat treatment may be performed on the substrate 400 and the gate electrode layer 401. For example, heat treatment may be performed at 650 ° C. for 1 minute to 5 minutes using a GRTA apparatus. Moreover, you may heat-process with an electric furnace for 500 degreeC and 30 minutes-1 hour.

Note that planarization treatment may be performed on the surface of the gate electrode layer 401 in order to improve the coverage with the gate insulating layer 402. In particular, when a thin insulating layer is used as the gate insulating layer 402, the surface of the gate electrode layer 401 is preferably flat.

As the gate insulating layer 402a, a nitride insulating layer formed by a plasma CVD method, a sputtering method, or the like can be preferably used. For example, a silicon nitride film, a silicon nitride oxide film, or the like can be given. By applying a nitride insulating layer as the gate insulating layer 402 a in contact with the gate electrode layer 401 and the substrate 400, an effect of preventing impurity diffusion from the gate electrode layer 401 or the substrate 400 is achieved.

Alternatively, as the gate insulating layer 402a, titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), zirconium (Zr), nickel (Ni), magnesium ( Metal oxide insulating film containing at least one selected from Mg) or barium (Ba) metal element (for example, aluminum oxide film, aluminum oxynitride film, hafnium oxide film, magnesium oxide film, zirconium oxide film) , A lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, aluminum nitride oxide film) can be used. For the gate insulating layer 402a, a gallium oxide film, an In—Zr—Zn-based oxide film, an In—Fe—Zn-based oxide film, an In—Ce—Zn-based oxide film, or the like can be used.

In this embodiment, a 30-nm-thick silicon nitride film formed by a plasma CVD method is used as the gate insulating layer 402a.

The gate insulating layer 402b has a thickness of 1 nm to 20 nm and can be formed as appropriate by using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like. Alternatively, the gate insulating layer 402b may be formed using a so-called CP sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

As a material of the gate insulating layer 402b, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used.

As materials for the gate insulating layer 402b, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0, The gate leakage current can be reduced by using a high-k material such as y> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), or lanthanum oxide.

In this embodiment, a 200-nm-thick silicon oxynitride film is formed by high-density plasma CVD. The CVD method can reduce the film formation tact compared with the sputtering method. In addition, the CVD method has less variation in the surface where the film is formed than the sputtering method, and particles are less likely to be mixed. For this reason, it is effective to form the gate insulating layer 402 using the CVD method particularly when the substrate has a large area.

Note that since the gate insulating layer 402b is an insulating layer in contact with the oxide semiconductor layer 403, it is preferable that impurities such as water and hydrogen be contained as little as possible. However, it is difficult for the plasma CVD method to reduce the hydrogen concentration in the film as compared with the sputtering method. Therefore, in this embodiment, heat treatment (dehydration or dehydrogenation treatment) for removing hydrogen atoms is performed on the gate insulating layer 402 after deposition.

The heat treatment temperature is 250 ° C. or higher and 650 ° C. or lower, preferably 450 ° C. or higher and 600 ° C. or lower, or lower than the strain point of the substrate. For example, a substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and the gate insulating layer 402 is subjected to heat treatment at 650 ° C. for 1 hour in a vacuum (depressurized) atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used. Note that when a GRTA apparatus is used as the heat treatment apparatus, the substrate may be heated in an inert gas heated to a high temperature of 650 ° C. to 700 ° C. because the processing time is short.

The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium). It is preferable that water, hydrogen, and the like are not contained in the atmosphere of nitrogen, oxygen, ultra-dry air, or rare gas. Further, the purity of nitrogen, oxygen, or a rare gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm). Or less).

By the heat treatment, the gate insulating layer 402 can be dehydrated or dehydrogenated, and the gate insulating layer 402 from which impurities such as hydrogen or water which cause a change in characteristics of the transistor are excluded can be formed.

In the heat treatment for performing dehydration or dehydrogenation, the surface of the gate insulating layer 402 interferes with the release of hydrogen, water, or the like (for example, a film that does not allow (block) hydrogen, water, or the like to be provided). The gate insulating layer 402 is preferably in a state where the surface is exposed.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatments.

Next, an oxide semiconductor layer is formed over the gate insulating layer 402 and processed into an island shape, so that the oxide semiconductor layer 403 is formed (see FIG. 2B).

Note that the gate insulating layer 402 and the oxide semiconductor layer are preferably formed successively without releasing the gate insulating layer 402 to the atmosphere. When the gate insulating layer 402 and the oxide semiconductor layer are formed successively without exposing the gate insulating layer 402 to the air, adsorption of impurities such as hydrogen and moisture to the surface of the gate insulating layer 402 can be prevented.

The oxide semiconductor layer 403 may have a single-layer structure or a stacked structure. Moreover, an amorphous structure may be sufficient and crystallinity may be sufficient. In the case where the oxide semiconductor layer 403 has an amorphous structure, a crystalline oxide semiconductor layer may be formed by performing heat treatment on the oxide semiconductor layer 403 in a later manufacturing process. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor layer is 250 ° C. or higher and 700 ° C. or lower, preferably 400 ° C. or higher, more preferably 500 ° C. or higher, and further preferably 550 ° C. or higher. Note that the heat treatment can also serve as another heat treatment in the manufacturing process.

As a method for forming the oxide semiconductor layer, a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method, or the like can be used as appropriate. The oxide semiconductor layer is formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicularly to the surface of the sputtering target, that is, a so-called CP sputtering apparatus (Column Plasma Sputtering system). May be.

When forming the oxide semiconductor layer, it is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor layer as much as possible. In order to reduce the hydrogen concentration, for example, when film formation is performed using a sputtering method, impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed as an atmospheric gas supplied into the processing chamber of the sputtering apparatus. A high-purity rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate.

In addition, the hydrogen concentration of the formed oxide semiconductor layer can be reduced by introducing a sputtering gas from which hydrogen and moisture are removed while removing residual moisture in the deposition chamber. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. The film formation chamber evacuated using a cryopump has a high exhaust capability such as a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as hydrogen molecules and water (H ₂ O). The concentration of impurities contained in the oxide semiconductor layer formed in the film chamber can be reduced.

Further, before the oxide semiconductor layer is formed, heat treatment may be performed on the substrate provided with the gate insulating layer in the sputtering apparatus. The heat treatment is preferably performed in a reduced-pressure atmosphere, and more preferably performed in a vacuum atmosphere. For example, the substrate 400 provided with a gate insulating layer may be placed in a sputtering apparatus in a vacuum atmosphere until the deposition surface of the oxide semiconductor layer reaches a deposition temperature. By this heat treatment, surface adsorbed water that can be adsorbed to the surface of the gate insulating layer can be removed; thus, the hydrogen concentration of the oxide semiconductor layer formed can be reduced.

In the case where the oxide semiconductor layer is formed by a sputtering method, the relative density (filling ratio) of the metal oxide target used for film formation is 90% to 100%, preferably 95% to 99.9%. . By using a metal oxide target having a high relative density, the formed oxide semiconductor layer can be a dense film.

In addition, forming the oxide semiconductor layer with the substrate 400 kept at a high temperature is also effective in reducing the concentration of impurities that can be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150 ° C. or higher and 450 ° C. or lower, and preferably the substrate temperature is 200 ° C. or higher and 350 ° C. or lower. In addition, the crystalline oxide semiconductor layer can be formed by heating the substrate at a high temperature during film formation.

An oxide semiconductor used for the oxide semiconductor layer 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain both In and Zn. In addition, it is preferable that gallium (Ga) be included in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide Oxides, Sn—Mg oxides, In—Mg oxides, In—Ga oxides, In—Ga—Zn oxides (also referred to as IGZO) which are oxides of ternary metals, In— Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu -Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, n-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn -Based oxides, In-Sn-Ga-Zn-based oxides that are oxides of quaternary metals, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn- An Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

However, the composition is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, etc.). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C, (A + B + C = 1) is the vicinity of r of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ It refers to meet the r ^2. For example, r may be 0.05. The same applies to other oxides.

As a sputtering gas used for forming the oxide semiconductor layer, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

The oxide semiconductor layer 403 is preferably a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor layer with a crystal-amorphous mixed phase structure where crystal parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

In the crystal part included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

A transistor including a CAAC-OS film can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

In the case where a CAAC-OS film is used as the oxide semiconductor layer 403, there are three methods for obtaining the CAAC-OS film. The first is a method in which an oxide semiconductor layer is formed at a film formation temperature of 200 ° C. or higher and 450 ° C. or lower, and is c-axis oriented substantially perpendicular to the surface. The second method is a method in which an oxide semiconductor layer is formed with a thin film thickness, and then heat treatment is performed at 200 ° C. to 700 ° C. so that the c-axis alignment is approximately perpendicular to the surface. The third method is a method of forming a thin film as a first layer, then performing a heat treatment at 200 ° C. or more and 700 ° C. or less to form a second layer, and aligning the c-axis substantially perpendicularly to the surface.

Before the formation of the oxide semiconductor layer, planarization treatment may be performed on the deposition surface of the oxide semiconductor layer. The planarization treatment is not particularly limited, and polishing treatment (for example, chemical mechanical polishing (CMP) method), dry etching treatment, or plasma treatment can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Reverse sputtering refers to a method of modifying the surface by applying a voltage to the substrate side using an RF power source in an argon atmosphere to form plasma near the substrate. Note that nitrogen, helium, oxygen, or the like may be used instead of argon. When reverse sputtering is performed, powdered substances (also referred to as particles or dust) attached to the surface of the oxide semiconductor layer can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate depending on the unevenness state of the oxide semiconductor layer.

Next, a conductive film to be a source electrode layer and a drain electrode layer (including a wiring formed using the same layer) is formed over the gate electrode layer 401, the gate insulating layer 402, and the oxide semiconductor layer 403.

The conductive film is formed using a material that can withstand heat treatment performed later. As the conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal containing the above-described element as a component A nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. The conductive film used for the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

A resist mask is formed over the conductive film by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b. After the source electrode layer 405a and the drain electrode layer 405b are formed, the resist mask is removed (see FIG. 2C).

Ultraviolet light, KrF laser light, or ArF laser light is preferably used for light exposure for forming the resist mask. The channel length L of the transistor 440 to be formed later is determined by the distance between the lower end portion of the source electrode layer 405a and the lower end portion of the drain electrode layer 405b which are adjacent to each other over the oxide semiconductor layer 403. Note that in the case of performing exposure with a channel length L of less than 25 nm, it is preferable to perform exposure at the time of forming a resist mask using extreme ultraviolet (Extreme Ultraviolet) having a very short wavelength of several nm to several tens of nm. Exposure by extreme ultraviolet light has a high resolution and a large depth of focus. Accordingly, the channel length L of a transistor to be formed later can be 10 nm to 1000 nm, and the operation speed of the circuit can be increased.

In order to reduce the number of photomasks used in the photolithography process and the number of processes, the etching process may be performed using a resist mask formed by a multi-tone mask that is an exposure mask in which transmitted light has a plurality of intensities. Good. A resist mask formed using a multi-tone mask has a shape with a plurality of thicknesses, and the shape can be further deformed by etching. Therefore, the resist mask can be used for a plurality of etching processes for processing into different patterns. . Therefore, a resist mask corresponding to at least two kinds of different patterns can be formed by using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be reduced, so that the process can be simplified.

In this embodiment mode, the conductive film is etched using a gas containing chlorine, such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like. A gas containing can be used. Alternatively, a gas containing fluorine, for example, a gas containing carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), or the like can be used. Alternatively, a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases can be used.

As an etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode temperature, etc.) are adjusted as appropriate so that the desired processed shape can be etched.

In this embodiment, a stack of a 100-nm-thick titanium film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film is used as the conductive film by a sputtering method. For the etching of the conductive film, the stack of the titanium film, the aluminum film, and the titanium film is etched by a dry etching method to form the source electrode layer 405a and the drain electrode layer 405b.

In this embodiment, after etching the two layers of the titanium film and the aluminum film under the first etching condition, the remaining titanium film single layer is removed under the second etching condition. Note that the first etching conditions are an etching gas (BCl ₃ : Cl ₂ = 750 sccm: 150 sccm), a bias power of 1500 W, an ICP power supply power of 0 W, and a pressure of 2.0 Pa. As the second etching condition, an etching gas (BCl ₃ : Cl ₂ = 700 sccm: 100 sccm) is used, the bias power is 750 W, the ICP power supply power is 0 W, and the pressure is 2.0 Pa.

Note that it is preferable that etching conditions be optimized so that the oxide semiconductor layer 403 is not etched and divided in the conductive film etching step. However, it is difficult to obtain a condition that only the conductive film is etched and the oxide semiconductor layer 403 is not etched at all. When the conductive film is etched, only a part of the oxide semiconductor layer 403 is etched and a groove (concave portion) is obtained. The oxide semiconductor layer may be included.

Next, an interlayer insulating layer 427 a and an interlayer insulating layer 417 b which are in contact with the oxide semiconductor layer 403 are sequentially formed so as to cover the source electrode layer 405 a and the drain electrode layer 405 b.

As the interlayer insulating layer 427a in contact with the oxide semiconductor layer 403, an insulating layer containing nitrogen, preferably an oxide insulating layer containing nitrogen as a composition is used. For example, as the interlayer insulating layer 427a, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxynitride film, an aluminum nitride film, an aluminum nitride oxide film, a gallium oxynitride film, a gallium nitride film, a gallium nitride oxide film, or the like Inorganic insulating layers can be used. The thickness of the interlayer insulating layer 427a is preferably greater than or equal to 50 nm and less than or equal to 100 nm.

As the interlayer insulating layer 417b, an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (eg, an aluminum nitride film) can be used.

Note that an aluminum oxide film has a high blocking effect (blocking effect) of preventing both hydrogen, moisture and other impurities, and oxygen from passing through the film, and causes hydrogen, moisture, and the like that cause fluctuations during and after the manufacturing process. It can function as a protective film that prevents entry of impurities into the oxide semiconductor layer 403 and release of oxygen, which is a main component material of the oxide semiconductor, from the oxide semiconductor layer 403. Therefore, an aluminum oxide film is preferably provided as the interlayer insulating layer 417b.

In this embodiment, a silicon oxynitride film is formed as the interlayer insulating layer 427a by a plasma CVD method. In addition, as the interlayer insulating layer 417b, an aluminum oxide film is formed by a sputtering method.

Note that since the interlayer insulating layer 427a is an insulating layer in contact with the oxide semiconductor layer 403, it is preferable that impurities such as water and hydrogen are not contained as much as possible in the same manner as the gate insulating layer 402b. Therefore, in this embodiment, heat treatment (dehydration or dehydrogenation treatment) for the purpose of removing hydrogen atoms is performed on the interlayer insulating layer 427a after deposition. Note that the aluminum oxide film used as the interlayer insulating layer 417b in this embodiment is a film having a blocking function of preventing hydrogen, water, or the like from passing therethrough. Therefore, heat treatment for the purpose of dehydration or dehydrogenation of the interlayer insulating layer 427a is preferably performed after the formation of the interlayer insulating layer 427a and before the formation of the interlayer insulating layer 417b.

The heat treatment temperature is 250 ° C. or higher and 650 ° C. or lower, preferably 450 ° C. or higher and 600 ° C. or lower, or lower than the strain point of the substrate. The details of the heat treatment for dehydration or dehydrogenation treatment can be performed in a manner similar to that of the gate insulating layer 402b.

Next, treatment for introducing oxygen 454 through the interlayer insulating layer 417b (also referred to as oxygen doping treatment or oxygen implantation treatment) is performed on the interlayer insulating layer 427a subjected to dehydration or dehydrogenation treatment. Thus, an interlayer insulating layer 417 including a stack of an interlayer insulating layer 417a having an oxygen excess region and an interlayer insulating layer 417b is formed (see FIG. 2E).

The oxygen 454 contains at least one of oxygen radicals, ozone, oxygen atoms, and oxygen ions (including molecular ions and cluster ions). By performing oxygen doping treatment on the interlayer insulating layer that has been subjected to dehydration or dehydrogenation treatment, oxygen can be included in the interlayer insulating layer, and oxygen that may be released by the previous heat treatment is compensated. , An oxygen-excess region can be formed.

For the introduction of the oxygen 454 into the interlayer insulating layer 427a, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used. A gas cluster ion beam may be used as the ion implantation method. In addition, the introduction of oxygen 454 may be performed on the entire surface of the substrate 400 at a time, or for example, a linear ion beam may be used. In the case of using a linear ion beam, oxygen 454 can be introduced to the entire surface of the interlayer insulating layer 427a by relatively moving (scanning) the substrate or the ion beam.

As a supply gas of oxygen 454, a gas containing O may be used. For example, O ₂ gas, N ₂ O gas, CO ₂ gas, CO gas, NO ₂ gas, or the like can be used. Note that a rare gas (eg, Ar) may be included in the oxygen supply gas.

For example, when oxygen is introduced by an ion implantation method, the dose of oxygen 454 is preferably 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less. The oxygen content in the interlayer insulating layer 417a is preferably higher than the stoichiometric composition ratio of the interlayer insulating layer 417a. Note that the region containing oxygen in excess of the stoichiometric composition ratio only needs to exist in part of the interlayer insulating layer 417a. Note that the depth of oxygen implantation may be appropriately controlled depending on the implantation conditions.

Note that in the case where an oxynitride insulating layer (eg, a silicon oxynitride film) is used as the interlayer insulating layer 417a, oxygen is one of main component materials in the oxynitride insulating layer. Therefore, it is difficult to accurately estimate the oxygen concentration in the oxynitride insulating layer by using a method such as SIMS (Secondary Ion Mass Spectroscopy). That is, it can be said that it is difficult to determine whether oxygen is intentionally added to the oxynitride insulating layer.

By the way, it is known that oxygen has isotopes such as ¹⁷ O and ¹⁸ O, and their abundance ratios in the natural world are about 0.038% and 0.2% of the whole oxygen atom, respectively. In other words, the concentration of these isotopes in the insulating layer in contact with the oxide semiconductor layer (the interlayer insulating layer in this embodiment) can be estimated by a method such as SIMS. Thus, the oxygen concentration in the insulating layer in contact with the oxide semiconductor layer may be able to be estimated more accurately. Therefore, by measuring these concentrations, it may be determined whether oxygen is intentionally added to the insulating layer in contact with the oxide semiconductor layer.

Note that treatment for introducing nitrogen into the interlayer insulating layer 427a may be performed before introducing oxygen 454 to the interlayer insulating layer 427a. Nitrogen introduced into the interlayer insulating layer 427a can be combined with oxygen 454 in the film. Therefore, the introduction efficiency of oxygen 454 can be improved. In the case where nitrogen doping is performed before oxygen doping is performed on the interlayer insulating layer 427a, an oxide insulating layer such as a silicon oxide film, a gallium oxide film, or an aluminum oxide film is used as the interlayer insulating layer 427a. You can also.

Through the above process, the transistor 420 of this embodiment is formed.

Charges may be generated due to oxygen vacancies in the oxide semiconductor layer. In general, oxygen vacancies in the oxide semiconductor layer partly serve as donors and emit electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. However, in the transistor described in this embodiment, the interlayer insulating layer in contact with the oxide semiconductor layer has an oxygen-excess region, so that oxygen extraction from the oxide semiconductor layer by the insulating layer can be suppressed or prevented. Therefore, generation of oxygen vacancies in the oxide semiconductor layer can be suppressed. Therefore, the oxygen deficiency density of the oxide semiconductor layer, which is a factor for shifting the threshold voltage in the negative direction, can be reduced.

Excess oxygen contained in the interlayer insulating layer 417a can be supplied to the oxide semiconductor layer 403 in contact with the interlayer insulating layer 417a by heat treatment in the manufacturing process of the transistor. Therefore, in the transistor 420, an oxygen-excess region may be formed at the interface between the interlayer insulating layer 417a and the oxide semiconductor layer 403 or at least part of the oxide semiconductor layer 403 (in the bulk). Note that a heat treatment step for supplying oxygen from the interlayer insulating layer 417a to the oxide semiconductor layer 403 may be provided.

In the case of a transistor including an oxide semiconductor, oxygen is supplied from the interlayer insulating layer to the oxide semiconductor layer, whereby the interface state density between the oxide semiconductor layer and the interlayer insulating layer can be reduced. As a result, carriers can be prevented from being trapped at the interface between the oxide semiconductor layer and the interlayer insulating layer due to the operation of the transistor, and a highly reliable transistor can be obtained.

In the transistor 420 of this embodiment, since the interlayer insulating layer having an oxygen-excess region is located over the oxide semiconductor layer, oxygen can be prevented from being released from the side surface and the top surface of the oxide semiconductor layer. Is possible.

In addition, excess oxygen contained in the interlayer insulating layer in contact with the oxide semiconductor layer also has an effect of extracting hydrogen in the oxide semiconductor layer. Thus, the carrier concentration in the oxide semiconductor layer can be further reduced; thus, by providing the interlayer insulating layer 417a, a highly reliable transistor in which variation in threshold voltage is reduced can be provided. .

Note that in this embodiment, the interlayer insulating layer 417 includes a stacked structure of an interlayer insulating layer 417a and an interlayer insulating layer 417b. Here, the interlayer insulating layer 417 only needs to include an oxygen-excess region and an insulating layer containing nitrogen as the interlayer insulating layer 417a that is at least an insulating layer in contact with the oxide semiconductor layer. Does not necessarily have an oxygen-excess region. However, in this embodiment, since the interlayer insulating layer 417a is subjected to oxygen doping treatment through the interlayer insulating layer 417b, the interlayer insulating layer 417b similarly has an oxygen-excess region by oxygen doping treatment to the interlayer insulating layer 417a. Can be a membrane. Note that the oxygen doping treatment on the interlayer insulating layer 417a may be performed after the dehydration or dehydrogenation treatment of the interlayer insulating layer 417a and before the formation of the interlayer insulating layer 417b. Alternatively, a process for the purpose of oxygen doping treatment for the interlayer insulating layer 417b may be separately provided.

Further, the dehydration or dehydrogenation treatment and / or the oxygen doping treatment on the interlayer insulating layer may be performed a plurality of times.

Note that although not illustrated, a planarization insulating layer for planarization may be provided over the transistor 420. As the planarization insulating layer, a heat-resistant organic material such as polyimide, acrylic, polyimide amide, ginzocyclobutene, polyamide, or epoxy can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), BPSG (phosphorus glass), or the like can be used. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

Further, after the transistor 420 is formed, heat treatment at 100 ° C to 400 ° C may be performed in the air. This heat treatment may be performed while maintaining a constant heating temperature, and is performed by repeatedly raising the temperature from room temperature to a heating temperature of 100 ° C. to 400 ° C. and lowering the temperature from the heating temperature to room temperature a plurality of times. May be. Further, this heat treatment may be performed under reduced pressure. When heat treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, oxygen contained in the interlayer insulating layer 417a can be supplied to the oxide semiconductor layer 403, whereby the reliability of the semiconductor device can be improved.

In the semiconductor device described in this embodiment, oxygen doping treatment is performed on the interlayer insulating layer 417 a provided in contact with the oxide semiconductor layer 403. The interlayer insulating layer 417a is an insulating layer containing nitrogen as a composition, and can effectively introduce introduced oxygen into the film. The insulating layer is a film in which water or hydrogen which is an impurity is removed as much as possible by dehydration or dehydrogenation treatment. By forming the interlayer insulating layer 417a in contact with the oxide semiconductor layer 403 so that the content of water and hydrogen is reduced and the content of oxygen is increased, water and hydrogen are mixed into the oxide semiconductor layer 403. Oxygen desorption from the oxide semiconductor layer 403 can be suppressed while being suppressed.

Accordingly, the oxygen deficiency density of the oxide semiconductor layer, which is a factor that shifts the threshold voltage in the negative direction, can be reduced, so that variation in the threshold voltage of the transistor 420 can be reduced, and A normally-off transistor can be realized. Further, the subthreshold value (S value) of the transistor 420 can be reduced.

Further, in the semiconductor device described in this embodiment, oxygen doping treatment is performed on the interlayer insulating layer 417 that is in contact with the upper layer of the oxide semiconductor layer 403. Therefore, the oxygen doping treatment is directly performed on the oxide semiconductor layer 403. Thus, the film quality and / or crystallinity of the oxide semiconductor layer 403 can be improved. In particular, in the case where the oxide semiconductor layer 403 is a CAAC-OS film, crystallinity may be impaired when oxygen doping treatment is performed on the CAAC-OS film; thus, a method for manufacturing the semiconductor device described in this embodiment It is effective to apply

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. Note that the same portions as those in the above embodiment or portions and processes having similar functions can be performed in the same manner as in the above embodiment, and repeated description is omitted. Detailed descriptions of the same parts are omitted.

FIG. 3 illustrates a configuration example of the transistor 430. 3A is a plan view of the transistor 430, FIG. 3B is a cross-sectional view taken along line X2-Y2 of FIG. 3A, and FIG. 3C is a cross-sectional view of FIG. It is sectional drawing in V2-W2. Note that in FIG. 3A, some components (for example, the interlayer insulating layer 407 and the like) are not illustrated in order to avoid complexity.

3 overlaps with the gate electrode layer 401 with the gate electrode layer 401 provided over the substrate 400, the gate insulating layer 412 provided over the gate electrode layer 401, and the gate insulating layer 412 interposed therebetween. The oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode layer 405b that are electrically connected to the oxide semiconductor layer 403, and the interlayer insulating film that covers the source electrode layer 405a and the drain electrode layer 405b and is in contact with the oxide semiconductor layer 403 And a layer 407.

A transistor 430 described in this embodiment includes a gate insulating layer 412 in which a gate insulating layer 412a and a gate insulating layer 412b are stacked in this order from the gate electrode layer 401 side, and an interlayer insulating layer 407a in order from the oxide semiconductor layer 403 side. And an interlayer insulating layer 407 in which an interlayer insulating layer 407b is stacked. Note that the embodiment of the present invention is not limited to this, and the gate insulating layer and the interlayer insulating layer may each have a single-layer structure or a stacked structure including three or more layers.

In the transistor 430 described in this embodiment, the gate insulating layer 412 in contact with the oxide semiconductor layer 403 is an insulating layer having a region containing oxygen in excess of the stoichiometric composition ratio and containing nitrogen. . More specifically, in the stacked structure in which the gate insulating layer 412 is formed, at least the gate insulating layer 412b in contact with the oxide semiconductor layer 403 includes a region containing oxygen in excess of the stoichiometric composition ratio. In addition, an insulating layer containing nitrogen is used. In this embodiment, a silicon nitride film is used as the gate insulating layer 402a, and a silicon oxynitride film having an oxygen-excess region is used as the gate insulating layer 412b.

Hereinafter, an example of a method for manufacturing the transistor 430 of this embodiment will be described with reference to FIGS.

A conductive film is formed over the substrate 400 having an insulating surface, and the conductive film is etched, so that the gate electrode layer 401 is formed. Next, a gate insulating layer 412a and a gate insulating layer 412b are formed in order over the gate electrode layer 401 (see FIG. 4A). The material, film thickness, and the like of the gate insulating layer 412a can be the same as those of the gate insulating layer 402a in Embodiment 1.

As a material of the gate insulating layer 422b, an insulating layer containing nitrogen as a composition, preferably an oxide insulating layer containing nitrogen as a composition is used. For example, an inorganic insulating layer such as a silicon oxynitride film or a silicon nitride oxide film can be used. The thickness of the gate insulating layer 422b is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Next, heat treatment (dehydration or dehydrogenation treatment) for removing hydrogen atoms is preferably performed on the gate insulating layer 402. By the heat treatment, the gate insulating layer 402 can be dehydrated or dehydrogenated, and the gate insulating layer 402 from which impurities such as hydrogen or water which cause a change in characteristics of the transistor are excluded can be formed.

Next, treatment for introducing oxygen 452 to oxygen into the gate insulating layer 412b (also referred to as oxygen doping treatment or oxygen implantation treatment) is performed. Thus, a gate insulating layer 412 having a stack of the gate insulating layer 412b having an oxygen excess region and the gate insulating layer 412a is formed (see FIG. 4B). The details of the treatment for introducing oxygen 452 can be performed in the same manner as the treatment for introducing oxygen 454 in Embodiment 1.

Note that dehydration or dehydrogenation treatment and / or oxygen doping treatment on the gate insulating layer may be performed a plurality of times.

Note that in this embodiment, the gate insulating layer 412 includes a stacked structure of a gate insulating layer 412a and a gate insulating layer 412b. Here, the gate insulating layer 412 only needs to include an oxygen-excess region and an insulating layer containing nitrogen as the gate insulating layer 412b which is an insulating layer in contact with at least the oxide semiconductor layer. Does not necessarily have an oxygen-excess region. However, the gate insulating layer 412a can also be a film having an oxygen-excess region by oxygen doping treatment of the gate insulating layer 412b. Alternatively, a process for the purpose of oxygen doping treatment of the gate insulating layer 412a may be additionally provided.

Next, as in Embodiment 1, an oxide semiconductor layer is formed over the gate insulating layer 402.

After the oxide semiconductor layer is formed, heat treatment for reducing, more preferably removing (dehydrating or dehydrogenating) excess hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor layer may be performed. preferable. The heat treatment temperature is set to be 300 ° C. or higher and 700 ° C. or lower or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere.

By this heat treatment, hydrogen which is an impurity imparting n-type conductivity can be reduced or removed from the oxide semiconductor. Further, by this heat treatment, oxygen contained in the gate insulating layer 402 can be supplied to the oxide semiconductor layer. By supplying oxygen from the gate insulating layer 402 which is simultaneously desorbed by dehydration or dehydrogenation of the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be filled.

Note that when heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is performed before the island-shaped oxide semiconductor layer 403 is processed, oxygen contained in the gate insulating layer 402 is released by the heat treatment. Can be prevented, which is preferable.

The heat treatment for dehydration or dehydrogenation may be combined with another heat treatment in the manufacturing process of the transistor 430.

In the heat treatment, it is preferable that water or hydrogen is not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

In addition, after the oxide semiconductor layer is heated by heat treatment, a high-purity oxygen gas, a high-purity oxygen dinitride gas, or ultra-dry air (CRDS) is maintained in the same furnace while maintaining the heating temperature or gradually cooling from the heating temperature. (Cavity Ring Down Laser Spectroscopy) The amount of water when measured using a dew point meter is 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less) Also good. It is preferable that water, hydrogen, or the like be not contained in the oxygen gas or the oxygen dinitride gas. Alternatively, the purity of the oxygen gas or oxygen dinitride gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or oxygen dinitride gas is 1 ppm or less, preferably 0.1 ppm or less). It is preferable to do. By supplying oxygen, which is a main component material of the oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or oxygen dinitride gas, the oxide The semiconductor layer can be highly purified and electrically i-type (intrinsic).

Next, after the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode layer 405b are formed over the oxide semiconductor layer 403 (see FIG. 4C).

Next, the interlayer insulating layer 407 is formed in order by covering the source electrode layer 405a and the drain electrode layer 405b and sequentially stacking the interlayer insulating layer 407a and the interlayer insulating layer 407b in contact with the oxide semiconductor layer 403 (see FIG. 4D). .

As a material of the interlayer insulating layer 407a, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. The interlayer insulating layer 407b can have a structure similar to that of the interlayer insulating layer 417b in Embodiment 1.

Note that since the interlayer insulating layer 407a is an insulating layer in contact with the oxide semiconductor layer 403, it is preferable that impurities such as water and hydrogen are not contained as much as possible. Therefore, it is preferable to perform heat treatment (dehydration or dehydrogenation treatment) for the purpose of removing hydrogen atoms on the interlayer insulating layer 407a after film formation.

Through the above process, the transistor 430 of this embodiment is formed.

In the semiconductor device described in this embodiment, oxygen doping treatment is performed on the gate insulating layer 412b provided in contact with the oxide semiconductor layer 403. The gate insulating layer 412b is an insulating layer containing nitrogen as a composition, and can effectively introduce introduced oxygen into the film. The insulating layer is a film in which water or hydrogen which is an impurity is removed as much as possible by dehydration or dehydrogenation treatment. By forming the gate insulating layer 412b in contact with the oxide semiconductor layer 403 while reducing the content of water and hydrogen and increasing the content of oxygen, water and hydrogen are mixed into the oxide semiconductor layer 403. Oxygen desorption from the oxide semiconductor layer 403 can be suppressed while being suppressed.

Accordingly, the oxygen deficiency density of the oxide semiconductor layer, which is a factor that shifts the threshold voltage in the negative direction, can be reduced, so that variation in threshold voltage of the transistor 430 can be reduced, and A normally-off transistor can be realized. Further, the subthreshold value (S value) of the transistor 430 can be reduced.

Further, in the semiconductor device described in this embodiment, oxygen doping treatment is performed on the gate insulating layer 412 that is in contact with the lower layer of the oxide semiconductor layer 403. Therefore, the oxygen doping treatment is directly performed on the oxide semiconductor layer 403. Thus, the film quality and / or crystallinity of the oxide semiconductor layer 403 can be improved. In particular, in the case where the oxide semiconductor layer 403 is a CAAC-OS film, crystallinity may be impaired when oxygen doping treatment is performed on the CAAC-OS film; thus, a method for manufacturing the semiconductor device described in this embodiment It is effective to apply

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, another embodiment of a semiconductor device is described with reference to FIGS. Note that the same portions as those in the above embodiment or portions and processes having similar functions can be performed in the same manner as in the above embodiment, and repeated description is omitted. Detailed descriptions of the same parts are omitted.

FIG. 5 illustrates a configuration example of the transistor 440. 5A is a plan view of the transistor 440, FIG. 5B is a cross-sectional view taken along line X3-Y3 in FIG. 5A, and FIG. 5C is a cross-sectional view of FIG. It is sectional drawing in V3-W3. Note that in FIG. 5A, some components (for example, the interlayer insulating layer 417 and the like) are not illustrated in order to avoid complexity.

A transistor 440 illustrated in FIG. 5 overlaps with the gate electrode layer 401 provided over the substrate 400, the gate insulating layer 412 provided over the gate electrode layer 401, and the gate electrode layer 401 with the gate insulating layer 412 interposed therebetween. The oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode layer 405b that are electrically connected to the oxide semiconductor layer 403, and the interlayer insulating film that covers the source electrode layer 405a and the drain electrode layer 405b and is in contact with the oxide semiconductor layer 403 And a layer 417.

A transistor 430 described in this embodiment includes a gate insulating layer 412 in which a gate insulating layer 412a and a gate insulating layer 412b are stacked in this order from the gate electrode layer 401 side, and an interlayer insulating layer 417a in order from the oxide semiconductor layer 403 side. And an interlayer insulating layer 417 in which an interlayer insulating layer 417b is stacked. Note that the embodiment of the present invention is not limited to this, and the gate insulating layer and the interlayer insulating layer may each have a single-layer structure or a stacked structure including three or more layers.

In the transistor 440 described in this embodiment, the gate insulating layer 412 in contact with the oxide semiconductor layer 403 has a region containing oxygen in excess of the stoichiometric composition ratio and is an insulating layer containing nitrogen. . More specifically, in the stacked structure in which the gate insulating layer 412 is formed, at least the gate insulating layer 412b in contact with the oxide semiconductor layer 403 includes a region containing oxygen in excess of the stoichiometric composition ratio. In addition, an insulating layer containing nitrogen is used. In this embodiment, a silicon nitride film is used as the gate insulating layer 402a, and a silicon oxynitride film having an oxygen-excess region is used as the gate insulating layer 412b.

In the transistor 440 described in this embodiment, the interlayer insulating layer 417 in contact with the oxide semiconductor layer 403 includes a region containing oxygen in excess of the stoichiometric composition ratio and containing nitrogen. It is. More specifically, in the stacked structure in which the interlayer insulating layer 417 is formed, at least the interlayer insulating layer 417a in contact with the oxide semiconductor layer 403 includes a region containing oxygen in excess of the stoichiometric composition ratio. In addition, an insulating layer containing nitrogen is used. In this embodiment, a silicon oxynitride film having an oxygen-excess region is used as the interlayer insulating layer 417a, and an aluminum oxide film is used as the interlayer insulating layer 417b.

Embodiments 1 and 2 can be referred to for details of the structure and the manufacturing method of the transistor 440.

In the semiconductor device described in this embodiment, an insulating layer containing nitrogen is used as an insulating layer (a gate insulating layer 412b and an interlayer insulating layer 417a) provided in contact with an upper layer and a lower layer of the oxide semiconductor layer 403. . Each of the insulating layers is a film subjected to oxygen doping treatment, and oxygen introduced by nitrogen contained in the film can effectively stay in the film. The insulating layer is a film in which water or hydrogen which is an impurity is removed as much as possible by dehydration or dehydrogenation treatment. By forming an insulating layer in contact with the top and bottom of the oxide semiconductor layer 403 to reduce the content of water and hydrogen and increase the content of oxygen, water and hydrogen are mixed into the oxide semiconductor layer 403. Oxygen desorption from the oxide semiconductor layer 403 can be suppressed while being suppressed.

Accordingly, the oxygen deficiency density of the oxide semiconductor layer, which is a factor that shifts the threshold voltage in the negative direction, can be reduced, so that variation in threshold voltage of the transistor 430 can be reduced, and A normally-off transistor can be realized. Further, the subthreshold value (S value) of the transistor 440 can be reduced.

In addition, since the semiconductor device described in this embodiment performs oxygen doping treatment on the insulating layer in contact with the oxide semiconductor layer 403, compared with the case where oxygen doping treatment is performed directly on the oxide semiconductor layer 403, oxidation is performed. The film quality and / or crystallinity of the physical semiconductor layer 403 can be improved. In particular, in the case where the oxide semiconductor layer 403 is a CAAC-OS film, crystallinity may be impaired when oxygen doping treatment is performed on the CAAC-OS film; thus, a method for manufacturing the semiconductor device described in this embodiment It is effective to apply

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
A semiconductor device having a display function (also referred to as a display device) can be manufactured using any of the transistors described in any of Embodiments 1 to 3. In addition, part or the whole of a driver circuit including a transistor can be formed over the same substrate as the pixel portion to form a system-on-panel.

In FIG. 6A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a substrate 4001 and is sealed with the substrate 4006. 6A, a single crystal semiconductor film or a polycrystalline semiconductor film is formed over an IC chip or a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the substrate 4001. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted. In addition, a variety of signals and potentials are supplied to a separately formed signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 from FPCs (Flexible Printed Circuits) 4018a and 4018b.

6B and 6C, a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the substrate 4001 and the scan line driver circuit 4004. A substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the substrate 4001, the sealant 4005, and the substrate 4006. 6B and 6C, a single crystal semiconductor film or a polycrystalline semiconductor is provided over an IC chip or a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the substrate 4001. A signal line driver circuit 4003 formed of a film is mounted. 6B and 6C, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from FPCs 4018 and 4018b. Yes.

6B and 6C illustrate an example in which the signal line driver circuit 4003 is separately formed and mounted on the substrate 4001, the invention is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and mounted.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, a TAB (Tape Automated Bonding) method, or the like can be used. 6A illustrates an example in which the signal line driver circuit 4003 and the scan line driver circuit 4004 are mounted by a COG method, and FIG. 6B illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method. FIG. 6C illustrates an example in which the signal line driver circuit 4003 is mounted by a TAB method.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, an IC (integrated circuit) is directly mounted on a connector, for example, a module to which an FPC or TAB tape or TCP is attached, a module in which a printed wiring board is provided at the end of the TAB tape or TCP, or a display element by a COG method. All modules are included in the display device.

The pixel portion and the scan line driver circuit provided over the substrate include a plurality of transistors, and any of the transistors described in any of Embodiments 1 to 3 can be used.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

One embodiment of a semiconductor device will be described with reference to FIGS. FIG. 8 corresponds to a cross-sectional view taken along line MN in FIG.

6 and 8, the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 each include a terminal included in the FPCs 4018 and 4018b and an anisotropic conductive layer 4019. Are electrically connected.

The connection terminal electrode 4015 is formed using the same conductive layer as the first electrode layer 4034, and the terminal electrode 4016 is formed using the same conductive layer as the source and drain electrode layers of the transistors 4040 and 4011.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the substrate 4001 include a plurality of transistors. In FIGS. 6 and 8, the transistor 4040 included in the pixel portion 4002 and the scan line driver circuit 4004 are included. The transistor 4011 included in FIG. 8A, insulating layers 4030 and 4032 are provided over the transistors 4040 and 4011. In FIG. 8B, an insulating layer 4021 is further provided.

The transistors described in any of Embodiments 1 to 3 can be used as the transistors 4010 and 4011. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 420 described in Embodiment 1 is applied is described. The transistors 4010 and 4011 are bottom-gate transistors.

The transistors 4010 and 4011 are transistors in which an insulating layer in which an oxygen-excess region is formed by oxygen doping treatment is used as the gate insulating layer 4020b and / or the insulating layer 4030 which are insulating layers in contact with the oxide semiconductor layer. The insulating layer having an oxygen excess region is an insulating layer containing nitrogen as its composition. Thus, the oxide semiconductor layer can be supplied with oxygen that does not contain impurities such as hydrogen or water that causes characteristics variation of the transistors 4010 and 4011 and fills oxygen vacancies. Therefore, the transistor 4010 and 4011 have suppressed variation in electrical characteristics.

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistors 4010 and 4011 having stable electric characteristics using the oxide semiconductor layer of this embodiment illustrated in FIGS.

Further, a conductive layer may be provided in a position overlapping with a channel formation region of the oxide semiconductor layer of the transistor 4011 for the driver circuit. By providing the conductive layer so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 before and after the bias-thermal stress test (BT test) can be further reduced. In addition, the potential of the conductive layer may be the same as or different from that of the gate electrode layer of the transistor 4011, and the conductive layer can function as a second gate electrode layer. Further, the potential of the conductive layer may be GND, 0 V, or a floating state.

The conductive layer also has a function of shielding an external electric field, that is, preventing the external electric field from acting on the inside (a circuit portion including a transistor) (particularly, an electrostatic shielding function against static electricity). With the shielding function of the conductive layer, the electrical characteristics of the transistor can be prevented from changing due to the influence of an external electric field such as static electricity.

A transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as display can be performed, and various display elements can be used.

FIG. 8A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 8A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4038 and 4033 functioning as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4034 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided for controlling the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Alternatively, a liquid crystal composition exhibiting a blue phase for which an alignment film is unnecessary may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008 is in contact with the first electrode layer 4034 and the second electrode layer 4031. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. The blue phase can be expressed using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. In addition, in order to widen the temperature range in which the blue phase develops, a liquid crystal layer is formed by adding a polymerizable monomer, a polymerization initiator, or the like to the liquid crystal composition that develops the blue phase, and performing a polymer stabilization treatment. You can also. A liquid crystal composition that develops a blue phase has a short response speed and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved. In a transistor using an oxide semiconductor layer, the electrical characteristics of the transistor may fluctuate significantly due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal composition exhibiting a blue phase for a liquid crystal display device including a transistor including an oxide semiconductor layer.

The specific resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

The size of the storage capacitor provided in the liquid crystal display device is set so that charges can be held for a predetermined period in consideration of a leakage current of a transistor arranged in the pixel portion. The size of the storage capacitor may be set in consideration of the off-state current of the transistor. By using a transistor including an oxide semiconductor layer disclosed in this specification, a storage capacitor having a capacitance of 1/3 or less, preferably 1/5 or less of the liquid crystal capacitance of each pixel is provided. It is enough.

In a transistor including an oxide semiconductor layer disclosed in this specification, a current value in an off state (off-state current value) can be controlled low. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, a transistor including the oxide semiconductor layer disclosed in this specification can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor capable of high-speed driving for a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

The liquid crystal display device includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetrical Micro-cell) mode, and an OCB mode. An FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, and the like can be used. The present invention can also be applied to a VA liquid crystal display device. A VA liquid crystal display device is a type of a method for controlling the alignment of liquid crystal molecules of a liquid crystal display panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied. Further, a method called multi-domain or multi-domain design in which pixels (pixels) are divided into several regions (sub-pixels) and molecules are tilted in different directions can be used.

In the display device, a black matrix (light shielding layer), a polarizing member, a retardation member, an optical member (an optical substrate) such as an antireflection member, and the like are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. In addition, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, there is RGBW (W represents white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

In addition, as a display element included in the display device, a light-emitting element utilizing electroluminescence can be used. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element. In this embodiment, an example in which an organic EL element is used as a light-emitting element is described.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes may be light-transmitting. Then, a transistor and a light emitting element are formed over the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. There is a light-emitting element having a dual emission structure in which light emission is extracted from the light-emitting element.

7A and 7B illustrate an example of a light-emitting device using a light-emitting element as a display element.

7A is a plan view of the light-emitting device, and a cross section taken along dashed-dotted lines S1-T1, S2-T2, and S3-T3 in FIG. 7A corresponds to FIG. Note that the electroluminescent layer 542 and the second electrode layer 543 are not illustrated in the plan view of FIG.

The light-emitting device illustrated in FIG. 7 includes a transistor 510, a capacitor 520, and a wiring layer intersection 530 over a substrate 500. The transistor 510 is electrically connected to the light-emitting element 540. Note that FIG. 7 illustrates a light emitting device having a bottom emission structure in which light from the light emitting element 540 is extracted through the substrate 500.

As the transistor 510, any of the transistors described in any of Embodiments 1 to 3 can be used. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 420 described in Embodiment 1 is applied is described. The transistor 510 is a bottom-gate transistor.

The transistor 510 includes gate electrode layers 511a and 511b, a gate insulating layer 502, an oxide semiconductor layer 512, and conductive layers 513a and 513b functioning as a source or drain electrode layer.

The transistor 510 is a transistor in which an insulating layer in which an oxygen-excess region is formed by oxygen doping treatment is used as the gate insulating layer 502 and / or the insulating layer 524 which are insulating layers in contact with the oxide semiconductor layer 512. The insulating layer having an oxygen excess region is an insulating layer containing nitrogen as its composition. In this embodiment, an aluminum oxide film is used as the insulating layer 525 provided over the insulating layer 524. Thus, the oxide semiconductor layer 512 can be supplied with oxygen that does not contain impurities such as hydrogen or water that causes a change in characteristics of the transistor 510 and fills oxygen vacancies. Therefore, the transistor 510 has suppressed variation in electrical characteristics.

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 510 having stable electric characteristics using the oxide semiconductor layer 512 of this embodiment illustrated in FIG. Further, such a highly reliable semiconductor device can be manufactured with high yield and high productivity can be achieved.

The capacitor 520 includes conductive layers 521a and 521b, a gate insulating layer 502, an oxide semiconductor layer 522, and a conductive layer 523. The conductive layers 521a and 521b and the conductive layer 523 include the gate insulating layer 502 and the oxide semiconductor layer 522. Capacitance is formed by adopting a structure that sandwiches.

The wiring layer intersection 530 is an intersection between the gate electrode layers 511a and 511b and the conductive layer 533, and the gate electrode layers 511a and 511b and the conductive layer 533 intersect with each other with the gate insulating layer 502 interposed therebetween. .

In this embodiment, a titanium film with a thickness of 30 nm is used as the gate electrode layer 511a and the conductive layer 521a, and a copper thin film with a thickness of 200 nm is used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

As the oxide semiconductor layers 512 and 522, an IGZO film with a thickness of 25 m is used.

An interlayer insulating layer 504 is formed over the transistor 510, the capacitor 520, and the wiring layer intersection 530, and a color filter layer 505 is provided in a region overlapping with the light-emitting element 540 on the interlayer insulating layer 504. An insulating layer 506 functioning as a planarization insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505.

A light-emitting element 540 including a stacked structure in which a first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected to each other when the first electrode layer 541 and the conductive layer 513a are in contact with each other in an opening formed in the insulating layer 506 and the interlayer insulating layer 504 reaching the conductive layer 513a. . Note that a partition 507 is provided so as to cover part of the first electrode layer 541 and the opening.

A photosensitive acrylic film with a thickness of 1500 nm can be used for the insulating layer 506, and a photosensitive polyimide film with a thickness of 1500 nm can be used for the partition 507.

As the color filter layer 505, for example, a chromatic translucent resin can be used. As the chromatic translucent resin, a photosensitive or non-photosensitive organic resin can be used. However, the use of a photosensitive organic resin layer can reduce the number of resist masks, thereby simplifying the process. preferable.

A chromatic color is a color excluding achromatic colors such as black, gray, and white, and the color filter layer is formed of a material that transmits only colored chromatic light. As the chromatic color, red, green, blue, or the like can be used. Further, cyan, magenta, yellow (yellow), or the like may be used. To transmit only colored chromatic light means that the transmitted light in the color filter layer has a peak at the wavelength of the chromatic light. In the color filter layer, the optimum film thickness may be appropriately controlled in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. For example, the thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

In the light-emitting device illustrated in FIG. 8B, a light-emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the pixel portion 4002. Note that although the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4034, the electroluminescent layer 4511, and the second electrode layer 4031, it is not limited to the structure shown. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like.

The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, a photosensitive resin material is used, and openings are formed on the first electrode layers 4034 and 541 so that the side walls of the openings are inclined surfaces formed with continuous curvature. preferable.

The electroluminescent layers 4511 and 542 may be composed of a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layers 4031 and 543 and the partition walls 4510 and 507 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting elements 4513 and 540. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Alternatively, a layer containing an organic compound that covers the light-emitting element 4513 may be formed by an evaporation method so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting elements 4513 and 540.

A space sealed by the substrate 4001, the substrate 4006, and the sealant 4005 is provided with a filler 4514 and sealed. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

In addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4514. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl) Butyl) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, as a display device, electronic paper that drives electronic ink can be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the same readability as paper, low power consumption compared to other display devices, and the advantage that it can be made thin and light. ing.

The electrophoretic display device may have various forms, and a plurality of microcapsules including first particles having a positive charge and second particles having a negative charge are dispersed in a solvent or a solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to display only the color of the particles assembled on one side. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

As described above, the electrophoretic display device is a display using a so-called dielectrophoretic effect in which a substance having a high dielectric constant moves to a high electric field region.

A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Color display is also possible by using particles having color filters or pigments.

Note that the first particle and the second particle in the microcapsule are a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoresis. A kind of material selected from the materials or a composite material thereof may be used.

In addition, a display device using a twisting ball display system can be used as the electronic paper. The twist ball display method is a method in which spherical particles separately painted in white and black are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and the first electrode layer and In this method, a potential difference is generated in the second electrode layer to control the orientation of spherical particles.

6 to 8, as the substrates 4001 and 500 and the substrate 4006, a flexible substrate can be used in addition to a glass substrate, for example, a light-transmitting plastic substrate can be used. . As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. In addition, a metal substrate (metal film) such as aluminum or stainless steel may be used if translucency is not necessary. For example, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

In this embodiment, a silicon nitride film is used as the gate insulating layer 4020a. Further, heat treatment and oxygen doping treatment for dehydration or dehydrogenation are performed using a silicon oxynitride film formed by a plasma CVD method as the gate insulating layer 4020b and the insulating layer 4030 in contact with the oxide semiconductor layer. In addition, the insulating layer 4032 is provided over the insulating layer 4030. In this embodiment, an aluminum oxide film is used as the insulating layer 4032.

An aluminum oxide film has a high blocking effect (blocking effect) that does not allow the film to permeate both impurities such as hydrogen and moisture, and oxygen.

Therefore, the aluminum oxide film is mixed with impurities such as hydrogen and moisture that cause fluctuation in the silicon oxynitride film that has been subjected to heat treatment for dehydration or dehydrogenation and oxygen doping treatment during and after the manufacturing process. And function as a protective film for preventing release of oxygen.

The insulating layers 4021 and 506 functioning as planarization insulating layers can be formed using a heat-resistant organic material such as acrylic, polyimide, benzocyclobutene, polyamide, or epoxy. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

The formation method of the insulating layers 4021 and 506 is not particularly limited, and a doctor knife such as a sputtering method, spin coating, dip, spray coating, droplet discharge method (inkjet method), screen printing, offset printing, and the like depending on the material. A roll coater, a curtain coater, a knife coater or the like can be used.

The display device performs display by transmitting light from a light source or a display element. Therefore, thin films such as a substrate, an insulating layer, and a conductive layer provided in the pixel portion where light is transmitted have a light-transmitting property with respect to light in the visible wavelength region.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) that applies a voltage to the display element, the direction of light to be extracted, the place where the electrode layer is provided, and What is necessary is just to select translucency and reflectivity by the pattern structure of an electrode layer.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin containing titanium oxide. A light-transmitting conductive material such as oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or graphene can be used.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), Metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or the like One or a plurality of types of alloys or metal nitrides thereof can be used.

In this embodiment mode, the light-emitting device illustrated in FIG. 7 is a bottom emission type; therefore, the first electrode layer 541 has a light-transmitting property and the second electrode layer 543 has a reflecting property. Therefore, when a metal film is used for the first electrode layer 541, the film thickness is thin enough to maintain translucency, and when a conductive layer having a light-transmitting property is used for the second electrode layer 543, a conductive material having a reflective property is used. Layers may be stacked.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

As described above, by using any of the transistors described in any of Embodiments 1 to 3, a semiconductor device having various functions can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
A semiconductor device having an image sensor function of reading information on an object can be manufactured using the transistor described in any of Embodiments 1 to 3.

FIG. 9A illustrates an example of a semiconductor device having an image sensor function. FIG. 9A is an equivalent circuit of the photosensor, and FIG. 9B is a cross-sectional view illustrating part of the photosensor.

In the photodiode 602, one electrode is electrically connected to the photodiode reset signal line 658 and the other electrode is electrically connected to the gate of the transistor 640. In the transistor 640, one of a source and a drain is electrically connected to the photosensor reference signal line 672, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor 656. The transistor 656 has a gate electrically connected to the gate signal line 659 and the other of the source and the drain electrically connected to the photosensor output signal line 671.

Note that in a circuit diagram in this specification, a symbol of a transistor using an oxide semiconductor layer is described as “OS” so that the transistor can be clearly identified as a transistor using an oxide semiconductor layer. In FIG. 9A, the transistor 640 and the transistor 656 can be any of the transistors described in any of Embodiments 1 to 3, and are transistors using an oxide semiconductor layer. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 420 described in Embodiment 1 is applied is described. The transistor 640 is a bottom-gate transistor.

FIG. 9B is a cross-sectional view of the photodiode 602 and the transistor 640 in the photosensor. The photodiode 602 and the transistor 640 functioning as a sensor are provided over a substrate 601 (an element substrate) having an insulating surface. Yes. A substrate 613 is provided over the photodiode 602 and the transistor 640 by using an adhesive layer 608.

An insulating layer 631, an insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided over the transistor 640. The photodiode 602 includes an electrode layer 641b formed over the interlayer insulating layer 633, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c sequentially stacked over the electrode layer 641b, and an interlayer insulating layer. An electrode layer 642 provided over the layer 634 and electrically connected to the electrode layer 641b through the first to third semiconductor films, and provided in the same layer as the electrode layer 641b and electrically connected to the electrode layer 642 An electrode layer 641a.

The electrode layer 641b is electrically connected to the conductive layer 643 formed in the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to the conductive layer 645 through the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a semiconductor film having a p-type conductivity type as the first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) as the second semiconductor film 606b, and an n-type conductivity type as the third semiconductor film 606c. A pin type photodiode in which a semiconductor film having the same is stacked is illustrated.

The first semiconductor film 606a is a p-type semiconductor film and can be formed using an amorphous silicon film containing an impurity element imparting p-type conductivity. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing a Group 13 impurity element (eg, boron (B)). Silane (SiH ₄ ) may be used as the semiconductor material gas. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. Alternatively, after an amorphous silicon film not containing an impurity element is formed, the impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing an impurity element by an ion implantation method or the like and then performing heating or the like. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The first semiconductor film 606a is preferably formed to have a thickness greater than or equal to 10 nm and less than or equal to 50 nm.

The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and is formed of an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. Silane (SiH ₄ ) may be used as the semiconductor material gas. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. The second semiconductor film 606b may be formed by an LPCVD method, a vapor deposition method, a sputtering method, or the like. The second semiconductor film 606b is preferably formed to have a thickness greater than or equal to 200 nm and less than or equal to 1000 nm.

The third semiconductor film 606c is an n-type semiconductor film and is formed using an amorphous silicon film containing an impurity element imparting n-type conductivity. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor material gas containing a Group 15 impurity element (eg, phosphorus (P)). Silane (SiH ₄ ) may be used as the semiconductor material gas. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. Alternatively, after an amorphous silicon film not containing an impurity element is formed, the impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing an impurity element by an ion implantation method or the like and then performing heating or the like. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The third semiconductor film 606c is preferably formed to have a thickness greater than or equal to 20 nm and less than or equal to 200 nm.

In addition, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi Amorphous Semiconductor: SAS)) may be formed using a semiconductor.

Further, since the mobility of holes generated by the photoelectric effect is smaller than the mobility of electrons, the pin type photodiode exhibits better characteristics when the p type semiconductor film side is the light receiving surface. Here, an example is shown in which light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed is converted into an electrical signal. In addition, since light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film as the light receiving surface becomes disturbance light, a conductive layer having a light shielding property is preferably used as the electrode layer. The n-type semiconductor film side can also be used as the light receiving surface.

As the insulating layer 631, the insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634, an insulating material is used. Depending on the material, a sputtering method, a plasma CVD method, spin coating, dipping, spray coating, droplets are used. It can be formed using a discharge method (inkjet method), screen printing, offset printing, or the like.

As the insulating layer 631, an oxide insulating layer containing nitrogen as a composition can be used as the inorganic insulating material. For example, a single layer or a stacked layer such as a silicon oxynitride layer or a silicon oxynitride layer is used. Can do.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method is used as the insulating layer 631, and heat treatment and oxygen doping treatment for dehydration or dehydrogenation are performed.

Further, it is preferable that an aluminum oxide film be formed over the silicon oxynitride film that has been subjected to heat treatment and oxygen doping treatment for dehydration or dehydrogenation, and then heat treatment is performed. In this embodiment, an insulating layer 632 is provided over the insulating layer 631, and an aluminum oxide film is used as the insulating layer 632.

An aluminum oxide film has a high blocking effect (blocking effect) that does not allow the film to permeate both impurities such as hydrogen and moisture, and oxygen.

Therefore, the aluminum oxide film is mixed with impurities such as hydrogen and moisture that cause fluctuation in the silicon oxynitride film that has been subjected to heat treatment for dehydration or dehydrogenation and oxygen doping treatment during and after the manufacturing process. And function as a protective film for preventing release of oxygen.

As the interlayer insulating layers 633 and 634, an insulating layer functioning as a planarization insulating layer is preferable in order to reduce surface unevenness. As the interlayer insulating layers 633 and 634, for example, an organic insulating material having heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic insulating material, a single layer or a stacked layer such as a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), or BPSG (phosphorus boron glass) can be used.

By detecting light incident on the photodiode 602, information on the object to be detected can be read. Note that a light source such as a backlight can be used when reading information on the object to be detected.

The transistor 640 is a transistor manufactured by using an insulating layer containing nitrogen for the gate insulating layer and / or the insulating layer 631 in contact with the oxide semiconductor layer and performing oxygen doping treatment on the insulating layer. Thus, oxygen that fills oxygen vacancies in the transistor 640 can be supplied to the oxide semiconductor layer. Thus, the transistor 640 has suppressed variation in electrical characteristics.

Therefore, a highly reliable semiconductor device including the transistor 640 having stable electric characteristics using the oxide semiconductor layer of this embodiment can be provided. In addition, a highly reliable semiconductor device can be manufactured with high yield and high productivity can be achieved.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). As electronic devices, television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound Examples include a playback device, a gaming machine (such as a pachinko machine or a slot machine), and a game housing. Specific examples of these electronic devices are shown in FIGS.

FIG. 10A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001, and an image can be displayed on the display portion 9003. Note that a structure in which the housing 9001 is supported by four legs 9002 is shown. In addition, the housing 9001 has a power cord 9005 for supplying power.

The semiconductor device described in any of the above embodiments can be used for the display portion 9003 and can impart high reliability to the electronic device.

The display portion 9003 has a touch input function. By touching a display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operation or information can be input. It is good also as a control apparatus which controls other household appliances by screen operation by enabling communication with household appliances or enabling control. For example, when the semiconductor device having the image sensor function described in Embodiment 5 is used, the display portion 9003 can have a touch input function.

Further, the hinge of the housing 9001 can be used to stand the screen of the display portion 9003 perpendicular to the floor, which can be used as a television device. In a small room, if a television apparatus with a large screen is installed, the free space becomes narrow. However, if the display portion is built in the table, the room space can be used effectively.

FIG. 10B illustrates a television device 9100. In the television device 9100, a display portion 9103 is incorporated in a housing 9101 and an image can be displayed on the display portion 9103. Note that here, a structure in which the housing 9101 is supported by a stand 9105 is illustrated.

The television device 9100 can be operated with an operation switch included in the housing 9101 or a separate remote controller 9110. Channels and volume can be operated with an operation key 9109 provided in the remote controller 9110, and an image displayed on the display portion 9103 can be operated. The remote controller 9110 may be provided with a display portion 9107 for displaying information output from the remote controller 9110.

A television device 9100 illustrated in FIG. 10B includes a receiver, a modem, and the like. The television apparatus 9100 can receive a general television broadcast by a receiver, and is connected to a wired or wireless communication network via a modem so that it can be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (between the sender and the receiver or between the receivers).

The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107, and can provide high reliability to the television device and the remote controller.

FIG. 10C illustrates a computer, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

The semiconductor device described in any of the above embodiments can be used for the display portion 9203 and can give high reliability to the computer.

11A and 11B illustrate a tablet terminal that can be folded. In FIG. FIG. 11A illustrates an open state in which the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, and a fastener 9033. And an operation switch 9038.

The semiconductor device described in any of the above embodiments can be used for the display portion 9631a and the display portion 9631b, so that a highly reliable tablet terminal can be provided.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. Note that in the display portion 9631a, for example, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown, but the structure is not limited thereto. The entire region of the display portion 9631a may have a touch panel function. For example, the entire surface of the display portion 9631a can display keyboard buttons to serve as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 11A illustrates an example in which the display areas of the display portion 9631b and the display portion 9631a are the same; however, there is no particular limitation, and one size may differ from the other size, and the display quality may also be different. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 11B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar cell 9633, and a charge / discharge control circuit 9634. Note that FIG. 11B illustrates a structure including a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 11A and 11B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date, or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge / discharge control circuit 9634 illustrated in FIG. 11B are described with reference to a block diagram in FIG. FIG. 11C illustrates a solar cell 9633, a battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are illustrated. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described. The power generated by the solar battery is boosted or lowered by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off SW1 and turning on SW2.

Note that the solar cell 9633 is described as an example of the power generation unit, but is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). There may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

In this example, oxygen doping treatment was performed on an insulating layer containing nitrogen used in the semiconductor device according to the disclosed invention, and the effect of the oxygen doping treatment was evaluated. In this example, oxygen plasma treatment using an ashing apparatus was performed as oxygen doping treatment. The results are shown in FIG. As an evaluation method, a TDS (Thermal Desorption Spectroscopy) analysis method was used.

A method for manufacturing a sample used for evaluation in this example is described below. In this example, a silicon oxynitride film having a thickness of 100 nm was formed on a silicon substrate, and this was used as a comparative sample A. Moreover, the oxygen dope process was given to the comparative sample A, and this was made into the Example sample B.

In Comparative Sample A and Example Sample B, a plasma CVD apparatus was used to form a silicon oxynitride film. The deposition conditions are SiH ₄ and N ₂ O (SiH ₄ : N ₂ O = 20 sccm: 3000 sccm) as a deposition gas, the pressure is 40 Pa, the substrate temperature is 350 ° C., and the radio frequency (RF) power supply power Was set to 1000W.

In Example Sample B, the conditions for the oxygen doping treatment were ICP (Inductively Coupled Plasma) power of 0 W, bias power of 5000 W, pressure of 15.0 Pa, and O ₂ gas flow rate of 250 sccm. ( ¹⁶ O: ¹⁸ O = 150 sccm: 100 sccm).

FIG. 12A shows a TDS result of M / z = 30 (NO) measured in Example Sample B in which the silicon oxynitride film was subjected to oxygen doping treatment. FIG. 12B shows a TDS result of M / z = 30 (NO) measured in the comparative sample A not subjected to oxygen doping treatment.

As shown in FIGS. 12 (A) and 12 (B), from the sample B subjected to the oxygen doping treatment, nitrogen monoxide (NO) is released from the silicon oxynitride film. In the comparative sample A that had not been processed, it was below the background of TDS measurement.

From the above results, it was confirmed that by performing oxygen doping treatment on the insulating layer containing nitrogen, a bond between nitrogen contained in the film and the introduced oxygen was formed.

Therefore, by applying the insulating layer as an insulating layer in contact with the oxide semiconductor layer, oxygen extraction from the oxide semiconductor layer by the insulating layer can be suppressed or prevented. Oxygen deficiency can be suppressed.

400 Substrate 401 Gate electrode layer 402 Gate insulating layer 402a Gate insulating layer 402b Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Interlayer insulating layer 407a Interlayer insulating layer 407b Interlayer insulating layer 412 Gate insulating layer 412a Gate insulating layer Layer 412b gate insulating layer 417 interlayer insulating layer 417a interlayer insulating layer 417b interlayer insulating layer 420 transistor 422b gate insulating layer 427a interlayer insulating layer 430 transistor 440 transistor 452 oxygen 454 oxygen 500 substrate 502 gate insulating layer 504 interlayer insulating layer 505 color filter layer 506 Insulating layer 507 Partition 510 Transistor 511a Gate electrode layer 511b Gate electrode layer 512 Oxide semiconductor layer 513a Conductive layer 513b Conductive layer 520 Capacitance element 521a Conduction Layer 521b conductive layer 522 oxide semiconductor layer 523 conductive layer 524 insulating layer 525 insulating layer 530 wiring layer intersection 533 conductive layer 540 light emitting element 541 electrode layer 542 electroluminescent layer 543 electrode layer 601 substrate 602 photodiode 606a semiconductor film 606b semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating layer 632 Insulating layer 633 Interlayer insulating layer 634 Interlayer insulating layer 640 Transistor 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal Line 671 Photosensor output signal line 672 Photosensor reference signal line 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scan line driver circuit 4005 Seal material 4006 Substrate 4008 Liquid crystal layer 4 10 4011 transistor 4013 liquid crystal element 4015 connection terminal electrode 4016 terminal electrodes 4018 FPC
4019 Anisotropic conductive layer 4020a Gate insulating layer 4020b Gate insulating layer 4021 Insulating layer 4030 Insulating layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4034 Electrode layer 4035 Spacer 4038 Insulating layer 4040 Transistor 4510 Partition 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling Material 9000 Table 9001 Housing 9002 Leg 9003 Display 9004 Display button 9005 Power cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television apparatus 9101 Housing 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation key 9110 Remote controller 9201 Main body 9202 Case 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Port Inting device 9630 Enclosure 9631 Display unit 9631a Display unit 9631b Display unit 9632a Region 9632b Region 9633 Solar cell 9634 Charge / discharge control circuit 9635 Battery 9636 DCDC converter 9637 Converter 9638 Operation key 9639 Button

Claims (1)

Forming a gate electrode layer;
Forming a gate insulating layer above the gate electrode layer;
A region that is non-single-crystal and has a c-axis oriented in a range of 85 ° to 95 ° with respect to a formation surface so as to have a region overlapping with the gate electrode layer above the gate insulating layer. Forming an oxide semiconductor layer having,
Forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;
An insulating layer having a region overlapping with the oxide semiconductor layer is formed above the source electrode layer and the drain electrode layer;
After adding nitrogen to the insulating layer, oxygen is added,
A method for manufacturing a semiconductor device, wherein heat is applied to supply oxygen in the insulating layer to the oxide semiconductor layer.

Images