JP5866614B1 - Switching power supply - Google Patents

Abstract

In a switching power supply device having a phase shift full bridge type DC / DC converter, an increase in size can be suppressed and high power conversion efficiency can be realized. A switching power supply apparatus includes a power factor correction circuit, a phase shift full bridge DC / DC converter having a full bridge type switching circuit, which is provided downstream of the power factor correction circuit, and is supplied to a load. An output current detection circuit that detects an output current, an output voltage detection circuit that detects an output voltage supplied to a load, and a PFC output voltage detection that detects a PFC output voltage input from the power factor correction circuit to the DC / DC converter And a controller that dynamically changes the dead time of the full-bridge switching circuit based on the PFC output voltage, output current, and output voltage, and the controller applies the changed dead time. A configuration for performing switching control of a full bridge type switching circuit is adopted. [Selection] Figure 4

Description

  The present invention relates to a switching power supply device having a phase shift full bridge type DC / DC converter.

  There have been phase / full bridge DC / DC converters. As shown in FIG. 1, the phase shift full bridge DC / DC converter includes a full bridge type switching circuit 31 having four switching elements Sa, Sb, Sc, and Sd. In the DC / DC converter of the phase shift full bridge system, as shown in the time charts of FIGS. 2A to 2D, the four switching elements Sa, Sb, Sc, and Sd are switched, depending on the load. Output power.

  In the full bridge type switching circuit, the input voltage Vi is output to the primary winding of the transformer Tr during the period Ton1 when both of the pair of switching elements Sa and Sd are turned on, and current flows through the switching elements Sa and Sd to the transformer Tr. Flowing. Further, during the period Ton2 when both of the other pair of switching elements Sb and Sc are turned on, the input voltage Vi is output in the reverse direction to the primary winding of the transformer Tr, and reversely passes through the switching elements Sb and Sc to the transformer Tr. Current flows.

  The four switching elements Sa, Sb, Sc, Sd are subjected to switching control with a predetermined duty ratio. The duty ratio is a value obtained by adding or subtracting the dead times Td1 and Td2 to 50%. When the load changes, the period Ton1 in which a current flows through the switching elements Sa and Sd is changed by changing the switching phase between one of the pair of switching elements Sa and Sd. Similarly, by changing the switching phase between one of the other pair of switching elements Sb and Sc and the other, the period Ton2 in which current flows in the switching elements Sb and Sc is changed. Thereby, according to the change of load, the period Ton1 and Ton2 in which an electric current flows increases / decreases, and output electric power changes.

  Further, in the phase shift full bridge type DC / DC converter, ZVS (Zero Voltage Switching) control has been conventionally performed to reduce the switching loss.

  In the control of ZVS, a delay is provided between turning off one of the two switching elements Sa and Sb connected in series between the input terminals and not turned on at the same time. This delay is the dead time Td1. Similarly, a dead time Td2 is provided between turning on one of the other two switching elements Sc and Sd that are not turned on at the same time (see FIGS. 2A to 2D). reference).

  By providing such dead times Td1, Td2, each of the switching elements Sa, Sb, Sc, Sd is turned on after the voltages Va, Vb, Vc, Vd at both ends become zero volts (FIG. 2 (e)). -See (h)). Both-end voltages Va, Vb, Vc, and Vd are source-drain voltages if the switching elements Sa, Sb, Sc, and Sd are FETs.

  When the voltage Va, Vb, Vc, Vd at both ends becomes zero volts, and the switching elements Sa, Sb, Sc, Sd are turned on, the on-resistance becomes an intermediate value between zero and infinity. It is possible to suppress a current from flowing through each of the switching elements Sa, Sb, Sc, and Sd during a certain period. Therefore, power (switching loss) consumed by each switching element Sa, Sb, Sc, Sd is reduced. The dead times Td1 and Td2 are normally set to ¼ of the resonance period determined from the inductance and capacitance values included in the circuit opened and closed by the switching elements Sa, Sb, Sc and Sd. The inductance and the capacitance value that cause resonance are, for example, the resonance inductor Lr and the parasitic capacitance Cr of the switching elements Sa, Sb, Sc, and Sd.

  Conventionally, a technique for further improving power conversion efficiency has been proposed in a ZVS-controlled phase shift full-bridge DC / DC converter (see, for example, Patent Document 1).

  In Patent Document 1, a saturable choke coil is provided after four switching elements connected in a full-bridge type, and the circuit inductance is changed according to the size of the load, thereby reducing wasteful power loss. doing. In Embodiment 2 of Patent Document 1, the standard dead time changes in accordance with the change in inductance of the saturable choke coil. Therefore, the ZVS control is performed by dynamically setting the dead time in accordance with the changing standard dead time.

JP 2013-188015 A

  In the DC / DC converter of the phase shift full bridge system, the resonance waveform generated in the full bridge type switching circuit may change from the standard waveform depending on the magnitude of the output or the magnitude of the input. Therefore, in the DC / DC converter of the phase shift full bridge system, the power conversion efficiency may be lowered due to the change of the resonance waveform based on the change of input / output.

  In Patent Document 1, since the inductance value of the saturable choke coil changes according to the output level, the standard resonance period also changes accordingly. Therefore, in Patent Document 1, the dead time is set so as to match the change in the standard resonance period. In Patent Document 1, the dead time is simply controlled so as to increase as the output current value increases (see paragraph 0061 of Patent Document 1). In such control, it is difficult to cope with a case where the resonance waveform changes from a standard waveform.

  Furthermore, the technique of Patent Document 1 has a problem that the power supply device is increased in size by newly providing a saturable choke coil.

  An object of the present invention is to suppress an increase in size and realize high power conversion efficiency in a switching power supply device having a phase shift full-bridge DC / DC converter.

A switching power supply according to an aspect of the present invention is a switching power supply that converts input power input from an AC power supply and supplies it to a load, and is provided at a stage subsequent to the power factor improvement circuit and the power factor improvement circuit. A phase shift full bridge DC / DC converter having a full bridge type switching circuit, an input current detection circuit for detecting an input current input from the AC power supply, and an input voltage input from the AC power supply. An input voltage detection circuit for detecting, an output current detection circuit for detecting an output current supplied to the load, an output voltage detection circuit for detecting an output voltage supplied to the load, and the DC from the power factor improvement circuit / includes a PFC output voltage detection circuit for detecting the PFC output voltage input to the DC converter, de prior SL full bridge switching circuit And a control unit which dynamically changes Dotaimu, the power factor correction circuit is a power factor correction circuit of an active type having a switching element which is switching-controlled by the control unit, the PFC Controlling the switching element of the power factor correction circuit so that an output voltage becomes a target voltage determined based on the input current, the input voltage, the output current, and the output voltage, and the PFC output voltage The dead time is dynamically changed based on the output current and the output voltage, and the changed dead time is applied to perform switching control of the full bridge switching circuit.

  A switching power supply according to an aspect of the present invention is a switching power supply that converts input power input from an AC power supply and supplies it to a load, and is provided at a stage subsequent to the power factor improvement circuit and the power factor improvement circuit. A phase shift full bridge DC / DC converter having a full bridge type switching circuit, an output current detection circuit for detecting an output current supplied to the load, and an output voltage supplied to the load An output voltage detection circuit; and a control unit that dynamically changes a dead time of the full-bridge switching circuit based on the output current and the output voltage, and the control unit uses the changed dead time. The configuration is applied to perform switching control of the full bridge type switching circuit.

  A switching power supply according to an aspect of the present invention is a switching power supply that converts input power into power and supplies it to a load, and includes a phase shift full-bridge DC / DC converter having a full-bridge switching circuit, An output current detection circuit for detecting an output current supplied to a load; an output voltage detection circuit for detecting an output voltage supplied to the load; and the full-bridge switching circuit based on the output current and the output voltage. A control unit that dynamically changes the dead time, and the control unit applies the changed dead time to perform switching control of the full-bridge switching circuit.

  According to the present invention, it is possible to suppress an increase in size and realize high power conversion efficiency in a switching power supply device having a phase shift full bridge DC / DC converter.

Circuit diagram showing basic part of DC / DC converter of phase shift full bridge system Time chart explaining operation of phase shift full bridge type DC / DC converter Configuration diagram of a switching power supply device according to an embodiment of the present invention Waveform diagrams showing first and second examples of resonance waveforms that change according to input and output Waveform diagrams showing third and fourth examples of resonance waveforms that change according to input / output Waveform diagrams showing fifth and sixth examples of resonance waveforms that change according to input and output Waveform diagrams showing seventh and eighth examples of resonance waveforms that change according to input and output

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a configuration diagram of the switching power supply device according to the embodiment of the present invention.

  The switching power supply according to the embodiment of the present invention includes an AC / DC converter 10, a DC / DC converter 30, a control unit 40, and a data table 50. Although not particularly limited, in the example of FIG. 3, a storage battery that outputs the power of the electric vehicle is employed as the load 60.

  The AC / DC converter 10 converts the power of the AC power supply Vs so as to suppress the backflow of the harmonics to the AC power supply Vs, and outputs a DC voltage. The AC / DC converter 10 is an active type having a rectifier circuit 11 that rectifies an AC power supply Vs, a smoothing capacitor C10 that smoothes the rectified voltage, and choke coils L11 and L12, switching elements S11 and S12, and a smoothing capacitor C21. Power factor correction circuit (PFC circuit) 13. The switching elements S11 and S12 are switching-controlled by the control unit 40.

  The AC / DC converter 10 further includes an input voltage detector 14 that detects an input voltage (rectified voltage) to the PFC circuit 13 and an input current detector 15 that detects an input current to the PFC circuit 13. The input voltage detection signal of the input voltage detection unit 14 and the input current detection signal of the input current detection unit 15 are sent to the control unit 40. Note that the input voltage detection unit 14 and the input current detection unit 15 may be provided after the smoothing capacitor C10.

  The AC / DC converter 10 further includes a PFC output voltage detection unit 22 that detects the output voltage of the PFC circuit 13. The PFC output voltage detection signal of the PFC output voltage detection unit 22 is sent to the control unit 40.

  The DC / DC converter 30 is a circuit of a phase shift / full bridge type PWM (Pulse Width Modulation) power source, receives a voltage from the AC / DC converter 10 and outputs electric power corresponding to the load 60. The DC / DC converter 30 includes a full bridge type switching circuit 31 in which four switching elements Sa, Sb, Sc, Sd are connected in a full bridge type, a resonance coil Lr, a transformer Tr, a rectifier circuit 32, and a choke. It has a coil L31 and a bypass capacitor C31.

  The DC / DC converter 30 further includes an output current detection unit 34 that detects an output current and an output voltage detection unit 35 that detects an output voltage. The output current detection signal of the output current detection unit 34 and the output voltage detection signal of the output voltage detection unit 35 are sent to the control unit 40.

  Each of the switching elements Sa, Sb, Sc, and Sd is a MOSFET (metal-oxide-semiconductor field-effect transistor), for example, and both terminals (source terminal and drain terminal) are controlled by controlling a control terminal (gate terminal). ) To supply current. When the resistance between both terminals of the switching elements Sa, Sb, Sc, Sd is substantially zero resistance (on) and non-conduction (off), the power consumed by the switching elements Sa, Sb, Sc, Sd Becomes almost zero. On the other hand, when the switching elements Sa, Sb, Sc, and Sd are switched from on to off or from off to on, an on-resistance between zero and infinity occurs between both terminals. For this reason, if a current flows during this period, power is consumed and a switching loss occurs.

  Each of the switching elements Sa, Sb, Sc, and Sd has, for example, a parasitic capacitance Cr (not shown) at one end of the parasitic diode.

  Note that the switching elements Sa, Sb, Sc, and Sd are elements that can be turned on / off by control of a control terminal, such as an IGBT (Insulated Gate Bipolar Transistor), so that a large current can flow between the two terminals. Any element may be applied.

  In the full bridge type switching circuit 31, the primary winding of the transformer Tr is connected between the two output nodes n1 and n2. The switching elements Sa, Sb, Sc, and Sd are subjected to switching control by the control unit 40 as shown in the time charts of FIGS. In the period Ton1 in which the switching elements Sa and Sd are turned on, a forward voltage is output between the two output nodes n1 and n2. Further, in the period Ton2 in which the switching elements Sb and Sc are turned on, a reverse voltage is output between the two output nodes n1 and n2. As a result, the full bridge type switching circuit 31 outputs a current that periodically changes the direction between the forward direction and the reverse direction to the transformer Tr.

The resonance coil Lr is connected in series with the primary winding of the transformer Tr between the two output nodes n1 and n2 of the full bridge type switching circuit 31. By switching control, when a current is output between the output nodes n1 and n2, any of the switching elements Sa, Sb, Sc, and Sd is turned off so as to cut off the current. At this time, resonance occurs between the parasitic capacitance Cr of the turned-off switching element and the resonance coil Lr by the resonance coil Lr and the parasitic capacitance Cr of the switching elements Sa, Sb, Sc, and Sd. A quarter period T0 of this resonance is expressed by the following equation (1).

  When the transformer Tr receives a periodically changing current from the full bridge type switching circuit 31, the transformer Tr outputs a voltage that similarly changes to the secondary winding. The transformer Tr ensures insulation between the primary winding side and the secondary winding side. The rectifier circuit 32 rectifies the output voltage of the transformer Tr and outputs it to the choke coil L31. The choke coil L31 causes a direct current to flow according to the voltage of the rectifier circuit 32 and outputs it to the load 60. The bypass capacitor C31 suppresses fluctuations in the output voltage.

  Hereinafter, the control unit 40 and the data table 50 according to the first to third embodiments will be described.

<Embodiment 1>
In the first embodiment, the control unit 40 determines the optimum dead times Td1 and Td2 with reference to the output current and the output voltage supplied to the load 60. Details of the dead times Td1 and Td2 will be described later.

  The data table 50 of the first embodiment has a data table in which the output voltage and output current supplied to the load 60 are associated with the optimum dead times Td1 and Td2.

  The control unit 40 of the first embodiment outputs a PFC switching signal to the control terminals of the switching elements S11 and S12 of the PFC circuit 13 to turn on and off the switching elements S11 and S12. Thereby, the control part 40 controls the PFC circuit 13 so that the target PFC output voltage (for example, 400V) is obtained, and the harmonics which flow out into AC power supply Vs are suppressed.

  The control unit 40 outputs a DC / DC switching signal to the control terminals of the switching elements Sa, Sb, Sc, Sd, and controls on / off of the switching elements Sa, Sb, Sc, Sd. Thereby, the DC / DC converter 30 operates so that an output voltage and an output current corresponding to the load 60 are obtained. Next, details of the control of the DC / DC converter 30 will be described with reference to FIGS.

  2A is a time chart showing on / off of the switching element Sa, FIG. 2B is a time chart showing on / off of the switching element Sb, and FIG. 2C is an on state of the switching element Sc. FIG. 2D is a time chart showing ON / OFF of the switching element Sd, FIG. 2E is a time chart of the voltage Va across the switching element Sa, and FIG. FIG. 2G is a time chart of the voltage Vc across the switching element Sc, and FIG. 2H is a time chart of the voltage Vd across the switching element Sd.

  The control unit 40 first performs phase shift control of the DC / DC converter 30 according to the load 60. In the phase shift control, the control unit 40 performs switching control of the four switching elements Sa, Sb, Sc, Sd with a predetermined duty ratio. When the load 60 changes, the control unit 40 changes the switching phase between one and the other of the pair of switching elements Sa and Sd. As a result, the period Ton1 during which current flows in the switching elements Sa and Sd changes. Similarly, the control unit 40 changes the switching phase between one of the other pair of switching elements Sb and Sc and the other. Thereby, the period Ton2 in which a current flows in the switching elements Sb and Sc changes. By such control, according to the change of the load 60, the periods Ton1 and Ton2 in which the current flows are increased and decreased, and the output power is changed.

  The control unit 40 further performs ZVS control of the DC / DC converter 30. In the ZVS control, the control unit 40 provides a dead time Td1 from turning off one of the two switching elements Sa and Sb that are not turned on at the same time to turning on the other. Similarly, a dead time Td2 is provided from when one of the two switching elements Sc and Sd that are not simultaneously turned on is turned on to the other.

  The control unit 40 determines the dead times Td1 and Td2 using the data table 50 based on the output voltage detection signal and the output current detection signal. The data table 50 stores the values of the optimum dead times Td1 and Td2 for each output voltage and output current, and the control unit 40 performs ZVS control using these values.

  The dead time Td1 from when the switching element Sb is turned off to when the switching element Sa is turned on will be described. By using the optimum value of the dead time Td1, the voltage Va (source-drain voltage) across the switching element Sa can be made zero at the end of the dead time Td1 period (see FIG. 2 (e)). reference). Even if the resonance waveform of the dead time Td1 is changed from the standard, the dead time Td1 different from the standard dead time value is used, so that the voltage Va across the switching element Sa is zero at the end of the dead time Td1 period. Can be. Thereby, a switching loss can be made very low.

  The same applies to the dead time Td1 from when the switching element Sa is turned off to when the switching element Sb is turned on, and the dead time Td2 related to the switching elements Sc and Sd.

<Description of optimum dead times Td1 and Td2>
Next, the optimum dead times Td1 and Td2 stored in the data table 50 will be described in detail.

  FIG. 4 is a waveform diagram showing a first example and a second example of a resonance waveform that changes according to the output. FIG. 4A is a standard waveform diagram, and FIG. 4B is a waveform diagram changed from the standard. FIG. 5 is a waveform diagram showing a third example and a fourth example of resonance waveforms that change according to the output. FIG. 5A is a standard waveform diagram, and FIG. 5B is a waveform diagram changed from the standard. 4 and 5 show waveforms when resonance is continued without switching on / off the switching elements Sa, Sb, Sc, and Sd at the end of the dead times Td1 and Td2. .

  The optimum dead times Td1 and Td2 are determined in advance based on a resonance waveform obtained from a simulation considering details of a circuit or a resonance waveform obtained by actually measuring a circuit in operation. As the circuit parameters, an output voltage and an output current are selected. By performing simulation or actual measurement according to a plurality of assumed parameters, it is possible to obtain optimum dead times Td1 and Td2 corresponding to a plurality of assumed operating states.

  Next, the dead time Td1 when the switching element Sa is turned on after the switching element Sb is turned off will be described. Since the dead time Td1 when the switching element Sb is turned on after the switching element Sa is turned off and the dead time Td2 related to the switching elements Sc and Sd are the same as the following, detailed description thereof is omitted.

<First example>
FIG. 4A shows a resonance waveform generated between the two output nodes n1 and n2 of the full bridge type switching circuit 31 when the output of the DC / DC converter 30 is an output voltage of 400V and an output current of 9A. ing.

  In the case of this parameter, description will be made assuming that a standard resonance waveform is obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. Voltage Vds) is zero.

  Therefore, the optimum dead time Td1 corresponding to this parameter is 1/4 of the standard LC resonance period, and this value is registered in the data table 50.

<Second example>
FIG. 4B shows a resonance waveform generated between the two output nodes n1 and n2 of the full bridge switching circuit 31 when the output of the DC / DC converter 30 is an output voltage of 400V and an output current of 18A. ing. Note that the PFC output voltages in FIGS. 4A and 4B are the same.

  In the case of this parameter, description will be made assuming that a resonance waveform different from the standard can be obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is lower than zero, and the timing when the both-end voltage Va becomes zero is earlier than ¼ of the LC resonance period.

  Therefore, the optimum dead time Td1 corresponding to this parameter is a value shorter than 1/4 of the standard LC resonance period (Td1 in FIG. 4B), and this value is registered in the data table 50. .

<Third example>
FIG. 5A shows a state between the two output nodes n1 and n2 of the full bridge type switching circuit 31 when the output of the DC / DC converter 30 is an output voltage of 400 V and an output current of 9 A (output power 3.6 kW). The resonance waveform generated in FIG.

  In the case of this parameter, description will be made assuming that a standard resonance waveform is obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is zero.

  Therefore, the optimum dead time Td1 corresponding to this parameter is 1/4 of the standard LC resonance period, and this value is registered in the data table 50.

<Fourth example>
FIG. 5B shows a state between the two output nodes n1 and n2 of the full bridge type switching circuit 31 when the output of the DC / DC converter 30 is an output voltage of 200 V and an output current of 18 A (output power 3.6 kW). The resonance waveform generated in FIG. In FIG. 5 (b), parameters are set so that the output power is the same as in FIG. 5 (a). Note that the PFC output voltages in FIGS. 5A and 5B are the same.

  In the case of this parameter, description will be made assuming that a resonance waveform different from the standard can be obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is lower than zero, and the timing when the both-end voltage Va becomes zero is earlier than ¼ of the LC resonance period.

  Therefore, the optimum dead time Td1 corresponding to this parameter is a value shorter than 1/4 of the standard LC resonance period (Td1 in FIG. 5B), and this value is registered in the data table 50. .

  In the first to fourth examples, a standard resonance waveform and an example of a resonance waveform different from the standard are shown. However, the resonance waveform different from the standard is variously deformed depending on the parameters of the output voltage and the output current. Therefore, the parameter values are changed in various ways, the simulation or the actual measurement of the circuit is performed, the optimum dead times Td1 and Td2 corresponding to the respective parameter values are obtained in advance, and these are registered in the data table 50. Thereby, the optimum ZVS control is achieved by the optimum dead times Td1 and Td2, and the switching loss can be greatly reduced.

<Embodiment 2>
In the second embodiment, the control unit 40 determines the optimum dead times Td1 and Td2 by referring to the PFC output voltage in addition to the output voltage and the output current.

  The data table 50 according to the second embodiment has a data table in which the PFC output voltage, the output voltage and output current supplied to the load 60, and the optimum dead times Td1 and Td2 are associated with each other.

  The control unit 40 of the second embodiment outputs a PFC switching signal to the control terminals of the switching elements S11 and S12 of the PFC circuit 13, and turns on / off the switching elements S11 and S12. Thereby, the control part 40 controls the PFC circuit 13 so that the target PFC output voltage (for example, 400V) is obtained, and the harmonics which flow out into AC power supply Vs are suppressed.

  The control unit 40 determines the dead times Td1 and Td2 using the data table 50 based on the PFC output voltage, the output voltage detection signal, and the output current detection signal. Further, the control unit 40 outputs a DC / DC switching signal to the control terminals of the switching elements Sa, Sb, Sc, and Sd, and controls on / off of the switching elements Sa, Sb, Sc, and Sd. Thereby, the DC / DC converter 30 operates so that an output voltage and an output current corresponding to the load 60 are obtained.

<Description of optimum dead times Td1 and Td2>
Next, the optimum dead times Td1 and Td2 stored in the data table 50 will be described in detail.

  FIG. 6 is a waveform diagram showing fifth and sixth examples of resonance waveforms that change according to input and output. FIG. 6A is a standard waveform diagram, and FIG. 6B is a waveform diagram changed from the standard. FIG. 7 is a waveform diagram showing a seventh example and an eighth example of resonance waveforms that change according to input / output. FIG. 7A is a standard waveform diagram, and FIG. 7B is a waveform diagram changed from the standard. 6 and 7 show waveforms when resonance is continued without switching on / off of the switching elements Sa, Sb, Sc, Sd at the end of the dead times Td1, Td2. .

  The optimum dead times Td1 and Td2 are determined in advance based on a resonance waveform obtained from a simulation considering details of a circuit or a resonance waveform obtained by actually measuring a circuit in operation. As circuit parameters, PFC output voltage, output voltage and output current are selected. By performing simulation or actual measurement according to a plurality of assumed parameters, it is possible to obtain optimum dead times Td1 and Td2 corresponding to a plurality of assumed operating states.

  Next, the dead time Td1 when the switching element Sa is turned on after the switching element Sb is turned off will be described. Since the dead time Td1 when the switching element Sb is turned on after the switching element Sa is turned off and the dead time Td2 related to the switching elements Sc and Sd are the same as the following, detailed description thereof is omitted.

<Fifth example>
FIG. 6A shows the resonance that occurs between the two output nodes n1 and n2 of the full-bridge switching circuit 31 when the PFC output voltage is 400V, the output voltage of the DC / DC converter 30 is 300V, and the output current is 9A. The waveform is shown.

  In the case of this parameter, description will be made assuming that a standard resonance waveform is obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. Voltage Vds) is zero.

  Therefore, the optimum dead time Td1 corresponding to this parameter is 1/4 of the standard LC resonance period, and this value is registered in the data table 50.

<Sixth example>
FIG. 6B shows resonance that occurs between the two output nodes n1 and n2 of the full-bridge switching circuit 31 when the PFC output voltage is 350V, the output voltage of the DC / DC converter 30 is 300V, and the output current is 9A. The waveform is shown.

  In the case of this parameter, description will be made assuming that a resonance waveform different from the standard can be obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is lower than zero, and the timing when the both-end voltage Va becomes zero is earlier than ¼ of the LC resonance period.

  Therefore, the optimum dead time Td1 corresponding to this parameter is a value shorter than 1/4 of the standard LC resonance period (Td1 in FIG. 6B), and this value is registered in the data table 50. .

<Seventh example>
FIG. 7A shows the resonance that occurs between the two output nodes n1 and n2 of the full-bridge switching circuit 31 when the PFC output voltage is 400V, the output voltage of the DC / DC converter 30 is 300V, and the output current is 9A. The waveform is shown.

  In the case of this parameter, description will be made assuming that a standard resonance waveform is obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is zero.

  Therefore, the optimum dead time Td1 corresponding to this parameter is 1/4 of the standard LC resonance period, and this value is registered in the data table 50.

<Eighth example>
FIG. 7B shows the resonance generated between the two output nodes n1 and n2 of the full-bridge switching circuit 31 when the PFC output voltage is 400V, the output voltage 350V of the DC / DC converter 30 and the output current 9A. The waveform is shown.

  In the case of this parameter, description will be made assuming that a resonance waveform different from the standard can be obtained. That is, the voltage Va (source / drain) of the switching element Sa that is turned on next is ¼ of the LC resonance period obtained from the inductance value of the resonance coil Lr and the capacitance value of the parasitic capacitance Cr of the switching element Sa. The voltage Vds) is lower than zero, and the timing when the both-end voltage Va becomes zero is earlier than ¼ of the LC resonance period.

  Therefore, the optimum dead time Td1 corresponding to this parameter is a value shorter than 1/4 of the standard LC resonance period (Td1 in FIG. 7B), and this value is registered in the data table 50. .

  In the second embodiment, the optimum dead times Td1 and Td2 are determined by referring to the PFC output voltage in addition to the output voltage and the output current. Therefore, the load applied to the DC / DC converter 30 can be assumed more accurately, and the dead times Td1 and Td2 that can significantly suppress the switching loss can be used.

<Embodiment 3>
In the third embodiment, the control unit 40 further determines the PFC output voltage based on the input of the PFC circuit 13 and the output of the DC / DC converter 30. Then, the control unit 40 determines optimum dead times Td1 and Td2 based on the PFC output voltage, output voltage, and output current. A control unit that controls the PFC output voltage and a control unit that controls the dead time may be provided separately.

  The data table 50 according to the third embodiment includes first data in which the input voltage and input current of the PFC circuit 13, the output voltage and output current supplied to the load 60, and the target PFC output voltage are associated with each other. Has a table.

  In this embodiment, the case where the input voltage, the input current, the output voltage, and the output current are associated with the target PFC output voltage is exemplified. For example, the input voltage, the output voltage, the target PFC, It may be a data table in which the PFC output voltage is associated. Instead of detecting all of the input voltage, input current, output voltage, and output current, three of the input voltage, input current, output voltage, and output current are detected, and the remaining one is the three detections. It may be estimated from the result.

  The data table 50 further includes a second data table in which the PFC output voltage, the output voltage and output current supplied to the load 60, and the optimum dead times Td1 and Td2 are associated with each other.

  The control unit 40 according to the third embodiment outputs a PFC switching signal to the control terminals of the switching elements S11 and S12 of the PFC circuit 13 to turn on and off the switching elements S11 and S12. Thereby, the control unit 40 controls the PFC circuit 13 so that a target PFC output voltage can be obtained and harmonics flowing out to the AC power supply Vs are suppressed.

  The control unit 40 determines a target PFC output voltage based on the input current detection signal, the input voltage detection signal, the output current detection signal, and the output voltage detection signal. At this time, the control unit 40 may obtain a target PFC output voltage using the data table 50.

  The control unit 40 outputs a DC / DC switching signal to the control terminals of the switching elements Sa, Sb, Sc, Sd, and controls on / off of the switching elements Sa, Sb, Sc, Sd. Thereby, the DC / DC converter 30 operates so that an output voltage and an output current corresponding to the load 60 are obtained.

  The control unit 40 determines the dead times Td1 and Td2 using the data table 50 based on the PFC output voltage, the output voltage detection signal, and the output current detection signal. In this case, the data table 50 may store the values of the dead times Td1 and Td2 that are optimal for the PFC output voltage, output voltage, and output current.

  Next, a method for determining the target PFC output voltage will be described in detail.

  In the switching power supply device having the PFC circuit 13 and the DC / DC converter 30, the PFC output voltage is determined based on the input of the PFC circuit 13 and the output of the DC / DC converter 30 in order to improve the power conversion efficiency of the entire switching power supply device. To do. Specifically, the control unit 40 determines the optimum “target target” based on the input data detection signal, the input voltage detection signal, the output current detection signal, the output voltage detection signal, and the first data table included in the data table 50. PFC output voltage "is determined.

  Note that the first data table is basically a table in which the target PFC output voltage increases as the input of the PFC circuit 13 and the output of the DC / DC converter 30 both increase.

  The control unit 40 controls the PFC circuit 13 so as to obtain the determined target PFC output voltage, while using the data table 50 based on the PFC output voltage, the output voltage detection signal, and the output current detection signal. The dead times Td1 and Td2 are determined. The method for determining the dead times Td1 and Td2 is the same as that in the second embodiment, and is therefore omitted.

  In the third embodiment, the PFC output voltage is dynamically changed based on the input of the PFC circuit 13 and the output of the DC / DC converter 30. Thereby, the power conversion efficiency of the whole switching power supply device can be improved.

  Further, in the third embodiment, since the dead times Td1 and Td2 are determined based on the PFC output voltage, the output voltage detection signal, and the output current detection signal, the dead times Td1 and Td2 are also moved along with the change of the PFC output voltage. Can be changed automatically. Thereby, improvement of the power conversion efficiency of the whole switching power supply device and suppression of switching loss can be realized, and high power conversion efficiency can be realized.

  As described above, according to the switching power supply device of the embodiment, even when the resonance waveform obtained by the ZVS control is different from the standard waveform in the phase shift full-bridge DC / DC converter, the standard value is obtained. By using the dead times Td1 and Td2 that are different from the above, switching loss can be significantly suppressed and high power conversion efficiency can be realized. Furthermore, according to the switching power supply device of the embodiment, since the saturable choke coil is not used as in the prior art document 1, it is possible to realize high power conversion efficiency while suppressing an increase in size.

  The embodiments of the present invention have been described above.

  In the above embodiment, the configuration including the AC / DC converter 10 in the previous stage of the DC / DC converter 30 is shown as the switching power supply device. However, the switching power supply device may not include the AC / DC converter 10. In this case, if the PFC output voltage is replaced with the input DC voltage of the DC / DC converter 30 in the description of the embodiment, the same operation as in the embodiment can be obtained.

  Moreover, although the said embodiment showed the structure which determines optimal dead time using a data table, you may determine dead time using a calculation formula.

  In addition, the details specifically described in the embodiments can be changed as appropriate without departing from the spirit of the invention.

  INDUSTRIAL APPLICABILITY The present invention can be used for a switching power supply device having a phase shift full bridge type DC / DC converter.

DESCRIPTION OF SYMBOLS 10 AC / DC converter 11 Rectifier circuit 13 PFC circuit 14 Input voltage detection part 15 Input current detection part 22 PFC output voltage detection part 30 DC / DC converter 31 Full bridge type switching circuit 32 Rectification circuit 34 Output current detection part 35 Output voltage detection Unit 40 Control unit 50 Data table 60 Load L11, L12 Choke coil S11, S12 Switching element C10, C21 Smoothing capacitor Sa, Sb, Sc, Sd Switching element Lr Resonance coil Tr Transformer L31 Choke coil C31 Bypass capacitor

Claims (2)

A switching power supply device that converts input power input from an AC power source and supplies it to a load,
A power factor correction circuit;
A DC / DC converter of a phase shift full bridge system provided at a stage subsequent to the power factor correction circuit and having a full bridge switching circuit;
An input current detection circuit for detecting an input current input from the AC power supply;
An input voltage detection circuit for detecting an input voltage input from the AC power supply;
An output current detection circuit for detecting an output current supplied to the load;
An output voltage detection circuit for detecting an output voltage supplied to the load;
A PFC output voltage detection circuit for detecting a PFC output voltage input from the power factor correction circuit to the DC / DC converter;
A control unit for dynamically changing the dead time provided before the SL full bridge switching circuit,
With
The power factor correction circuit is an active power factor correction circuit having a switching element that is switching-controlled by the controller.
The control unit controls the switching element of the power factor correction circuit so that the PFC output voltage becomes a target voltage determined based on the input current, the input voltage, the output current, and the output voltage. And dynamically changing the dead time based on the PFC output voltage, the output current and the output voltage, and applying the changed dead time to control the switching of the full-bridge switching circuit. Do,
Switching power supply. A data table in which the PFC output voltage, the output current and the output voltage are associated with the dead time;
The data registered in the data table includes the value of the dead time that improves the power conversion efficiency compared to when the dead time is set to ¼ period of resonance generated in the full-bridge switching circuit. And
The control unit dynamically changes the dead time based on the data table.
The switching power supply device according to claim 1 .

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