JP5866215B2 - Dither control circuit - Google Patents

Description

  The present invention relates to a dither control circuit and an audio output system.

  Conventionally, a system including a ΔΣ DAC (Digital Analog Converter) is known. For example, Patent Document 1 discloses a DAC including a delta-sigma modulator and an analog LPF (Low Pass Filter). The delta-sigma modulator converts the input digital audio signal into one bit, converts it into a digital signal, and outputs it. The analog LPF converts the digital signal output from the delta sigma modulator into an analog audio signal. This analog audio signal becomes the DAC output.

JP 2011-019209 A

  However, according to the system including the conventional ΔΣ DAC, the distortion rate may be deteriorated. The distortion rate is a value representing the degree of distortion of the signal, and is represented by the ratio of the entire harmonic component to the fundamental wave component. It is considered that the distortion rate is deteriorated due to an error in the pulse density due to the asymmetry of the rise and fall of the pulse signal that controls the DAC analog part (the input signal of the DAC analog part).

  That is, FIG. 10A shows a waveform of an input signal of a system including a conventional ΔΣ DAC. Reference numeral 101 means near full scale, and reference numeral 102 means near zero cross. FIGS. 10B and 10C are graphs showing waveforms of pulse signals that control the DAC analog unit. FIG. 10B shows a pulse signal near the full scale 101, and FIG. 10C shows a pulse signal near the zero crossing 102.

  As shown in FIGS. 10B and 10C, the pulse signal is asymmetric at the rise and fall. In the vicinity of full scale 101, as shown in FIG. 10B, the amount of change in the pulse signal is small, so that the level conversion error is small. On the other hand, in the vicinity of the zero crossing 102, as shown in FIG. 10C, the amount of change in the pulse signal is large, so that the level conversion error is large. For this reason, as the input level is decreased, the level conversion error near the zero cross 102 gradually appears as distortion, which is considered to deteriorate the dynamic range.

  An object of the present invention is to provide a dither control circuit and an audio output system capable of improving the distortion rate.

According to one aspect of the present invention, a dither generation circuit that generates a dither signal, a level detection circuit that detects a level of an input signal, a coefficient control circuit that controls a coefficient according to a detection result of the level detection circuit, A multiplier that multiplies the dither signal output from the dither generation circuit by the coefficient output from the coefficient control circuit, and the level detection circuit has the input signal having a large signal area, a medium signal area, and a small signal area. The coefficient control circuit performs control so that the dither signal is added only to the input signal belonging to the middle signal range, and from the large signal range or the small signal range, the coefficient control circuit When the sequence shifts to the middle signal range, the soft transition is made so that the dither signal gradually increases, and when the sequence moves from the middle signal range to the large signal range or the small signal range, Dither control circuit for soft transition to serial dither signal gradually decreases is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the dither control circuit and audio | voice output system which can improve a distortion can be provided.

1 is a schematic block diagram illustrating the configuration of an audio output system according to an embodiment. The figure which illustrates the calculation timing at the time of the oversampling which concerns on this Embodiment. FIG. 2 is a schematic circuit block diagram illustrating the configuration of a ΔΣ DAC according to this embodiment. FIG. 3 is a schematic circuit block diagram illustrating the configuration of a dither control circuit according to the present embodiment. It is explanatory drawing of the sequence which concerns on this Embodiment, Comprising: (a) Small signal area, medium signal area, explanatory diagram of large signal area, (b) Sequence state transition diagram, (c) Case with hysteresis FIG. It is a timing chart which illustrates operation | movement of the audio | voice output system which concerns on this Embodiment, Comprising: (a) Input signal, (b) Sequence, (c) Dither signal. It is a timing chart which illustrates other operation | movement of the audio | voice output system which concerns on this Embodiment, Comprising: (a) Input signal, (b) Sequence, (c) Dither signal. It is a graph which illustrates the difference in the characteristic at the time of ON / OFF of a dither signal, (a) The graph which shows the relationship between the magnitude | size (vertical axis) of an output signal, and a frequency (horizontal axis), (b) Distortion rate ( The vertical axis | shaft) and the graph which shows the relationship between the magnitude | size (horizontal axis) of an input signal. The typical block diagram which illustrates other composition of the audio output system concerning this embodiment. It is explanatory drawing of the conventional subject, (a) The graph which shows the waveform of the input signal of the system containing conventional delta-sigma DAC, (b) The graph which shows the full scale vicinity of the pulse signal which controls the conventional DAC analog part, c) A graph showing the vicinity of a zero cross of a pulse signal for controlling a conventional DAC analog unit.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, and structure of each component. The arrangement is not specified below. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[Embodiment]
Hereinafter, embodiments will be described with reference to FIGS.

  The audio output system according to the present embodiment includes an audio DSP (Digital Signal Processor) 10 that performs predetermined audio signal processing on an input signal, and an 8 × oversampling of data at a frequency 8 times the sampling frequency of the input signal. A sampling filter 20, a dither control circuit 70 that generates a dither signal according to the level of the input signal, an adder 30 that adds the dither signal to the input signal, and a digital-analog conversion process on the input signal to which the dither signal is added The ΔΣ DAC 40 and the DAC analog unit 60 are provided.

  Further, the dither control circuit 70 detects whether the input signal belongs to the level of the large signal region P3, the medium signal region P1, P2, or the small signal region P0, and only the input signal belonging to the medium signal region P1, P2. You may control so that a dither signal is added.

  Further, when the sequence shifts from the large signal region P3 or the small signal region P0 to the middle signal region P1, P2, the dither control circuit 70 performs a soft transition so that the dither signal gradually increases, and from the middle signal region P1, P2 When the sequence moves to the large signal range P3 or the small signal range P0, a soft transition may be performed so that the dither signal gradually decreases.

  In the dither control circuit 70, the times t11, t12, t13, and t14 required for each soft transition may be set individually.

  In the dither control circuit 70, the time t14 required for the soft transition when the sequence is shifted from the middle signal range P1, P2 to the large signal range P3 is set shorter than the times t11, t12, t13 required for the other soft transitions. May be.

  The dither control circuit 70 moves the sequence from the large signal area P3 to the intermediate signal area P2 when the input signal in the intermediate signal area P2 is continuously detected for a predetermined time in the state of the large signal area P3, and the intermediate signal areas P1, P2 In this state, when the input signal in the small signal area P0 is continuously detected for a predetermined time, the sequence may be shifted from the middle signal areas P1 and P2 to the small signal area P0.

  Further, the dither control circuit 70 moves the sequence from the small signal region P0 to the middle signal region P1 as soon as it detects the input signal in the middle signal region P1 in the state of the small signal region P0. As soon as an input signal in the large signal range P3 is detected in the state of P2, the sequence may be shifted from the small signal range P0 or the middle signal range P1, P2 to the large signal range P3.

  Further, the dither control circuit 70 may be connected in parallel with the 8-times oversampling filter 20.

(Configuration of audio output system)
FIG. 1 is a schematic block diagram illustrating the configuration of an audio output system according to this embodiment. As shown in FIG. 1, the audio output system includes an audio DSP 10, an 8-times oversampling filter 20, an adder 30, a ΔΣ DAC 40, a 64-bit shift register 50, a DAC analog unit 60, and a dither control circuit 70. It has.

  The audio DSP 10 receives a digital signal, performs audio signal processing such as gain control and tone control, for example, generates a PCM (Pulse Code Modulation) type digital audio signal, and outputs the digital audio signal to the 8-times oversampling filter 20.

  The 8-times oversampling filter 20 oversamples the digital signal and outputs it to the adder 30. Specifically, data is sampled at a frequency (8 fs) that is eight times the sampling frequency fs of the original input signal, and, for example, a sampling frequency of 48 kHz or 44.1 kHz is converted to a PWM frequency of 384 kHz or 352.8 kHz. .

  The 8 × oversampling filter 20 includes an FIR (Finite Impulse Response) filter configured by 2 × 3 stages. Each FIR filter samples at a frequency twice the sampling frequency of the input signal (original). Here, the 8 times oversampling process in the 1 fs period in the 8 times oversampling filter 20 is realized by calculation timings A to N as illustrated in FIG. Each calculation timing A to N performs a calculation operation as follows.

Arithmetic timing A: 2 times oversampling 1st time (2fs)
Calculation timing B: 2nd oversampling second time (2 fs)
Calculation timing C: 2 times oversampling first time (4 fs)
Calculation timing D: 2 times oversampling second time (4 fs)
Arithmetic timing E: 3rd oversampling (4fs)
Calculation timing F: 4 times oversampling (4fs)
Arithmetic timing G: 2 times oversampling 1st time (8fs)
Calculation timing H: Second oversampling second time (8 fs)
Calculation timing I: 2 times oversampling third time (8 fs)
Arithmetic timing J: Double oversampling 4th time (8fs)
Calculation timing K: 5 times oversampling (8 fs)
Calculation timing L: 6 times oversampling (8 fs)
Arithmetic timing M: 7 times oversampling twice (8fs)
Calculation timing N: 2 times oversampling 8th time (8fs)
The dither control circuit 70 generates a dither signal according to the level of the digital audio signal output from the audio DSP 10 and outputs the dither signal to the adder 30. Details of the dither control circuit 70 will be described later.

  The adder 30 adds (adds) the dither signal output from the dither control circuit 70 to the digital audio signal output from the 8-times oversampling filter 20 and outputs the resultant signal to the ΔΣ DAC 40.

  The ΔΣ DAC 40 is a digital part of a delta-sigma (ΔΣ) type DAC, and includes, for example, five integrators 41 to 45 and a quantizer 46 as shown in FIG. The integrators 41 to 45 output the integrated value of the digital signal by adding the digital signal one sampling period before the digital signal. The quantizer 46 quantizes the integral value with 1 bit and outputs a pulse signal. That is, 0 is output when the integral value is a positive number, and 1 is output when the integral value is a negative number. Here, it is assumed that the ΔΣ DAC 40 operates at a frequency (128 fs) that is 128 times the sampling frequency fs of the original input signal.

  The 64-bit shift register 50 temporarily stores the digital signal output from the ΔΣ DAC 40. The DAC analog unit 60 is an analog unit of the DAC, converts the digital signal stored in the 64-bit shift register 50 into an analog signal, and outputs the analog signal.

(Configuration of dither control circuit)
As already described, conventionally, in a system including a ΔΣ DAC, the distortion rate may be deteriorated. Specifically, when the magnitude of the input signal is about −30 dB to −70 dB, the distortion rate is deteriorated. Therefore, in the present embodiment, the input signal is divided into a large signal range (0 dB to −10 dB) P3, a medium signal range (−10 dB to −80 dB) P1 and P2, and a small signal range (−80 dB or less) P0. A dither signal is added only to the areas P1 and P2. The reason why the dither signal is not added in the large signal range P3 is that the distortion does not deteriorate even if the dither signal is not added, and overflows if added. The reason why the dither signal is not added in the small signal area P0 is that the S / N deteriorates if added.

  FIG. 4 is a schematic circuit block diagram illustrating the configuration of the dither control circuit 70 according to this embodiment. As shown in this figure, the dither control circuit 70 includes a dither generation circuit 71, a level detection circuit 72, a coefficient control circuit 73, and a multiplier 74.

  The dither generation circuit 71 generates a square wave dither signal and outputs it to the multiplier 74. The level detection circuit 72 detects whether the input signal belongs to the level of the large signal range P3, the middle signal range P1, P2, or the small signal range P0, and outputs the detection result to the coefficient control circuit 73. The coefficient control circuit 73 controls the coefficient according to the detection result of the level detection circuit 72. For example, when the level detection circuit 72 detects input signals in the middle signal ranges P 1 and P 2, the coefficient control circuit 73 outputs the coefficient 1 to the multiplier 74. When the level detection circuit 72 detects an input signal in the small signal range P0 or the large signal range P3, the coefficient control circuit 73 outputs the coefficient 0 to the multiplier 74. The coefficient 1 corresponds to the dither signal ON, and the coefficient 0 corresponds to the dither signal OFF. The multiplier 74 multiplies the dither signal from the dither generation circuit 71 by the coefficient from the coefficient control circuit 73 and outputs the result.

(Dither sequence)
FIG. 5A is an explanatory diagram of the small signal region P0, the middle signal regions P1 and P2, and the large signal region P3 according to the present embodiment. As shown in this figure, a dither signal is added (dither ON) only to input signals belonging to the middle signal ranges P1 and P2. The symbol P1 means a state where the signal is shifted from the small signal region to the middle signal region, and the symbol P2 means a state where the signal is shifted from the large signal region to the middle signal region.

  The large signal range P3 is the largest level when the magnitude of the input signal is classified into three levels, and is 0 dB to −10 dB here. The middle signal ranges P1 and P2 are levels in the middle when the magnitude of the input signal is classified into three levels, and are set to −10 dB to −80 dB here. The small signal region P0 is the smallest level when the magnitude of the input signal is classified into three levels, and is set to −80 dB or less here.

  Of course, the signal region classification method is not limited to this. That is, other classification methods may be adopted as long as the dither signal is added to the signal region where the distortion rate is deteriorated.

  FIG. 5B is a state transition diagram of the sequence according to the present embodiment. As shown in this figure, when the level detection circuit 72 continuously detects the input signal in the middle signal range P2 for several tens of ms in the state of the large signal range P3, the coefficient control circuit 73 starts from the large signal range P3 to the middle signal range P3. Move the sequence to P2. When the level detection circuit 72 continuously detects the input signal in the small signal region P0 for several tens of ms in the state of the middle signal region P2, the coefficient control circuit 73 moves the sequence from the middle signal region P2 to the small signal region P0. .

  Here, the sequence is shifted when detection is continuously performed for several tens of ms, but the timing of shifting the sequence is not limited to this. That is, it is possible to set an arbitrary timing with a command such as 50 ms, 100 ms, 200 ms, 400 ms or the like.

  On the other hand, when the level detection circuit 72 detects the input signal in the middle signal region P1 in the state of the small signal region P0, the coefficient control circuit 73 immediately shifts the sequence from the small signal region P0 to the middle signal region P1. If the level detection circuit 72 detects an input signal in the large signal range P3, the coefficient control circuit 73 shifts from any state to the large signal range P3. In other words, when the level detection circuit 72 detects the input signal of the large signal region P3 in the state of the small signal region P0 or the medium signal region P1, P2, the coefficient control circuit 73 immediately detects the small signal region P0 or the medium signal region P1, The sequence is shifted from P2 to the large signal area P3.

  FIG.5 (c) is explanatory drawing at the time of giving a hysteresis. That is, the large signal range P3 is set to 0 dB to −10 dB, the middle signal ranges P1 and P2 are set to −10 dB to −80 dB, and the small signal range P0 is set to −80 dB or less. When a signal of −80 dB or −10 dB is handled, It is considered that which signal range the signal is indeterminate.

  Therefore, a hysteresis is provided when the large signal region P3, the middle signal regions P1 and P2, and the small signal region P0 are transited. That is, when the transition from the large signal range P3 to the middle signal range P2 is made, the transition is made when it falls below −16 dB, and when the transition is made from the middle signal range P2 to the large signal range P3, it is judged that the transition is made when it exceeds −10 dB. To do. Similarly, when the transition is made from the middle signal range P1 to the small signal range P0, the transition is made when it falls below −80 dB, and when the transition is made from the small signal range P0 to the middle signal range P1, the transition is made when it exceeds −74 dB. judge. By performing control with hysteresis in this way, determination can be made even in the above case.

  The large signal range P3 may be set to 0 dB to less than −10 dB, the middle signal ranges P1 and P2 may be set to −10 dB to less than −80 dB, and the small signal range P0 may be set to −80 dB or less. Thus, if it is a method which does not have the part which overlaps in each signal area, it can also determine simply.

(Operation of audio output system)
FIG. 6 is a timing chart illustrating the operation of the audio output system according to this embodiment. Here, as shown in FIG. 6A, the case where the magnitude of the input signal changes in the order of large, medium, and small will be described.

  In this case, when the level detection circuit 72 continuously detects the input signal in the middle signal range P2 for several tens of ms in the state of the large signal range P3 (t1), the coefficient control circuit 73, as shown in FIG. The sequence is moved from the large signal range P3 to the middle signal range P2. Specifically, as shown in FIG. 6C, the dither signal is changed from OFF to ON. When the level detection circuit 72 continuously detects the input signal of the small signal region P0 for several tens of ms in the state of the middle signal region P2 (t2), the coefficient control circuit 73, as shown in FIG. The sequence is moved from the middle signal range P2 to the small signal range P0. Specifically, as shown in FIG. 6C, the dither signal is shifted from ON to OFF.

  Such dither signal ON / OFF is preferably performed by soft transition. That is, as shown in FIG. 6C, when the sequence moves from the large signal region P3 to the middle signal region P2, the coefficient control circuit 73 makes the dither signal soft transition and turns it ON. Soft transition here means gradually increasing the dither signal over a predetermined time t11. Further, when the sequence shifts from the middle signal range P2 to the small signal range P0, the coefficient control circuit 73 performs a soft transition on the dither signal and turns it off. Here, the soft transition refers to gradually decreasing the dither signal over a predetermined time t12.

  FIG. 7 is a timing chart illustrating another operation of the audio output system according to this embodiment. Here, as shown in FIG. 7A, a case where the magnitude of the input signal changes in the order of small, medium, and large will be described.

  In this case, when the level detection circuit 72 detects the input signal in the middle signal range P1 in the state of the small signal range P0 (t3), the coefficient control circuit 73 immediately starts the small signal range P0 as shown in FIG. 7B. To the middle signal range P1. Specifically, as shown in FIG. 7C, the dither signal is changed from OFF to ON. When the level detection circuit 72 detects the large signal region P3 in the state of the middle signal region P1 (t4), the coefficient control circuit 73 immediately starts from the middle signal region P1 to the large signal region as shown in FIG. Move the sequence to P3. Specifically, as shown in FIG. 7C, the dither signal is shifted from ON to OFF.

  Such dither signal ON / OFF is preferably performed by soft transition. That is, as shown in FIG. 7C, when the sequence moves from the small signal region P0 to the middle signal region P1, the coefficient control circuit 73 performs a soft transition of the dither signal and turns it ON. The soft transition here means gradually increasing the dither signal over a predetermined time t13. When the sequence moves from the middle signal range P1 to the large signal range P3, the coefficient control circuit 73 performs a soft transition on the dither signal and turns it off. Here, the soft transition refers to gradually reducing the dither signal over a predetermined time t14.

  In the coefficient control circuit 73, the time required for each soft transition (soft transition time) t11, t12, t13, t14 is individually set by a command. It is desirable that the soft transition time t14 when the sequence is shifted from the middle signal range P1, P2 to the large signal range P3 is set shorter than the other soft transition times t11, t12, t13. This is because there is a problem of overflow when the soft transition time t14 becomes longer, so that this can be avoided reliably.

(Difference in characteristics when dither signal is ON / OFF)
FIG. 8 is a graph illustrating the difference in characteristics when the dither signal is ON / OFF.

  FIG. 8A shows the relationship between the magnitude (vertical axis) of the output signal and the frequency (horizontal axis). The output signal here is an output signal from the DAC analog unit 60. When the dither signal is OFF, harmonic components such as 2 kHz, 3 kHz, and 4 kHz are large as shown by the dotted waveform l1. When the dither signal is turned on, it can be seen that these harmonic components are reduced as shown by the solid line waveform l2.

  FIG. 8B shows the relationship between the distortion rate (vertical axis) and the magnitude of the input signal (horizontal axis). The distortion rate is a value representing the degree of distortion of the signal, and is represented by the ratio of the entire harmonic component to the fundamental wave component. When the dither signal is OFF, as shown by the dotted line waveform 13, the distortion rate deteriorates when the magnitude of the input signal is about −30 dB to −70 dB. When the dither signal is turned on, it can be seen that the distortion rate is improved as shown by the solid line waveform l4.

  As described above, according to the present embodiment, since the dither signal is added according to the level of the input signal, the amount of change in the pulse signal near the zero cross is reduced to improve the distortion rate. Is possible. Also, since the dither signal is turned ON / OFF by soft transition, no shock sound is produced. Also, different soft transition times can be set when moving from the large signal region P3 to the medium signal region P2 and when moving from the small signal region P0 to the medium signal region P1. Further, it is possible to provide a hysteresis so that different threshold levels can be selected when moving from the middle signal range P1, P2 to the small signal range P0 and when shifting from the small signal range P0 to the middle signal range P1. It is.

  As described above, according to the present invention, it is possible to provide a dither control circuit and an audio output system capable of improving the distortion rate.

[Other embodiments]
As described above, an embodiment of the present invention has been described. However, it should be understood that the description and drawings which form part of this disclosure are illustrative and do not limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein. For example, FIG. 1 illustrates a configuration in which the dither control circuit 70 is connected in parallel with the 8-times oversampling filter 20, but the location where the dither control circuit 70 is provided is not limited to this. That is, as shown in FIG. 9, the dither control circuit 70 can be provided after the 8-times oversampling filter 20. However, since a delay of 1 ms occurs in the 8 × oversampling filter 20, the dither control circuit 70 is preferably connected in parallel with the 8 × oversampling filter 20. In this way, the dither control circuit 70 can be operated by flying for 1 ms as compared with the case where it is provided at the subsequent stage of the 8-times oversampling filter 20.

  The dither control circuit and sound output system according to the present invention can be applied to all devices that output sound, such as televisions, minicomponents, radio cassettes, and car audios. In particular, it is effective when applied to a device that requires improvement in distortion.

10: Audio processing circuit (audio DSP)
20 ... Oversampling filter (8 times oversampling filter)
30 ... Additional circuit (adder)
40. Digital-analog conversion circuit (ΔΣDAC)
60: Digital-analog conversion circuit (DAC analog part)
70 ... Dither control circuit 71 ... Dither generation circuit 72 ... Level detection circuit 73 ... Coefficient control circuit 74 ... Multiplier P0 ... Small signal region P1, P2 ... Medium signal region P3 ... Large signal region t11, t12, t13, t14 ... Software Time required for transition (soft transition time)

Claims (5)

A dither generation circuit for generating a dither signal;
A level detection circuit for detecting the level of the input signal;
A coefficient control circuit for controlling the coefficient according to the detection result of the level detection circuit;
A multiplier for multiplying a dither signal output from the dither generation circuit by a coefficient output from the coefficient control circuit ;
The level detection circuit detects whether the input signal belongs to a level of a large signal range, a medium signal range, or a small signal range,
The coefficient control circuit controls the dither signal to be added only to the input signal belonging to the middle signal range, and when the sequence moves from the large signal range or the small signal range to the middle signal range, Soft transition is performed so that the signal gradually increases, and when the sequence moves from the middle signal region to the large signal region or the small signal region, the dither signal is gradually transitioned so that the signal gradually decreases.
A dither control circuit characterized by that. The dither control circuit according to claim 1 , wherein the coefficient control circuit has a time required for each soft transition individually set. Said coefficient control circuit according to claim 2, characterized in that the time required from the in the signal region to the soft transition when the sequence moves to the large signal range is set shorter than the time required for other software transition The dither control circuit described in 1. The coefficient control circuit shifts the sequence from the large signal region to the intermediate signal region when the input signal in the intermediate signal region is continuously detected for a predetermined time in the state of the large signal region, and in the state of the medium signal region. 2. The dither control circuit according to claim 1 , wherein when an input signal in the small signal area is continuously detected for a predetermined time, the sequence is shifted from the middle signal area to the small signal area. The coefficient control circuit moves the sequence from the small signal region to the intermediate signal region as soon as it detects the input signal in the medium signal region in the state of the small signal region, and in the state of the small signal region or the medium signal region 2. The dither control circuit according to claim 1 , wherein a sequence is shifted from the small signal area or the medium signal area to the large signal area as soon as an input signal in the large signal area is detected.

Images