JP5862319B2 - Circuit device and printing device - Google Patents

Description

  The present invention relates to a circuit device, a printing device, and the like.

  The ink cartridge (printing material container) includes a storage device, and the storage device stores information on the type of the ink cartridge and information on the level of the amount of ink (printing material) stored in the ink cartridge, A technique is known in which information is acquired by a printing apparatus communicating with a storage device (for example, Patent Document 1).

JP 2007-196664 A

  Communication between the printing device and the storage device is performed via a circuit device provided in a cartridge holder in which an ink cartridge is mounted. A power supply voltage from the printing device is supplied to a power supply terminal of the circuit device. A voltage is supplied from the power supply terminal to the storage device. At this time, when the wiring length from the power supply terminal to the power supply terminal becomes long, there is a problem that the fluctuation of the power supply voltage supplied to the memory device becomes large.

  According to some embodiments of the present invention, it is possible to provide a circuit device, a printing device, and the like that can suppress fluctuations in power supply voltage supplied to a storage device.

  One embodiment of the present invention is a circuit device that communicates with a plurality of storage devices provided in a plurality of printing material containers, and is supplied with one of a high potential side power supply voltage and a low potential side power supply voltage. A power supply terminal; a first second potential power supply terminal and a second second potential power supply terminal to which the other of the high potential side power supply voltage and the low potential side power supply voltage is supplied; the first potential power supply terminal; A first terminal group provided between the first second potential power supply terminal and a second terminal group provided between the first potential power supply terminal and the second second potential power supply terminal. The first terminal group includes a first first potential power supply terminal that supplies a power supply voltage from the first potential power supply terminal to a first storage device of the plurality of storage devices; A first power supply voltage supplied from a second potential power supply terminal to the first storage device; A second potential power supply terminal, and the second terminal group supplies a power supply voltage from the first potential power supply terminal to a second storage device of the plurality of storage devices. Two first potential power supply terminals, and a second second potential power supply terminal for supplying a power supply voltage from the second second potential power supply terminal to the second storage device, At least the first first potential power supply terminal and the first second potential power supply terminal of the first terminal group, and at least the second first potential power supply terminal and the first of the second terminal group. The second second potential power supply terminal relates to a circuit device in which the arrangement order of the terminals is symmetrical with respect to the first potential power supply terminal.

  According to one aspect of the present invention, at least a first first potential power supply terminal and a first second potential power supply terminal of the first terminal group, and at least a second first potential power supply of the second terminal group. The terminals and the second second potential power supply terminal are arranged in a symmetrical arrangement order with respect to the first potential power supply terminal. As a result, fluctuations in the power supply voltage supplied to the storage device can be suppressed.

  In one embodiment of the present invention, the first first potential power supply terminal is the closest to the first potential power supply terminal among the terminals included in the first terminal group, and the second terminal group includes The second first potential power supply terminal may be closest to the first potential power supply terminal.

  In this way, the distance from the first potential power supply terminal to the first and second first potential power supply terminals can be reduced, so the first and second first potential power supply terminals to the first and second potentials. One voltage fluctuation of the high potential side power supply voltage and the low potential side power supply voltage supplied to the memory device can be suppressed.

  In one embodiment of the present invention, the first second potential power supply terminal is closest to the first second potential power supply terminal among the terminals of the first terminal group, and the second terminal group has Among the terminals, the second second potential power supply terminal may be closest to the second second potential power supply terminal.

  In this way, since the distance from the first and second second potential power supply terminals to the first and second first potential power supply terminals can be shortened, the first and second second potential power supply terminals. Thus, the other voltage fluctuation of the high potential side power supply voltage and the low potential side power supply voltage supplied to the first and second storage devices can be suppressed.

  In one embodiment of the present invention, the first terminal group includes a data signal, a reset signal, and a clock signal based on power supply voltages from the first first potential power supply terminal and the first second potential power supply terminal. Having a first data terminal, a first reset terminal, and a first clock terminal respectively supplied to the first storage device, wherein the second terminal group includes the second first potential power supply terminal and the first terminal. A second data terminal, a second reset terminal, and a second clock terminal for supplying a data signal, a reset signal, and a clock signal based on the power supply voltage from the second second potential power supply terminal to the second storage device, respectively. The first data terminal, the first reset terminal, and the first clock terminal, and the second data terminal, the second reset terminal, and the second clock terminal are connected to the first potential power source. The order of arrangement of the terminals may be symmetrical with respect to the child.

  In this way, the difference between the voltage fluctuations at the first and second first potential power supply terminals and the voltage fluctuation at the first and second second potential power supply terminals can be reduced. Thereby, the difference between the signal level of the data signal, the reset signal, and the clock signal based on the voltage can be reduced between the first terminal group and the second terminal group.

  In the aspect of the invention, the first data terminal, the first reset terminal, and the first clock terminal may be connected between the first first potential power supply terminal and the first second potential power supply terminal. The second data terminal, the second reset terminal, and the second clock terminal are disposed between the second first potential power supply terminal and the second second potential power supply terminal. May be.

  In this way, voltage fluctuations at the first and second first potential power supply terminals and voltage fluctuations at the first and second second potential power supply terminals can be reduced, so that a data signal based on the voltage, Voltage fluctuations in the signal level of the reset signal and clock signal can be reduced.

  In one embodiment of the present invention, the high potential side power supply voltage from any one of the first potential power supply terminal and the first second potential power supply terminal is supplied to the first potential power supply terminal. The first buffer circuit for outputting and the high potential side power supply voltage from the first potential power supply terminal or the second second potential power supply terminal are output to the second first potential power supply terminal. A second buffer circuit.

  According to this configuration, the high potential side power supply voltage from the first potential power supply terminal or the first second potential power supply terminal is output to the first first potential power supply terminal via the first buffer circuit. it can. Further, the high potential side power supply voltage from the first potential power supply terminal or the second second potential power supply terminal can be output to the second first potential power supply terminal via the second buffer circuit.

  In one aspect of the present invention, when the first storage device is not accessed, the first buffer circuit sets the first first potential power supply terminal to a high impedance state, and the non-access to the second storage device. At the time of access, the second buffer circuit may set the second first potential power supply terminal to a high impedance state.

  In this way, when there is a possibility that the terminal to which a voltage higher than the high potential side power supply voltage is applied and the first and second first potential power supply terminals are short-circuited, the high voltage is Application to the circuit device can be prevented.

  In one aspect of the present invention, the first power supply wiring connected along the terminal arrangement region of the circuit device, connected to the first potential power supply terminal, and wired along the terminal arrangement region, Second potential power supply terminal and a second power supply wiring connected to the second second potential power supply terminal, wherein the first power supply wiring and the second power supply wiring are the first first potential power supply. On the first buffer circuit disposed in the I / O region (input / output region) of the supply terminal and on the second buffer circuit disposed in the I / O region of the second first potential power supply terminal The high potential side power supply voltage and the low potential side power supply voltage may be supplied to the first buffer circuit and the second buffer circuit.

  In this way, since the wiring length from the first potential power supply terminal to the first buffer circuit and the second buffer circuit can be shortened, voltage fluctuations of the voltages output from the first buffer circuit and the second buffer circuit can be suppressed.

  In one embodiment of the present invention, a second first potential power supply terminal to which the one of the high potential side power supply voltage and the low potential side power supply voltage is supplied, the second first potential power supply terminal, and the first A third terminal group provided between two second potential power supply terminals, wherein the first terminal group is the first memory among the first to nth memory devices that are the plurality of memory devices. A power supply voltage and a control signal are supplied to the device, and the second terminal group is connected to the second storage device and the third to n-1th storage devices among the first to nth storage devices. The power supply voltage and the control signal are supplied through a common bus, and the third terminal group supplies the power supply voltage and the control signal to the nth storage device among the first to nth storage devices. Also good.

  In this way, even if a short circuit occurs at the terminals of the first and nth storage devices, the circuit device and the second to nth storage devices are separated from the second to n-1th storage devices. -1 It is possible to prevent the communication with the storage device from being affected.

  Another aspect of the present invention relates to a printing apparatus including any one of the circuit devices described above and the plurality of printing material containers provided with the plurality of storage devices.

  In another aspect of the present invention, a main control unit that supplies the high-potential-side power supply voltage and the low-potential-side power supply voltage to the circuit device may be included.

  In another aspect of the present invention, a circuit board on which the circuit device is provided may be provided, and a mounting portion on which the plurality of printing material containers are mounted may be included.

The pad arrangement example in the circuit device of this embodiment. 4 is a layout arrangement example of power supply wirings in the circuit device according to the present embodiment. 4 is a layout arrangement example of buffer circuits in the circuit device of the present embodiment. FIG. 3 is a perspective view illustrating a configuration example of a printing apparatus. 5A and 5B are perspective views showing the appearance of the printing material container. 6A and 6B show examples of substrate structures. Configuration examples of a printing material container and a circuit board. 2 is a basic configuration example of an electrical configuration of a printing apparatus. The flowchart of mounting | wearing detection and memory access. 10A to 10D are detailed configuration examples of the output circuit and the input / output circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows an example of pad arrangement in the circuit device 10 (integrated circuit device) of this embodiment. FIG. 1 shows a plan view of a silicon substrate of a circuit device 10 from a surface side on which circuit elements are formed by a semiconductor process.

  The circuit device 10 shown in FIG. 1 includes a first low potential side power supply terminal VSS1, a second low potential side power supply terminal VSS2, a first high potential side power supply terminal VDD1, a second high potential side power supply terminal VDD2, 1st-3rd terminal group PG1-PG3 is included. These terminals correspond to pads formed by a semiconductor circuit formation process.

  As will be described later with reference to FIG. 8, the circuit device 10 corresponds to a control unit 300 that performs communication processing with the storage device 203 provided in the printing material container 100 (for example, an ink cartridge). The circuit device 10 performs communication processing with the main control unit 400 via the bus BUS, and performs communication processing with the storage device 203 via the terminal group PG1 (or PG2, PG3) based on the communication processing. Further, the power supply terminals VDD1, VDD2, VSS1, and VSS2 of the circuit device 10 are supplied with the power supply voltages VDD and VSS from the low voltage power supply 441 of the main control unit 400 in FIG. 8, and the circuit device 10 is connected to the terminal group PG1 (or The power supply voltages VDD and VSS are supplied to the storage device 203 via PG2 and PG3). 8 are provided in the printing apparatus 1000, the holder 1100, and the printing material container 100 in FIG. 4, respectively.

  As shown in FIG. 1, the terminal group PG1 includes a first high potential side power supply terminal P_VDD1 that outputs a high potential side power supply voltage VDD and a first low potential side power supply that outputs a low potential side power supply voltage VSS. A terminal P_VSS1, a first clock terminal P_SCK1 that outputs a clock signal, a first reset terminal P_XRST1 that outputs a reset signal, a first data terminal P_SDA1 that inputs and outputs a data signal, and an input and output of a test signal And a first test terminal TCV1. Here, the high-potential-side power supply voltage VDD corresponds to, for example, the high-potential-side power supply voltage VDD output from the low-voltage power supply 441 in FIG. 8, and the low-potential-side power supply voltage VSS is, for example, from the low-voltage power supply 441 in FIG. This corresponds to the power supply voltage VSS on the low potential side to be output.

  Similarly, the terminal group PG2 includes a second high potential side power supply terminal P_VDD2, a second low potential side power supply terminal P_VSS2, a second clock terminal P_SCK2, a second reset terminal P_XRST2, and a second data terminal P_SDA2. And a second test terminal TCV2.

  The terminals of these terminal groups PG 1 and PG 2 and the power supply terminals VSS 1, VDD 1 and VSS 2 are arranged along the peripheral of the circuit device 10. In the plan view of the circuit device 10, the counterclockwise direction along the peripheral is defined as a first direction D1, and the clockwise direction along the peripheral is defined as a second direction D2. At this time, starting from the power supply terminal VDD1, the terminal group PG1 and the power supply terminal VSS1 are arranged in this order in the direction D1, and the terminal group PG2 and the power supply terminal VSS2 are arranged in the direction D2.

  More specifically, the terminal arrangement order in the direction D1 of the terminal group PG1 and the terminal arrangement order in the direction D2 of the terminal group PG2 are symmetric with respect to the power supply terminal VDD1. That is, in the terminal group PG1, the power supply terminal P_VDD1 is provided next to the direction D1 side of the power supply terminal VDD1, and the power supply terminal P_VSS2 is provided next to the direction D2 side of the power supply terminal VSS1. In contrast, in the terminal group PG2, the power supply terminal P_VDD2 is provided next to the direction D2 side of the power supply terminal VDD1, and the power supply terminal P_VSS2 is provided next to the direction D1 side of the power supply terminal VSS2. The control terminals P_SCK1, P_XRST1, and P_SDA1 of the terminal group PG1 are provided between the power supply terminals P_VDD1 and P_VSS1, and symmetrically, the control terminals P_SCK2, P_XRST2, and P_SDA2 of the terminal group PG2 are between the power supply terminals P_VDD2 and P_VSS2. Provided. The arrangement order of the control terminals is symmetric about the power supply terminal VDD1.

  The terminal group PG3 includes a third high potential side power supply terminal P_VDD3, a third low potential side power supply terminal P_VSS3, a third clock terminal P_SCK3, a third reset terminal P_XRST3, a third data terminal P_SDA3, A third test terminal TCV3 is provided. The terminals of the terminal group PG3 and the power supply terminal VDD2 are arranged along the peripheral of the circuit device 10. The terminal arrangement order in the direction D1 of the terminal group PG2 and the terminal arrangement order in the direction D2 of the terminal group PG3 are the power supply terminals. Symmetrical with respect to VSS2.

  Thus, by making the arrangement order of the power supply terminals VDD1, VSS1, VSS2 and the terminal groups PG1, PG2 symmetrical, the wiring resistance from the power supply terminals VDD1, VSS1, VSS2 to the power supply terminals P_VDD1, P_VSS1, P_VDD2, P_VSS2 is reduced. It becomes possible to do. Similarly, the wiring resistance from the power supply terminals VSS2, VDD1, VDD2 to the power supply terminals P_VDD2, P_VSSS2, P_VDD3, P_VSS3 is reduced by making the arrangement order of the power supply terminals VSS2, VDD1, VDD2 and the terminal groups PG2, PG3 symmetrical. It becomes possible to do. Thereby, the fluctuation | variation (for example, voltage drop) of the voltage which a power supply terminal outputs can be suppressed. In addition, the terminal groups PG1 to PG3 can have almost the same voltage fluctuation.

  Note that the positional relationship between the sides and corners of the silicon substrate of the circuit device 10 and the terminals is not limited to the configuration in FIG. 1, and the terminal arrangement order may be symmetrical as described above.

2. Power Supply Wiring Layout FIG. 2 shows a layout arrangement example of power supply wiring in the circuit device 10. As shown in FIG. 2, the wiring layer of the circuit device 10 includes a wiring LS connected to the low potential side power supply terminals VSS1 and VSS2, a wiring LD connected to the high potential side power supply terminals VDD1 and VDD2, and a terminal group. Wirings LPS1 to LPS3 connected to the low potential side power supply terminals P_VSS1 to P_VSS3 of PG1 to PG3 and wirings LPD1 to LPD3 connected to the high potential side power supply terminals P_VDD1 to P_VDD3 of the terminal groups PG1 to PG3, respectively. Wired.

  The wirings LS and LD are wired inside the terminals along the terminal arrangement direction D1 (or D2). Although some of the wirings LS and LD are illustrated in FIG. 2, the wirings LS and LD may be wired in a ring shape along the terminal arrangement direction. For example, when the common voltage VSS is used as the ground voltage in the circuit device 10, the wiring LS may be annular.

  The wirings LPS1 to LPS3 are wired so as to extend in the direction D2 from the power supply terminals P_VSS1 to P_VSS3 side. The wirings LPD1 to LPD3 are wired so as to extend in the direction D1 from the power supply terminals P_VDD1 to P_VDD3 side. When viewed from the peripheral of the circuit device 10 toward the center, the wiring LS, the wirings LPS1 to LPS3, the wirings LPD1 to LPD3, and the wiring LD are arranged in this order. Note that the wiring arrangement order is not limited to this.

  Each of the above wirings is formed by, for example, a metal (for example, aluminum) wiring layer of a semiconductor process. Inside the wiring LD, a circuit such as a circuit for outputting a control signal to the terminal groups PG1 to PG3 is disposed.

  FIG. 3 shows a layout arrangement example of buffer circuits arranged in the I / O area (input / output area) of each terminal. FIG. 3 shows buffer circuits corresponding to the terminal groups PG1 and PG2, but the same applies to the buffer circuits corresponding to the omitted terminal group PG3.

  The circuit device 10 outputs a power supply voltage VSS supplied from the wiring LS to the terminal P_VSS1 via the wiring LPS1, and a power supply voltage VDD supplied from the wiring LD to the terminal P_VDD1 via the wiring LPD1. And a buffer circuit BD1 for output. In addition, the circuit device 10 uses the voltages of the power supply terminals P_VSS1 and P_VDD1 as signal levels and outputs a clock signal to the terminal P_SCK1, and the voltage of the power supply terminals P_VSS1 and P_VDD1 as signal levels to the terminal P_XRST1. On the other hand, it includes a buffer circuit BR1 that outputs a reset signal and a buffer circuit IO1 that inputs and outputs a data signal through the terminal P_SDA1 with the voltages of the power supply terminals P_VSS1 and P_VDD1 as signal levels.

  The buffer circuits BS1, BC1, BR1, IO1, and BD1 are arranged corresponding to the terminals of the terminal group PG1, and are arranged in the same order as the arrangement order of the terminals along the terminal arrangement direction. On the buffer circuits BS1, BC1, BR1, IO1, and BD1, a wiring LS is arranged on the terminal side, and a wiring LS is arranged on the side away from the terminal. Further, on the buffer circuits BC1, BR1, and IO1, wirings LPS1 and LPD1 are disposed between the wirings LS and LD.

  The circuit device 10 includes buffer circuits BS2, BC2, BR2, IO2, and BD2 as buffer circuits corresponding to the terminal group PG2. These buffer circuits BS2, BC2, BR2, IO2, and BD2 have a symmetrical arrangement order with respect to the buffer circuits BS1, BC1, BR1, IO1, and BD1 of the terminal group PG1, corresponding to the symmetrical arrangement order of the terminals. Has been placed.

  Note that the detailed configuration of the buffer circuit will be described later with reference to FIGS.

  Since the terminals and the buffer circuits are arranged in a symmetrical arrangement order as described above, it is possible to make the voltage fluctuations of the power supply terminals almost the same in the terminal groups PG1 and PG2. The voltage fluctuation of the control signal to be level is almost the same in the terminal groups PG1 and PG2. Accordingly, it is possible to suppress the circuit level fluctuation (noise storage device 203 in FIG. 8) from malfunctioning due to fluctuations in the signal level.

  Now, when power is supplied to each terminal group from a set of high potential side power supply terminals and low potential side power supply terminals, the wiring resistance from the power supply terminals to the terminal group is different, so the terminal groups farther from the power supply terminals There is a problem that voltage drop or the like is likely to occur and the power supply voltage is likely to fluctuate. When the power supply voltage fluctuates, a stable voltage power supply cannot be supplied to the storage device in the subsequent stage, and there is a possibility that the noise of the control signal increases.

  In this regard, according to the present embodiment, as shown in FIG. 1, the first terminal group (for example, the terminal group PG1) includes the first potential power terminal (for example, the high potential side power terminal VDD1) and the first second power terminal. It is provided between a potential power supply terminal (for example, the low potential power supply terminal VSS1). The second terminal group (eg, terminal group PG2) is provided between the first potential power supply terminal VDD1 and the second second potential power supply terminal (eg, low potential side power supply terminal VSS2). Then, at least a first potential power supply terminal (for example, a high potential power supply terminal P_VDD1) and a first second potential power supply terminal (for example, a low potential power supply terminal P_VSS1) of the first terminal group PG1, At least a second first potential power supply terminal (for example, a high potential side power supply terminal P_VDD2) and a second second potential power supply terminal (for example, a low potential side power supply terminal P_VSS2) of the second terminal group PG2 The arrangement order of the terminals is symmetric with respect to the one-potential power supply terminal VDD1.

  Note that the case where the first potential power supply terminal and the second potential power supply terminal are terminals supplied with the high potential side power supply voltage VDD and the low potential side power supply voltage VSS, respectively, will be described as an example. Without being limited thereto, the first potential power supply terminal and the second potential power supply terminal may be terminals supplied with the low potential power supply voltage VSS and the high potential power supply voltage VDD, respectively. That is, the first potential power supply terminal, the first second potential power supply terminal, the second second potential power supply terminal, the first terminal group, and the second terminal group are the low potential side power supply terminal VSS2 and the high potential in FIG. It may correspond to the side power supply terminal VDD2, the high potential side power supply terminal VDD1, the terminal group PG3, and the terminal group PG2. In this case, the same can be said as described below.

  As a result, the wiring resistance from the power supply terminal VDD1 to the power supply terminals P_VDD1, P_VDD2 and the wiring resistance from the power supply terminals VSS1, VSS2 to the power supply terminals P_VSS1, P_VSS2 can be reduced. Variations in the output voltage (for example, voltage drop) can be suppressed. Further, since the arrangement order is symmetric, the difference between the wiring resistance from the power supply terminal VDD1 to the power supply terminal P_VDD1 and the wiring resistance from the power supply terminal VDD1 to the power supply terminal P_VDD2 is reduced in the terminal groups PG1 and PG2. Similarly, the difference between the wiring resistance from the power supply terminal VSS1 to the power supply terminal P_VSS1 and the wiring resistance from the power supply terminal VSS2 to the power supply terminal P_VSS2 is reduced. As a result, there is no specific terminal group that is distant from the power supply terminal, so that it is possible to prevent a problem from occurring in the storage device connected to such a specific terminal group. Ideally, one set of power supply terminals may be provided for each terminal group. However, in this embodiment, the power supply terminals VDD1 can be shared by the terminal groups PG1 and PG2 by arranging them symmetrically, so that the area of the circuit device 10 is increased. Can be reduced.

  In the present embodiment, the first first potential power supply terminal P_VDD1 is the closest to the first potential power supply terminal VDD1 among the terminals included in the first terminal group PG1, and the second terminal group PG2 includes the first terminal among the terminals included in the second terminal group PG2. Two first potential power supply terminals P_VDD2 are closest to the first potential power supply terminal VDD1.

  In this way, since the distance from the first potential power supply terminal VDD1 to the first and second first potential power supply terminals P_VDD1 and P_VDD2 can be reduced, the first and second first potential power supply terminals P_VDD1, Voltage fluctuation at P_VDD2 can be reduced. For example, as will be described later with reference to FIG. 10C, the power supply voltage VDD supplied from the terminal VDD1 is supplied to the terminals P_VDD1 and P_VDD2 as the power supply voltage CVDD through the transistor TP5. In this case, the voltage drop of CVDD can be reduced by shortening the wiring to the transistor TP5. Further, since the distance between the terminals can be reduced, the width of the wiring can be reduced, so that the layout area of the circuit device 10 can be reduced.

  In the present embodiment, among the terminals of the first terminal group PG1, the first second potential power supply terminal P_VSS1 is closest to the first second potential power supply terminal VSS1, and the terminal of the second terminal group PG2 Among them, the second second potential power supply terminal P_VSS2 is closest to the second second potential power supply terminal VSS2.

  In this way, the distance from the first and second second potential power supply terminals VSS1 and VSS2 to the first and second first potential power supply terminals P_VSS1 and P_VSS2 can be shortened, so the first and second Voltage fluctuations at the second potential power supply terminals P_VSS1 and P_VSS2 can be reduced. For example, as will be described later with reference to FIG. 10B, the power supply voltage VSS supplied from the terminal VSS1 is supplied to the terminals P_VSS1 and P_VSS2 as the power supply voltage CVSS through the transistor TN4. In this case, the voltage drop of CVSS can be reduced by shortening the wiring to the transistor TN4. Further, since the distance between the terminals can be reduced, the width of the wiring can be reduced, so that the layout area of the circuit device 10 can be reduced.

  In the present embodiment, the first data terminal P_SDA1, the first reset terminal P_XRST1, the first clock terminal P_SCK1, and the second data terminal P_SDA2 and the second reset terminal P_XRST2 included in the second terminal group PG2 are included in the first terminal group PG1. The second clock terminal P_SCK2 is symmetrical in terminal arrangement order with respect to the first potential power supply terminal VDD1.

  Further, in the present embodiment, the first data terminal P_SDA1, the first reset terminal P_XRST1, and the first clock terminal P_SCK1 are between the first first potential power supply terminal P_VDD1 and the first second potential power supply terminal P_VSS1. Be placed. The second data terminal P_SDA2, the second reset terminal P_XRST2, and the second clock terminal P_SCK2 are disposed between the second first potential power supply terminal P_VDD2 and the second second potential power supply terminal P_VSS2.

  In this way, as shown in FIG. 2, since the terminal arrangement order is symmetric, the lengths of the wirings LPS1 and LPS2 that supply CVSS can be made substantially the same, and the lengths of the wirings LPD1 and LPD2 that supply CVDD Can be almost the same. As will be described later with reference to FIGS. 10A and 10D, control signals CSDA, CRST, and CSCK are output from transistors TP2, TN2, TP7, and TN7 that operate based on CVDD and CVSS. In this case, since the wiring lengths are the same, the difference between the noise amounts of the control signals CSDA, CRST, and CSCK (noise due to variations in CVDD and CVSS) can be reduced between the terminal groups PG1 and PG2. In addition, since the voltage fluctuations of CVDD and CVSS can be reduced as described above, fluctuations in the signal levels of control signals CSDA, CRST, and CSCK whose signal levels are CVDD and CVSS can be reduced. Thereby, the malfunction of the memory | storage device resulting from a noise can be suppressed.

  In the present embodiment, as shown in FIG. 3, the first power supply wiring LD and the second power supply wiring LS are provided in the first buffer circuit BD1 arranged in the I / O region of the first first potential power supply terminal P_VDD1. , And the second buffer circuit BD2 disposed in the I / O region of the second first potential power supply terminal P_VDD2, and the high potential side power supply for the first buffer circuit BD1 and the second buffer circuit BD2. The voltage VDD and the low potential side power supply voltage VSS are supplied.

  Here, “upper” of “wiring up” refers to a direction away from a plane in a direction perpendicular to a plane on which a circuit is formed by a semiconductor process among the planes of the silicon substrate of the circuit device 10. That is, the buffer circuits BD1 and BD2 are formed on the plane of the silicon substrate, and the wirings LD and LS are further laminated on the direction side farther from the plane of the silicon substrate than the buffer circuits BD1 and BD2.

  In this way, since the wiring length from the first potential power supply terminal VDD1 to the first buffer circuit BD1 and the second buffer circuit BD2 can be shortened, the voltage CVDD output from the first buffer circuit BD1 and the second buffer circuit BD2 can be reduced. Voltage fluctuation can be suppressed.

3. Printing Device FIG. 4 is a perspective view illustrating a configuration example of a printing device according to the present embodiment. Hereinafter, a case where the printing material container is an ink cartridge that stores ink as a printing material will be described as an example. However, the present embodiment is not limited to this, and the printing material container is a printing material other than ink. The present embodiment can also be applied when accommodating.

  The printing apparatus 1000 includes a cartridge mounting unit 1100 to which an ink cartridge (printing material container in a broad sense) is mounted, a rotatable cover 1200, and an operation unit 1300. The cartridge mounting portion 1100 is also referred to as “cartridge holder” or simply “holder”. In the example shown in FIG. 4, four ink cartridges can be mounted independently on the cartridge mounting unit 1100, for example, four types of ink cartridges (printing material containers) 100 of black, yellow, magenta, and cyan are mounted. Is done. The cover 1200 can be omitted. The operation unit 1300 is an input device for the user to make various instructions and settings, and includes a display unit for making various notifications to the user.

  5A and 5B are perspective views showing the appearance of the ink cartridge 100. FIG. The XYZ axes in FIGS. 5A and 5B correspond to the XYZ axes in FIG. The ink cartridge is also simply referred to as “cartridge”. This cartridge 100 has a flat, substantially rectangular parallelepiped external shape, and among the dimensions L1, L2, and L3 in three directions, the length L1 (size in the insertion direction) is the largest, and the width L2 is the smallest. The height L3 is intermediate between the length L1 and the width L2.

  The cartridge 100 has two side surfaces, a front end surface (first surface) Sf, a rear end surface (second surface) Sr, a ceiling surface (third surface) St, and a bottom surface (fourth surface) Sb. (Fifth and sixth surfaces) Sc and Sd. Inside the cartridge 100, an ink storage chamber 120 (also referred to as an “ink storage bag”) formed of a flexible material is provided. The front end surface Sf has two positioning holes 131 and 132 and an ink supply port 110. The ceiling surface st is provided with a substrate 200 on which a storage device is mounted. A non-volatile storage device for storing information about ink is mounted on the substrate 200. The first side surface Sc and the second side surface Sd face each other, and are orthogonal to the front end surface Sf, the ceiling surface St, the rear end surface Sr, and the bottom surface Sb. The concave / convex fitting portion 134 is disposed at a position where the second side surface Sd and the front end surface Sf intersect.

  FIG. 6A shows the configuration of the substrate 200 in this embodiment. The surface of the substrate 200 is a surface exposed to the outside when the substrate 200 is mounted on the cartridge 100. FIG. 6B shows a view from the side surface of the substrate 200. A boss groove 201 is formed at the upper end of the substrate 200, and a boss hole 202 is formed at the lower end of the substrate 200.

  An arrow SD in FIG. 6A indicates the mounting direction of the cartridge 100 to the cartridge mounting portion 1100. This mounting direction SD coincides with the mounting direction (X direction) of the cartridge shown in FIG. The substrate 200 has a storage device 203 on the back surface, and a terminal group including nine terminals is provided on the front surface. Although not shown in the drawings, wiring for connecting the terminals and the storage device 203 and other wirings, and wiring for electrically connecting the wiring on the front surface and the wiring on the back surface of the substrate are provided on the front surface and the back surface of the substrate 200. Hall is arranged. The storage device 203 stores information related to the cartridge 100 and information related to ink stored in the cartridge 100 (for example, ink amount information, ink remaining amount, and ink consumption). These terminals are formed in a substantially rectangular shape, and are arranged so as to form two rows substantially perpendicular to the mounting direction SD.

  The substrate 200 includes a plurality of storage device terminals RST, SCK, SDA, VDD, VSS, a first attachment detection terminal DT1, a second attachment detection terminal DT2, a first short-circuit detection terminal CO1, and a first Two short-circuit detection terminals CO2 are provided.

  Of the two columns, an example on the near side in the mounting direction SD (a column located on the upper side in FIG. 6A) is referred to as an upper column A1 (first column), and a column on the back side in the mounting direction SD (FIG. 6). The lower column in (A) is referred to as a lower column A2 (second column). Note that these rows A1 and A2 can be considered to be rows formed by contact portions cp of a plurality of terminals. The contact portions cp of the plurality of terminals are portions where connectors provided inside the holder for connecting the holder-side circuit board 450 and the cartridge-side board 200 come into contact with the plurality of terminals when the cartridge is mounted in the holder. is there.

The terminals CO1, RST, SCK, CO2 forming the upper column A1 and the terminals DT1, VDD, VSS, SDA, DT2 forming the lower column A2 have the following functions (uses), respectively.
<Upper row A1>
(1) First short-circuit detection terminal CO1
(2) Reset terminal RST
(3) Clock terminal SCK
(4) Second short-circuit detection terminal CO2
<Lower row A2>
(5) First mounting detection terminal DT1
(6) First power supply terminal (power supply terminal) VDD
(7) Second power supply terminal (ground terminal) VSS
(8) Data terminal SDA
(9) Second mounting detection terminal DT2

  The first and second mounting detection terminals DT1 and DT2 are used when detecting whether or not the ink cartridge 100 is correctly mounted on the cartridge mounting portion 1100, as will be described later. The first and second short detection terminals CO1 and CO2 are used when detecting a short circuit with the first and second mounting detection terminals DT1 and DT2. The other five terminals RST, SCK, VDD, VSS, and SDA are terminals for the storage device 203 and are also referred to as “memory terminals”.

  Each terminal includes a contact portion cp in contact with a corresponding terminal among the plurality of device-side terminals at the center thereof. The contact portions cp of the terminals forming the upper row A1 and the contact portions cp of the terminals forming the lower row A2 are alternately arranged to form a so-called staggered arrangement. Further, the terminals forming the upper row A1 and the terminals forming the lower row A2 are also arranged in a staggered manner so that the terminal centers are not aligned in the mounting direction SD.

  The contact portions of the first and second short-circuit detection terminals CO1 and CO2 in the upper row A1 are arranged at both ends of the upper row A1, that is, the outermost side of the upper row A1, respectively. Further, the contact portions of the first and second mounting detection terminals DT1 and DT2 in the lower row A2 are disposed at both ends of the lower row A2, that is, the outermost side of the lower row A2. The contact portions of the memory terminals RST, SCK, VDD, VSS, and SDA are collectively arranged at the center in the region where all nine terminals are arranged. The contact portions of the first and second short-circuit detection terminals CO1 and CO2 and the first and second mounting detection terminals DT1 and DT2 are arranged at the four corners of the set of memory terminals RST, SCK, VDD, VSS, and SDA. ing.

  In a printing apparatus such as an ink jet printer, conductive ink or the like may adhere to the terminal side of the substrate 200. As shown in FIG. 6A, the first short detection terminal CO1 and the first mounting detection terminal DT1 are adjacent to each other, and the second short detection terminal CO2 and the second mounting detection terminal DT2 are Next to each other. Therefore, for example, when conductive ink or the like adheres to the terminal side of the substrate 200, two adjacent terminals CO1 and DT1 or CO2 and DT2 may be short-circuited (leaked) by the conductive ink or the like. There is. In addition, the first mounting detection terminal DT1 and the power supply terminal VDD may be short-circuited, or the second mounting detection terminal DT2 and the data terminal SDA may be short-circuited.

  The first and second mounting detection terminals DT1 and DT2 are terminals for detecting the mounting of the printing material container 100, and a high voltage (for example, 42V) is applied to DT1 and DT2 when detecting the mounting. Is done. Therefore, when DT1 or DT2 is short-circuited with other terminals by conductive ink or the like, for example, a high voltage may be applied to a circuit such as the storage device 203, and the circuit may be destroyed.

  As will be described below, in the printing apparatus according to the present embodiment, even when a short circuit occurs between terminals due to conductive ink or the like, the storage device 203 is driven by a high voltage applied to the mounting detection terminals DT1 and DT2 when mounting is detected. This prevents the circuit from being destroyed.

FIG. 7 shows a configuration example of the printing material container and the circuit board in the printing apparatus of the present embodiment. This configuration example includes the first printing material container 100-1 to the fourth printing material container 100-4, the control unit 300, and the fourth printing material container 100-4 (n is an integer of 4 or more in this configuration example ). A circuit board 450 is included. Note that the printing apparatus according to the present embodiment is not limited to the configuration shown in FIG. 7, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.

  The printing material containers 100-1 to 100-4 include a storage device 203 (203-1 to 203-4) that stores printing material information, a plurality of storage device terminals RST, SCK, VDD, VSS, SDA, and mounting detection. Terminals DT1 and DT2 and short circuit detection terminals CO1 and CO2 are provided, respectively. A mounting detection resistance element RD is provided between DT1 and DT2. CO1 and CO2 are electrically connected by wiring inside the printing material container 100.

  The control unit 300 corresponds to the circuit device 10 shown in FIGS. The terminal groups PG1 to PG3 of the control unit 300 are connected to the plurality of storage device terminals RST, SCK, VDD, VSS, and SDA of the first to fourth printing material containers 100-1 to 100-4. 300 controls reading or writing of data with respect to the storage device 203.

  Of the first to fourth printing material containers 100-1 to 100-4, the second (i in the broad sense (i is an integer satisfying 1 <i <n-1)) to the third (in the broad sense). A plurality of storage device terminals RST, SCK, VDD, VSS, and SDA of each of the j-th printing material containers 100-2 and 100-3 (j is an integer satisfying i <j <n) are connected to the bus MBS. Commonly connected to the control unit 300. The plurality of storage device terminals RST, SCK, VDD, VSS, and SDA of the first printing material container 100-1 are separated from the bus MBS and connected to the control unit 300. The plurality of storage device terminals RST, SCK, VDD, VSS, and SDA of the fourth (nth in a broad sense) printing material container 100-4 are separated from the bus MBS and connected to the control unit 300.

  The circuit board 450 is a circuit board for a printing apparatus, on which the control unit 300 is mounted, and includes a high potential side power terminal TVD, a low potential side power terminal TVS, and first to fourth (nth in a broad sense) terminals. It has groups TG1 to TG4 and bus wiring of bus MBS. The first to fourth printing material containers 100-1 to 100-4 are connected to the first to fourth terminal groups TG1 to TG4. The first to fourth terminal groups TG1 to TG4 have a plurality of storage devices for accessing the storage devices 203-1 to 203-4 included in the first to fourth printing material containers 100-1 to 100-4. Each has terminals RST, SCK, VDD, VSS, and SDA. The first to fourth terminal groups TG1 to TG4 have mounting detection terminals DT1 and DT2 for detecting the mounting of the first to fourth printing material containers 100-1 to 100-4, respectively.

  The first terminal group TG1 is arranged on the first end side of the circuit board 450, and the fourth (nth in a broad sense) terminal group TG4 is the first end side of the circuit board 450 facing the first end side. 2 is arranged on the edge side. Of the first to fourth (nth in a broad sense) terminal groups TG1 to TG4, the second (i in a broad sense (i is an integer satisfying 1 <i <n-1)) to the third (in a broad sense). Are j-th (j is an integer satisfying i <j <n)) terminal groups TG2 and TG3 are commonly connected to the control unit 300 by the bus wiring of the bus MBS. The first terminal group TG1 is separated from the bus wiring of the bus MBS and connected to the control unit 300. The fourth (nth in a broad sense) terminal group TG4 is separated from the bus wiring of the bus MBS and connected to the control unit 300.

  The power supply terminal TVD is connected to the high potential side power supply terminals VDD1 and VDD2 of the control unit 300, and the power supply terminal TVS is connected to the low potential side power supply terminals VSS1 and VSS2 of the control unit 300. The power supply terminals TVD and TVS are connected to the main control unit 400 described later with reference to FIG. 8 through, for example, an FPC (flat flexible cable) connected to the circuit board 450. The high-potential-side power supply voltage VDD supplied from the main control unit 400 is supplied to the power supply terminals VDD1 and VDD2 of the control unit 300, and the power supply terminals VSS1 and VSS2 of the control unit 300 are supplied from the main control unit 400. The low potential side power supply voltage VSS is supplied.

  As shown in FIG. 7, in the printing apparatus according to the present embodiment, the first terminal group TG1 disposed on the first end side of the circuit board 450 and the second end side facing the first end side. The fourth terminal group TG4 arranged in is separated from the common bus MBS and connected to the terminal groups PG1 and PG3 of the control unit 300, respectively. That is, the terminals RST, SCK, VDD, VSS, and SDA for the storage devices (first and nth storage devices) of the first and fourth printing material containers 100-1 and 100-4 are stored in other printing material containers. The storage device (second to (n-1) th storage device) terminals RST, SCK, VDD, VSS, and SDA of the bodies 100-2 and 100-3 are separated and connected to the control unit 300.

  In an inkjet printer or the like, when ink is ejected from a print head, a part of the ink is atomized (mist) and released into the air. Since this ink mist wraps around from the edge side of the circuit board 450, the printing material containers 100-1 and 100-4 located on the edge side of the printing material containers 100-2 and 100-3 far from the edge side. In this case, there is a higher possibility that a short circuit between the terminals due to adhesion of ink mist occurs.

  In the printing apparatus of the present embodiment, even when a short circuit occurs in the printing material containers 100-1 and 100-4 on the edge side, the printing material containers 100-2 and 100-3 are separated from the other printing material containers 100-2 and 100-3. Therefore, it is possible to prevent communication between the control unit 300 and the storage devices 203-2 and 203-3 of other printing material containers from being affected. Further, it is possible to prevent a high voltage from being applied to the storage devices 203-2 and 203-3 at the time of mounting detection. As a result, it is possible to reliably and safely detect the mounting of the printing material containers 100-1 to 100-4.

4). Circuit Configuration FIG. 8 shows a basic configuration example of the electrical configuration of the printing apparatus according to this embodiment. The printing apparatus of this configuration example includes a printing material container (ink cartridge) 100, a circuit board 450, a control unit 300, a main control unit 400, a low voltage power supply 441, a high voltage power supply 442, and a display unit 430. The control unit 300 includes a short circuit detection unit 310, a voltage application unit 320, a mounting detection unit 330, a CO (cartridge out) detection unit 340, and a communication processing unit 350. Note that the printing apparatus according to the present embodiment is not limited to the configuration shown in FIG. 8, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.

  Although FIG. 8 shows only one printing material container 100 as an example, the printing apparatus of this configuration example can include a plurality of printing material containers 100. In other words, the printing apparatus performs first to nth printing (n is an integer of 2 or more) having a storage device 203 for storing printing material information and a plurality of storage device terminals RST, SCK, VDD, VSS, and SDA. The material container 100-1 to 100-n is included. Further, the control unit 300 further includes a control unit 300 that is connected to the plurality of storage device terminals of the first to nth printing material containers 100-1 to 100-, and controls data reading or writing with respect to the storage device 203. .

  The circuit board 450 includes a terminal group having nine terminals and a plurality of wirings that electrically connect each terminal of the terminal group and the control unit 300. Specifically, the terminal group includes a reset terminal CRST, a clock terminal CSCK, a power supply terminal CVDD, a ground terminal CVSS, a data terminal CSDA, a first attachment detection terminal CDT1, a second attachment detection terminal CDT2, and a first short circuit detection terminal. CCO1 and a second short-circuit detection terminal CCO2 are included. The circuit board 450 is provided, for example, in the cartridge mounting portion 1100 in FIG. A control unit 300 is provided (mounted) on the circuit board 450.

  The control unit 300 includes a communication processing unit 350, and controls reading or writing of data with respect to the storage device 203 together with the main control unit 400. For example, when the main control unit 400 controls data writing or reading with respect to the storage device 203, the communication processing unit 350 relays communication of writing data or reading data. Further, the control unit 300 includes a mounting detection unit 330, a CO detection unit 340, a short circuit detection unit 310, a voltage application unit 320, and a high voltage control unit 360, and processes such as mounting detection, CO detection, short circuit detection, and high voltage interruption. I do. The control unit 300 can be realized by a logic circuit including, for example, a CMOS transistor, and may be a one-chip integrated circuit device.

  The main control unit 400 includes a CPU 410 and a memory 420, and controls printing processing. In addition, necessary communication is performed with the control unit 300 via the bus BUS. In the configuration example illustrated in FIG. 8, the control unit is divided into the main control unit 400 and the control unit 300, but may be configured as one control unit.

  The display unit 430 is for notifying the user of various kinds of information such as the operating state of the printing apparatus 1000 and the cartridge mounting state. The display unit 430 is provided, for example, in the operation unit 1300 in FIG.

  The low voltage power supply 441 generates a low power supply voltage (first power supply voltage) VDD. The first power supply voltage VDD is a normal power supply voltage (rated 3.3 V) used in the logic circuit. The high voltage power supply 442 generates a high power supply voltage (second power supply voltage) VHV. The second power supply voltage VHV is a high voltage (for example, rated 42 V) used to drive the print head and eject ink, and generates the mounting detection voltage VHO applied to the first mounting detection terminal DT1. It is also used to These voltages VDD and VHV are supplied to the controller 300, and are also supplied to other circuits as necessary. Specifically, for example, the power supply voltage VHV is supplied from the high voltage power supply 442 to the voltage applying unit 320 of the control unit 300, and the mounting detection voltage VHO output from the voltage applying unit 320 is the first mounting of the ink cartridge 100. It is supplied to the detection terminal DT1 and the attachment detection unit 330. The mounting detection voltage VHO is higher than a power supply voltage (for example, 3.3 V) supplied to the storage device 203.

  Among the nine terminals provided on the substrate 200 (FIG. 6A) of the printing material container 100, the reset terminal RST, the clock terminal SCK, the power supply terminal VDD, the data terminal SDA, and the ground terminal VSS The storage device 203 is electrically connected. The storage device 203 does not have an address terminal, and a memory cell to be accessed is determined based on the number of pulses of the clock signal input from the clock terminal SCK and command data input from the data terminal SDA, and is synchronized with the clock signal. Thus, the non-volatile memory receives data from the data terminal SDA or transmits data from the data terminal SDA. The clock terminal SCK is used to supply a clock signal from the control unit 300 to the storage device 203.

  A power supply voltage (for example, 3.3 V) and a ground voltage (0 V) for driving the storage device 203 from the printing apparatus 1000 are supplied to the power supply terminal VDD and the ground terminal VSS, respectively. A power supply voltage for driving the storage device 203 is generated and supplied by the control unit 300 based on the low voltage power supply 441.

  The data terminal SDA is used for exchanging data signals between the control unit 300 and the storage device 203. The reset terminal RST is used for supplying a reset signal from the control unit 300 to the storage device 203.

  The first and second mounting detection terminals DT1 and DT2 are used when detecting whether or not the printing material container 100 is correctly mounted on the cartridge mounting portion 1100. A mounting detection resistance element RD is provided between the first mounting detection terminal DT1 and the second mounting detection terminal DT2. The mounting detection unit 330 detects mounting of the printing material container 100 based on the mounting detection voltage VHO output from the voltage application unit 320 and the current flowing through the mounting detection resistance element RD. Specifically, by applying the mounting detection voltage VHO output from the voltage application unit 320 to the first mounting detection terminal DT1, a voltage is applied to the mounting detection resistance element RD, and a current flows. The mounting is detected by the mounting detection unit 330 detecting the current. The method for detecting this attachment will be described later in detail.

  The first and second short circuit detection terminals CO1 and CO2 are electrically connected by wiring inside the printing material container 100 (specifically, the substrate 200). As will be described later, the CO detection unit 340 detects electrical continuity between CO1 and CO2 to determine whether CO1 and CO2 are in electrical contact with corresponding terminals of the cartridge mounting unit 1100, respectively. That is, it is possible to detect whether or not the printing material container 100 is correctly attached. However, in the printing apparatus of the present embodiment, the first and second mounting detection terminals DT1 and DT2 and the mounting detection unit 330 are provided, and the mounting of the ink cartridge 100 can be detected by using these. The CO detector 340 can be omitted. When the CO detection unit 340 is omitted or when mounting detection (cartridge out detection) using the CO detection unit 340 is not performed, the CO1 and the CO2 do not have to be electrically connected.

  In the following description, the mounting detection by the mounting detection unit 330 is referred to as “mounting detection”, and the mounting detection by the CO detection unit 340 is referred to as “cartridge out detection” or “CO detection”.

  Diodes D1 and D2 are provided between the first and second short-circuit detection terminals CO1 and CO2 and the detection node ND. When CO detection (cartridge out detection) is not performed, the diodes are not interposed. , CO1, CO2 may be directly connected to the detection node ND.

  The short circuit detection unit 310 is connected to the first short circuit detection terminal CO1 and the second short circuit detection terminal CO2 directly or via diodes D1 and D2 (given circuit elements in a broad sense). For example, the first and second short-circuit detection terminals are detected by a short circuit between at least one of the first and second short-circuit detection terminals CO1 and CO2 and at least one of the first and second mounting detection terminals DT1 and DT2. The fact that a high voltage that is not originally applied to the terminals CO1 and CO2 (application of an abnormal voltage) is detected based on a comparison between the voltage at the detection node ND and the reference voltage. That is, a short circuit (abnormal voltage) is detected when the voltage at the detection node ND is higher than the reference voltage. When the short circuit detection unit 310 detects a short circuit, it outputs a short circuit detection signal VSHT to the high voltage control unit 360, and the high voltage control unit 360 controls the voltage application unit 320 based on the short circuit detection signal VSHT. The signal VCNT is output. The voltage application unit 320 stops the supply of the mounting detection voltage VHO based on the control signal VCNT from the high voltage control unit 360.

  Here, the reference voltage is set to a voltage value that does not destroy the storage device 203 (or a circuit such as the CO detection unit 340) when the short circuit occurs. In this way, the short circuit detection unit 310 can detect a short circuit before the voltage of the detection node ND reaches a voltage value that destroys a circuit such as the storage device 203.

  The communication processing unit 350 includes output circuits OB1 to OB4 and an input / output circuit IOB. The output circuits OB1 to OB4 output signals or voltages to the reset terminal CRST, clock terminal CSCK, power supply terminal CVDD, and ground terminal CVSS provided on the circuit board 450, respectively. The input / output circuit IOB inputs / outputs a data signal to / from a data terminal CSDA provided on the circuit board 450. The reset terminal CRST, clock terminal CSCK, power supply terminal CVDD, ground terminal CVSS, and data terminal CSDA are connected to the reset terminal RST, clock terminal SCK, power supply terminal VDD, ground terminal VSS, and data terminal SDA provided in the printing material container 100, respectively. Each is connected. Detailed configurations of the output circuits OB1 to OB4 and the input / output circuit IOB will be described later.

  As shown in FIG. 6A, the first short detection terminal CO1 and the first attachment detection terminal DT1 are adjacent to each other, and the second short detection terminal CO2 and the second attachment detection terminal DT2 are adjacent to each other. Are next to each other. Therefore, for example, when conductive ink or the like adheres to the terminal side of the substrate 200, two adjacent terminals CO1 and DT1 or CO2 and DT2 may be short-circuited (leaked) by the conductive ink or the like. There is. In addition, the first mounting detection terminal DT1 and the power supply terminal VDD may be short-circuited, or the second mounting detection terminal DT2 and the data terminal SDA may be short-circuited.

  As described above, when mounting is detected by the mounting detector 330, the mounting detection voltage VHO is applied to the first mounting detection terminal DT1. Accordingly, when the first and second mounting detection terminals DT1 and DT2 and the first and second short circuit detection terminals CO1 and CO2 are short-circuited (leakage) due to conductive ink or the like, CO detection is performed when mounting is detected. There is a risk that a high voltage is applied to the portion 340. Further, when the first and second mounting detection terminals DT1 and DT2 and the power supply terminal VDD or the data terminal SDA are short-circuited, a high voltage may be applied to the storage device 203.

  According to the printing apparatus of the present embodiment, when the short circuit detection unit 310 detects that a short circuit may occur between the terminals and detects that there is a possibility that a short circuit has occurred. The voltage application unit 320 can stop the supply of the mounting detection voltage VHO.

  Specifically, for example, as shown in B1 of FIG. 8, when DT1 and CO1 are short-circuited, a forward current of the diode D1 flows from DT1 to CO1, and from CO1 to the detection node ND, As a result, the potential of the detection node ND increases. Further, as shown in B2 of FIG. 8, when DT2 and CO2 are short-circuited, a forward current of the diode D2 flows from DT2 to CO2 and from CO2 to the detection node ND. As a result, the detection node The potential of ND increases. The short circuit detection unit 310 can detect a short circuit by comparing the voltage of the detection node ND with the reference voltage.

  Further, according to the printing apparatus of the present embodiment, the control unit 300 has a plurality of storage device terminals (memory terminals) when the voltage application unit 320 applies the mounting detection voltage VHO to the first mounting detection terminal DT1. ) RST, SCK, VDD, VSS, SDA are set to a high impedance state (floating state). By doing so, for example, even when DT1 and CO1 and VDD or DT2 and CO2 and SDA are short-circuited, before the high voltage is applied to the storage device 203 at the time of mounting detection, the short-circuit detection unit 310 Detects that an overvoltage has been applied to the node ND, and based on this, the control unit 300 stops supplying the mounting detection voltage VHO, so that a voltage exceeding the maximum rating of the storage device 203 is applied to the storage device 203. Can be prevented.

  As described above, according to the printing apparatus of the present embodiment, even when a short circuit occurs between terminals due to adhesion of a printing material such as ink, a high voltage is applied to the storage device 203 when mounting is detected. The possibility can be reduced. Further, the memory terminal can be set to the same potential before access to the storage device 203, and application of a high voltage can be stopped during access. As a result, reliable and safe mounting detection and highly reliable memory access can be realized.

  FIG. 9 is a flowchart of mounting detection and memory access in the printing apparatus of this embodiment. As described above, in the printing apparatus of the present embodiment, ink information (for example, ink usage in the ink cartridge, ink cartridge manufacturing information, etc.) is stored in the storage device 203 provided in the ink cartridge 100. This ink information is obtained by the main control unit 400 via the control unit 300 every time when a predetermined unit amount of ink in the ink cartridge is consumed by the head cleaning or printing, or when the printing apparatus is turned off. It is written in the storage device 203. The ink amount information is read from the storage device 203 via the control unit 300 in response to a request from the main control unit 400 when the printing apparatus is turned on. This flow is executed under the control of the main control unit 400 and the control unit 300.

  The main control unit 400 and the control unit 300 always set the memory terminals to a high impedance state after the printing apparatus is turned on except during memory access. In addition, mounting detection and CO detection are always or periodically executed. Note that CO detection (cartridge out detection) is executed even during memory access.

  When the main control unit 400 starts memory access, first, attachment detection is stopped. That is, the process of detecting the attachment by applying VHO is stopped (step SP1).

  In step SP2, the memory terminal is set from the high impedance state HZ to the GND level (ground level, VSS level). At this time, if a short circuit occurs between the CO terminal (CO1 or CO2) and the memory terminal, for example, between CO1 and VDD, or between CO2 and SDA, the CO detection unit 340 can detect the short circuit.

  In step SP3, it is determined whether or not the printing material container 100 is normal. That is, it is determined whether or not the printing material container 100 is properly mounted and a short circuit between the terminals has not occurred. If it is normal, the process proceeds to the next step SP4, and if it is not normal, error processing is executed. The error process is a process of displaying an error message on the display unit 430, for example.

  In step SP4, memory access to the storage device 203 is performed. That is, the control unit 300 supplies necessary signals and power supply voltages to each memory terminal, and performs data writing processing or reading processing on the storage device 203.

  In step SP5, it is determined whether or not the memory access has been normally performed. Specifically, at the time of writing, a write completion signal is transmitted from the storage device 203 to the control unit 300 at a predetermined timing after the control unit 300 transmits a write command and write data to the storage device 203. The Upon receiving this write completion signal, the control unit 300 determines whether the memory access has been normally completed. At the time of reading, since the parity bit is added to the data read from the storage device 203 and transmitted to the control unit 300, a parity check is performed, and whether or not the data read from the storage device 203 is normal. Can be determined. If the memory access is normal, the process proceeds to step SP6, and if it is not normal, error processing is executed.

  When the memory access ends normally, in step SP6, the memory terminal is set to the GND level. Here, cartridge out detection by the CO detection unit 340 can be performed. At this time, if a short circuit between the terminals (for example, CO1-VDD, CO2-SDA) occurs, the CO detection unit 340 can detect the short circuit.

  In step SP7, the mounting detection voltage VHO is applied to the mounting detection terminals DT1 and DT2, and mounting detection is resumed.

  In step SP8, the memory terminal is set to the high impedance state HZ. Here, when a short circuit between terminals (for example, DT1-CO1, DT2-CO2) has occurred, the short circuit detection unit 310 can detect this.

  As shown in the flowchart of FIG. 9, according to the printing apparatus of the present embodiment, when the memory is not accessed, the memory detection terminals DT1 and DT2 and the short-circuit detection terminals CO1 and CO2 are short-circuited by setting the memory terminals to a high impedance state. By doing so, it is possible that the memory terminal is also short-circuited with the mounting detection terminals DT1 and DT2, and the application of VHO is stopped, and the possibility that VHO is applied to the storage device 203 can be reduced. As a result, it is possible to realize highly reliable memory access while performing mounting detection.

  10A to 10D show detailed configuration examples of the output circuits OB1 to OB4 and the input / output circuit IOB. 10A is a configuration example of OB1 and OB2, FIG. 10B is a configuration example of OB4, FIG. 10C is a configuration example of OB3, and FIG. 10D is a configuration example of IOB. The output circuits OB1, OB2, OB3, OB4, and the input / output circuit IOB respectively correspond to the buffer circuits BR1, BC1, BD1, BS1, IO1 (or BR2, BC2, BD2, BS2, IO2) of FIG. The output circuits OB1 to OB4 and the input / output circuit IOB according to the present embodiment are not limited to the configurations shown in FIGS. 10A to 10D, and some of the components may be omitted or other components may be used. Various modifications such as replacement with the above or addition of other components are possible.

  As shown in FIG. 10A, the output circuits OB1 and OB2 include P-type transistors TP1 and TP2 and N-type transistors TN1, TN2, and TN3. TP1 and TN1 are for preventing element destruction (electrostatic breakdown) due to electrostatic discharge (ESD). TP2 and TN2 are respectively controlled by control signals S1 and S2, and set the terminal CSCK (or CRST) to the H level, the L level, or the high impedance state. Specifically, when both S1 and S2 are at the L level, the terminal CSCK (CRST) is set to the H level, and when both S1 and S2 are at the H level, the terminal CSCK (CRST) is set to the L level. When S2 is at the L level, the high impedance state is set. TN3 is controlled by the control signal S3, and when normal, S3 is at the L level. However, for example, when an abnormal condition such as when a high voltage is detected, S3 becomes H level, and amplification is performed to lower the terminal CSCK (CRST) to the L level. Act as a buffer

  As shown in FIG. 10B, the output circuit OB4 includes a P-type transistor TP4 and an N-type transistor TN4 controlled by the control signal S4. When the control signal S4 is at the H level, the terminal CVSS is set to the VSS level (ground level), and when the control signal S4 is at the L level, the terminal CVSS is set to the high impedance state. TP4 is an element for preventing electrostatic breakdown, and TN4 also operates as an element for preventing electrostatic breakdown.

  As shown in FIG. 10C, the output circuit OB3 includes a P-type transistor TP5 controlled by the control signal S5 and an N-type transistor TN5 controlled by the control signal S6. When the control signals S5 and S6 are both at the L level, the terminal CVDD is set to the VDD level, and when both the control signals S5 and S6 are at the H level, the terminal CVDD is set to the VSS level. When S5 is at H level and S6 is at L level, a high impedance state is set. Note that TP5 and TN5 also operate as an electrostatic breakdown preventing element.

  As shown in FIG. 10D, the input / output circuit IOB includes P-type transistors TP6, TP7, TP11 and N-type transistors TN6, TN7, TN8, TN11. TP6 and TN6 are elements for preventing electrostatic breakdown. TP7 and TN7 are controlled by control signals S7 and S8, respectively. Specifically, when both S7 and S8 are at the L level, the terminal CSDA is set to the H level. When both S7 and S8 are at the H level, the terminal CSDA is set to the L level. When L is at the L level, the high impedance state is set. TP11 and TN11 constitute a transmission gate (analog switch) and are turned on / off by control signals S11 and S12. Specifically, when the terminal CSDA is used as an output terminal, S11 is set to H level, S12 is set to L level, and the transmission gate is turned off. On the other hand, when the terminal CSDA is used as an input terminal, S11 is set to L level and S12 is set to H level, the transmission gate is turned on, and the data signal input to the terminal CSDA may pass through the transmission gate. it can.

  As described above, the output circuits OB1 to OB4 and the input / output circuit IOB shown in FIGS. 10A to 10D set the memory terminals RST, SCK, VDD, VSS, and SDA to a high impedance state when mounting is detected. Before access to, the VSS level (a constant voltage level in a broad sense) can be set. The control signals S1 to S9, S11, and S12 are generated by the control unit 300 according to the above-described mounting detection and memory access flow (FIG. 9).

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. In addition, the configurations and operations of the circuit device, the storage device, the printing material container, the printing device, and the like are not limited to those described in this embodiment, and various modifications can be made.

10 circuit device, 100 printing material container, 110 ink supply port,
120 ink storage chamber, 131, 132 holes, 134 uneven fitting portion,
200 substrate, 201 boss groove, 202 boss hole, 203 storage device,
300 control unit, 310 short-circuit detection unit, 320 voltage application unit,
330 mounting detection unit, 340 CO detection unit, 350 communication processing unit,
360 high voltage control unit, 400 main control unit, 410 CPU,
420 memory, 430 display, 441 low voltage power supply,
442 high voltage power supply, 450 circuit board, 1000 printing device,
1100 cartridge mounting unit, 1200 cover, 1300 operation unit,
BC1, BD1, BR1, BS1, IO1 buffer circuit,
BUS bus, CCO1 short circuit detection terminal, CDT1 installation detection terminal,
CO1 short circuit detection terminal, CRST reset terminal, CSCK clock terminal,
CSDA data terminal, CVDD power supply terminal, CVSS ground terminal,
DT1 wearing detection terminal, IOB input / output circuit,
LD, LS, LPD1, LPS1 wiring, MBS common bus,
OB1 output circuit, P_SCK1 clock terminal, P_SDA1 data terminal,
P_VDD1 high potential side power supply terminal, P_VSS1 low potential side power supply terminal,
P_XRST1 reset terminal, PG1 first terminal group,
RD mounting detection resistance element, RST reset terminal, S1 control signal,
SCK clock terminal, SDA data terminal, TCV1 test terminal,
TG1 terminal group, TN1 N-type transistor, TP1 P-type transistor,
TVD high potential side power supply terminal, TVS low potential side power supply terminal, VCNT control signal,
VDD high potential side power supply voltage, VDD1 high potential side power supply terminal,
VHO mounting detection voltage, VHV high power supply voltage, VSHT short-circuit detection signal,
VSS Low-potential-side power supply voltage, VSS1 Low-potential-side power supply terminal, cp contact part

Claims (12)

A circuit device that communicates with a plurality of storage devices provided in a plurality of printing material containers,
A first potential power supply terminal to which one of a high potential side power supply voltage and a low potential side power supply voltage is supplied;
A first second potential power supply terminal and a second second potential power supply terminal to which the other of the high potential side power supply voltage and the low potential side power supply voltage is supplied;
A first terminal group provided between the first potential power supply terminal and the first second potential power supply terminal;
A second terminal group provided between the first potential power supply terminal and the second second potential power supply terminal;
Including
The first terminal group includes:
A first first potential power supply terminal for supplying a power supply voltage from the first potential power supply terminal to a first storage device of the plurality of storage devices;
A first second potential power supply terminal for supplying a power supply voltage from the first second potential power supply terminal to the first storage device;
Have
The second terminal group includes:
A second first potential power supply terminal for supplying a power supply voltage from the first potential power supply terminal to a second storage device of the plurality of storage devices;
A second second potential power supply terminal for supplying a power supply voltage from the second second potential power supply terminal to the second storage device;
Have
At least the first first potential power supply terminal and the first second potential power supply terminal of the first terminal group, and at least the second first potential power supply terminal and the first of the second terminal group. The second second potential power supply terminal is characterized in that the arrangement order of the terminals is symmetrical with respect to the first potential power supply terminal. In claim 1,
Among the terminals of the first terminal group, the first first potential power supply terminal is closest to the first potential power supply terminal,
The circuit device characterized in that the second first potential power supply terminal is closest to the first potential power supply terminal among the terminals of the second terminal group. In claim 1 or 2,
Among the terminals of the first terminal group, the first second potential power supply terminal is closest to the first second potential power supply terminal,
2. The circuit device according to claim 1, wherein the second second potential power supply terminal is closest to the second second potential power supply terminal among the terminals of the second terminal group. In any one of Claims 1 thru | or 3,
The first terminal group includes:
A first signal that supplies a data signal, a reset signal, and a clock signal based on a power supply voltage from the first first potential power supply terminal and the first second potential power supply terminal to the first storage device, respectively. A data terminal, a first reset terminal, a first clock terminal;
The second terminal group includes:
A second signal that supplies a data signal, a reset signal, and a clock signal based on the power supply voltages from the second first potential power supply terminal and the second second potential power supply terminal to the second storage device, respectively. A data terminal, a second reset terminal, a second clock terminal;
The first data terminal, the first reset terminal, and the first clock terminal, and the second data terminal, the second reset terminal, and the second clock terminal are terminals of the first potential power supply terminal. A circuit device characterized in that the arrangement order is symmetrical. In claim 4,
The first data terminal, the first reset terminal, and the first clock terminal are disposed between the first first potential power supply terminal and the first second potential power supply terminal,
The second data terminal, the second reset terminal, and the second clock terminal are disposed between the second first potential power supply terminal and the second second potential power supply terminal. A circuit device. In any one of Claims 1 thru | or 5,
A first buffer circuit for outputting the high-potential-side power supply voltage from either the first potential power supply terminal or the first second potential power supply terminal to the first first potential power supply terminal; ,
A second buffer circuit for outputting the high potential side power supply voltage from the first potential power supply terminal or the second second potential power supply terminal to the second first potential power supply terminal;
A circuit device comprising: In claim 6,
When the first storage device is not accessed, the first buffer circuit sets the first first potential power supply terminal to a high impedance state,
The circuit device, wherein the second buffer circuit sets the second first potential power supply terminal to a high impedance state when the second memory device is not accessed. In claim 6 or 7,
A first power supply wiring routed along a terminal arrangement region of the circuit device and connected to the first potential power supply terminal;
A second power supply wiring connected along the terminal arrangement region and connected to the first second potential power supply terminal and the second second potential power supply terminal;
Including
The first power supply wiring and the second power supply wiring are:
The first buffer circuit disposed in the I / O region of the first first potential power supply terminal and the second buffer circuit disposed in the I / O region of the second first potential power supply terminal And a circuit device for supplying the high potential side power supply voltage and the low potential side power supply voltage to the first buffer circuit and the second buffer circuit. In any one of Claims 1 thru | or 8.
A second first potential power supply terminal to which the one of the high potential side power supply voltage and the low potential side power supply voltage is supplied;
A third terminal group provided between the second first potential power supply terminal and the second second potential power supply terminal;
Including
The first terminal group includes:
Supplying a power supply voltage and a control signal to the first storage device among the first to n-th storage devices (n is an integer of 4 or more) as the plurality of storage devices,
The second terminal group includes:
Supplying a power supply voltage and a control signal to the second storage device and the third to n-1th storage devices among the first to nth storage devices through a common bus,
The third terminal group includes:
A circuit device that supplies a power supply voltage and a control signal to an nth memory device among the first to nth memory devices. A circuit device according to any one of claims 1 to 9,
The plurality of printing material containers provided with the plurality of storage devices; and
A printing apparatus comprising: In claim 10,
A printing apparatus, comprising: a main control unit that supplies the high-potential-side power supply voltage and the low-potential-side power supply voltage to the circuit device. In claim 10 or 11,
A printing apparatus, comprising: a circuit board provided with the circuit device; and a mounting portion on which the plurality of printing material containers are mounted.

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