JP5849744B2 - Function allocation device, function allocation program, and function allocation method - Google Patents

Description

  The present invention relates to a function placement device, a function placement program, and a function placement method, and more particularly to optimization of function placement in a function placement device.

  In recent years, the speed of processors such as a CPU (Central Processing Unit) has been rapidly increased, and the difference between the access time of an external memory such as a DRAM (Dynamic Random Access Memory) and the processing speed is increasing. For this reason, there is a problem that the execution speed of the program cannot always be increased although the processing speed of the processor is increased. Therefore, in general, in many computers, in addition to a processor that operates at high speed and an external memory such as a DRAM having a low access speed, a cache memory that is a buffer that can be accessed at high speed in order to fill the difference between these speeds. It is installed in the core of the.

  In the computer configured as described above, it is possible to realize high-speed program execution by copying a part of a function loaded on an external memory such as a DRAM having a low access speed into the cache memory. It becomes. In general, when a program is executed, a function on the external memory once accessed is likely to be accessed again in the near future. Therefore, the access speed is high so that the function once accessed can be read immediately. This is because the program can be executed efficiently by copying it to the cache memory.

  However, since a high-speed cache memory is expensive, its size must be smaller than that of an external memory. Therefore, which part of the program to be executed is stored in the cache is extremely important for executing the program at high speed. Therefore, as a technique to improve the execution speed of the program, profile the execution of the program, recompile the program so that the function address allocation is shifted so that functions with high execution frequency do not cause cache conflicts, A technique for improving the cache hit rate has been devised and already known (for example, Patent Document 1).

  According to the technique disclosed in Patent Document 1, it is possible to prevent functions with high execution frequency from being placed on the same cache line, thereby preventing the occurrence of cache conflict and improving the execution speed of a program. be able to.

  However, since the technique described in Patent Document 1 is a technique related to a processor in which a cache memory is incorporated, for example, a cache memory such as an inexpensive low-end microcomputer (hereinafter referred to as “microcomputer”) is used. In a processor that is not provided, the technique described in Patent Document 1 cannot be applied. Therefore, some microcomputers or the like that do not include a cache memory include a memory that is configured by an SRAM (Static Random Access Memory) that can be accessed at a higher speed than a DRAM instead of the cache memory. . In such a microcomputer, a DRAM having a low access speed and an SRAM having a high access speed are provided as external memories, and functions are distributed and arranged in both of them.

  As described above, in a processor that does not include a cache memory and includes both an SRAM having a high access speed and a DRAM having a low access speed as an external memory, in order to improve the execution speed of the program, It is desirable to place a long function in an SRAM memory having a high access speed. However, at present, there is a problem that it is not possible to efficiently perform the function arrangement because the user needs to manually determine the function arrangement.

  Such a problem is not limited to the memory constituted by the DRAM and the SRAM, and an external memory is constituted by a memory having a high access speed and a memory having a low access speed in view of the balance between the function and the cost. In some cases, it can be problematic as well.

  The present invention has been made to solve such a problem, and when executing a program in a system equipped with a plurality of types of memories having different reading speeds from the processor, the program is not time-consuming for the user. The purpose is to improve the execution speed.

  In order to solve the above-described problem, a plurality of functions are read out and executed on either the first storage medium or the second storage medium whose reading speed from the processor is slower than that of the first storage medium. A function arrangement apparatus for determining an arrangement order of the plurality of functions in an execution program, the execution program generation unit generating the execution program based on a source code describing the plurality of functions, and the generated execution A data size calculation unit that calculates a data size of each of the plurality of functions included in the program, and an execution time calculation unit that calculates an execution time of each of the plurality of functions included in the generated execution program, The execution program generation unit includes the data size, the execution time, the storage capacity of the first storage medium, the first storage medium, and the second storage medium. By determining the arrangement order of the plurality of functions in the execution program based on the reading speed of each medium, the first storage medium of the plurality of functions when the execution program is executed, and the It is characterized in that the read state to the second storage medium is determined.

According to another aspect of the present invention, a plurality of functions are respectively read out and executed on either the first storage medium or the second storage medium whose reading speed from the processor is slower than that of the first storage medium. A function arrangement program for determining an arrangement order of the plurality of functions in an executed program, the step of generating the execution program based on a source code describing the plurality of functions, and the generated execution program Calculating the data size of each of the plurality of functions included in the program, calculating the execution time of each of the plurality of functions included in the generated execution program, the data size, the execution time, the first The realization of the plurality of functions based on the storage capacity of one storage medium, the reading speed of each of the first storage medium and the second storage medium Determining a read state of each of the plurality of functions to the first storage medium and the second storage medium when the execution program is executed by determining an arrangement order in the program; allowed to run, it characterized in Rukoto.

  According to still another aspect of the present invention, a plurality of functions are respectively read out to either the first storage medium or the second storage medium having a slower reading speed from the processor than the first storage medium. A function arrangement method for determining an arrangement order of the plurality of functions in an execution program to be executed, wherein the execution program is generated based on a source code describing the plurality of functions, and the generated execution program The data size of each of the plurality of functions included is calculated, the execution time of each of the plurality of functions included in the generated execution program is calculated, the data size, the execution time, and the first storage medium The arrangement order of the plurality of functions in the execution program is determined based on the storage capacity, the reading speed of each of the first storage medium and the second storage medium. And by, and determines the read state of the during the execution program is executed, to the plurality of functions each of said first storage medium and said second storage medium.

  According to the present invention, when a program is executed in a system equipped with a plurality of types of memories having different reading speeds from the processor, the execution speed of the program can be improved without taking time and effort for the user.

It is a block diagram which shows typically the hardware constitutions of the function arrangement | positioning apparatus which concerns on embodiment of this invention. It is a figure which shows an example of RAM information referred when the function arrangement | positioning apparatus which concerns on embodiment of this invention arrange | positions each function in either SRAM or DRAM. It is a figure which shows an example of the function information which the function arrangement | positioning apparatus which concerns on embodiment of this invention produces | generates. It is a flowchart for demonstrating the process at the time of the function arrangement | positioning apparatus which concerns on embodiment of this invention optimizes function arrangement | positioning, and produces | generates an execution program. It is a flowchart for demonstrating the process at the time of the function arrangement | positioning apparatus which concerns on embodiment of this invention optimizing a function arrangement | positioning so that the sum total of the total execution time of a function may become the minimum. It is a figure which shows the result of the function arrangement | positioning apparatus which concerns on embodiment of this invention optimizing function arrangement | positioning.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, in a system such as a microcomputer (hereinafter referred to as “microcomputer”) including an SRAM (Static Random Access Memory) having a high reading speed from a processor and a DRAM (Dynamic Random Access Memory) having a low reading speed. A description will be given of a function placement apparatus that automatically determines the placement of functions included in an execution program when the execution program is executed by a processor such as a CPU (Central Processing Unit). That is, in this embodiment, the SRAM functions as a first storage medium, and the DRAM functions as a second storage medium.

  In such a function arrangement device, one of the gist according to the present embodiment is that when the execution program is executed by the processor in a system including an SRAM having a high reading speed from the processor and a DRAM having a low reading speed, the execution time The long function is automatically arranged in the SRAM having a high reading speed with the maximum allowable data amount.

  Therefore, according to the function arrangement device according to the present embodiment, the optimum function arrangement can be automatically determined so as to minimize the execution time of the program, so that the execution speed of the program without taking time and effort for the user. Can be improved. Details will be described below.

  FIG. 1 is a block diagram schematically showing a functional configuration of the function arrangement device 1 according to the present embodiment. As shown in FIG. 1, the function placement device 1 according to this embodiment includes a compiler 11, a linker 12, a program execution unit 13, and a profiler 14. The compiler 11 compiles the source code 2 and generates an object file 3. The generated object file 3 includes a function to be placed by the function placement apparatus 1 according to the present embodiment.

  The linker 12 generates the execution program 4 by linking the object file 3 generated by the compiler 11 and placing each function in either SRAM or DRAM. That is, here, the compiler 11 and the linker 12 function as an execution program generation unit. The linker 12 calculates the data size of each function when linking the object file 3 generated by the compiler 11. That is, here, the linker 12 functions as a data size calculation unit. The data size of each function may be calculated by a dedicated tool in addition to the linker 12. The linker 12 determines whether to arrange each function in either SRAM or DRAM based on the data size of the calculated function, RAM information described later, and profile information 5 generated by the profiler 14.

  The program execution unit 13 executes the execution program 4 generated by the linker 12. The profiler 14 generates profile information 5 by profiling a function call during program execution by the program execution unit 13. Here, the profile information 5 includes the total execution time for each function when the functions are arranged in the DRAM. Note that the profile information 5 generated by the profiler 14 is recorded on a recording medium (not shown) and is referred to when the object file 3 is linked by the linker 12.

  The profiler 14 is software that monitors the function execution time while interpreting the instruction code in the execution program one instruction at a time. For example, software such as a DBA (Dynamic Binary Analysis) tool is known. Below, the data size of the function calculated by the linker 12 and the total execution time included in the profile information 5 are collectively referred to as function information.

  Next, RAM information to be referred to when the function placement apparatus 1 according to the present embodiment places each function in either SRAM or DRAM will be described with reference to FIG. FIG. 2 is a diagram showing an example of RAM information referred to when the function placement apparatus 1 according to the present embodiment places each function in either SRAM or DRAM. As shown in FIG. 2, the RAM information referred to when the function placement apparatus 1 according to the present embodiment places each function in either SRAM or DRAM includes the start address, end address, and reading speed for each memory device. The memory size is associated and managed as a table by the function placement device 1.

  The “start address” and “end address” indicate address areas where functions can be placed. “Reading speed” is the speed at which the processor reads data from the memory device. In the example shown in FIG. 2, the time required for reading data per 4 bytes is shown. “Memory size” indicates the data size of an area allocated for function arrangement of each memory device.

  Next, function information generated by the function placement apparatus 1 according to the present embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of function information generated by the function placement apparatus 1 according to the present embodiment. As shown in FIG. 3, the function information generated by the function placement device 1 according to the present embodiment is managed in the function placement device 1 as a table in which the function data size and the total execution time are associated with each function name. Has been.

  The total execution time includes “total execution time when arranged in SRAM” and “total execution time when arranged in DRAM”, and “total execution time when arranged in DRAM” is The information included in the profile information 5 generated by the profiler 14 is the total execution time for each function when the functions are arranged in the DRAM as described above. The “total execution time when arranged in the SRAM” is a value calculated from the “total execution time when arranged in the DRAM” by the ratio of the reading speed between the SRAM and the DRAM shown in FIG. . Therefore, in the present embodiment, “total execution time when arranged in SRAM” is half of “total execution time when arranged in DRAM”. That is, here, the profiler 14 functions as an execution time calculation unit, and “total execution time when arranged in SRAM” represents the first execution time, and “total execution time when arranged in DRAM”. "Represents the second execution time.

  Next, processing when the function placement apparatus 1 according to the present embodiment optimizes function placement and generates an execution program will be described with reference to FIG. FIG. 4 is a flowchart for explaining processing when the function placement apparatus 1 according to the present embodiment optimizes function placement and generates an execution program. As shown in FIG. 4, when the function placement apparatus 1 according to the present embodiment optimizes the function placement and generates an execution program, first, the compiler 11 receives the source code 2 and compiles the object file 3. Generate (S401), and record the generated object file 3 on a recording medium or an external recording medium provided in the function placement apparatus 1. That is, here, the recording medium and the external recording medium provided in the function arrangement device 1 function as a function storage unit.

  Then, the linker 12 calculates the data size of each function by linking the object file 3 generated in S401 (S402), and places the function generated by referring to RAM information described later in the memory to execute the program. 4 is generated (S403). At this time, all the generated functions are arranged in the DRAM. When the execution program 4 is generated, the program execution unit 13 executes the generated execution program 4 and at the same time, the profiler 14 profiles the function call at the time of program execution by the program execution unit 13 to generate the profile information 5 ( S404). The profile information 5 generated here is recorded on a recording medium provided in the function arrangement device 1 or an external recording medium.

  Next, the linker 12 relinks the object file 3 generated in S401, so that the data size calculated in S402, the profile information 5 generated in S404, and the RAM information described in FIG. The function arrangement is optimized to generate the execution program 4 (S405), and the function arrangement apparatus 1 according to the present embodiment ends the process when the function arrangement is optimized and the execution program is generated.

  In the process of S405, the linker 12 arranges the generated functions in the SRAM and the DRAM so that the total execution time of the functions when the execution program 4 is executed by the program execution unit 13 is minimized. In the process of S405, if the object file 3 generated in S401 is not readable from the function placement device 1, the compiler 11 receives the source code 2 again, compiles it, and generates the object file 3 again. Anyway.

  Next, FIG. 5 shows details of the processing when the function placement device 1 according to the present embodiment optimizes the function placement so that the total execution time of the functions is minimized, that is, the details of the processing of S405 in FIG. The description will be given with reference. FIG. 5 is a flowchart for explaining processing when the function placement apparatus 1 according to the present embodiment optimizes function placement so that the total total execution time of functions is minimized.

  As shown in FIG. 5, when the function placement apparatus 1 according to the present embodiment optimizes function placement so that the total total execution time of functions is minimized, the linker 12 first determines that the total data size is Any one of the generated functions is arbitrarily selected so as to fit in the size of the area allocated for function arrangement on the SRAM (S501). In this case, the difference between the size of the area allocated for function arrangement on the SRAM and the sum of the data sizes of the selected functions should not be larger than the data size of any other functions not selected. Selected.

  The linker 12 calculates the total execution time T1 when the functions selected in S501 are arranged in the SRAM with reference to FIG. 3, and refers to FIG. 3 for the functions not selected in S501. The total T2 of the total execution time when arranged in the DRAM is calculated, and the sum of T1 and T2 is calculated as the total T of the total execution time of the function (S502). That is, in S502, the execution time of the execution program 4 by the processor in the microcomputer is calculated.

  For all possible combinations (S503 / NO, S504), the linker 12 selects a function in the same manner as the processing of S501 and S502, and calculates the total T of the total execution time of the function. When the linker 12 has finished calculating the total T of the total execution time of the functions for all the combinations (S503 / YES), the linker 12 sets the combination when the total T of the total execution times of the functions becomes the minimum as the optimal function arrangement ( S505). Then, the linker 12 generates an execution program by allocating functions to the SRAM and DRAM according to the allocation (S506), so that the function allocation apparatus 1 according to the present embodiment minimizes the total execution time of the functions. The processing for optimizing the function arrangement is finished.

  As a result of optimizing the function arrangement in this way, as shown in FIG. 6, in this embodiment, “FuncB” is arranged in the DRAM, and “FuncA”, “FuncC”, “FuncD” and “FuncE” are arranged, and the total of the total execution time T of the function at that time is “23010 (ms)”.

  As described above, the function placement apparatus 1 according to the present embodiment has a long execution time when a program is executed by a processor in a system including an SRAM having a high reading speed from the processor and a DRAM having a low reading speed. The function can be automatically arranged in the SRAM having a high reading speed at the maximum limit of the data allowance.

  Therefore, according to the function arrangement device 1 according to the present embodiment, the optimum function arrangement can be automatically determined so as to minimize the execution time of the program. Speed can be improved.

  In the present embodiment, the microcomputer constituted by the DRAM and the SRAM has been described. However, the present invention is not limited to the microcomputer constituted by the DRAM and the SRAM, and a memory having a high reading speed from the processor and a memory having a low reading speed. The microcomputer may constitute an external memory.

  In the present embodiment, a microcomputer having two types of memories, DRAM and SRAM, has been described. Furthermore, a memory having a faster reading speed from a processor than an SRAM such as TCM (Title Coupled Memory) or a DRAM. A microcomputer having a memory with a slow reading speed may be used. Even in such a case, as described in the present embodiment, the same function and effect can be obtained by arranging the functions so that the total execution time of the functions is minimized.

DESCRIPTION OF SYMBOLS 1 Function allocation apparatus 2 Source code 3 Object file 4 Execution program 5 Profile information 11 Compiler 12 Linker 13 Program execution part 14 Profiler

JP 2003-271394 A

Claims (9)

The plurality of functions in an execution program in which a plurality of functions are read out and executed in any one of the first storage medium and the second storage medium whose reading speed from the processor is slower than that of the first storage medium A function placement device for determining the placement order of
An execution program generation unit that generates the execution program based on source code describing the plurality of functions;
A data size calculator that calculates the data size of each of the plurality of functions included in the generated execution program;
An execution time calculation unit that calculates an execution time of each of the plurality of functions included in the generated execution program;
Including
The execution program generation unit is configured to calculate the plurality of functions based on the data size, the execution time, the storage capacity of the first storage medium, the reading speed of each of the first storage medium and the second storage medium. By determining the arrangement order in the execution program, the read state of the plurality of functions to the first storage medium and the second storage medium when the execution program is executed is determined. A function arrangement device characterized by the above.   The execution time calculation unit is a second execution time that is an execution time of each of the plurality of functions when each of the plurality of functions included in the execution program is read and executed on the second storage medium. The function allocating device according to claim 1, wherein The execution time calculation unit is configured to calculate each of the plurality of functions included in the execution program from the second execution time based on a ratio of reading speeds of the first storage medium and the second storage medium. 3. The function arrangement device according to claim 2 , wherein a first execution time which is an execution time of each of the plurality of functions when read and executed on the first storage medium is calculated. The execution program generation unit generates the plurality of functions based on the source code,
4. The function arrangement device according to claim 1, further comprising a function storage unit that stores the plurality of generated functions. 5.   The execution program generation unit determines the arrangement order of the plurality of functions in the execution program so that the total execution time of each of the plurality of functions is the shortest, whereby the execution program is executed. 5. The function arrangement device according to claim 1, wherein a read state of each of the plurality of functions to the first storage medium and the second storage medium is determined. The execution program generator generates the first function in ascending order of the first execution time so as to be as close as possible to the upper limit of the storage capacity of the first storage medium based on the data size. An arrangement order of the plurality of functions in the execution program is arranged such that a function that is not arranged in the first storage medium among the plurality of functions is arranged in the second storage medium. by determining, in claim 3, wherein the determining the read state of the during the execution program is executed, to the plurality of functions each of said first storage medium and said second storage medium The function placement device described.   The arrangement order is such that the execution time is the shortest among all arrangement orders that can be arranged when the plurality of functions are arranged on either the first storage medium or the second storage medium. The function placement device according to claim 1, wherein the function placement device is a function placement device. The plurality of functions in an execution program in which a plurality of functions are read out and executed in any one of the first storage medium and the second storage medium whose reading speed from the processor is slower than that of the first storage medium A function placement program that determines the placement order of
Generating the execution program based on source code describing the plurality of functions;
Calculating a data size of each of the plurality of functions included in the generated execution program;
Calculating an execution time of each of the plurality of functions included in the generated execution program;
Arrangement order of the plurality of functions in the execution program based on the data size, the execution time, the storage capacity of the first storage medium, the reading speed of each of the first storage medium and the second storage medium Determining a read state of each of the plurality of functions to the first storage medium and the second storage medium when the execution program is executed,
The function configuration program characterized Rukoto is executed. The plurality of functions in an execution program in which a plurality of functions are read out and executed in any one of the first storage medium and the second storage medium whose reading speed from the processor is slower than that of the first storage medium A function arrangement method for determining the arrangement order of
Generating the execution program based on source code describing the plurality of functions;
Calculating a data size of each of the plurality of functions included in the generated execution program;
Calculating an execution time of each of the plurality of functions included in the generated execution program;
Arrangement order of the plurality of functions in the execution program based on the data size, the execution time, the storage capacity of the first storage medium, the reading speed of each of the first storage medium and the second storage medium Determining the read state of each of the plurality of functions to the first storage medium and the second storage medium when the execution program is executed. .

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