JP5846779B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device such as a high electron mobility transistor (HEMT) and a laser diode, and more particularly to a semiconductor device including a nitride semiconductor layer and a manufacturing method thereof.

  One of the important issues for operating a HEMT using a group III nitride semiconductor at high output and high frequency is to sufficiently reduce the contact resistance of the source / drain electrodes. This is because if the contact resistance is large, the parasitic resistance increases and the transconductance decreases, resulting in a decrease in output voltage and operating frequency.

  As means for obtaining a good ohmic contact with an n-type group III nitride semiconductor layer, Patent Document 1 discloses that an alloy containing Ti and Al, or Ti and Al are laminated on a Si-doped GaN layer. A method for forming an electrode from a plurality of films is described.

  However, if an electrode containing Al is employed as in the method described in Patent Document 1, the contact resistance can be lowered, but the electrode is damaged by etching in the forming process. Therefore, Patent Document 2 proposes an electrode structure mainly composed of Nb instead of Al.

JP-A-7-221103 JP 2010-212406 A

  However, as a result of investigation, the inventor has found that even when the three-layer stacked type ohmic electrode proposed in Patent Document 2 is formed, the electrode may be damaged by etching. In the technique of Patent Document 2, although the heat treatment is performed for a short time at a temperature of 400 to 700 ° C. after the electrode is formed, the mutual diffusion of refractory metals such as Nb and Pt is not sufficient. The inventor thought that this might cause galvanic corrosion due to the standard electrode potential difference in the case of, and erosion in the order of low corrosion resistance of the metal layer.

  Accordingly, the present invention has been made in view of the above-described problems, and provides a technique capable of improving ohmic characteristics in a semiconductor device and having high resistance to acid / alkali corrosion. The purpose is to do.

The semiconductor device according to the present invention, have a impurity region to which an impurity is _{added, Al x Ga 1-x N} (0 ≦ x ≦ 1) layer, _{or, Al x In y Ga 1-} xy N (0 ≦ x ≦ a 1,0 ≦ y ≦ 1, x + y ≦ 1) nitride ing from layer semiconductor layer, viewed including the underlying electrode layer and the main electrode layer which are sequentially stacked on the impurity region, the nitride semiconductor layer and the ohmic And an electrode to be contacted . The main electrode layer contains, as a main component, an alloy composed of Nb having a work function closer to that of the nitride semiconductor layer than the base electrode layer and Pt having a lower ionization tendency than hydrogen. The base electrode layer contains, as a main component, any one of Ti, Ta, and Ni as a metal having a higher reactivity with nitrogen than the main electrode layer, and Nb diffused from the main electrode layer .

  According to the present invention, the main electrode layer includes the first metal having a work function closer to the nitride semiconductor layer than the base electrode layer, and the base electrode layer also includes the first metal. Therefore, a semiconductor device with good ohmic characteristics can be obtained. The main electrode layer includes a second metal having a smaller ionization tendency than hydrogen as an alloy with the first metal. As a result, the interdiffusion between the first metal and the second metal can be improved as compared with the conventional structure in which these are laminated as a metal layer, so that a semiconductor device having high resistance to acid / alkali corrosion is obtained. Can do.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. It is a graph which shows the electricity supply characteristic according to the injection | pouring presence or absence of an impurity. It is a graph which shows the relationship between Si density | concentration and depth. It is a figure which shows the contact resistance of a sample. 6 is a cross-sectional view showing a configuration of a HEMT according to a second embodiment. FIG.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device includes a nitride semiconductor layer 1 having a high concentration impurity region (impurity region) 2 into which n-type impurities are implanted (added), and an electrode including a plurality of electrode layers provided on the high concentration impurity region 2 11. It is assumed that nitride semiconductor layer 1 is formed on a SiC substrate (not shown).

In the present embodiment, n-type impurities are implanted into nitride semiconductor layer 1 under electrode 11 to form high concentration impurity region 2. Although details will be described later, since the carrier concentration in the high-concentration impurity region 2 is increased, the contact resistance in the contact region between the electrode 11 (ohmic electrode) and the nitride semiconductor layer 1 can be reduced. It has become. In the present embodiment, the n-type impurity in the high-concentration impurity region 2 is Si, and the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ .

  FIG. 2 shows current-carrying characteristics when Si is implanted as an n-type impurity into the nitride semiconductor layer 1 made of AlGaN (open square points) and current-carrying characteristics when not implanted (black circle points). It is a graph which shows. The horizontal axis represents the applied voltage, and the vertical axis represents the current flowing through the semiconductor device. According to this graph, when Si is injected, the current value increases in proportion to the magnitude of the applied voltage, and a good ohmic property can be confirmed, but when Si is not injected, the applied voltage is Regardless, almost no current flows. In the present embodiment, Si is implanted into the nitride semiconductor layer 1 to form the high-concentration impurity region 2 as described above, so that the ohmic property is good.

  Next, the electrode 11 formed on the high-concentration impurity region 2 includes a base electrode layer 3, a main electrode layer 4, and a protective electrode layer 5 that are sequentially stacked.

  The base electrode layer 3 contains a metal having a higher reactivity with nitrogen than the main electrode layer 4 as a main component. Therefore, it becomes easy to combine with nitrogen in the nitride semiconductor layer 1, and the adhesion between the electrode 11 and the nitride semiconductor layer 1 is increased. That is, the electrode 11 is difficult to peel off from the nitride semiconductor layer 1. In the present embodiment, the base electrode layer 3 contains Ti as a main component, and the base electrode layer 3 has a thickness of 20 nm. The base electrode layer 3 also contains a first metal described below.

  The main electrode layer 4 contains an alloy composed of a first metal and a second metal as a main component. Here, the first metal is a metal whose work function is closer (lower in this case) than that of the base electrode layer 3 to the nitride semiconductor layer 1. The second metal is, for example, a noble metal and is a metal having a smaller ionization tendency than hydrogen. Although details will be described later, the electrode 11 includes such a main electrode layer 4, thereby having an ohmic electrode having low resistance and high corrosion resistance. In the present embodiment, the first metal and the second metal are Nb and Pt, respectively, and the main electrode layer 4 has a thickness of 50 nm.

  The protective electrode layer 5 contains a metal (for example, any one of Sb, Bi, Cu, Ag, Pd, Au, Pt, and Ir) having a smaller ionization tendency than hydrogen as a main component, and erodes the main electrode layer 4. Suppressed. In the present embodiment, the metal of the protective electrode layer 5 is the same metal (Pt) as the second metal, and the thickness of the protective electrode layer 5 is 55 nm.

  In the present embodiment, the protective electrode layer 5 is provided on the main electrode layer 4 in order to greatly enhance the corrosion resistance of the main electrode layer 4, but even if the protective electrode layer 5 is not provided. The corrosion resistance can be increased by the action of the second metal in the main electrode layer 4. However, it is preferable to provide the protective electrode layer 5 from the viewpoint of reliably suppressing erosion along the grain boundary of the alloy due to long-term exposure to acid / alkali, that is, enhancing the corrosion resistance of the main electrode layer 4. . In addition, the metal contained in the protective electrode layer 5 need not be the same metal as the noble metal contained in the main electrode layer 4, but the galvanic corrosion caused by the standard electrode potential difference caused when different metals are used. From the viewpoint of suppression, it is preferable to use the same metal unless there are special circumstances.

  Next, it will be described that the problem can be solved by taking the structure of the semiconductor device as described above.

  First, the ohmic property is improved by implanting (adding) high-concentration impurities (n-type impurities) into the nitride semiconductor layer 1. Here, in general, when a metal and a semiconductor are joined, the Fermi levels of these two substances must match in a thermal equilibrium state, so ideally the difference between the work function of the metal and the electron affinity of the semiconductor. An energy barrier corresponding to is present at the interface between the metal and the semiconductor.

  In contrast, in the present embodiment, since the impurity is added to the nitride semiconductor layer 1 as described above, the energy band due to the metal / semiconductor contact is modulated, and the electrode 11 to which the impurity is added is added. The conduction band energy near the interface is reduced. As a result, although the height of the above-described energy barrier does not change, the thickness is reduced, and the probability that electrons tunnel through the energy barrier can be increased. Therefore, contact resistance can be reduced.

  Second, the base electrode layer 3 is combined with nitrogen in the nitride semiconductor layer 1 to stabilize the electrode 11 by forming a nitride. That is, the occurrence of peeling of the electrode 11 from the nitride semiconductor layer 1 can be suppressed. In addition, nitrogen vacancies generated by the elimination of nitrogen in nitride semiconductor layer 1 function as n-type impurities. Therefore, the effect of thinning the energy barrier described above can be obtained, and the contact resistance can be expected to be reduced. In addition, although there exist Ti, Ta, Ni as the base electrode layer 3 which can anticipate the above two effects, if the base electrode layer 3 is formed using Ti and Ta which are easy to form a nitride, it is excellent. Can be expected.

  Thirdly, the selection of the base electrode layer 3 as described above has a main purpose of facilitating the formation of nitrides and suppressing the peeling of the electrode 11, and does not have the main purpose of reducing the contact resistance. Therefore, the main electrode layer 4 is configured to reliably reduce the contact resistance.

  Specifically, as described above, the height of the energy barrier existing at the metal / semiconductor contact interface corresponds to the difference between the work function of the metal and the electron affinity of the semiconductor. Here, in the present embodiment, the main electrode layer 4 includes a metal whose work function is close to the electron affinity of the nitride semiconductor layer 1 as the first metal, and the first metal is nitrided in the base electrode layer 3. It is diffused so as to be in contact with the physical semiconductor layer 1. Therefore, according to the present embodiment, the height of the energy barrier can be reduced, and the probability that electrons move beyond the energy barrier and the tunnel probability can be increased. Therefore, a reduction in contact resistance can be expected. For reference, the work function of a metal and the electron affinity data of a semiconductor are cited as follows: Ti (4.33 eV), Ta (4.25 eV), Ni (5.15 eV), Al (4.28 eV), Nb (4.3 eV), GaN (4.1 eV), and AlN (0.6 eV).

  In order for the first metal to diffuse in the base electrode layer 3 and come into contact with the nitride semiconductor layer 1, it is necessary for the metal of the main electrode layer 4 and the metal of the base electrode layer 3 to mutually diffuse. is there. Therefore, for example, it is essential to perform a treatment such as heat treatment after the formation of the base electrode layer 3 and the main electrode layer 4 to promote diffusion. Here, when the film thickness of the base electrode layer 3 is made too thin so that the first metal can easily come into contact with the nitride semiconductor layer 1, the above-described nitrogen vacancies are hardly generated, so that the contact resistance increases. Conversely, if the base electrode layer 3 is made too thick so that nitrogen vacancies are likely to be generated, the interdiffusion cannot be performed sufficiently, and the contact resistance is considered to increase. Therefore, it is desirable to provide an upper limit and a lower limit on the film thickness of the base electrode layer 3 as will be described later.

  Now, if the main electrode layer 4 is formed using only the first metal having a work function close to the electron affinity of the nitride semiconductor layer 1, it is difficult to obtain sufficient corrosion resistance against acid / alkali. is there.

  Therefore, fourthly, in the present embodiment, the main electrode layer 4 contains a metal having a smaller ionization tendency than hydrogen ions, that is, a metal having high chemical stability, as the second metal. Moreover, in the present embodiment, the main electrode layer 4 includes such a second metal as an alloy with the first metal. Thereby, since the interdiffusion between the first metal and the second metal can be improved as compared with the conventional structure in which these are laminated as a metal layer, it can have high resistance to corrosion by acid / alkali. In addition, from the viewpoint of surely suppressing deterioration of corrosion resistance to acids and alkalis due to the transformation of the electrode material due to natural oxidation, the second metal is preferably a noble metal that is difficult to oxidize, such as Au or Pt.

<Manufacturing process>
Next, a manufacturing process of the semiconductor device according to the present embodiment will be described.

<Formation of Nitride Semiconductor Layer 1 and High Concentration Impurity Region 2>
First, one or more layers of n-type Al _x Ga _1-x N (0 ≦ x ≦ 1) are formed on a SiC substrate (not shown) by metal organic chemical vapor deposition (MOCVD). These layers are epitaxially grown to form the nitride semiconductor layer 1. Then, Si ions are selectively implanted into the nitride semiconductor layer 1.

FIG. 3 shows the relationship between the Si concentration and the depth when Si ions are implanted into the nitride semiconductor layer 1 with an acceleration energy of 30 to 200 KeV and an implantation concentration of 1 × 10 ¹⁵ cm ⁻² by Monte Carlo calculation. It is the calculated | required graph. From FIG. 3, when the acceleration energy is 50 KeV, the implantation concentration is 1 × 10 ¹⁵ cm ⁻² , and Si ions are implanted into the nitride semiconductor layer 1 described above, the Si concentration on the surface of the nitride semiconductor layer 1 Is 1 × 10 ¹⁹ cm ⁻³ or more.

Based on the above results, in this embodiment, the acceleration energy is 50 KeV, the implantation concentration is 1 × 10 ¹⁵ cm ⁻² , and Si ions are implanted into the nitride semiconductor layer 1, so that the Si concentration on the surface is reduced. A high concentration impurity region 2 having a density of 1 × 10 ¹⁹ cm ⁻³ is formed. However, the formation of the high concentration impurity region 2 is not limited to this, and the Si concentration on the surface of the nitride semiconductor layer 1 is 1 × 10 ¹⁹ cm ⁻ by increasing the implantation concentration to 1 × 10 ¹⁵ cm ⁻² or more. ^It may be ³ or more. Although it is possible to form the electrode 11 that does not easily peel from the nitride semiconductor layer 1 without performing Si ion implantation, in this embodiment, the ohmic characteristics are improved as shown in FIG. The injection is carried out.

  Thereafter, a rapid thermal annealing (RTA) process is performed on the nitride semiconductor layer 1 having the high concentration impurity region 2 at a temperature of 1100 to 1200 ° C. for a short time.

<Formation of electrode 11>
Next, the electrode 11 is formed. Here, a resist pattern (not shown) is formed on the nitride semiconductor layer 1 other than where the electrode 11 is formed, that is, where the high-concentration impurity region 2 is formed. And after laminating | stacking the base electrode layer 3, the main electrode layer 4, and the protective electrode layer 5 in order by the vapor deposition method etc. on each of the nitride semiconductor layer 1 in which the resist pattern was not formed, and a resist pattern, The resist pattern is removed. That is, in this embodiment mode, the electrode 11 is formed using a lift-off method.

  Next, the formation of the base electrode layer 3, the main electrode layer 4, and the protective electrode layer 5 will be described in detail.

  First, the base electrode layer 3 is formed using a metal whose energy for forming a bond with nitrogen is lower than that of the metal of the main electrode layer 4. Thereafter, the main electrode layer 4 is formed on the base electrode layer 3 using an alloy composed of the first and second metals described above. Then, the protective electrode layer 5 is formed on the main electrode layer 4 using a metal having a smaller ionization tendency than hydrogen.

  Here, the main electrode layer 4 may be formed by vapor deposition or sputtering using a target in which the first and second metals are pre-alloyed. Alternatively, the main electrode layer 4 may be formed by putting a target composed of the first and second metals alone into the same crucible and co-depositing while melting with an electron beam. However, in the latter case, since the first and second metals may not be deposited at the same time due to differences in the melting points and thermal conductivities of the first and second metals, the first and second metals whose melting points and thermal conductivities are not significantly different. It is thought that it can be adopted only for.

  In the present embodiment, the base electrode layer 3, the main electrode layer 4, and the protective electrode layer 5 are formed to have thicknesses of 20 nm, 50 nm, and 55 nm, respectively, that is, the electrode 11 has a thickness of 125 nm. To do. The thickness of these electrode layers will be described later in detail.

<Alloying electrode 11>
Then, as a process of promoting the mutual diffusion of various metals in the base electrode layer 3 and the main electrode layer 4 including the diffusion of the first metal from the main electrode layer 4 to the base electrode layer 3, it is performed at 650 to 1000 in a nitrogen atmosphere. Perform a short RTA treatment at a temperature of ° C.

  Here, the upper limit of the temperature of RTA is set to 1000 ° C. However, if only the improvement of metal thermal diffusion is considered, it should be as high as possible among the temperatures below the melting point of the metal element constituting electrode 11. Is preferred. However, since it should be considered that the nitride semiconductor layer 1 may be decomposed at a temperature exceeding 1000 ° C., which is close to the growth temperature of the nitride semiconductor, RTA here is a temperature of 1000 ° C. or less. Should be kept in.

As a result of interdiffusion by RTA, the first metal (Nb in this case) in the alloy of the main electrode layer 4 comes into contact with the nitride semiconductor layer 1 in the base electrode layer 3. In the present embodiment, since the first metal has a work function closer to that of the nitride semiconductor layer 1 than that of the base electrode layer 3 that is a metal nitride, an energy barrier between the electrode 11 and the nitride semiconductor layer 1 is used. The electrode 11 having a low contact resistance can be obtained. Separately from this, in the present embodiment, the nitride semiconductor layer 1 contains Si as an impurity, and the impurity concentration is set to 1 × 10 ¹⁹ cm ⁻³ or more. Therefore, the electrode 11 and the nitride semiconductor layer 1 The energy barrier between the two can be reduced. This works effectively in obtaining the electrode 11 with low contact resistance.

As described above, in the present embodiment, nitride semiconductor layer 1 contains Si as an impurity in an amount of 1 × 10 ¹⁹ cm ⁻³ or more, and the first metal has a work function close to that of nitride semiconductor layer 1. Since the base electrode layer 3 and the main electrode layer 4 contain the synergistic effect by these. Therefore, in the present embodiment, it is possible to obtain the electrode 11 in which the contact resistance is relatively greatly reduced.

<Thickness of base electrode layer 3>
As described above, the semiconductor device according to the present embodiment can be manufactured. In the above description, the thicknesses of the base electrode layer 3, the main electrode layer 4, and the protective electrode layer 5 are 20 nm, 50 nm, and 55 nm, respectively. However, the thicknesses are not necessarily required. However, as already described, in this embodiment, the ohmic characteristics are improved by generating nitrogen vacancies, and the first metal contained in the main electrode layer 4 is diffused to contact the nitride semiconductor layer 1. Therefore, it is expected that the film thickness of the base electrode layer 3 has an upper limit and a lower limit.

Therefore, first, in order to examine the lower limit of the film thickness, evaluation was performed by changing the film thickness of the base electrode layer 3. Specifically, the film thickness of the main electrode layer 4 made of an alloy of Nb and Pt is made constant at 50 nm, and the base electrode layer 3 made of Ti is formed with a film thickness of 10 nm, 15 nm, 20 nm, and 25 nm, respectively. Along with this, protective electrode layers 5 made of Pt were formed with film thicknesses of 65 nm, 60 nm, 55 nm, and 50 nm, respectively. That is, the sample was prepared by keeping the total thickness of the electrodes 11 constant at 125 nm. And about these samples from which the thickness of the base electrode layer 3 and the protective electrode layer 5 differs, contact resistance (contact resistance) (rho) _c was _calculated | required by TLM (Transfer Length Method) method.

  FIG. 4 is a diagram showing the results at that time. The horizontal axis indicates the film thickness of Ti (base electrode layer 3), and the horizontal axis indicates the contact resistance. According to this, when the Ti film thickness is 15 nm or less, the contact resistance tends to increase rapidly. Therefore, it can be seen that the thickness of the base electrode layer 3 is preferably 15 nm or more.

  Next, the upper limit of the thickness of the base electrode layer 3 will be described. The effect of the base electrode layer 3 is to improve the adhesion of the electrode 11 to the nitride semiconductor layer by bonding with nitrogen in the nitride semiconductor layer 1. No attention is paid to wet etching resistance. Here, if the base electrode layer 3 is formed too thick, the first metal of the main electrode layer 4 is prevented from diffusing and coming into contact with the nitride semiconductor layer 1, and the contact resistance cannot be reduced. . Not only that, the result is a lack of corrosion resistance to acid and alkali at the electrode 11 which is a problem. Empirically, if the base electrode layer 3 is formed so that its film thickness is 25 nm or less, which is the maximum value in FIG. 4, ohmic characteristics are good and etching resistance such as wet etching is good. .

  In summary, the base electrode layer 3 is desirably formed in a range of 15 nm to 25 nm. Thereby, it is possible to obtain the electrode 11 having high adhesion with the nitride semiconductor layer 1 and having good ohmic characteristics.

<Effect>
In the present embodiment, the main electrode layer 4 includes a first metal (Nb in this case) having a work function closer to that of the nitride semiconductor layer 1 than that of the base electrode layer 3, and the base electrode layer 3 also includes the first metal ( Here, the first metal diffused) is included. Therefore, a semiconductor device with low contact resistance, that is, good ohmic characteristics can be obtained. Further, the main electrode layer 4 contains a second metal (here, Pt) having a smaller ionization tendency than hydrogen as an alloy with the first metal. As a result, the interdiffusion between the first metal and the second metal can be improved as compared with the conventional structure in which these are laminated as a metal layer, so that a semiconductor device having high resistance to acid / alkali corrosion is obtained. Can do. In addition, since the base electrode layer 3 contains a metal that is more reactive with nitrogen than the main electrode layer 4, the occurrence of peeling of the electrode 11 from the nitride semiconductor layer 1 can be reduced.

  In the present embodiment, the protective electrode layer 5 is provided on the main electrode layer 4. Therefore, since the oxidation of the main electrode layer 4 can be prevented, resistance to corrosion by acid / alkali can be enhanced. In addition, an effect of ensuring etching resistance such as dry etching can be expected.

  In the present embodiment, the electrode 11 is subjected to RTA treatment for promoting the diffusion of the first metal from the main electrode layer 4 to the base electrode layer 3. Therefore, the ohmic characteristics can be improved. Further, diffusion of the second metal can be expected, and an effect of ensuring etching resistance such as wet etching can be expected.

In the present embodiment, the impurity in the high concentration impurity region 2 is Si, and the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more. Therefore, the ohmic characteristics can be improved.

  In the present embodiment, the base electrode layer 3 is mainly composed of Ti. Thereby, it is possible to achieve both good adhesion of the electrode 11 to the nitride semiconductor layer 1 and improvement of ohmic characteristics. Note that the base electrode layer 3 does not have to contain Ti as a main component as long as both of these can be achieved. For example, Ta or Ni may be used as a main component. That is, the base electrode layer 3 may be composed mainly of any one of Ti, Ta, and Ni.

  In the present embodiment, the base electrode layer 3 has a thickness of 15 nm or more. Thereby, an ohmic characteristic can be made more favorable.

Further, in the present embodiment, the nitride semiconductor layer _{1, Al x Ga 1-x N} (0 ≦ x ≦ 1) is a one layer or more layers of layer, the nitride semiconductor layer 1, Al _x The layer is not limited to the Ga _1-x N (0 ≦ x ≦ 1) layer, but other crystal layers such as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) layer may be included. Even in this case, a semiconductor device similar to that described above can be obtained.

  In the above description, the nitride semiconductor layer 1 is formed by the MOCVD method, but may be formed by using another epitaxial growth method such as an MBE (Molecular Beam Epitaxy) method. Although the substrate on which the nitride semiconductor layer 1 is formed is SiC, the same effect as described above can be obtained even if it is a GaN substrate, AlN substrate, Si substrate, or sapphire substrate.

<Embodiment 2>
FIG. 5 is a cross-sectional view schematically showing the structure of the HEMT according to the second embodiment of the present invention. Hereinafter, in the description of the HEMT according to the present embodiment, components similar to those described in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

The HEMT according to the present embodiment includes a substrate 21, a buffer layer 22 formed on the substrate 21 in order, a channel layer 23, a barrier layer 24 corresponding to the above-described nitride semiconductor layer 1, and the above-described electrode 11. A corresponding source / drain electrode 25 and a gate electrode 26 provided between the source / drain electrodes 25 are provided. Here, high-concentration impurity regions 2 having Si as an impurity and an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ are provided from the surface of the barrier layer 24 to the channel layer 23.

<Manufacturing process>
Next, a process for manufacturing the HEMT according to the present embodiment will be described. First, the buffer layer 22, the channel layer 23, and the barrier layer 24 are formed in this order on the substrate 21. Next, only in the region where the source / drain electrode 25 is formed, the acceleration energy is set to 50 KeV, the implantation concentration is set to 1 × 10 ¹⁵ cm ⁻² , and Si ions are channeled by the same method as in the first embodiment. 23 and the barrier layer 24 are implanted to form the high concentration impurity region 2.

  Next, a resist pattern (not shown) is formed on the barrier layer 24 other than the place where the source / drain electrode 25 is formed, that is, the place where the high-concentration impurity region 2 is formed, by the same method as in the first embodiment. To do. And after laminating | stacking the base electrode layer 3, the main electrode layer 4, and the protective electrode layer 5 in this order on each of the barrier layer 24 and the resist pattern in which the resist pattern was not formed, the resist pattern is removed. That is, in the present embodiment, the source / drain electrodes 25 are formed using a lift-off method. Similarly, the gate electrode 26 is formed by a lift-off method.

  In the HEMT configured as described above, the contact resistance value of the source / drain electrode 25 is reduced as in the first embodiment. Therefore, a HEMT that can operate at a high voltage and a high frequency can be obtained.

  In the above description, the case where the present invention is applied to a planar transistor has been described. However, the same effect as that of this embodiment can be obtained also when applied to a gate recess structure formed by selective etching or selective growth. .

  DESCRIPTION OF SYMBOLS 1 Nitride semiconductor layer, 2 high concentration impurity area | region, 3 base electrode layer, 4 main electrode layer, 5 protective electrode layer, 11 electrodes.

Claims (9)

It has an impurity region to which an impurity is added, and an Al _x Ga _1-x N (0 ≦ x ≦ 1) layer or Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) , X + y ≦ 1) nitride semiconductor layer,
Including a base electrode layer and a main electrode layer sequentially stacked on the impurity region, and an electrode in ohmic contact with the nitride semiconductor layer;
The main electrode layer includes, as a main component, an alloy composed of Nb having a work function closer to the nitride semiconductor layer than the base electrode layer and Pt having a lower ionization tendency than hydrogen,
The base electrode layer includes, as a main component, any one of Ti, Ta, and Ni as a metal having higher reactivity with nitrogen than the main electrode layer, and Nb diffused from the main electrode layer. . The semiconductor device according to claim 1,
The electrode is
A semiconductor device further comprising a protective electrode layer provided on the main electrode layer and containing Pt as a main component, which has a smaller ionization tendency than hydrogen. The semiconductor device according to claim 1 or 2, wherein
Wherein the impurity of the impurity region is Si, an impurity concentration Ru der 1 × 10 ¹⁹ cm ^-3 or more, the semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the base electrode layer has a thickness of 15 nm or more. (A) An Al _x Ga _1-x N (0 ≦ x ≦ 1) layer or an Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) layer Forming an impurity region by implanting impurities into the nitride semiconductor layer;
(B) a step of sequentially laminating a base electrode layer and a main electrode layer on the impurity region to form an electrode in ohmic contact with the nitride semiconductor layer;
The step (b)
(B-1) forming the base electrode layer containing, as a main component, any one of Ti, Ta, and Ni as a metal having higher reactivity with nitrogen than the main electrode layer on the impurity region;
(B-2) On the base electrode layer, using the alloy composed of Nb having a work function closer to the nitride semiconductor layer than the base electrode layer and Pt having a lower ionization tendency than hydrogen, Forming an electrode layer,
After (c) said step (b), further Ru comprising the step of promoting the diffusion of Nb into the underlying electrode layer from the main electrode layer, a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
In the step (c),
A method of manufacturing a semiconductor device, wherein an RTA (Rapid Thermal Annealing) process for promoting the diffusion is performed on the electrode at a temperature of 650 ° C. to 1000 ° C. in a nitrogen atmosphere . A method of manufacturing a semiconductor device according to claim 5 ,
In the step (a),
A region having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more is formed as the impurity region by implanting Si ions into the nitride semiconductor layer at an implantation concentration of 1 × 10 ¹⁵ cm ⁻² or more.
In the step (c),
A method of manufacturing a semiconductor device, wherein an RTA (Rapid Thermal Annealing) process for promoting the diffusion is performed on the electrode at a temperature of 650 ° C. to 1000 ° C. in a nitrogen atmosphere. A method of manufacturing a semiconductor device according to any one of claims 5 to 7,
The step (b)
A method for manufacturing a semiconductor device, comprising: forming a protective electrode layer on the main electrode layer using Pt having a smaller ionization tendency than hydrogen. A method of manufacturing a semiconductor device according to any one of claims 5 to 8,
In the step (b),
A method for manufacturing a semiconductor device, comprising forming the base electrode layer having a thickness of 15 nm or more.

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