[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP5842109B2 - Resin-sealed semiconductor device and manufacturing method thereof - Google Patents

Resin-sealed semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5842109B2
JP5842109B2 JP2013525060A JP2013525060A JP5842109B2 JP 5842109 B2 JP5842109 B2 JP 5842109B2 JP 2013525060 A JP2013525060 A JP 2013525060A JP 2013525060 A JP2013525060 A JP 2013525060A JP 5842109 B2 JP5842109 B2 JP 5842109B2
Authority
JP
Japan
Prior art keywords
control element
power element
exterior body
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013525060A
Other languages
Japanese (ja)
Other versions
JPWO2013124940A1 (en
Inventor
南尾　匡紀
匡紀 南尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Priority to JP2013525060A priority Critical patent/JP5842109B2/en
Publication of JPWO2013124940A1 publication Critical patent/JPWO2013124940A1/en
Application granted granted Critical
Publication of JP5842109B2 publication Critical patent/JP5842109B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、樹脂封止型半導体装置及びその製造方法に関する。   The present invention relates to a resin-encapsulated semiconductor device and a method for manufacturing the same.

近年、インバータ制御機器等に搭載されるパワー半導体素子は、高密度化及び高速化が求められている。その結果、パワー半導体素子では、高温動作を可能にする窒化ガリウム（ＧａＮ）又は炭化珪素（ＳｉＣ）等の新材料が実用化されている。新材料を用いたパワー半導体素子では、半導体素子を実装するパッケージの放熱構造が重要である。   In recent years, power semiconductor elements mounted on inverter control devices and the like are required to have higher density and higher speed. As a result, new materials such as gallium nitride (GaN) or silicon carbide (SiC) that enable high-temperature operation have been put to practical use in power semiconductor elements. In a power semiconductor element using a new material, a heat dissipation structure of a package for mounting the semiconductor element is important.

パッケージの放熱構造として、半導体素子を金属製カバーで覆い、金属製カバーの内部に絶縁性の冷媒を封入する放熱構造を備えた密閉型パッケージが提案されている（例えば、特許文献１を参照。）。   As a package heat dissipation structure, a hermetic package including a heat dissipation structure in which a semiconductor element is covered with a metal cover and an insulating refrigerant is sealed inside the metal cover has been proposed (for example, see Patent Document 1). ).

また、図９に示すように、金属製カバーと冷媒との間に空隙を設け、多孔質部材に吸着させた冷媒の気化熱を利用して半導体素子を冷却する放熱構造を備えた密閉型パッケージも提案されている（例えば、特許文献２を参照。）。   Further, as shown in FIG. 9, a sealed package having a heat dissipation structure in which a gap is provided between the metal cover and the refrigerant and the semiconductor element is cooled by using the heat of vaporization of the refrigerant adsorbed on the porous member. Has also been proposed (see, for example, Patent Document 2).

以下、特許文献２に示された密閉型パッケージの放熱構造について説明する。   Hereinafter, the heat dissipation structure of the hermetic package disclosed in Patent Document 2 will be described.

図９は、特許文献２に示された従来の密閉型パッケージの断面構成を示している。   FIG. 9 shows a cross-sectional configuration of a conventional hermetic package disclosed in Patent Document 2.

図９に示すように、密閉型パッケージは、半導体素子１０１を実装した基板１０２と、基板１０２の実装面を覆うと共に実装面を密閉する金属製カバー１０３と、柔軟性を有するシート１０４と、冷媒を吸着した多孔質部材１０５とから構成されている。半導体素子１０１は、シート１０４を介して多孔質部材１０５と接している。このため、半導体素子１０１の温度が上がると、多孔質部材１０５に吸着されている冷媒が気化する。その結果、冷媒の気化熱により半導体素子１０１が冷却される。なお、気化した冷媒の蒸気は、金属製カバー１０３の内壁面で水滴状に凝結して液化し、液化した冷媒は、多孔質部材１０５に吸着される。   As shown in FIG. 9, the sealed package includes a substrate 102 on which the semiconductor element 101 is mounted, a metal cover 103 that covers the mounting surface of the substrate 102 and seals the mounting surface, a flexible sheet 104, and a coolant It is comprised from the porous member 105 which adsorb | sucked. The semiconductor element 101 is in contact with the porous member 105 through the sheet 104. For this reason, when the temperature of the semiconductor element 101 rises, the refrigerant adsorbed on the porous member 105 is vaporized. As a result, the semiconductor element 101 is cooled by the heat of vaporization of the refrigerant. The vaporized refrigerant vapor condenses and liquefies on the inner wall surface of the metal cover 103, and the liquefied refrigerant is adsorbed by the porous member 105.

特開２００８−００４６８８号公報JP 2008-004688 A 特開平０７−０６６５７５号公報Japanese Patent Laid-Open No. 07-066655

しかしながら、従来の密閉型パッケージでは、半導体素子を覆う金属製カバーと基板との接合部に、気化した冷媒の蒸気圧による応力が掛かる。   However, in the conventional hermetic package, stress due to the vapor pressure of the vaporized refrigerant is applied to the joint between the metal cover that covers the semiconductor element and the substrate.

さらに、従来の密閉型パッケージは、金属製カバーを接合する前に、多孔質部材を金属製カバーの内部に配置する必要があるため、その製造工程が複雑である。   Further, since the conventional sealed package needs to arrange the porous member inside the metal cover before joining the metal cover, the manufacturing process is complicated.

以上のように、従来の密閉型パッケージは、冷媒の蒸気圧により金属製カバーと基板との接合部に応力が掛かることから、半導体素子の長期信頼性を確保することが困難であるという課題がある。   As described above, the conventional hermetic package has a problem that it is difficult to ensure the long-term reliability of the semiconductor element because the joint portion between the metal cover and the substrate is stressed by the vapor pressure of the refrigerant. is there.

上記の課題を解決するために、本発明に係る樹脂封止型半導体装置は、外装体と、外装体の内部に封止されると共に、外装体から端部が突出したリードフレームと、外装体の内部に封止されると共に、リードフレームに実装されたパワー素子と、外装体の内部に封止されると共に、リードフレームに実装された制御素子とを備え、外装体におけるパワー素子と制御素子との間の領域は、パワー素子と制御素子との間を断熱するために他の領域と比べてフィラーの含有割合が高く、外装体におけるパワー素子と制御素子との間を除く領域は、外装体を介してパワー素子からの熱を放熱するためにパワー素子と制御素子との間の領域と比べてフィラーの含有割合が低く、フィラーは、パワー素子と制御素子とを接続する第１金属部材を完全に覆うように配置されたことを特徴とする。 In order to solve the above problems, a resin-encapsulated semiconductor device according to the present invention includes an exterior body, a lead frame that is sealed inside the exterior body, and has an end protruding from the exterior body, and the exterior body A power element mounted in the lead frame and a control element sealed in the exterior body and mounted in the lead frame, the power element and the control element in the exterior body The region between and the power element and the control element insulate the space between the power element and the control element in order to insulate the filler, and the area excluding the space between the power element and the control element in the exterior body is the exterior. content of the filler in comparison with the region between the power element and the control element in order to radiate heat from the power device via the body rather low, filler, first metal connecting the power device and the control device Fully cover the part Characterized in that the sea urchin arranged.

また、上記の課題を解決するために、本発明に係る樹脂封止型半導体装置の製造方法は、パワー素子及び制御素子が実装されたリードフレームを金型の内部に配置し、パワー素子と制御素子との間の領域にフィラーを含有する第１封止樹脂を注入した後、パワー素子、制御素子及びリードフレームを第２封止樹脂で封止することで、パワー素子と制御素子との間の領域が、パワー素子と制御素子との間を断熱するために他の領域と比べてフィラーの含有割合が高く、パワー素子と制御素子との間を除く領域が、外装体を介してパワー素子からの熱を放熱するためにパワー素子と制御素子との間の領域と比べてフィラーの含有割合が低い外装体を形成することを特徴とする。 In addition, in order to solve the above-described problems, a method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes arranging a lead frame on which a power element and a control element are mounted inside a mold, and controlling the power element and the control element. After injecting the first sealing resin containing the filler into the region between the elements, the power element, the control element, and the lead frame are sealed with the second sealing resin, so that the gap between the power element and the control element is reached. In order to insulate between the power element and the control element, the content ratio of the filler is higher than that of the other areas, and the area excluding the space between the power element and the control element is the power element through the exterior body. In order to dissipate the heat from the outer surface, an exterior body having a lower filler content than the region between the power element and the control element is formed.

本発明によれば、半導体素子の長期信頼性を確保することができる。   According to the present invention, long-term reliability of a semiconductor element can be ensured.

図１は本発明の一実施形態に係る半導体装置を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. 図２は本発明の一実施形態に係る半導体装置の内部構造を示す部分的な拡大断面図である。FIG. 2 is a partial enlarged cross-sectional view showing the internal structure of the semiconductor device according to the embodiment of the present invention. 図３は本発明の一実施形態に係る半導体装置の内部構造を示す平面図である。FIG. 3 is a plan view showing the internal structure of the semiconductor device according to the embodiment of the present invention. 図４は本発明の一実施形態に係る半導体装置に用いる多孔質フィラーを示す拡大平面図である。FIG. 4 is an enlarged plan view showing a porous filler used in a semiconductor device according to an embodiment of the present invention. 図５は本発明の一実施形態に係る半導体装置の製造方法を示す一工程の断面図である。FIG. 5 is a cross-sectional view of a process showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図６は本発明の一実施形態に係る半導体装置の製造方法を示す一工程の平面図である。FIG. 6 is a plan view of one process showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 図７は本発明の一実施形態に係る半導体装置の製造方法を示す次工程の断面図である。FIG. 7 is a cross-sectional view of the next step showing the method for manufacturing a semiconductor device according to one embodiment of the present invention. 図８は本発明の一実施形態に係る半導体装置の製造方法を示す次工程の平面図である。FIG. 8 is a plan view of the next step showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図９は従来の密閉型パッケージを示す断面図である。FIG. 9 is a cross-sectional view showing a conventional sealed package.

本発明の一実施形態について図面を参照しながら説明する。   An embodiment of the present invention will be described with reference to the drawings.

なお、本発明は、本明細書に記載された基本的な特徴に基づく限り、以下に記載の内容に限定されない。   The present invention is not limited to the contents described below as long as it is based on the basic characteristics described in this specification.

（一実施形態）
図１は、一実施形態に係る半導体装置の断面構成を示している。図２は、図１の領域Ａを拡大した断面構成を示している。本実施形態に係る半導体装置は、樹脂封止型半導体装置である。本実施形態に係る半導体装置は、太陽光発電システム、又は家電用若しくは電気自動車（ＥＶ）用モータ等の組み込み対象装置に組み込んで使用される。(One embodiment)
FIG. 1 shows a cross-sectional configuration of a semiconductor device according to an embodiment. FIG. 2 shows an enlarged cross-sectional configuration of region A in FIG. The semiconductor device according to this embodiment is a resin-encapsulated semiconductor device. The semiconductor device according to the present embodiment is used by being incorporated in a photovoltaic power generation system or a device to be incorporated such as a motor for home appliances or an electric vehicle (EV).

図１及び図２に示すように、本実施形態に係る半導体装置１０は、少なくとも、リードフレーム１１と、パワー素子１２と、放熱板３０と、制御素子１４と、外装体１５とを備えている。リードフレーム１１は、パワー素子１２を搭載する第１ダイパッド部１６と、制御素子１４を搭載する第２ダイパッド部４０と、複数のリードとを有する。   As shown in FIGS. 1 and 2, the semiconductor device 10 according to the present embodiment includes at least a lead frame 11, a power element 12, a heat radiating plate 30, a control element 14, and an exterior body 15. . The lead frame 11 includes a first die pad portion 16 on which the power element 12 is mounted, a second die pad portion 40 on which the control element 14 is mounted, and a plurality of leads.

リードフレーム１１は、例えば銅（Ｃｕ）等の熱伝導性が高い材料から形成されている。リードフレーム１１の一部は外装体１５に封止され、リードフレーム１１の複数のリードの端部は、外装体１５の側面から外装体１５の外側に向けて突出している。リードフレーム１１における第１ダイパッド部１６の上面１６ａには、パワー素子１２が実装されている。パワー素子１２は、例えばろう材２６により、上面１６ａに実装されている。また、リードフレーム１１における第２ダイパッド部４０の上面４０ａには、制御素子１４が実装されている。制御素子１４は、例えば銀（Ａｇ）ペーストにより、上面４０ａに実装されている。   The lead frame 11 is formed of a material having high thermal conductivity such as copper (Cu). A part of the lead frame 11 is sealed by the exterior body 15, and the ends of the leads of the lead frame 11 protrude from the side surface of the exterior body 15 toward the outside of the exterior body 15. A power element 12 is mounted on the upper surface 16 a of the first die pad portion 16 in the lead frame 11. The power element 12 is mounted on the upper surface 16a by a brazing material 26, for example. A control element 14 is mounted on the upper surface 40 a of the second die pad portion 40 in the lead frame 11. The control element 14 is mounted on the upper surface 40a by, for example, silver (Ag) paste.

パワー素子１２は、例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）、又はパワーＭＯＳＦＥＴ（金属酸化膜型電界効果トランジスタ）である。パワー素子１２のボンディングパッド（図示せず）とリードフレーム１１の複数のリードとは、金属部材１３により電気的に接続されている。   The power element 12 is, for example, an IGBT (insulated gate bipolar transistor) or a power MOSFET (metal oxide field effect transistor). A bonding pad (not shown) of the power element 12 and a plurality of leads of the lead frame 11 are electrically connected by a metal member 13.

制御素子１４は、パワー素子１２を制御する素子であり、駆動回路又は過電流防止回路等を内蔵している。制御素子１４のボンディングパッド（図示せず）とリードフレーム１１の複数のリードとは、金属部材１３により電気的に接続されている。パワー素子１２のボンディングパッド（図示せず）と制御素子１４のボンディングパッド（図示せず）とは、金属部材１３により電気的に接続されている。制御素子１４は、これらの金属部材１３を介して、パワー素子１２を制御している。   The control element 14 is an element that controls the power element 12 and incorporates a drive circuit or an overcurrent prevention circuit. A bonding pad (not shown) of the control element 14 and a plurality of leads of the lead frame 11 are electrically connected by a metal member 13. A bonding pad (not shown) of the power element 12 and a bonding pad (not shown) of the control element 14 are electrically connected by a metal member 13. The control element 14 controls the power element 12 through these metal members 13.

以下の説明では、パワー素子１２として、ダイオード５０が接続された縦型パワーＭＯＳＦＥＴを例にしている。ダイオード５０とパワー素子１２のボンディングパッド（図示せず）とは、金属部材１３により電気的に接続されている。また、金属部材１３として、例えばアルミニウム（Ａｌ）ワイヤ又は金（Ａｕ）ワイヤを例にして説明する。なお、金属部材１３として、アルミニウムワイヤ又は金ワイヤの代わりに、アルミニウム（Ａｌ）リボン又は銅（Ｃｕ）クリップを用いてもよい。アルミニウムリボン又は銅クリップは、アルミニウムワイヤ又は金ワイヤと比べて断面積が大きく、配線抵抗値が小さくなるため、半導体装置１０における電力損失を低減することができる。   In the following description, as the power element 12, a vertical power MOSFET to which a diode 50 is connected is taken as an example. The diode 50 and the bonding pad (not shown) of the power element 12 are electrically connected by the metal member 13. Further, as the metal member 13, for example, an aluminum (Al) wire or a gold (Au) wire will be described as an example. As the metal member 13, an aluminum (Al) ribbon or a copper (Cu) clip may be used instead of an aluminum wire or a gold wire. Since an aluminum ribbon or a copper clip has a larger cross-sectional area and a lower wiring resistance value than an aluminum wire or a gold wire, power loss in the semiconductor device 10 can be reduced.

放熱板３０は、例えば、銅（Ｃｕ）又はアルミニウム（Ａｌ）等の熱伝導性が高い金属から形成されている。リードフレーム１１における第１ダイパッド部１６の下面１６ｂには、絶縁性シート４１を介して、放熱板３０が固着されている。絶縁性シート４１は、絶縁層を接着層で挟む３層構造を有する熱伝導性の絶縁材料で形成されている。絶縁性シート４１は、パワー素子１２から発生する熱を効果的に放熱板３０へ伝達する。放熱板３０は、該放熱板３０の下面３０ｂが外装体１５の下面１５ｂから露出するように、外装体１５により封止されている。このため、パワー素子１２から生じる熱は、絶縁性シート４１を介して、露出した放熱板３０の下面３０ｂから外部に、効率良く伝達される。また、半導体装置１０において、放熱板３０の側面３０ｃは外装体１５で覆われているため、放熱板３０とリードフレーム１１とは一体化されている。   The heat radiating plate 30 is made of a metal having high thermal conductivity such as copper (Cu) or aluminum (Al). A heat radiating plate 30 is fixed to the lower surface 16 b of the first die pad portion 16 in the lead frame 11 via an insulating sheet 41. The insulating sheet 41 is formed of a heat conductive insulating material having a three-layer structure in which an insulating layer is sandwiched between adhesive layers. The insulating sheet 41 effectively transmits heat generated from the power element 12 to the heat radiating plate 30. The heat radiating plate 30 is sealed by the outer package 15 so that the lower surface 30 b of the heat radiating plate 30 is exposed from the lower surface 15 b of the outer package 15. For this reason, the heat generated from the power element 12 is efficiently transmitted from the exposed lower surface 30 b of the heat sink 30 to the outside via the insulating sheet 41. Further, in the semiconductor device 10, since the side surface 30 c of the heat sink 30 is covered with the exterior body 15, the heat sink 30 and the lead frame 11 are integrated.

外装体１５は、その一部に多孔質フィラー３５を含有する封止樹脂であって、例えばエポキシ等の熱硬化性樹脂からなる封止樹脂で構成される。外装体１５の一部である多孔質フィラー３５を含有する領域については、図３を用いて後述する。本実施形態では、外装体１５を構成する封止樹脂において、多孔質フィラー３５を含有する領域を「断熱用封止樹脂領域」とし、その他の領域を「通常封止樹脂領域」としている。外装体１５は、パワー素子１２、制御素子１４、第２ダイパッド部４０を含むリードフレーム１１の一部、並びに放熱板３０の側面３０ｃを内包して封止している。このように封止することにより、リードフレーム１１と放熱板３０とを一体化すると共に、パワー素子１２と制御素子１４とを保護することが可能となる。   The exterior body 15 is a sealing resin containing a porous filler 35 in a part thereof, and is composed of a sealing resin made of a thermosetting resin such as epoxy. The area | region containing the porous filler 35 which is a part of the exterior body 15 is later mentioned using FIG. In the present embodiment, in the sealing resin constituting the outer package 15, the region containing the porous filler 35 is referred to as “insulating sealing resin region”, and the other regions are referred to as “normal sealing resin regions”. The exterior body 15 encloses and seals a part of the lead frame 11 including the power element 12, the control element 14, the second die pad portion 40, and the side surface 30 c of the heat sink 30. By sealing in this way, the lead frame 11 and the heat dissipation plate 30 can be integrated, and the power element 12 and the control element 14 can be protected.

図３は、本実施形態に係る半導体装置１０の内部構造であって、その平面構成を示している。   FIG. 3 shows the internal structure of the semiconductor device 10 according to the present embodiment, and shows its planar configuration.

図３に示すように、リードフレーム１１の端部は、それぞれ外装体１５の側面から突出している。リードフレーム１１の端部は、半導体装置１０の実装端子として、例えばインバータ制御機器等の回路と接続される。   As shown in FIG. 3, the end portions of the lead frame 11 protrude from the side surfaces of the exterior body 15, respectively. The end portion of the lead frame 11 is connected to a circuit such as an inverter control device as a mounting terminal of the semiconductor device 10.

ここで、本実施形態に係る半導体装置１０は、図２及び図３に示すように、外装体１５を構成する封止樹脂の内部において、パワー素子１２と制御素子１４との間の領域に、他の領域と比べて多孔質フィラー３５を密に配置して、断熱用封止樹脂領域（多孔質フィラー３５を密に含む領域）を形成していることを特徴とする。パワー素子１２と制御素子１４との間に断熱用封止樹脂領域を形成している（多孔質フィラー３５を密に配置している）のは、パワー素子１２から発生する熱が、一般的に熱に弱い制御素子１４に伝達されることを、防ぐためである。本実施形態では、具体的には、断熱用封止樹脂領域において、多孔質フィラー３５を、７０重量％以上（さらに望ましくは９０重量％以上）の割合で含有させている。   Here, as shown in FIGS. 2 and 3, the semiconductor device 10 according to the present embodiment is provided in a region between the power element 12 and the control element 14 in the sealing resin constituting the exterior body 15. It is characterized in that the porous fillers 35 are densely arranged compared to other regions to form a heat-insulating sealing resin region (a region containing the porous filler 35 densely). The reason why the sealing resin region for heat insulation is formed between the power element 12 and the control element 14 (the porous filler 35 is densely arranged) is that heat generated from the power element 12 is generally This is to prevent transmission to the heat-sensitive control element 14. In the present embodiment, specifically, the porous filler 35 is contained in a proportion of 70% by weight or more (more desirably 90% by weight or more) in the sealing resin region for heat insulation.

さらに、本実施形態に係る半導体装置１０では、多孔質フィラー３５を、制御素子１４側よりもパワー素子１２側に偏在して配置している。多孔質フィラー３５が制御素子１４側よりもパワー素子１２側に偏在して配置されることで、パワー素子１２から発生する熱が制御素子１４に伝達されることを、さらに確実に防ぐことができる。   Furthermore, in the semiconductor device 10 according to the present embodiment, the porous filler 35 is arranged unevenly on the power element 12 side rather than on the control element 14 side. By arranging the porous filler 35 so as to be unevenly distributed on the power element 12 side rather than the control element 14 side, it is possible to more reliably prevent the heat generated from the power element 12 from being transmitted to the control element 14. .

また、外装体１５を構成する封止樹脂の内部において、多孔質フィラー３５は、パワー素子１２と制御素子１４とを接続する金属部材１３を囲むように、その周囲に配置されている。パワー素子１２と制御素子１４とを接続する金属部材１３は、第１金属部材の一例である。ここで、断熱用封止樹脂領域（多孔質フィラー３５を密に含む領域）と通常封止樹脂領域（その他の領域）との界面に金属部材１３が位置していると、界面にかかるせん断応力により金属部材１３が破断する可能性がある。そこで、本実施形態では、図２に示すように、パワー素子１２と制御素子１４とを接続する金属部材１３を多孔質フィラー３５が完全に覆うように配置している。すなわち、パワー素子１２と制御素子１４とを接続する金属部材１３の全てが、断熱用封止樹脂領域内に位置するように配置している。このように多孔質フィラー３５を配置することにより、金属部材１３が破断する可能性を低減することができる。   In addition, inside the sealing resin constituting the exterior body 15, the porous filler 35 is disposed around the metal member 13 that connects the power element 12 and the control element 14. The metal member 13 that connects the power element 12 and the control element 14 is an example of a first metal member. Here, if the metal member 13 is located at the interface between the heat-insulating sealing resin region (region containing the porous filler 35 densely) and the normal sealing resin region (other regions), the shear stress applied to the interface As a result, the metal member 13 may be broken. Therefore, in the present embodiment, as shown in FIG. 2, the metal member 13 that connects the power element 12 and the control element 14 is disposed so that the porous filler 35 completely covers the metal member 13. That is, all the metal members 13 that connect the power element 12 and the control element 14 are disposed so as to be located in the sealing resin region for heat insulation. Thus, by arrange | positioning the porous filler 35, possibility that the metal member 13 will fracture | rupture can be reduced.

本実施形態に係る半導体装置１０において、パワー素子１２から発生する熱が制御素子１４に伝達されるのを防ぐことができる理由について、以下に説明する。   The reason why heat generated from the power element 12 can be prevented from being transmitted to the control element 14 in the semiconductor device 10 according to the present embodiment will be described below.

一般的に、パワー素子は、高速又は大電流でのスイッチング動作により発熱する。このとき、例えばパワー素子のジャンクション温度が上昇して１２５℃以上になると、動作に対する信頼性が著しく低下し、パワー素子が誤動作する可能性がある。そこで、パワー素子の構成材料として、ＧａＮ又はＳｉＣ等の高耐熱素子が適用され始めている。しかし、パワー素子自体が高熱に耐えられても、制御素子は、シリコン（Ｓｉ）により形成されるため、その耐熱性が低い。例えば、パワー素子からの熱伝導により制御素子の温度が上昇して１２５℃以上になると、該制御素子の動作に対する信頼性が著しく低下して、制御素子が誤動作する場合がある。制御素子が誤動作すると、正常な信号がパワー素子に伝達されず、半導体装置全体の特性及び信頼性が著しく低下する。本実施形態に係る半導体装置１０は、この課題を解決し、パワー素子１２と制御素子１４との間の領域に多孔質フィラー３５を、他の領域よりも密に配置して、断熱用封止樹脂領域を形成することにより、長期信頼性が高い半導体装置１０を実現することを可能としている。   Generally, a power element generates heat by a switching operation at a high speed or a large current. At this time, for example, when the junction temperature of the power element rises to 125 ° C. or higher, the reliability of the operation is remarkably lowered, and the power element may malfunction. Therefore, a high heat resistance element such as GaN or SiC has begun to be applied as a constituent material of the power element. However, even if the power element itself can withstand high heat, since the control element is formed of silicon (Si), its heat resistance is low. For example, when the temperature of the control element rises to 125 ° C. or higher due to heat conduction from the power element, the reliability of the operation of the control element is significantly reduced, and the control element may malfunction. If the control element malfunctions, a normal signal is not transmitted to the power element, and the characteristics and reliability of the entire semiconductor device are significantly reduced. The semiconductor device 10 according to the present embodiment solves this problem, and arranges the porous filler 35 in a region between the power element 12 and the control element 14 more densely than other regions, thereby sealing for heat insulation. By forming the resin region, it is possible to realize the semiconductor device 10 with high long-term reliability.

ここで、断熱用封止樹脂領域（パワー素子１２と制御素子１４との間の領域）に密に配置した多孔質フィラー３５の作用について説明する。   Here, the effect | action of the porous filler 35 arrange | positioned densely in the sealing resin area | region for insulation (area | region between the power element 12 and the control element 14) is demonstrated.

図４に、本実施形態に係る半導体装置１０に用いる多孔質フィラー３５を拡大して示す。多孔質フィラー３５は、図４に示すように、多孔質フィラー部位３５ａの内部に、空気層である複数の孔部位３５ｂを含む。   FIG. 4 shows an enlarged view of the porous filler 35 used in the semiconductor device 10 according to this embodiment. As shown in FIG. 4, the porous filler 35 includes a plurality of hole portions 35b that are air layers inside the porous filler portion 35a.

多孔質フィラー３５の材料としては、例えば二酸化珪素（シリカ：ＳｉＯ２）、酸化マグネシウム（ＭｇＯ）、酸化アルミニウム（アルミナ：Ａｌ２Ｏ３）又は窒化ボロン（ＢＮ）がある。また、多孔質フィラー３５は、比表面積が３００ｍ２／ｇ以上で、平均粒径が約１μｍ以上且つ１０μｍ以下の、例えば球状のフィラーが望ましい。多孔質フィラー３５が球状であると、多孔質フィラー３５と外装体１５の封止樹脂とが面接触でなく点接触するため、多孔質フィラー３５と外装体１５の封止樹脂との接触面積を可能な限り大きくすることができる。多孔質フィラー３５と外装体１５の封止樹脂との接触面積を大きくすることで、封止樹脂の充填密度を向上させると共に、封止樹脂への多孔質フィラー３５の密着性を向上させることができる。Examples of the material of the porous filler 35 include silicon dioxide (silica: SiO 2 ), magnesium oxide (MgO), aluminum oxide (alumina: Al 2 O 3 ), and boron nitride (BN). The porous filler 35 is preferably a spherical filler having a specific surface area of 300 m 2 / g or more and an average particle size of about 1 μm or more and 10 μm or less. When the porous filler 35 is spherical, the porous filler 35 and the sealing resin of the outer package 15 are in point contact instead of surface contact, and therefore the contact area between the porous filler 35 and the sealing resin of the outer package 15 is increased. It can be as large as possible. By increasing the contact area between the porous filler 35 and the sealing resin of the exterior body 15, the filling density of the sealing resin can be improved and the adhesion of the porous filler 35 to the sealing resin can be improved. it can.

本実施形態では、平均粒径が２．８μｍで且つ比表面積が３８０ｍ２／ｇである球状の多孔質フィラー３５を約９０重量％含有したビフェニル系エポキシ樹脂を準備し、準備したビフェニル系エポキシ樹脂を断熱用封止樹脂として用い、パワー素子１２と制御素子１４との間の領域をこの断熱用封止樹脂で封止して、半導体装置１０を製造した。本実施形態の場合の多孔質フィラー３５内の空気層である孔部位３５ｂは、熱伝導率が０.０２４１Ｗ／ｍ・Ｋであり、エポキシ樹脂の熱伝導率における０．２〜０．４Ｗ／ｍ・Ｋの値の５分の１から１０分の１程度である。In this embodiment, a biphenyl epoxy resin containing about 90% by weight of a spherical porous filler 35 having an average particle diameter of 2.8 μm and a specific surface area of 380 m 2 / g is prepared, and the prepared biphenyl epoxy resin is prepared. Was used as a sealing resin for heat insulation, and the region between the power element 12 and the control element 14 was sealed with this sealing resin for heat insulation, and the semiconductor device 10 was manufactured. The hole part 35b which is an air layer in the porous filler 35 in the present embodiment has a thermal conductivity of 0.0241 W / m · K, and is 0.2 to 0.4 W / in the thermal conductivity of the epoxy resin. It is about 1/5 to 1/10 of the value of m · K.

パワー素子１２の発熱によりパワー素子１２の温度が上昇した場合、その発熱は、第１ダイパッド部１６と絶縁性シート４１を介して放熱板３０に伝達されると共に、パワー素子１２を覆っている外装体１５へと伝達される。このとき、本実施形態に係る半導体装置１０では、断熱用封止樹脂領域で熱の伝達が遮断され（断熱され）、制御素子１４への熱影響が低減される。これは、多孔質フィラー３５に含まれる空気層である孔部位３５ｂが、外装体１５を形成するエポキシ樹脂よりも熱伝導率が低いためであると考えられる。具体的には、本実施形態に係る半導体装置１０では、パワー素子１２が発熱して２００℃近くまで温度上昇した際にも、制御素子１４の温度を１２５℃未満に抑えることができた。   When the temperature of the power element 12 rises due to the heat generation of the power element 12, the heat generation is transmitted to the heat radiating plate 30 through the first die pad portion 16 and the insulating sheet 41 and the exterior covering the power element 12. It is transmitted to the body 15. At this time, in the semiconductor device 10 according to this embodiment, heat transfer is blocked (insulated) in the sealing resin region for heat insulation, and the thermal influence on the control element 14 is reduced. This is presumably because the hole portion 35 b that is an air layer contained in the porous filler 35 has a lower thermal conductivity than the epoxy resin that forms the outer package 15. Specifically, in the semiconductor device 10 according to the present embodiment, the temperature of the control element 14 can be suppressed to less than 125 ° C. even when the power element 12 generates heat and the temperature rises to near 200 ° C.

本実施形態に係る半導体装置１０によれば、パワー素子１２と制御素子１４との間の領域に密に配置した多孔質フィラー３５により、制御素子１４の発熱温度を１２５℃未満に保つことができる。これにより、密閉パッケージ構造を必要とせず、小型で生産性に優れ、パワー素子１２及び制御素子１４の長期動作信頼性が高い半導体装置を実現することができる。   According to the semiconductor device 10 according to the present embodiment, the heat generation temperature of the control element 14 can be kept below 125 ° C. by the porous filler 35 densely arranged in the region between the power element 12 and the control element 14. . As a result, it is possible to realize a semiconductor device that does not require a hermetically sealed package structure, is small and excellent in productivity, and has high long-term operation reliability of the power element 12 and the control element 14.

以下、本発明の一実施形態に係る半導体装置の製造方法について、図５〜図８を用いて説明する。   Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

まず、図５に示すように、上面に絶縁性シート４１を仮接着した放熱板３０を下にして、下金型６２に載置する。続いて、リードフレーム１１における第１ダイパッド部１６の下面１６ｂが絶縁性シート４１と接するように、下金型６２にリードフレーム１１を載置する。その後、上金型６３を下降させ、リードフレーム１１を、上金型６３と下金型６２とによってクランプする。これにより、上金型６３と下金型６２との間に、キャビティ６５が形成される。続いて、例えばトランスファモールド法により、多孔質フィラー３５を含有したエポキシ樹脂７５を、上金型６３に設けられた少なくとも１つのゲート７０から、キャビティ６５の内部に充填する。エポキシ樹脂７５は、断熱用封止樹脂領域を形成するための封止樹脂であり、第１封止樹脂の一例である。ゲート７０は、キャビティ６５の内部に配置されたパワー素子１２と制御素子１４との間の空間の鉛直上方に、形成されている。これにより、パワー素子１２と制御素子１４との間に、多孔質フィラー３５を含有したエポキシ樹脂７５が充填される。   First, as shown in FIG. 5, the radiator plate 30 with the insulating sheet 41 temporarily bonded to the upper surface is placed on the lower mold 62 with the heat sink 30 facing down. Subsequently, the lead frame 11 is placed on the lower mold 62 so that the lower surface 16 b of the first die pad portion 16 in the lead frame 11 is in contact with the insulating sheet 41. Thereafter, the upper mold 63 is lowered, and the lead frame 11 is clamped by the upper mold 63 and the lower mold 62. Thereby, a cavity 65 is formed between the upper mold 63 and the lower mold 62. Subsequently, an epoxy resin 75 containing the porous filler 35 is filled into the cavity 65 from at least one gate 70 provided in the upper mold 63 by, for example, a transfer mold method. The epoxy resin 75 is a sealing resin for forming a heat insulating sealing resin region, and is an example of a first sealing resin. The gate 70 is formed vertically above the space between the power element 12 and the control element 14 disposed inside the cavity 65. Thereby, the epoxy resin 75 containing the porous filler 35 is filled between the power element 12 and the control element 14.

このとき、上金型６３に設けられたゲート７０の位置は、図５及び図６に示すように、パワー素子１２と制御素子１４との中間位置よりも、パワー素子１２に近い側に配置されることが好ましい。ゲート７０の位置をパワー素子１２に近い側に配置することにより、多孔質フィラー３５を含有する割合が、制御素子１４側よりもパワー素子１２側が高くなる。すなわち、本実施形態に係る半導体装置１０では、多孔質フィラー３５が、制御素子１４側よりもパワー素子１２側に偏在して配置される。なお、ゲート７０を複数個配置することにより、多孔質フィラー３５を含有したエポキシ樹脂７５を、より確実に充填することができる。   At this time, the position of the gate 70 provided in the upper mold 63 is arranged closer to the power element 12 than the intermediate position between the power element 12 and the control element 14 as shown in FIGS. It is preferable. By disposing the position of the gate 70 on the side close to the power element 12, the ratio containing the porous filler 35 is higher on the power element 12 side than on the control element 14 side. That is, in the semiconductor device 10 according to the present embodiment, the porous filler 35 is arranged unevenly on the power element 12 side rather than on the control element 14 side. In addition, by arranging a plurality of gates 70, the epoxy resin 75 containing the porous filler 35 can be more reliably filled.

続いて、図７及び図８に示すように、上金型６３の側面に設けたゲート６４からエポキシ樹脂６６を注入し、該エポキシ樹脂６６をキャビティ６５の内部に充填する。エポキシ樹脂６６は、通常封止樹脂領域を形成するための封止樹脂であり、第２封止樹脂の一例である。本実施形態では、エポキシ樹脂６６として流動性が高い組成の樹脂を用いているため、エポキシ樹脂６６は、上金型６３のキャビティ６５を完全に充填するように入り込んでいく。本実施形態では、ゲート７０から注入されたエポキシ樹脂７５よりも、ゲート６４から注入されたエポキシ樹脂６６の方が、流動性が高い。このため、図７に示すように、ゲート６４から注入されたエポキシ樹脂６６は、既にゲート７０から充填されたエポキシ樹脂７５を除く領域を埋めるように充填される。すなわち、断熱用封止樹脂領域に予め充填されたエポキシ樹脂７５はそのままで、残りの領域（通常封止樹脂領域）にエポキシ樹脂６６が充填される。その結果、パワー素子１２と制御素子１４との間の領域（断熱用封止樹脂領域）にエポキシ樹脂７５が充填され、それ以外の領域（通常封止樹脂領域）にエポキシ樹脂６６が充填される。そして、これらエポキシ樹脂７５、６６を硬化させることで、図１に示す外装体１５を構成し、半導体装置１０を製造することができる。   Subsequently, as shown in FIGS. 7 and 8, an epoxy resin 66 is injected from a gate 64 provided on the side surface of the upper mold 63, and the epoxy resin 66 is filled into the cavity 65. The epoxy resin 66 is a sealing resin for forming a normal sealing resin region, and is an example of a second sealing resin. In the present embodiment, since the resin having a high fluidity is used as the epoxy resin 66, the epoxy resin 66 enters so as to completely fill the cavity 65 of the upper mold 63. In the present embodiment, the epoxy resin 66 injected from the gate 64 has higher fluidity than the epoxy resin 75 injected from the gate 70. For this reason, as shown in FIG. 7, the epoxy resin 66 injected from the gate 64 is filled so as to fill the region excluding the epoxy resin 75 already filled from the gate 70. That is, the epoxy resin 75 filled in the sealing resin region for heat insulation is left as it is, and the remaining region (normal sealing resin region) is filled with the epoxy resin 66. As a result, the region between the power element 12 and the control element 14 (insulation sealing resin region) is filled with the epoxy resin 75, and the other region (normal sealing resin region) is filled with the epoxy resin 66. . And the exterior body 15 shown in FIG. 1 is comprised by hardening these epoxy resins 75 and 66, and the semiconductor device 10 can be manufactured.

なお、本実施形態では、多孔質フィラー３５を含まないエポキシ樹脂６６の粘性は、０．０１Ｐａ・ｓ程度であり、多孔質フィラー３５を含むエポキシ樹脂７５の粘性は、２Ｐａ・ｓ程度である。   In this embodiment, the viscosity of the epoxy resin 66 not including the porous filler 35 is about 0.01 Pa · s, and the viscosity of the epoxy resin 75 including the porous filler 35 is about 2 Pa · s.

本実施形態では、外装体１５の内部におけるパワー素子１２と制御素子１４との配置の比率に基づいて、ゲート７０から注入したエポキシ樹脂７５とゲート６４から注入したエポキシ樹脂６６との体積比を、エポキシ樹脂７５：エポキシ樹脂６６＝１：３とした。なお、外装体１５からも放熱することを考えると、エポキシ樹脂７５の体積は、エポキシ樹脂６６の体積の３分の１以下であることが望ましい。   In the present embodiment, the volume ratio between the epoxy resin 75 injected from the gate 70 and the epoxy resin 66 injected from the gate 64 is based on the ratio of the arrangement of the power element 12 and the control element 14 inside the exterior body 15. Epoxy resin 75: Epoxy resin 66 = 1: 3. In consideration of heat dissipation from the exterior body 15, the volume of the epoxy resin 75 is preferably equal to or less than one third of the volume of the epoxy resin 66.

なお、まず、パワー素子１２と制御素子１４との間に充填したエポキシ樹脂７５を硬化させた後に、その周囲を囲むようにエポキシ樹脂６６を充填させて、外装体１５を形成してもよい。この場合、エポキシ樹脂７５による断熱用封止樹脂領域を、パワー素子１２と制御素子１４との間により確実に形成することができる。   First, after the epoxy resin 75 filled between the power element 12 and the control element 14 is cured, the exterior body 15 may be formed by filling the epoxy resin 66 so as to surround the periphery. In this case, the sealing resin region for heat insulation by the epoxy resin 75 can be more reliably formed between the power element 12 and the control element 14.

本実施形態に係る半導体装置１０は、外装体１５の内部において、多孔質フィラー３５をパワー素子１２と制御素子１４との近傍に密に配置すると共に、パワー素子１２側に偏在させている。これにより、パワー素子１２と制御素子１４との間の断熱効果を高めた半導体装置１０を実現することができる。本実施形態により、パワー素子１２と制御素子１４との間の断熱効果を高めると共に、パワー素子１２から放熱板３０への放熱特性は、従来通りの半導体装置１０を実現できる。そのため、パワー素子１２の温度が高くなっても、制御素子１４への熱の影響を小さくでき、動作が安定した半導体装置１０を実現することができる。   In the semiconductor device 10 according to the present embodiment, the porous filler 35 is densely arranged in the vicinity of the power element 12 and the control element 14 in the exterior body 15 and is unevenly distributed on the power element 12 side. Thereby, the semiconductor device 10 in which the heat insulation effect between the power element 12 and the control element 14 is enhanced can be realized. According to the present embodiment, the heat insulation effect between the power element 12 and the control element 14 is enhanced, and the heat radiation characteristic from the power element 12 to the heat sink 30 can realize the conventional semiconductor device 10. Therefore, even when the temperature of the power element 12 increases, the influence of heat on the control element 14 can be reduced, and the semiconductor device 10 with stable operation can be realized.

なお、外装体１５におけるパワー素子１２と制御素子１４との間を除く領域（通常封止樹脂領域）では、多孔質フィラー３５の含有割合は、できる限り低い方が望ましい。これは、パワー素子１２と制御素子１４との間を除く領域（通常封止樹脂領域）においても多孔質フィラー３５の含有割合が高くなると、外装体５を通してパワー素子１２の駆動により発生する熱を放出できず、パワー素子１２の放熱経路が放熱板３０を経由する以外になくなり、放熱板３０等の大型化が必要となるためである。   In addition, in the area | region (normal sealing resin area | region) except between the power element 12 and the control element 14 in the exterior body 15, the one where the content rate of the porous filler 35 is as low as possible is desirable. This is because the heat generated by driving the power element 12 through the exterior body 5 is increased when the content ratio of the porous filler 35 is increased in the area excluding the space between the power element 12 and the control element 14 (usually the sealing resin area). This is because the heat dissipation path of the power element 12 is lost except through the heat dissipation plate 30 and the heat dissipation plate 30 and the like need to be enlarged.

また、本実施形態に係る半導体装置１０では、リードフレーム１１の枚数は、本発明の目的を実現する限り、これに限られない。例えば、２枚の個別のリードフレームを一体化したリードフレームを用いてもよい。   In the semiconductor device 10 according to this embodiment, the number of lead frames 11 is not limited to this as long as the object of the present invention is realized. For example, a lead frame in which two individual lead frames are integrated may be used.

また、放熱板３０の熱伝導率を非常に高くすることが可能であれば、外装体１５からの放熱が不要となり、多孔質フィラー３５を含有したエポキシ樹脂７５を、キャビティ６５の内部の全体に充填させることも可能であると考えられる。すなわち、外装体１５として、エポキシ樹脂６６を使用しないことも可能であると考えられる。   Further, if the heat conductivity of the heat sink 30 can be made extremely high, it is not necessary to release heat from the exterior body 15, and the epoxy resin 75 containing the porous filler 35 is applied to the entire inside of the cavity 65. It is thought that filling is also possible. In other words, it is considered possible not to use the epoxy resin 66 as the exterior body 15.

本発明に係る樹脂封止型半導体装置及びその製造方法は、エアコン等の大電力用の機器に用いられる半導体装置等に適用できる。   The resin-encapsulated semiconductor device and the manufacturing method thereof according to the present invention can be applied to a semiconductor device or the like used in high-power equipment such as an air conditioner.

１０ 半導体装置
１１ リードフレーム
１２ パワー素子
１３ 金属部材
１４ 制御素子
１５ 外装体
１５ｂ，１６ｂ，３０ｂ 下面
１６ 第１ダイパッド部
１６ａ，４０ａ 上面
２６ ろう材
３０ 放熱板
３０ｂ 下面
３０ｃ 側面
３５ 多孔質フィラー
３５ａ 多孔質フィラー部位
３５ｂ 孔部位
４０ 第２ダイパッド部
４１ 絶縁性シート
５０ ダイオード
６２ 下金型
６３ 上金型
６４，７０ ゲート
６５ キャビティ
６６，７５ エポキシ樹脂DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Lead frame 12 Power element 13 Metal member 14 Control element 15 Exterior body 15b, 16b, 30b Lower surface 16 1st die pad part 16a, 40a Upper surface 26 Brazing material 30 Heat sink 30b Lower surface 30c Side surface 35 Porous filler 35a Porous Filler part 35b Hole part 40 Second die pad part 41 Insulating sheet 50 Diode 62 Lower mold 63 Upper mold 64,70 Gate 65 Cavity 66,75 Epoxy resin

Claims (13)

外装体と、
前記外装体の内部に封止されると共に、前記外装体から端部が突出したリードフレームと、
前記外装体の内部に封止されると共に、前記リードフレームに実装されたパワー素子と、
前記外装体の内部に封止されると共に、前記リードフレームに実装された制御素子と、を備え、
前記外装体における前記パワー素子と前記制御素子との間の領域は、前記パワー素子と前記制御素子との間を断熱するために他の領域と比べてフィラーの含有割合が高く、
前記外装体における前記パワー素子と前記制御素子との間を除く領域は、前記外装体を介して前記パワー素子からの熱を放熱するために前記パワー素子と前記制御素子との間の領域と比べて前記フィラーの含有割合が低く、
前記フィラーは、前記パワー素子と前記制御素子とを接続する第１金属部材を完全に覆うように配置された、
樹脂封止型半導体装置。 An exterior body,
A lead frame that is sealed inside the exterior body and has an end protruding from the exterior body;
A power element sealed inside the exterior body and mounted on the lead frame,
A control element mounted inside the lead frame and sealed inside the exterior body,
The region between the power element and the control element in the exterior body has a high filler content compared to other regions in order to insulate between the power element and the control element,
The region except between the power element and the control element in the exterior body is compared with the area between the power element and the control element in order to dissipate heat from the power element through the exterior body. the content of the filler Te is rather low,
The filler is disposed so as to completely cover the first metal member that connects the power element and the control element.
Resin-sealed semiconductor device. 外装体と、
前記外装体の内部に封止されると共に、前記外装体から端部が突出したリードフレームと、
前記外装体の内部に封止されると共に、前記リードフレームに実装されたパワー素子と、
前記外装体の内部に封止されると共に、前記リードフレームに実装された制御素子と、を備え、
前記外装体における前記パワー素子と前記制御素子との間の領域は、前記パワー素子と前記制御素子との間を断熱するために他の領域と比べてフィラーの含有割合が高く、
前記外装体における前記パワー素子と前記制御素子との間を除く領域は、前記外装体を介して前記パワー素子からの熱を放熱するために前記パワー素子と前記制御素子との間の領域と比べて前記フィラーの含有割合が低く、
前記フィラーは、前記制御素子側と比べて前記パワー素子側に偏在して配置されている、
樹脂封止型半導体装置。 An exterior body,
A lead frame that is sealed inside the exterior body and has an end protruding from the exterior body;
A power element sealed inside the exterior body and mounted on the lead frame,
A control element mounted inside the lead frame and sealed inside the exterior body,
The region between the power element and the control element in the exterior body has a high filler content compared to other regions in order to insulate between the power element and the control element,
The region except between the power element and the control element in the exterior body is compared with the area between the power element and the control element in order to dissipate heat from the power element through the exterior body. the content of the filler Te is rather low,
The filler is arranged unevenly on the power element side compared to the control element side,
Resin-sealed semiconductor device. 前記外装体における前記パワー素子と前記制御素子との間の領域に配置された第１封止樹脂は、他の領域に配置された第２封止樹脂と比べて前記フィラーの含有割合が高く、
前記第１封止樹脂の流動性よりも前記第２封止樹脂の流動性が高い、
請求項１又は２に記載の樹脂封止型半導体装置。 The first sealing resin disposed in a region between the power element and the control element in the exterior body has a higher content of the filler than the second sealing resin disposed in another region,
The fluidity of the second sealing resin is higher than the fluidity of the first sealing resin.
The resin-encapsulated semiconductor device according to claim 1. 前記第１封止樹脂の体積は、前記第２封止樹脂の体積の３分の１以下である、
請求項３に記載の樹脂封止型半導体装置。 The volume of the first sealing resin is 1/3 or less of the volume of the second sealing resin.
The resin-encapsulated semiconductor device according to claim 3 . 前記外装体における前記パワー素子と前記制御素子との間の領域において、前記フィラーは、７０重量％以上の割合で含有された、
請求項１から４のいずれか１項に記載の樹脂封止型半導体装置。 In the region between the power element and the control element in the exterior body, the filler was contained at a ratio of 70% by weight or more.
The resin-encapsulated semiconductor device according to any one of claims 1 to 4 . 前記外装体における前記パワー素子と前記制御素子との間の領域において、前記フィラーは、９０重量％以上の割合で含有された、
請求項５に記載の樹脂封止型半導体装置。 In the region between the power element and the control element in the exterior body, the filler was contained at a ratio of 90% by weight or more.
The resin-encapsulated semiconductor device according to claim 5 . 請求項１から６のいずれか１項に記載の樹脂封止型半導体装置が組み込まれた装置。 Resin-sealed semiconductor device is incorporated according to any one of claims 1 6. パワー素子及び制御素子が実装されたリードフレームを金型の内部に配置し、前記パワー素子と前記制御素子との間の領域にフィラーを含有する第１封止樹脂を注入した後、
前記パワー素子、前記制御素子及び前記リードフレームを第２封止樹脂で封止することで、
前記パワー素子と前記制御素子との間の領域が、前記パワー素子と前記制御素子との間を断熱するために他の領域と比べてフィラーの含有割合が高く、前記パワー素子と前記制御素子との間を除く領域が、外装体を介して前記パワー素子からの熱を放熱するために前記パワー素子と前記制御素子との間の領域と比べて前記フィラーの含有割合が低い外装体を形成する、
樹脂封止型半導体装置の製造方法。 After placing the lead frame on which the power element and the control element are mounted inside the mold and injecting a first sealing resin containing a filler in a region between the power element and the control element,
By sealing the power element, the control element and the lead frame with a second sealing resin,
The region between the power element and the control element has a higher filler content than other regions in order to insulate the power element and the control element, and the power element and the control element The region excluding the space between the power element and the control element forms an exterior body with a lower content of the filler in order to dissipate heat from the power element through the exterior body. ,
Manufacturing method of resin-encapsulated semiconductor device. 前記フィラーは、前記パワー素子と前記制御素子とを接続する第１金属部材を完全に覆うように配置された、
請求項８に記載の樹脂封止型半導体装置の製造方法。 The filler is disposed so as to completely cover the first metal member that connects the power element and the control element.
A method for manufacturing a resin-encapsulated semiconductor device according to claim 8 . 前記フィラーは、前記制御素子側と比べて前記パワー素子側に偏在して配置されている、
請求項８又は９に記載の樹脂封止型半導体装置の製造方法。 The filler is arranged unevenly on the power element side compared to the control element side,
A method for manufacturing a resin-encapsulated semiconductor device according to claim 8 or 9 . 前記フィラーは、多孔質フィラーである、
請求項８から１０のいずれか１項に記載の樹脂封止型半導体装置の製造方法。 The filler is a porous filler,
Method for producing a resin-encapsulated semiconductor device according to any one of claims 8 10. 前記フィラーの含有割合が前記制御素子側よりも前記パワー素子側が高くなるように、前記第１封止樹脂を注入するゲートを、前記金型に配置された前記制御素子よりも前記パワー素子に近い側に配置した、
請求項８から１１のいずれか１項に記載の樹脂封止型半導体装置の製造方法。 The gate for injecting the first sealing resin is closer to the power element than the control element arranged in the mold so that the filler content is higher on the power element side than on the control element side. Placed on the side,
Method for producing a resin-encapsulated semiconductor device according to any one of claims 8 11. 前記第１封止樹脂を注入して硬化させた後に、前記第２封止樹脂を注入する、
請求項８から１２のいずれか１項に記載の樹脂封止型半導体装置の製造方法。 After injecting and curing the first sealing resin, injecting the second sealing resin;
Method for producing a resin-encapsulated semiconductor device according to claim 8 in any one of 12.
JP2013525060A 2012-02-23 2012-12-14 Resin-sealed semiconductor device and manufacturing method thereof Expired - Fee Related JP5842109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013525060A JP5842109B2 (en) 2012-02-23 2012-12-14 Resin-sealed semiconductor device and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2012037100 2012-02-23
JP2012037100 2012-02-23
PCT/JP2012/008023 WO2013124940A1 (en) 2012-02-23 2012-12-14 Resin-sealed semiconductor device and method for manufacturing same
JP2013525060A JP5842109B2 (en) 2012-02-23 2012-12-14 Resin-sealed semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPWO2013124940A1 JPWO2013124940A1 (en) 2015-05-21
JP5842109B2 true JP5842109B2 (en) 2016-01-13

Family

ID=49005164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013525060A Expired - Fee Related JP5842109B2 (en) 2012-02-23 2012-12-14 Resin-sealed semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP5842109B2 (en)
WO (1) WO2013124940A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6270549B2 (en) * 2014-03-06 2018-01-31 株式会社 日立パワーデバイス Semiconductor device, motor using the same, and air conditioner
JP6980179B2 (en) * 2016-09-20 2021-12-15 株式会社Flosfia Semiconductor device
US10186478B2 (en) * 2016-12-30 2019-01-22 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface
JP7223968B2 (en) * 2017-01-31 2023-02-17 パナソニックＩｐマネジメント株式会社 Electrolytic capacitor
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2543452Y2 (en) * 1990-12-21 1997-08-06 富士通テン株式会社 Semiconductor device
JPH1143566A (en) * 1997-07-29 1999-02-16 Nippon Zeon Co Ltd Norbornene-based resin composition
JP3924968B2 (en) * 1997-12-17 2007-06-06 トヨタ自動車株式会社 Igniter
JP4381047B2 (en) * 2003-07-09 2009-12-09 東芝三菱電機産業システム株式会社 Semiconductor device
JP2005101580A (en) * 2003-08-28 2005-04-14 Matsushita Electric Ind Co Ltd Module with built-in circuit components, and its manufacturing method
JP4164874B2 (en) * 2004-05-31 2008-10-15 サンケン電気株式会社 Semiconductor device
JP4135101B2 (en) * 2004-06-18 2008-08-20 サンケン電気株式会社 Semiconductor device
JP4492257B2 (en) * 2004-08-26 2010-06-30 富士電機システムズ株式会社 Semiconductor module and manufacturing method thereof
JP2009295959A (en) * 2008-05-09 2009-12-17 Panasonic Corp Semiconductor device, and method for manufacturing thereof
JP2012038792A (en) * 2010-08-04 2012-02-23 Panasonic Corp Resin sealed semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
WO2013124940A1 (en) 2013-08-29
JPWO2013124940A1 (en) 2015-05-21

Similar Documents

Publication Publication Date Title
US11862533B2 (en) Fluid-cooled package having shielding layer
US8772923B2 (en) Semiconductor device having leads with cutout and method of manufacturing the same
JP6115738B2 (en) Semiconductor device and manufacturing method thereof
US9171773B2 (en) Semiconductor device
US9716072B2 (en) Power semiconductor device and method of manufacturing the same
US11862542B2 (en) Dual side cooling power module and manufacturing method of the same
WO2014097798A1 (en) Semiconductor device
US11776867B2 (en) Chip package
WO2012053205A1 (en) Semiconductor device and production method for same
JP5842109B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
US9754855B2 (en) Semiconductor module having an embedded metal heat dissipation plate
JP2009111154A (en) Power semiconductor module
JP6124810B2 (en) Power module
JP5921723B2 (en) Semiconductor device
JP2012209470A (en) Semiconductor device, semiconductor device module, and manufacturing method of the semiconductor device
JP2011238643A (en) Power semiconductor module
EP3958305A1 (en) Power semiconductor module arrangement and method for producing the same
JP2017092250A (en) Semiconductor device and method of manufacturing the same
JP5412532B2 (en) Semiconductor device and manufacturing method thereof
JP2013157485A (en) Semiconductor device and manufacturing method thereof
JP2012038792A (en) Resin sealed semiconductor device and method for manufacturing the same
KR101204223B1 (en) Power module package and method for manufacturing the same
JPS6129162A (en) Semiconductor device
JP5352856B2 (en) Semiconductor device
JP2015095619A (en) Mold package

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150407

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150512

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150602

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150624

R151 Written notification of patent or utility model registration

Ref document number: 5842109

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees