JP5840283B1 - Receiver - Google Patents

Abstract

Provided is a receiving device that can be easily designed and has low phase noise. In a receiving apparatus that extracts a pilot signal included in a received signal and converts the frequency of the received signal using the pilot signal, conversion for converting the frequency of the received signal based on a local signal generated from the pilot signal is performed. Means (frequency conversion unit 11), extraction means (BPF 12) for extracting a pilot signal from a signal output from the conversion means, a pilot signal extracted by the extraction means is multiplied to generate a local signal, and the conversion means A multiplying unit for supplying the multiplying unit, and the multiplying unit is configured by connecting a plurality of PLLs 13 and 14 in cascade. [Selection] Figure 1

Description

  The present invention relates to a receiving apparatus.

  The transmitting device superimposes a pilot signal on the signal of interest, converts the pilot signal to a predetermined frequency and transmits it, and the receiving device extracts the pilot signal from the received signal. As a technique for converting a signal of interest into an original frequency based on a local signal generated from the signal, there are techniques shown in Patent Documents 1 and 2, for example.

  In the technique disclosed in Patent Document 1, a signal in which a pilot signal Pr is superimposed on a signal Si that is a target in a transmission device is frequency-converted to a high-frequency signal Sh & Pr using the pilot signal, and then transmitted. FIG. 11 shows a configuration in which a pilot signal is extracted from the receiving apparatus shown in Patent Document 1 and an intermediate frequency unit that performs frequency conversion using a local signal generated from the pilot signal is extracted. In the intermediate frequency unit 100 shown in FIG. 11, the frequency conversion unit 110 converts the received high-frequency signal Sh & Pr based on a signal supplied from a VCO (Voltage Controlled Oscillator) 114 to generate an intermediate frequency signal Si & Pr. Output. At this time, the BPF (Band Pass Filter) 112 extracts the pilot signal Pr from the intermediate frequency signal Si & Pr output from the frequency converter 110 and supplies the pilot signal Pr to the PLL (Phase Locked Loop) 113. The PLL 113 multiplies the pilot signal supplied from the BPF 112 and outputs it to the VCO 114. The VCO 114 supplies a local signal obtained by oscillating based on the signal supplied from the PLL 113 to the frequency converter 110. The frequency divider 115 divides the local signal output from the VCO 114 and supplies it to the PLL 113.

  Further, in the technique disclosed in Patent Document 2, a pilot signal is superimposed on the upper side of the spectrum constituting the OFDM signal so as to have a frequency slightly separated from the spectrum of the OFDM signal and transmitted from the transmission apparatus. That is, in the receiving device 211 of Patent Document 2 shown in FIG. 12, a signal transmitted from the transmitting device is received by the receiving antenna 214, a predetermined frequency is extracted by the input filter unit 215, and is supplied to the frequency converting unit 216. The frequency conversion unit 216 converts the frequency of the signal supplied from the input filter unit 215 based on the local signal supplied from the multiplication unit 213 and outputs the signal. Here, the multiplier 217 multiplies the pilot signal supplied from the frequency converter 216 and outputs it. The comparison unit 218 controls the local oscillation unit 212 so that the phase difference between the signal supplied from the multiplication unit 217 and the signal output from the local oscillation unit 212 is eliminated. The multiplier 213 multiplies the signal output from the local oscillator 12 and supplies it to the frequency converter 216.

JP 2000-92142 A JP-A-11-205280

  By the way, in the technique disclosed in Patent Document 1, as shown in FIG. 11, the intermediate frequency unit 100 included in the receiving device includes a frequency converter 110, a BPF 112, a PLL 113, and a parent loop having a VCO 114, a PLL 113, There is a VCO 114 and a child loop with a divider 115. For this reason, since it is necessary to optimally design these two loops in order to design a receiving apparatus having such an intermediate frequency unit 100, there is a problem that the design becomes complicated.

  In the technique disclosed in Patent Document 2, the receiving device 211 has two units, a multiplier 213 and a multiplier 217, which form a closed loop, and therefore, a pilot signal output from the frequency converter 216. When the phase noise has phase noise, the phase noise is increased by the multipliers 217 and 213 and further increased by the multiplier every time it circulates in the closed loop. Therefore, the influence of the phase noise cannot be ignored. There is a problem.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a receiving apparatus that can be easily designed and has low phase noise.

In order to solve the above-described problems, the present invention extracts a pilot signal included in a received signal and converts the frequency of the received signal using the pilot signal into a local signal generated from the pilot signal. Conversion means for converting the frequency of the received signal based on the extraction means, extraction means for extracting the pilot signal from the signal output from the conversion means, and multiplying the pilot signal extracted by the extraction means to convert the local signal generated, anda multiplying means for supplying to said converting means, said multiplying means comprises two a PLL (Phase Locked Loop) are cascaded Rutotomoni, the second stage than the first stage The cutoff frequency of the PLL is set to be low .
According to such a configuration, it is possible to provide a receiving apparatus that can be easily designed and has little phase noise.

Further, the present invention is characterized by further comprising frequency dividing means arranged on a path from the extracting means to the converting means and dividing the pilot signal and outputting it.
According to such a configuration, a local signal having a desired frequency can be generated by adjusting the frequency division ratio of the frequency dividing means and the PLL multiplication rate.

The present invention is characterized in that, among the two PLLs, the last-stage PLL has a dielectric resonance oscillator as a voltage-controlled oscillator.
According to such a configuration, for example, a high-frequency local signal such as a GHz band can be generated.

Further, the present invention is characterized in that, among the two PLLs, the last-stage PLL directly inputs the oscillation signal generated by the dielectric resonance oscillator to the phase comparator without dividing the oscillation signal.
According to such a configuration, the design can be simplified by excluding the frequency divider that is difficult to operate at a high frequency.

The present invention is further characterized by further comprising another multiplying means arranged on the path from the extracting means to the converting means and for multiplying and outputting the pilot signal.
According to such a configuration, a local signal having a desired frequency can be easily obtained by adjusting the multiplication factor of the other multiplication unit and the multiplication factor of the multiplication unit.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to design easily with a simple structure, and to provide a receiver with little phase noise.

It is a figure which shows the structural example of the receiver which concerns on 1st Embodiment of this invention. It is a figure which shows the structural example of PLL13 shown in FIG. It is a figure which shows the structural example of PLL14 shown in FIG. It is a figure for demonstrating operation | movement of 1st Embodiment. It is a figure for demonstrating operation | movement of 1st Embodiment. It is a figure for demonstrating operation | movement of 1st Embodiment. It is a figure for demonstrating operation | movement of 1st Embodiment. It is a figure which shows the structural example of the receiver which concerns on 2nd Embodiment of this invention. It is a figure which shows the structural example of the receiver which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the receiver which concerns on 4th Embodiment of this invention. It is a figure which shows the structure of the conventional receiver. It is a figure which shows the structure of the conventional receiver.

  Next, an embodiment of the present invention will be described.

(A) Description of Configuration of First Embodiment of the Present Invention FIG. 1 is a diagram illustrating a configuration example of a receiving apparatus according to the first embodiment of the present invention. As illustrated in FIG. 1, the receiving device 10 according to the first embodiment of the present invention includes a frequency conversion unit 11, a BPF 12, a PLL 13, and a PLL 14.

  Here, the frequency conversion unit 11 receives the signal Vin supplied from the preceding device (for example, an antenna not shown), converts the frequency (down-conversion) based on the local signal supplied from the PLL 14, and outputs the converted signal. To do.

  The BPF 12 extracts a pilot signal from the signal output from the frequency converter 11, attenuates the other signals, and supplies them to the PLL 13.

  The PLL 13 multiplies the pilot signal extracted by the BPF 12 (N1 / R1 times) and supplies it to the PLL 14. The PLL 14 further multiplies the signal output from the PLL 13 (N2 / R2 times) and supplies the signal to the frequency converter 11 as a local signal.

  FIG. 2 is a diagram showing a detailed configuration example of the PLL 13 shown in FIG. As shown in FIG. 2, the PLL 13 includes a frequency divider 131, a phase detector 132, an LPF 133, a VCO 134, and a frequency divider 134.

  Here, the frequency divider 131 divides the frequency of the input signal by 1 / R1 and outputs it. The phase detector 132 compares the phase of the signal output from the frequency divider 131 with that of the signal output from the frequency divider 135, and outputs a signal of these differences.

  An LPF (Low Pass Filter) 133 is a filter having a cut-off frequency fc1, passes a signal component having a frequency lower than the cut-off frequency fc1, and attenuates and outputs a signal component having a high frequency.

  The VCO 134 oscillates at a frequency corresponding to the voltage of the signal supplied from the LPF 133 and outputs an oscillation signal. The frequency divider 135 divides the frequency of the signal output from the VCO 134 by 1 / N1 and outputs the result.

  FIG. 3 is a diagram showing a detailed configuration example of the PLL 14 shown in FIG. As shown in FIG. 3, the PLL 14 includes a frequency divider 141, a phase detector 142, an LPF 143, a VCO 144, and a frequency divider 145.

  Here, the frequency divider 141 divides the frequency of the input signal by 1 / R2 and outputs it. The phase detector 142 compares the phase of the signal output from the frequency divider 141 with the signal output from the frequency divider 145, and outputs a signal of these differences.

  The LPF 143 is a filter having a cutoff frequency fc2, passes a signal component having a frequency lower than the cutoff frequency fc2, and attenuates and outputs a signal component having a high frequency.

  The VCO 144 oscillates at a frequency corresponding to the voltage of the signal supplied from the LPF 143 and outputs an oscillation signal. The frequency divider 145 divides the frequency of the signal output from the VCO 144 by 1 / N 2 and outputs the result.

(B) Description of Operation of First Embodiment of the Invention Next, operation of the first embodiment will be described. The frequency converter 11 converts a signal supplied from a device (for example, an antenna) in the previous stage (not shown) into a frequency of these frequencies by a local signal of a predetermined frequency (for example, several GHz to several tens GHz) supplied from the PLL 14. Frequency-converted (down-converted) to the difference frequency and output.

  The BPF 12 passes a pilot signal having a predetermined frequency (for example, several hundred MHz) included in the signal output from the frequency converter 11, and other components are attenuated and supplied to the PLL 13.

  The frequency divider 131 of the PLL 13 divides the signal supplied from the BPF 12 into 1 / R1 and outputs it. The phase detection unit 132 compares the phase of the signal supplied from the frequency divider 131 with that of the signal supplied from the frequency divider 135, and outputs a signal corresponding to the difference between these phases. The LPF 133 passes the low frequency component of the signal output from the phase detector 132 and attenuates and outputs the high frequency component. The VCO 134 outputs a signal having a frequency corresponding to the signal supplied from the LPF 133. The frequency divider 135 divides the frequency of the signal output from the VCO 134 by 1 / N1 and outputs the result. As a result, the VCO 134 outputs a signal having a frequency N1 times the frequency of the signal output from the frequency divider 131. That is, the phase detector 132 supplies a control signal to the VCO 134 via the LPF 133 so that the signal output from the frequency divider 131 and the signal output from the frequency divider 135 are equal in phase. The VCO 134 outputs a signal having a frequency N1 times the frequency of the signal output from the frequency divider 131. The signal output in this way is supplied to the PLL 14.

  The frequency divider 141 of the PLL 14 divides the signal supplied from the PLL 13 by 1 / R2 and outputs it. The phase detector 142 compares the phase of the signal supplied from the frequency divider 141 with the phase of the signal supplied from the frequency divider 145, and outputs a signal corresponding to the difference between these phases. The LPF 143 passes the low frequency component of the signal output from the phase detector 142 and attenuates and outputs the high frequency component. The VCO 144 outputs a signal having a frequency corresponding to the signal supplied from the LPF 143. The frequency divider 145 divides the frequency of the signal output from the VCO 144 by 1 / N 2 and outputs the result. As a result, the VCO 144 outputs a signal having a frequency N2 times the frequency of the signal output from the frequency divider 141. That is, since the phase detector 142 supplies the control signal to the VCO 144 via the LPF 143 so that the phase of the signal output from the frequency divider 141 is equal to the phase of the signal output from the frequency divider 145, The VCO 144 outputs a signal having a frequency N2 times the frequency of the signal output from the frequency divider 141. The signal output in this way is supplied to the frequency converter 11.

  The frequency conversion unit 11 performs frequency conversion (down-conversion) on a signal having a predetermined frequency (for example, several GHz to several tens GHz) supplied from the preceding apparatus by a local signal supplied from the PLL 14 and outputs the signal. The signal output in this way is supplied to the BPF 12, a local signal is generated by the above-described processing, and is supplied to the frequency conversion unit 11.

  By the way, in the technique disclosed in Patent Document 2 described above, a pilot signal is multiplied by two multipliers 217 and 213 to generate a local signal. In this case, when the pilot signal output from the frequency converter 216 has phase noise, such phase noise is increased and output by the multipliers 217 and 213. For example, if the frequency is multiplied by N by both of these multipliers 217 and 213, the phase noise increases by 20 · log (N) [dB].

  FIG. 4 is a diagram illustrating phase noise. FIG. 4A shows the original signal. In this figure, the horizontal axis represents frequency and the vertical axis represents power. One protruding line segment near the center indicates a pilot signal, and a plurality of short line segments indicate phase noise.

  FIG. 4B is a diagram illustrating a signal output from the multiplier used in Patent Document 2. As described above, the signal whose frequency is multiplied by N by the multiplier is output with the signal frequency multiplied by N and the phase noise increased by 20 · log (N) dB over the entire band.

  FIG. 4C is a diagram illustrating signals output from the PLL 13 and the PLL 14 used in the first embodiment. As described above, the signals output from the PLLs 13 and 14 are output after being multiplied by N within the loop band of the PLLs 13 and 14 in the same manner as the multipliers, but decrease according to the loop characteristics outside the loop band. More specifically, the value obtained by multiplying the phase noise included in the original signal by N (in detail, 20 · log (N)) is dominant within the loop band of the PLLs 13 and 14, and outside the loop band, The phase noise generated by the VCOs 134 and 144 becomes dominant.

  That is, in the technique disclosed in Patent Document 2, the multiplication unit adds 20 · log (N) of phase noise included in the input signal regardless of the frequency. In the PLLs 13 and 14 of the first embodiment, 20 · log (N) is added to the frequency in the loop band, and the phase noise generated by the VCOs 134 and 144 is dominant in other cases. Therefore, in the first embodiment, the phase noise included in the input signal is reduced and the phase noise generated by the VCOs 134 and 144 is reduced by appropriately setting the cutoff frequency fs of the loop gain of the PLLs 13 and 14. By setting (using a low-noise VCO), the phase noise of the entire apparatus can be reduced.

Next, the relationship between the cut-off frequency fs of the loop gain in the PLL and the phase noise will be described in detail using the phase noise model of the PLL shown in FIG. Equation (1) shown below is the phase noise N _in included in the input signal Vin of the PLL 13 and the output signal Vout _{in the} phase noise model shown in FIG. 5A when R1 = 1 of the frequency divider 131. _Is a transfer function of the phase noise _Nout included in. Here, K _V1 / s is a conversion gain of the VCO 134, K _P1 is a gain of the phase detector 132, and F ₁ (s) is a transfer function of the LPF 133.

Further, the following equation (2) is obtained by calculating the phase noise N _vco included in the signal output from the VCO 134 in the phase noise model shown in FIG. 5B when R1 = 1 of the frequency divider 131, is the transfer function of the phase noise _{N out} contained in the output signal Vout.

In Expression (1), s is a large value at a high frequency, and F ₁ (s) is a transfer function of the LPF, and therefore has a small value at a frequency higher than the cutoff frequency. For this reason, s / F ₁ (s) has a large value at a frequency higher than the cutoff frequency of the LPF, and this dominates in the denominator of the equation (1), and N _out / N _in has a small value. This means that the influence of the phase noise included in the input signal can be satisfactorily reduced at a high frequency. In Equation (2), s is a small value at a low frequency, and F ₁ (s) is a transfer function of LPF, and thus is close to 1 at a frequency lower than the cutoff frequency. Therefore, the value obtained by multiplying F ₁ (s) / s by K _P1 and K _V1 becomes a large value at a frequency lower than the cutoff frequency of the LPF, and behaves dominantly in the denominator of the equation (3), and N _out / N _vco is a small value. This means that the influence of the phase noise included in the VCO 134 can be satisfactorily reduced at a low frequency.

Therefore, if the cutoff frequency of these transfer functions is fs, the influence of the phase noise included in the input signal is dominant below fs, and the influence of the phase noise included in the VCO 134 is dominant above fs. In the above example, the PLL 13 has been described as an example, but the PLL 14 is also the same. Expressions (1) and (2) in the case of the PLL 14 are obtained by replacing K _V1 , K _P1 and F ₁ (s) with K _V2 , K _P2 and F ₂ (s), respectively.

  FIG. 6 is a diagram showing a spectrum of the PLL. In this figure, a curve C1 indicated by a solid line indicates the phase noise (C / N) of the input signal of the PLL, and a curve C2 indicated by a broken line disconnects the PLL feedback loop from the VCO and inputs an ideal DC voltage to the VCO. In this case, the phase noise of the VCO is shown, a curve C3 indicated by a one-dot chain line indicates phase noise of a PLL having an LPF with a low cutoff frequency, and a curve C4 indicated by a two-dot chain line is a curve C4 of a PLL having an LPF with a high cutoff frequency. Indicates phase noise. Since the PLL involves frequency conversion, the input signal C1 and the output signals C2 to C4 have different frequencies, but the center frequency is shown on the horizontal axis for comparison of phase noise characteristics. In FIG. 6, fs represents a frequency at which the gain of the entire loop including the LPF becomes 1, and Δf represents a frequency shift from the center frequency. As shown in FIG. 6, the phase noise included in the output signal of the PLL gradually approaches the curve C2 that is the phase noise of the VCO when Δf> fs as shown by the curves C3 and C4, and Δf < In fs, it gradually approaches a curve C1 of the phase noise of the input signal through a flat section. Further, from the comparison between the curve C3 and the curve C4, the phase noise characteristic changes according to the cutoff frequency fc of the LPF. More specifically, setting the LPF cut-off frequency fc low is preferable because phase noise is reduced in a region where Δf is large, but is not preferable in a region where Δf is small. For this reason, it is necessary to set the characteristics of the LPF based on the above characteristics.

As described above, it is possible to reduce the phase noise by using the PLL for multiplying the pilot signal. However, on the right side of the equation (2), the relation of division with respect to F ₁ (s) / s is obtained. There is N1. This means that when the multiplication factor is high, N1 increases and the effect of reducing noise contained in the VCO 134 due to F ₁ (s) / s decreases. Therefore, in the first embodiment, the PLL 13 and the PLL 14 are connected in cascade, and the frequency of the pilot signal is multiplied by these two PLLs 13 and 14 in two stages. As a result, the multiplication factor in each PLL is increased while lowering the multiplication factor in each PLL and maintaining the effect of reducing the phase noise of the VCO. According to such a configuration, design can be simplified, and phase noise can be reduced by optimally designing each of the PLL 13 and the PLL 14. That is, in the first embodiment, the PLLs 13 and 14 have a two-stage configuration, so that the loop gain of each PLL can be set lower than in the case of a single-stage configuration, thereby providing a phase margin. By having it, the design can be simplified. Further, by using a two-stage configuration, the phase noise can be more effectively reduced by increasing the degree of freedom in setting the cutoff frequency of each PLL. Further, since the second stage PLL 14 outputs the phase noise output from the first stage PLL 13 by N2 / R2 times, by using low noise components for the first stage, Phase noise can be efficiently reduced. Further, as shown in FIG. 7, phase noise (noise indicated by a broken-line circle) in the region where Δf is large in the output of the first-stage PLL 13 can be removed by the feedback loop characteristic of the second-stage PLL 14. By adjusting the LPF 133 and LPF 143 so that the cut-off frequency fc13 of the first-stage LPF 133 is increased and the cut-off frequency fc14 of the second-stage LPF 143 is lower than that, the phase noise of the VCO 13 in the region where Δf is small It is possible to reduce phase noise in a region where Δf is large while reducing the influence of.

  As described above, according to the first embodiment of the present invention, two PLLs 13 and 14 are connected in cascade, and the frequency of the pilot signal is multiplied by these two PLLs 13 and 14. The phase noise can be reduced as compared with the case where the multiplier shown in FIG. Further, by connecting the two PLLs 13 and 14 in cascade, the loop gain of each PLL can be lowered to facilitate the design. Moreover, the phase noise to be output can be further reduced by individually adjusting the cutoff frequencies of the PLLs 13 and 14.

(C) Description of Second Embodiment of the Present Invention Next, a second embodiment of the present invention will be described. FIG. 8 is a diagram illustrating a configuration example of the second embodiment. In FIG. 8, portions corresponding to those in FIG. In the receiving apparatus 10A shown in FIG. 8, a frequency divider 20 is added between the BPF 12 and the PLL 13 as compared with FIG. The rest of the configuration is the same as in FIG. Here, the frequency divider 20 divides and outputs the pilot signal output from the BPF 12.

  Next, the operation of the second embodiment will be described. In the second embodiment, the pilot signal output from the BPF 12 is frequency-divided by the frequency divider 20 and supplied to the PLL 13. The PLL 13 multiplies the frequency of the signal output from the frequency divider 20 and supplies it to the PLL 14. The PLL 14 multiplies the frequency of the signal output from the PLL 13 and supplies the frequency conversion unit 11 as a local signal. The frequency converting unit 11 converts (down-converts) the frequency of the input signal based on the local signal supplied from the PLL 14 and outputs the converted signal.

  Since the second embodiment has a frequency divider 20 as compared with the first embodiment, various combinations of the frequency division ratio of the frequency divider 20 and the multiplication ratios of the PLLs 13 and 14 can be used. Application of the present invention to frequency becomes possible. Thereby, for example, by sharing parts, the manufacturing cost can be reduced, and the design burden can be reduced.

  As described above, according to the second embodiment of the present invention, in addition to the effects described in the first embodiment, a combination of the frequency division ratio of the frequency divider 20 and the multiplication ratio of the PLLs 13 and 14 is used. Thus, the present invention can be applied to various frequencies, and the manufacturing cost and design burden can be reduced.

  In the example of FIG. 8, the frequency divider 20 is arranged between the BPF 12 and the PLL 13. However, if the frequency divider 20 is on the path from the output of the BPF 12 to the input of the frequency converter 11, it is arranged elsewhere. You may make it do.

(D) Description of Third Embodiment of the Present Invention Next, a third embodiment of the present invention will be described. FIG. 9 is a diagram showing a configuration example of the third embodiment of the present invention. In FIG. 9, parts corresponding to those in FIG. In the receiving apparatus 10B illustrated in FIG. 9, the PLL 14 is replaced with a PLL 24 as compared with FIG. 1. The rest of the configuration is the same as in FIG.

  Here, the PLL 24 includes a multiplier 241, an SPD (Sampling Phase Detector) 242, an LPF 243, and a DRO (Dielectric Resonance Oscillator) 245. Here, the multiplier 241 multiplies the frequency of the signal output from the PLL 13 by N2, and outputs it. The SPD 242 compares the phase of the signal output from the multiplier 241 and the signal output from the DRO 245, calculates the difference between these signals, and outputs the calculated difference. The LPF 243 passes a signal component having a frequency lower than the cutoff frequency fc from the signal output from the SPD 242 and attenuates and outputs a signal component having a higher frequency. The DRO 245 is a dielectric resonance oscillator that can perform low-noise oscillation at a high frequency.

  Next, the operation of the third embodiment will be described. Note that the third embodiment is different from the first embodiment in that the PLL 24 is different, and therefore the PLL 24 will be mainly described.

  The PLL 24 is different from the PLL 14 in that the frequency divider 135 is excluded and a multiplier 241 is added. In the PLL 24, the frequency of the input signal is multiplied by N2 times by the multiplier 241 and is not multiplied in the loop of the SPD 242, the LPF 243, and the DRO 245. This is because when a signal generated by the DRO 245 has a high frequency in the GHz band, for example, it is difficult to obtain a frequency divider that can handle such a high frequency. For this reason, in the third embodiment, the frequency divider is excluded, and a multiplier 241 is used instead to multiply the input signal. In the multiplier 241, the phase noise is amplified over the entire band as shown in FIG. 4B. However, in the third embodiment, a loop including the LPF 243 exists in the subsequent stage of the multiplier 241. The phase noise output from the multiplier 241 is reduced by the characteristic shown in the above-described equation (1).

  As described above, according to the third embodiment of the present invention, since the frequency of the input signal is multiplied using the multiplier 241, the frequency division that can cope with the high frequency signal generated by the DRO 245. Can be excluded from the PLL 24. As a result, the design can be simplified and the manufacturing cost can be reduced. In addition, phase noise can be reduced by a circuit subsequent to the multiplier 241.

(E) Explanation of 4th Embodiment of this invention Next, 4th Embodiment of this invention is described. FIG. 10 is a diagram showing a configuration example of the fourth embodiment of the present invention. In FIG. 10, parts corresponding to those in FIG. In the receiving apparatus 10 </ b> C illustrated in FIG. 10, a multiplier 25 is added to the subsequent stage of the PLL 24 as compared with FIG. 9. The rest of the configuration is the same as in FIG.

  In the fourth embodiment, since the multiplier 25 is arranged between the PLL 24 and the frequency conversion unit 11, various frequencies can be obtained by combining the multiplication ratio of the multiplier 25 and the multiplication ratios of the PLLs 13 and 24. The present invention can be applied, and the manufacturing cost and the design burden can be reduced. Further, as described above, the phase noise can be reduced by the circuit subsequent to the multiplier 241.

(F) Description of Modified Embodiment The above embodiment is an example, and it is needless to say that the present invention is not limited to the case described above. For example, in each of the above-described embodiments, the two-stage configuration of the PLLs 13 and 14 or the PLLs 13 and 24 is used.

  Further, the frequency dividers 131 and 141 are provided in the PLLs 13 and 14, but the frequency dividers 131 and 141 may not be provided depending on circuit conditions.

  In the second embodiment shown in FIG. 8, the frequency divider 20 is arranged between the BPF 12 and the PLL 13, but if this is on the path from the output of the BPF 12 to the input of the frequency converter 11, You may make it arrange | position in places other than.

  In the fourth embodiment shown in FIG. 10, the multiplier 25 is arranged between the PLL 24 and the frequency converter 11. However, if the multiplier 25 is on the path from the output of the BPF 12 to the input of the frequency converter 11. Alternatively, it may be arranged in a place other than this.

10, 10A, 10B, 10C Receiver 11 Frequency converter (converter)
12 BPF (extraction means)
13, 14, 24 PLL (part of multiplication means)
20 frequency divider (frequency divider)
25 Multiplier (multiplication means)
131,141 Frequency Divider 132,142 Phase Detector 133,143 LPF
134,144 VCO
135,145 Divider 241 Multiplier 242 SPD
243 LPF
245 DRO

Claims (5)

In a receiving apparatus that extracts a pilot signal contained in a received signal and converts the frequency of the received signal using the pilot signal,
Conversion means for frequency-converting the received signal based on a local signal generated from the pilot signal;
Extracting means for extracting the pilot signal from the signal output from the converting means;
A multiplier for multiplying the pilot signal extracted by the extractor to generate the local signal and supplying the local signal to the converter;
Said multiplying means, characterized in that two of a PLL (Phase Locked Loop) is are cascaded Rutotomoni, the second-stage PLL cut-off frequency than the first stage is set to be lower A receiving device.   2. The receiving apparatus according to claim 1, further comprising frequency dividing means arranged on a path from the extracting means to the converting means and dividing the pilot signal and outputting the result. The receiving apparatus according to claim 1 or 2, wherein the last-stage PLL of the two PLLs has a dielectric resonance oscillator as a voltage-controlled oscillator. 4. The reception according to claim 3, wherein, of the two PLLs, the last-stage PLL directly inputs an oscillation signal generated by the dielectric resonance oscillator to a phase comparator without dividing the oscillation signal. apparatus. 5. The reception according to claim 1, further comprising another multiplying unit arranged on a path from the extracting unit to the converting unit and multiplying and outputting the pilot signal. apparatus.

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