JP5729546B2 - Semiconductor design support apparatus, timing constraint generation method, and program - Google Patents

Description

  The present invention uses a CDC (Clock Domain Crossing: Asynchronous circuit) verification result performed in an upstream process at the time of LSI development, and performs logic synthesis / layout design (place and route) / STA performed in a downstream process after layout. The present invention relates to a semiconductor design support apparatus that provides a function of extracting a timing constraint for (Static Timing Analysis).

  In recent LSI (Large Scale Integration) development, as the miniaturization of advanced devices (60nm → 40nm → 28nm) progresses, the functions mounted on one device have become larger / complex. There is a tendency that the number of clock lines used in the LSI increases with the increase in scale / complexity of the LSI. In addition, it is considered that the number of clock lines further increases with further miniaturization in the future.

In digital circuit design performed at the time of LSI development, an increase in the number of clock lines can be a cause of various problems. For example, the following problems are likely to occur.
(1) The frequency of occurrence of the meta-stability state increases, and the MTBF of the entire apparatus decreases.
This is because an increase in the number of clock lines increases the combination of transmission paths between different clocks, resulting in an increase in the number of asynchronous circuits. Asynchronous circuits cause a meta-stability condition, and the meta-stability condition propagates to the subsequent circuit, causing the LSI to malfunction and eventually causing intermittent hardware failures as a device. It is easy to become.
(2) The timing specifications as a device are not met and the processing capability does not improve.
This is because an increase in the number of clock lines tends to cause inadequate timing constraints (clock omission, clock cycle error, etc.) given during layout design, and the desired processing speed and timing specifications with the opposing device may be satisfied. It becomes a factor that becomes impossible.

In order to avoid the above problems, the following methods can be taken.
In (1), a clock system diagram and timing specifications are created in an upstream process (specification design). With reference to these, a synchronizer function is inserted into the asynchronous connection portion to guarantee logical operation. Check if the synchronizer function is correctly inserted with the CDC verification tool.
In (2), in the downstream process (logic synthesis / layout design / STA), a clock constraint, an input / output timing constraint, an internal delay constraint, etc. are created from the clock system diagram and timing specifications. Check with each tool whether the constraints are correctly reflected without omission.

  As a technique for LSI design support, Patent Document 1 describes a semiconductor design support apparatus that can extract a false path from logic circuit data described in RTL (Register Transfer Level).

JP 2008-226069 A

  As described above, the increase in the number of clocks associated with the increase in the design of electrical circuits such as LSIs makes the circuit configuration very complex, and the difficulty of giving appropriate timing constraints to the design circuit is a problem. Become. In other words, the issue is how to provide a development flow in which appropriate timing constraints can be efficiently performed within limited user resources with appropriate and low resources. In the present invention, this is solved.

  In general, in order to avoid the problem of an increase in the number of clock lines, it is necessary to create a clock system diagram and a timing specification along with the specification formulation. Even in the methods exemplified as (1) and (2), it is essential to create a clock system diagram and timing specifications.

However, the following problems occur in the methods (1) and (2).
The clock system diagram is often changed during the design. In many cases, the contents of the change are reflected in the source code in real time, but the clock system diagram is corrected later, so there is a period in which the equivalence between the clock system diagram and the source code cannot be obtained. Alternatively, there is a case where “source code = specification” without creating a clock system diagram.

  Particularly in the case of (2), in the downstream process, a clock constraint, an input / output timing constraint, an internal delay constraint, etc. are created as timing constraints used by various tools from the clock system diagram and timing specifications. Check with each tool whether the design is correctly reflected in the design without omissions.

  In this case, manual timing is required when creating timing constraints for each tool from the clock system diagram, so it is easy for description errors and omissions to occur, and there are cases where placement and routing and STA are executed many times in the downstream process. It becomes easy. The lead time increases as the development becomes larger, so that it takes time until the layout Fix. In addition, a large amount of resources are consumed when feedback is provided to the upstream process.

  The present invention has been made by trying a new approach to the above problem, and it is possible to give an appropriate timing constraint in the downstream process after logic synthesis without depending on the designer by processing of the upstream process. An object of the present invention is to provide a semiconductor design support apparatus.

The semiconductor design support apparatus for performing asynchronous verification according to the present invention is determined by the CDC verification result performed on the source code at the time of designing the electric circuit including the asynchronous circuit and the specification formulation process used for coding the source code. Means for clarifying all the clocks included in the source code from the known information obtained, and collecting and acquiring as a setting file for CDC verification, asynchronous file obtained from the CDC verification setting file and the CDC verification result A means for extracting and processing a predetermined information from the input / output path for each path so as to match a format readable by a design tool used in a downstream process, and generating and outputting a timing constraint file. The means for collecting and acquiring as a CDC verification setting file is obtained as the CDC verification result. , Clock line list, clock input / output terminal list, estimated undefined clock list, asynchronous path list including presence / absence of meta-stability measures, referring to the clock system diagram and timing specifications as the known information, It is characterized in that all clocks included in the source code, the period of each clock, the correlation between clocks, and information indicating the input / output terminals related to each clock are clarified and generated as a CDC verification setting file. To do.
  The program according to the present invention includes a control unit of an information processing apparatus that performs asynchronous verification of an electric circuit including an asynchronous circuit, a clock line list of a verification target source code, an input / output terminal list related to a clock, an estimated Referring to the definition clock list and the CDC verification result including the asynchronous path list including the presence or absence of meta-stability measures and the known information including the clock system diagram and timing specifications of the source code, all of the source code included The clock is operated as means for extracting and collecting information indicating the clock cycle, the correlation between the clocks, and the input / output terminals related to the individual clocks as a setting file for CDC verification.
  The program according to the present invention includes a control unit of an information processing device that performs asynchronous verification of an electrical circuit that includes an asynchronous circuit, and includes a clock line list of the source code for all clocks included in the source code to be verified, List of input / output terminals related to clock, estimated undefined clock list, CDC verification result including asynchronous path list including presence / absence of meta-stability countermeasure, and known information including clock system diagram and timing specification of source code concerned On the basis of all the clocks included in the source code, the period of each clock, the correlation between the clocks, and the information on the input / output terminals related to each clock, and the asynchronous path obtained from the CDC verification result To a format that can be read by design tools used in downstream processes. Extracts predetermined information on timing constraints to, characterized in that to operate as means for automatically generating a timing constraint file.
  A method of designing a semiconductor integrated circuit using an information processing apparatus according to the present invention performs CDC verification on a source code, and from the source code, a clock line list, an input / output terminal list related to a clock, and an estimated undefined clock The list and the asynchronous path list including the presence / absence of the meta-stability measure are extracted as CDC verification information, and the CDC verification information extracted as the CDC verification result, and the clock system diagram and the timing specification as the known information are referred to. , Clarification of information indicating all clocks included in the source code, the period of each clock, correlation between the clocks, and input / output terminals related to each clock, and generation processing as a setting file for CDC verification Asynchronous paths that cause metastability due to asynchronous clocks If there is a correction path that needs to be corrected, the source code is corrected so that a meta-stability measure is incorporated into the detected asynchronous path, and the process returns to the CDC verification information extraction process, and the asynchronous code included in the CDC verification information is returned. Asynchronous path information indicating a transmission clock, a reception clock, and a From / to path for each asynchronous path is extracted from the path list, and timing constraints are indicated from the asynchronous path information and the CDC verification setting file. The information can be output in a format that can be read by at least one of a logic synthesis tool, a layout tool, and a STA tool used in a downstream process.
  In the timing constraint generation method by the information processing apparatus according to the present invention, the CDC verification is performed by the information processing apparatus on the source code coded based on the specification determined in the specification formulation process when designing the semiconductor integrated circuit including the asynchronous circuit. And an asynchronous path list including a clock line list, an input / output terminal list related to the clock, an estimated undefined clock list, and the presence / absence of meta-stability countermeasures as a CDC verification result, With reference to the obtained CDC verification result and known information including the clock system diagram and timing specifications of the source code, all the included clocks, the period of each clock, the correlation between clocks, Extract and process information indicating input / output terminals related to clock Generate a configuration file for CDC verification, and match the format that can be read by the design tool used in the downstream process from the configuration file for CDC verification and the input / output path for each asynchronous path obtained from the CDC verification result Extracts predetermined information and generates and outputs a timing constraint file. The design tool used in the downstream process reads the timing constraint file generated by the information processing device, identifies the timing constraint of each clock, and performs asynchronous verification. It is characterized by performing.

  According to the present invention, it is possible to provide a semiconductor design support apparatus that can provide an appropriate timing constraint in a downstream process after logic synthesis without depending on a designer by processing in an upstream process.

1 is a block diagram showing a configuration of a semiconductor design support apparatus 100 according to an embodiment. It is a flowchart which shows operation | movement of the semiconductor design support apparatus 100 concerning one Embodiment. It is explanatory drawing which shows the relevance of the example of a process which makes timing restrictions artificially, and the information used by each process. It is explanatory drawing which shows the relevance of the information used at each process, if a timing constraint is extracted and generated automatically.

  An embodiment of the present invention will be described with reference to FIGS. It should be noted that description of parts that are not related to the present invention and obvious parts is simplified or omitted.

FIG. 1 is a block diagram illustrating a part of the configuration of a semiconductor design support apparatus 100 according to an embodiment.
As illustrated, the semiconductor design support apparatus 100 includes a CDC detection tool execution unit 110, a clock clarification processing unit 120, a metastability countermeasure unit 130, a data format conversion unit 140, and a storage unit 150. It is desirable to operate by adding the same configuration as the existing semiconductor design support apparatus to the configuration shown in the figure.

The CDC verification tool execution unit 110 performs CDC verification on the source code recorded in the storage unit 150, and from the source code, a clock line list, a clock input / output terminal list, an undefined clock list, The asynchronous path list including information indicating the presence or absence of the path meta-stability measure is extracted as CDC verification information and recorded in the storage unit 150. The output CDC verification information may be a single report file or may be divided into a plurality of report files and output.
As the CDC verification tool, an existing CDC verification tool may be used. For example, “0-In CDC manufactured by Mentor Graphics” may be used.

The clock clarification processing unit 120 refers to the CDC verification information created by the CDC verification tool execution unit 110 and known information such as a clock system diagram and timing specifications created in advance as a specification formulation, and serves as a CDC verification setting file. The following information is clarified and then recorded in the storage unit 150. The CDC verification setting file includes all clocks included in the source code from which the CDC verification information is extracted, the period (frequency) of each clock, the correlation between the clocks, and input / output terminals related to each clock. . These pieces of information are extracted from the clock system diagram and timing specifications as necessary, and then the CDC verification information is corrected again by the CDC verification tool and clarified for all clocks included in the source code. .
Note that the clock system diagram and timing specifications are created in advance in the upstream process, and source code for verification is created corresponding to these.

The metastability countermeasure unit 130 detects an asynchronous path that requires a metastability measure from the CDC verification information created by the CDC verification tool execution unit 110 and detects the source code recorded in the storage unit 150. The code is modified so that meta-stability measures are incorporated into the asynchronous path.
If no measures are taken for an asynchronous path, the path may cause a meta-stability state due to asynchronous clocks.

  The data format conversion unit 140 indicates a transmission clock, a reception clock, and a From / to path for each asynchronous path from the CDC verification setting file recorded in the storage unit 150 and the asynchronous path list included in the CDC verification information. Asynchronous path information is extracted and output from the CDC verification configuration file and asynchronous path information to the storage unit 150 as information indicating timing constraints in a format that can be read by each tool used in the downstream process. Configured to save. In other words, the information indicating the timing constraint is adjusted to the format of each tool by the data format conversion unit 140 to be a timing constraint file, so that an existing logic synthesis tool or layout such as “Synopsys Design Compiler” is used as it is. STA tools such as the tool “Synopsys PrimeTime” can be used.

  The storage unit 150 stores and holds in advance the CDC verification tool, source code, clock system diagram, timing specifications, and the like used in the above units, and also extracts and generates CDC verification information, CDC verification setting files, timings, etc. A constraint file is stored and held. In addition, information indicating timing constraints generated by the data format conversion unit 140 in response to various requests is provided.

  By configuring in this way, it is possible to obtain the semiconductor design support apparatus 100 that can give timing constraints correctly and without omission in the downstream process without depending on the designer.

  Next, the operation of the semiconductor design support apparatus 100 according to the embodiment will be described.

FIG. 2 is a flowchart showing an operation example of the semiconductor design support apparatus 100.
In FIG. 2, the process in which each unit automatically generates timing constraints from the CDC verification result will be described more specifically as item numbers 1 to 13 of the flow.

Item 1: When performing CDC verification for the first time, the CDC detection tool execution unit 110 first performs analysis using the CDC verification tool with only source code as input. The second and subsequent analyzes are also performed using the CDC verification setting file. As an analysis, the CDC detection tool execution unit 110 identifies all signals connected to the clock pins of the sequential circuit on the source code, regards the short-circuited signals as the same line, and uses the following as CDC verification information: 3 report is output.
-Report file (1): Clock line list and I / O terminal list setting template
-Report file (2): Undefined clock list (tool estimation)
-Report file (3): Asynchronous path list and meta-stability measures

  Item number 2: The clock clarification processing unit 120 proceeds to item number 4 only when the contents of the clock line list of the report file (1) are reflected in the CDC verification setting file. Therefore, when the CDC verification is performed for item No. 1 for the first time, the CDC verification setting file has not yet been created, and the process proceeds to item No. 3. When the setting file for CDC verification already exists, the process proceeds to item number 4 only when the contents of the clock line list of the report file (1) are reflected.

  No. 3: The clock clarification processing unit 120 refers to the clock line list setting template described in the report file (1) and compares it with the clock system diagram which is known information in the specification document. Transfer the list to the CDC verification setting file and return to item number 1.

Item number 4: The clock clarification processing unit 120 proceeds to item number 5 when the undefined clock list extracted by the tool is described in the report file (2). If the undefined clock list is not described, go to item 6.
Here, the undefined clock is an internally generated clock, a gated / multiplexed clock, or the like.

No. 5: The clock clarification processing unit 120 uses the transfer of No. 3 to convert the undefined clock in the report file (2) for CDC verification according to the clock setting format already described in the CDC verification setting file. Add to the setting file and return to No. 1. At this time, the undefined clock revealed by the automatic extraction may be confirmed later.
In this way, the clock clarification processing unit 120 explicitly defines an undefined clock such as an internally generated clock in the CDC verification setting file in the same manner as a pre-defined clock. Clocks that are omitted, forgotten, or not noticed at the time of extraction are accurately reflected.

  No. 6: The clock clarification processing unit 120, when the clock period of each clock is not described in the clock setting in the CDC verification setting file updated in No. 3 and No. 5, or between clocks If there is a frequency correlation and the relationship is not described, go to No. 7. If all of the above is written in the clock setting, go to item 8.

Item No. 7: The clock clarification processing unit 120 adds a period (frequency) to the clock setting from known information such as a clock system diagram and timing specifications according to the description format of the CDC verification setting file. Further, when there is a frequency correlation between clocks due to the circuit configuration exemplified below, the correlation (parent-child relationship) between the source clock and the destination clock is added to the CDC verification setting file.
・ Internally generated clock by PLL or frequency divider
・ Gated clock, multiplexed clock

  No. 8: The clock clarification processing unit 120 is set or has not been set in the input / output terminal in the CDC verification setting file updated in No. 3, No. 5, and No. 7. However, if the synchronous relationship with the clock is not set, go to No. 9. If all of the above are set without omission, go to No. 10.

  Item 9: The clock clarification processing unit 120 refers to the input / output terminal list setting template described in the report file (1), compares the input / output terminal list with the timing specifications, etc., and performs CDC verification. Post to the configuration file. After that, for each input / output terminal setting, an option is added to clearly indicate whether the signal is an asynchronous signal or a signal synchronized with the clock.

  No. 10: The metastability countermeasure unit 130 checks the asynchronous path list described in the report file (3) and the presence / absence of meta-stability countermeasures, and corrects any asynchronous path. If it has been reported that is not performed, the process proceeds to item number 11. If there is no description of the asynchronous path list, even if there is an asynchronous path, a report indicating that meta-stability measures are being taken correctly, such as by inserting a synchronizer, or a circuit that delivers a level signal If the source code does not need to be meta-stabilized as in the case where the meta-stability state does not propagate to the latter stage, the process proceeds to item 12.

  Item No. 11: The metastability countermeasure unit 130 performs circuit correction such as synchronizer insertion on the asynchronous path for which the meta-stability countermeasure is not properly performed, and returns to item No. 1.

  The CDC verification is completed at the time when the processing from No. 1 to No. 11 is completed.

Item number 12: The data format conversion unit 140 extracts the following content as an intermediate file from the result of the fixed CDC verification setting file and the report file (3) of the CDC verification information performed last, and the item number Move to 13.
・ Configuration file for CDC verification: All information
-Report file (3): Asynchronous path information (send clock, receive clock, from / to path)

Item number 13: The data format conversion unit 140 converts the constraint values of individual clocks from the known information into parameters (variables) for the generated intermediate file information, and then matches the input format of the downstream process tool. Then, the timing constraint file can be generated and output.
As an example of a method for generating a timing constraint file, the data format conversion unit 140 creates a command conversion table in advance because the CDC verification setting file is described as a command for the CDC verification tool. Perform format conversion in the order of reading with the tool. At this time, since the report file (3) is listed in an array, create a command table and a hierarchical path conversion table in advance, and apply restrictions between clock lines or restrictions between from / to paths The sequence to be used is extracted according to whether or not it is attached.
However, specific numerical values used for timing constraints do not appear as the automatically generated information other than the clock cycle. This is because the CDC verification tool does not use it. Therefore, the constraint value is parameterized (variable) and input based on the timing specification.

  Also, the timing constraint command format may differ depending on the type of downstream process tool.Therefore, when using multiple tools, it is possible to prepare multiple conversion tables, or to all multiple tools. A corresponding conversion table may be prepared.

  With the above processing, the timing constraint file automatically generated by the semiconductor design support apparatus 100 by performing CDC verification can be provided to the downstream process.

  Next, the designer uses the generated timing constraint file at the timing of each process and uses it as an input file for the downstream process (logic synthesis / layout / STA) tool.

  Next, FIG. 3 shows an example of a process for artificially creating timing constraints, and FIG. 4 shows an example of a process for automatically extracting and generating timing constraints. Both diagrams show a general process chart and each information generated and used in each process in a limited manner, and show the relationship between the information.

  In the example of the process for artificially creating timing constraints shown in FIG. 3, the designer creates a CDC verification setting file and STA timing constraints based on the clock system diagram and timing specifications created as basic specifications / detailed specifications. It will be. At this time, the source code coded after the specification formulation process is subjected to CDC verification by the CDC verification tool, and the clock system diagram and timing specifications are fed back and corrected while referring to the asynchronous circuit obtained as a result. Thereafter, a timing constraint (file) is created by the designer with reference to the corrected clock system diagram and timing specifications.

  The existing CDC verification tool analyzes all clock lines of the source code in order to detect an asynchronous circuit, and calculates the relationship between each clock line from the physical connection relationship and the difference between clock cycles. -Circuits that may fall into the stability state are extracted.

  In this method, since EDA (electronic design automation) tools that are different for CDC verification and STA are mostly used, compatibility between the two cannot be achieved. For this reason, both the CDC verification setting file and the STA timing constraint file are sequentially created.

  On the other hand, as described above, in this CDC verification method, the existing CDC verification is used, and as a result of the CDC verification, not only asynchronous circuit extraction but also a list of clock lines and a correlation between clock lines are verified by CDC verification. By outputting synchronous (asynchronous) settings between the input / output data terminal and the clock to the information (CDC verification setting file) that is output as information (report) and further for CDC verification, the first order from the input terminal The path from the circuit or the sequential circuit at the final stage to the output terminal is associated.

  This information can be used as necessary and sufficient information for creating timing constraints to be used in downstream processes. By using this information to automatically generate timing constraints in software, it is linked to existing CDC verification. In this way, a highly accurate timing constraint file can be created at the upstream process stage.

  Therefore, it is possible not only to eliminate description mistakes and omissions due to manual work, but also to reduce lead time due to feedback from downstream processes. In other words, by reducing the area of human work, the same result as human work when existing mistakes did not occur with limited user resources can be obtained immediately, and the upstream process and downstream process Linkage is enhanced and it can be an efficient development flow.

  Further, since the setting and result of CDC verification and timing constraints are linked as information, it is easy to centrally manage the source code → CDC verification (setting / result) → timing constraint as a development flow.

  Also, timing constraints are not created manually, but are automatically generated according to each tool used downstream using a conversion table, etc., which not only prevents mistakes and omissions in writing, but also helps designer skills. It is also possible to generate constraints without depending on them. In addition, it is possible to easily generate a timing constraint file that does not depend on the designer's skill by the work of replacing the conversion table for a new tool.

  Furthermore, since most of the work can be performed at the time of CDC verification, which is an upstream process, with regard to backtracking due to malfunctions and work feedback for improving accuracy, it is overwhelmingly shorter than the lead time required in the downstream process. (Small resources) is possible, and total development TAT (turn around time) can be shortened.

  Each part of the semiconductor design support apparatus may be realized by using a combination of hardware and software. In a form in which hardware and software are combined, a semiconductor design support program is expanded in the RAM, and each unit is realized as various means by operating hardware such as a control unit (CPU) based on the program. The program may be recorded on a storage medium and distributed. The program recorded on the recording medium is read into a memory via a wired, wireless, or recording medium itself, and operates a control unit or the like. Examples of the recording medium include an optical disk, a magnetic disk, a semiconductor memory device, and a hard disk.

  In other words, the information processing apparatus operating as the semiconductor design support apparatus is based on the semiconductor design support program developed in the RAM. The CDC verification means, the clock clarification means, the metastability countermeasure means It can be realized by operating the control unit as a data format conversion means or the like. Further, the semiconductor design support program may be divided as appropriate to provide individual means.

  As described above, according to the present invention, it is possible to provide a semiconductor design support apparatus that can provide an appropriate timing constraint in the downstream process after logic synthesis without depending on the designer by processing in the upstream process. .

  In addition, the specific configuration of the present invention is not limited to the above-described embodiment, and changes within a range not departing from the gist of the present invention are included in the present invention.

In addition, a part or all of the above-described embodiments can be described as follows. Note that the following supplementary notes do not limit the present invention.
[Appendix 1]
From the CDC verification results performed on the source code during the design of the electrical circuit that includes the asynchronous circuit and the known information determined in the specification development process used for coding the source code, everything contained in the source code Means for clarifying and collecting and acquiring as a CDC verification setting file,
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. A semiconductor design support apparatus for performing asynchronous verification, comprising: means for generating and outputting a constraint file.

[Appendix 2]
Based on an asynchronous path that may cause a meta-stability state in the verified source code included in the CDC verification result, a means for correcting so that a meta-stability measure is incorporated in the asynchronous path that has detected the source code. Have
The semiconductor design support according to the above-mentioned appendix, wherein information indicating an asynchronous path in which the source code is modified and a countermeasure is taken against the cause of occurrence of meta-stability state is reflected in the CDC verification setting file apparatus.

[Appendix 3]
Performs CDC verification on the source code, and from the source code, an asynchronous path list including a clock line list, a list of input / output terminals related to clocks, an estimated undefined clock list, and presence or absence of meta-stability measures CDC verification means for extracting the above as CDC verification information;
The CDC verification information obtained from the CDC verification means as the CDC verification result, the clock system diagram and the timing specification as the known information, all the clocks included in the source code, the period of each clock, and the clock Clarifying means for clarifying information indicating the correlation between the I / O and the input / output terminals related to each clock and generating as a CDC verification setting file,
Metastability countermeasure means for detecting an asynchronous path that is a cause of occurrence of a metastability state due to clock asynchronousness, and correcting the source code so that a metastability countermeasure is incorporated in the detected asynchronous path;
Asynchronous path information indicating a transmission clock, a reception clock, and a From / to path for each asynchronous path is extracted from the asynchronous path list included in the CDC verification information, and the asynchronous path information and the CDC verification setting file are extracted. And a data format conversion means for outputting the information indicating the timing constraint in accordance with a format that can be read by any of the logic synthesis tool, layout tool, and STA tool used in the downstream process. Semiconductor design support device described in the supplementary notes.

[Appendix 4]
The data format conversion means includes a clock constraint, an input / output timing constraint, and a format that can be read from the asynchronous path information and the CDC verification setting file for each of a plurality of tools used in a downstream process. The semiconductor design support apparatus according to the above supplementary note, wherein information indicating a plurality of timing constraints is output as an internal delay constraint.

[Appendix 5]
The clock clarification unit is configured to generate, based on the known information used for coding, each of the clocks generated on the basis of another clock generated in the semiconductor integrated circuit undefined by the CDC verification unit. The semiconductor design support apparatus as described in the above supplementary note, wherein the CDC verification setting file is generated by repeating the clarification processing together with the CDC verification means until the clock cycle or the correlation between the clocks can be clarified.

[Appendix 6]
The CDC verification is performed by using an existing CDC verification tool.

[Appendix 7]
The design tool used in the downstream process is an existing logic synthesis tool, layout tool, or STA tool.

[Appendix 8]
The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
CDC verification settings by clarifying all clocks included in the source code from the results of CDC verification performed on the source code and the known information determined in the specification development process used for coding the source code A program characterized by operating as a means for collecting and acquiring as a file.

[Appendix 9]
The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
Timing constraints from the clarified information for all clocks included in the source code and the input / output paths for each asynchronous path obtained from the CDC verification results to match the format readable by the design tool used in the downstream process A program that operates as means for automatically generating a timing constraint file by extracting predetermined information relating to the timing.

[Appendix 10]
The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
CDC verification is performed by clarifying all clocks included in the source code from the result of CDC verification performed on the source code and the known information determined in the specification development process used for coding the source code. Means to collect and acquire as a configuration file for
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. A program that operates as a means for generating and outputting a constraint file.

[Appendix 11]
Based on an asynchronous path that may cause a meta-stability state in the verified source code included in the CDC verification result, a means for correcting so that a meta-stability measure is incorporated in the asynchronous path that has detected the source code. Have
The program according to the above-mentioned supplementary note, wherein the CDC verification setting file reflects information indicating an asynchronous path in which the source code is corrected and a countermeasure is taken against a cause of occurrence of a meta-stability state.

[Appendix 12]
The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
Performs CDC verification on the source code, and from the source code, an asynchronous path list including a clock line list, a list of input / output terminals related to clocks, an estimated undefined clock list, and presence or absence of meta-stability measures CDC verification means for extracting the above as CDC verification information;
The CDC verification information obtained from the CDC verification means as the CDC verification result, the clock system diagram and the timing specification as the known information, all the clocks included in the source code, the period of each clock, and the clock Clarifying means for clarifying information indicating the correlation between the I / O and the input / output terminals related to each clock and generating as a CDC verification setting file,
Metastability countermeasure means for detecting an asynchronous path that is a cause of occurrence of a metastability state due to clock asynchronousness, and correcting the source code so that a metastability countermeasure is incorporated in the detected asynchronous path;
Asynchronous path information indicating a transmission clock, a reception clock, and a From / to path for each asynchronous path is extracted from the asynchronous path list included in the CDC verification information, and the asynchronous path information and the CDC verification setting file are extracted. And, as information indicating timing constraints, a program that operates as a data format conversion unit that outputs in accordance with a format that can be read by any of a logic synthesis tool, a layout tool, and a STA tool used in a downstream process .

[Appendix 13]
As the data format conversion means, from the asynchronous path information and the setting file for CDC verification, a clock constraint, an input / output timing constraint, The program according to the above supplementary note, wherein information indicating a plurality of timing constraints is output as an internal delay constraint.

[Appendix 14]
As the clock clarification means, each of the known information used for coding is individually obtained from a clock generated based on another clock generated in the semiconductor integrated circuit undefined by the CDC verification means. The program according to the above supplementary note, wherein the CDC verification setting file is generated by repeating the clarification processing together with the CDC verification means until the clock period or the correlation between the clocks can be clarified.

[Appendix 15]
The program according to the above supplementary note, wherein the CDC verification result uses a result obtained by using an existing CDC verification tool.

[Appendix 16]
The program according to the above-mentioned supplementary note, wherein information indicating timing constraints is output for an existing logic synthesis tool, layout tool, and STA tool as a design tool used in the downstream process.

[Appendix 17]
From the CDC verification results performed on the source code during the design of the electrical circuit that includes the asynchronous circuit and the known information determined in the specification development process used for coding the source code, everything contained in the source code Clarify the clock and collect and acquire it as a CDC verification configuration file.
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. A timing constraint generation method characterized by generating and outputting a constraint file.

[Appendix 18]
Performs CDC verification on the source code, and from the source code, an asynchronous path list including a clock line list, a list of input / output terminals related to clocks, an estimated undefined clock list, and presence or absence of meta-stability measures Are extracted as CDC verification information,
The CDC verification information obtained as a result of CDC verification, the clock system diagram and the timing specification as the known information, all the clocks included in the source code, the period of each clock, and the correlation between the clocks, , Clarification of information indicating input / output terminals related to individual clocks, and generation processing as a setting file for CDC verification,
Detects asynchronous paths that cause metastability status due to asynchronous clocks, and if there is a path that needs to be corrected, corrects so that metastability measures are incorporated into the asynchronous path that detected the source code. Together with the CDC verification information extraction process,
Asynchronous path information indicating a transmission clock, a reception clock, and a From / to path for each asynchronous path is extracted from the asynchronous path list included in the CDC verification information, and the asynchronous path information and the CDC verification setting file are extracted. The timing constraint generation method is characterized in that the timing constraint information can be output in a format that can be read by at least one of a logic synthesis tool, a layout tool, and a STA tool used in a downstream process.

[Appendix 19]
When designing a semiconductor integrated circuit including an asynchronous circuit, CDC verification is performed by an information processing device on a source code coded based on a specification determined in a specification development process,
The information processing device performs clarification processing on all clocks included in the source code from the CDC verification result that has been executed and the known information related to the specification determined in the specification formulation process used for coding the source code. Generate a configuration file for CDC verification,
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. Generate and output constraint file,
A design method of a semiconductor integrated circuit, wherein a design tool used in a downstream process reads a timing constraint file generated by the information processing apparatus, identifies a timing constraint of each clock, and performs asynchronous verification.

  The present invention can be used in a digital circuit design flow when developing a semiconductor integrated circuit. Therefore, the present invention can be applied to device development such as ASIC / PLD / FPGA / ASSP.

100 Semiconductor Design Support Device 110 CDC Detection Tool Execution Unit (CDC Verification Unit)
120 Clock clarification processing unit (clock clarification means)
130 Metastability Countermeasures Section (Metastability Countermeasures)
140 Data format converter (data format converter)
150 storage unit (storage means)

Claims (10)

From the result of CDC (Clock Domain Crossing) verification performed on the source code at the time of designing the electrical circuit including the asynchronous circuit and the known information determined in the specification development process used for coding the source code, the source Means for clarifying all the clocks included in the code and collecting and acquiring them as a setting file for CDC verification;
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. and means for generating and outputting a constraint file only contains,
As the clarification processing, the means for collecting and acquiring as a CDC verification setting file includes a clock line list, a clock input / output terminal list, an estimated undefined clock list, and meta stability obtained as the CDC verification result. Asynchronous path list including presence / absence of countermeasure, clock system diagram and timing specification as the known information, all clocks included in the source code, period of each clock, correlation between clocks, and individual clocks A semiconductor design support apparatus for performing asynchronous verification, characterized in that information indicating input / output terminals related to the data is clarified and generated as a CDC verification setting file . Based on an asynchronous path that may cause a meta-stability state in the verified source code included in the CDC verification result, a means for correcting so that a meta-stability measure is incorporated in the asynchronous path that has detected the source code. Have
2. The semiconductor design according to claim 1, wherein the CDC verification setting file reflects information indicating an asynchronous path in which the source code is corrected and a countermeasure is taken against a cause of occurrence of a meta-stability state. Support device. By performing CDC verification with respect to the source code, asynchronous path including from the source code, and a clock line list, and input-output terminal list relating to the clock, and an undefined clock list estimated, the presence of meta-stability measures and CDC verification means for extracting the list as the CDC verification information,
Clock clarification means for executing the clarification processing with reference to the CDC verification information obtained from the CDC verification means and the known information ;
Metastability countermeasure means for detecting an asynchronous path that is a cause of occurrence of a metastability state due to clock asynchronousness, and correcting the source code so that a metastability countermeasure is incorporated in the detected asynchronous path;
Asynchronous path information indicating a transmission clock, a reception clock, and a From / to path for each asynchronous path is extracted from the asynchronous path list included in the CDC verification information, and the asynchronous path information and the CDC verification setting file are extracted. Data format conversion means for outputting information in accordance with a format that can be read by any of the logic synthesis tool, layout tool, and STA (Static Timing Analysis) tool used in the downstream process as information indicating timing constraints. The semiconductor design support apparatus according to claim 2. The data format conversion means includes a clock constraint, an input / output timing constraint, and a format that can be read from the asynchronous path information and the CDC verification setting file for each of a plurality of tools used in a downstream process. 4. The semiconductor design support apparatus according to claim 3, wherein information indicating a plurality of timing constraints is output as an internal delay constraint. The clock clarification unit is configured to generate, based on the known information used for coding, each of the clocks generated on the basis of another clock generated in the semiconductor integrated circuit undefined by the CDC verification unit. The CDC verification setting file is generated by repeating the process of clarifying all clocks included in the source code together with the CDC verification unit until the clock period or the correlation between clocks can be clarified. 5. The semiconductor design support apparatus according to claim 3 or 4, wherein:   The semiconductor design support apparatus according to claim 1, wherein the CDC verification is performed using an existing CDC verification tool. The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
The CDC verification result including the clock line list, the input / output terminal list related to the clock, the estimated undefined clock list, and the asynchronous path list including the presence / absence of the meta-stability countermeasure of the source code to be verified and the source code Referring to the known information including a clock system diagram and timing specifications, for the source code, all clock, the period of each clock included, correlation between clock, and information indicating the input and output terminals according to individual clock A program characterized by being operated as means for extracting and collecting and acquiring a CDC verification setting file. The control unit of the information processing device that performs asynchronous verification of the electrical circuit that contains the asynchronous circuit,
Asynchronous path for all clocks included in the source code to be verified , including the clock line list, the list of input / output terminals related to the clock, the estimated undefined clock list, and the presence or absence of meta-stability measures Based on the CDC verification result including the list and the known information including the clock system diagram and timing specification of the source code, all the clocks included in the source code, the period of each clock, the correlation between the clocks, and the individual Predetermined timing constraints to match the format that can be read by the design tool used in the downstream process from the information that clarifies the input / output terminals related to the clock and the input / output paths for each asynchronous path obtained from the CDC verification results As a means to automatically extract timing information and generate timing constraint files Program characterized thereby. Performs CDC verification on the source code, and from the source code, an asynchronous path list including a clock line list, a list of input / output terminals related to clocks, an estimated undefined clock list, and presence or absence of meta-stability measures Are extracted as CDC verification information,
Said CDC verification information extracted as CDC verification results, referring to the clock system diagram and timing specifications as known information, all the clocks included in the source code, and the period of each clock, and the correlation between the clocks , Clarification of information indicating input / output terminals related to individual clocks, and generation processing as a setting file for CDC verification,
Detects asynchronous paths that cause metastability status due to asynchronous clocks, and if there is a path that needs to be corrected, corrects so that metastability measures are incorporated into the asynchronous path that detected the source code. Together with the CDC verification information extraction process,
From an asynchronous path list included in the CDC verification information, is extracted handles asynchronous path information showing a transmitting clock and the receiving clock and the From /-to-pass for each asynchronous path, setting the CDC and verification the asynchronous path information According to an information processing apparatus characterized in that information indicating timing constraints can be output from a file in a format that can be read by at least one of a logic synthesis tool, a layout tool, and a STA tool used in a downstream process. Timing constraint generation method. When designing a semiconductor integrated circuit including an asynchronous circuit, the information processing device performs CDC verification on the source code coded based on the specification determined in the specification development process , and the clock line list and the input / output terminals related to the clock As a CDC verification result, a list, an estimated undefined clock list, and an asynchronous path list including presence / absence of meta-stability countermeasures are acquired .
By the information processing apparatus, reference the known information including the acquired CDC verification result and the clock system diagram and timing specification of the source code for the source code, all clock, the period of each clock included, inter-clock To generate a CDC verification setting file by extracting information indicating the correlation and the input / output terminals related to each clock ,
Timing is determined by extracting predetermined information from the CDC verification setting file and the input / output path for each asynchronous path obtained from the CDC verification result so as to match the format readable by the design tool used in the downstream process. Generate and output constraint file,
Reads the timing constraint file design tool is generated by said information processing apparatus used in the downstream process, identify the timing constraints of each clock, a semiconductor integrated circuit design method according to an information processing apparatus and performs asynchronous validation .

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