JP5727358B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a memory circuit and a self-test circuit for testing the memory circuit.

  In many cases, a semiconductor device including a memory circuit incorporates a self test circuit (MBIST circuit, Memory Built-In Self-Test circuit) for testing the memory circuit.

  Patent Document 1 describes a semiconductor device on which a RAM and a BIST circuit for repairing the RAM are mounted. FIG. 17 is a circuit diagram showing a configuration of the semiconductor device described in Patent Document 1. In FIG. Referring to FIG. 17, in the comparison circuit 140 included in the BIST circuit, the read data of RAM and the expected value data are compared by XOR (exclusive OR) gates G1 and G2, and if there is a failure, XOR The output of at least one of the circuits G1 and G2 is “1”. The outputs of the XOR gates G1 and G2 are converted into a 1-bit error signal by an OR (logical sum) gate G20. The error signal becomes input data of the flip-flop FF20 via the OR gate G21 and the selector.

  When “1” is taken into the flip-flop FF20, the determination result of the test of the semiconductor device is FAIL (defective product). In the semiconductor device described in Patent Document 1 (FIG. 17), once “1” is taken into the flip-flop FF20 (that is, a state indicating FAIL), “1” is held by the OR gate G21. The

  Although not explicitly shown in the circuit diagram of FIG. 17, a comparison enable signal for controlling comparison / non-comparison is supplied from the pattern generator 120 to the comparison circuit 140. Whether or not data is taken into the flip-flop FF20 is controlled by the comparison enable signal.

  FIG. 18 is a block diagram schematically showing the configuration of the semiconductor device described in Patent Document 1. In FIG. Referring to FIG. 18, the semiconductor device includes a RAM 112 and a BIST (Built-In Self-Test) circuit for testing the RAM 112. The BIST circuit includes a test pattern generation circuit 111 (Pattern Generator) 111, comparison circuits U0 to U3, an OR gate G20, an AND gate 20, an OR gate G21, and a flip-flop FF20. The comparison circuits U0 to U3 each have an XOR gate G1.

  The test pattern generation circuit 111 generates a RAM test pattern and an expected value EXPDATA. The fail flag holding circuit (OR gate G21, flip-flop F20 in FIG. 18) holds the error signal ERR detected by the comparison circuit (XOR gate G1, OR gate G20, and AND gate A20 in FIG. 18).

  FIG. 19 is a waveform showing the operation of the semiconductor device of FIG. FIG. 19 shows a case where continuous reading is performed for four addresses a (0) to a (3). If any one of the error signals ERR (r (0) to r (3)) becomes 1, the file flag signal FAILFLAG is finally set to 1 by the OR gate G21 (f (3) = 1). Therefore, according to the semiconductor device of FIG. 18, a failure of the RAM 112 can be detected.

  As described above, the BIST circuit described in Patent Literature 1 compares the data read from the RAM 112 with the expected value generated by the test pattern generation circuit 111 (XOR gate G1, OR gate G20, The comparison circuit compares the bit included in the bit string of the data with the bit included in the bit string of the expected value. When the fail flag holding circuit (OR gate G21, flip-flop F20) detects the first mismatch, it holds a flag indicating the mismatch. According to such a BIST circuit, it is possible to detect that at least one of the bits does not match between the bit string of the data and the bit string of the expected value.

  As a related technique, Patent Document 2 describes a semiconductor device having a RAM failure analysis function.

Japanese Patent Laying-Open No. 2006-236551 (FIG. 2) JP 2001-035196 A

  The following analysis was made by the present inventors.

  In the semiconductor device described in Patent Document 1, since the self-test circuit (BIST circuit) itself is on the same semiconductor device as the memory circuit (RAM), an erroneous determination occurs due to test conditions such as power supply voltage and temperature conditions. There is a fear. This misjudgment makes it difficult to distinguish between a non-defective product and a defective product of a semiconductor device provided with a memory circuit.

  For example, if the BIST circuit itself has a delay (exceeding a cycle, cycle shift) more than expected, the semiconductor device described in Patent Document 1 (FIGS. 17 and 18) has an abnormal RAM access time (cycles). There is a risk that it may not be possible to detect a cycle deviation).

  FIG. 20 is a timing chart for explaining a case where such an erroneous determination occurs in the semiconductor device described in Patent Document 1.

  For example, when the expected value EXPDATA of the BIST circuit reaches the XOR gate G1 over the cycle and the comparison enable signal COMPEN reaches the AND gate A20 over the cycle during the RAM test under the low voltage condition, the thick line in FIG. As shown by solid arrows.

  Under this condition, when the access time of the RAM 112 exceeds the cycle, a thick broken line arrow appears. At this time, the fail flag signal FAILFLAG operates with a delay of one cycle compared to the normal operation. When the function of the RAM 112 is normal, the same value (f (3) = 0) is finally left as the fail flag signal FAILFLAG regardless of whether the access time cycle is exceeded or not. Therefore, under the conditions as shown in FIG. 20, an abnormality in the access time of the RAM 112 cannot be detected, resulting in an erroneous determination.

  As described above, according to the BIST circuit described in Patent Document 1, the reliability of the test result of the RAM 112 is low, and it may be difficult to determine manufacturing test conditions (voltage, temperature, etc.).

  As described above, the semiconductor device described in Patent Document 1 does not take measures against erroneous determination due to signal delay due to voltage drop or the like. That is, even if there is a failure (cycle shift failure) in which the delay of the output data signal from the RAM 112 exceeds the determination point (for example, the rising edge of the operation clock), the comparison enable signal and expected value signal generated by the self-test circuit Is delayed by one cycle, the determination result is a non-defective product (PASS), which is erroneously determined.

  Therefore, according to the semiconductor device described in Patent Document 1, a state in which read data of RAM, expected value data, and comparison enable signal are delayed at the same time cannot be determined as a defective product (FAIL).

  Generally, in a semiconductor device, an operating frequency is defined as a product specification. As an example, assume a product specification in which the power supply voltage is 2 V and the operating frequency is 100 MHz. 100 MHz corresponds to 10 nsec in clock cycle time. If the delay of the read data of the RAM is 11 nsec, it is a defective product. However, according to the comparison circuit 140 of the semiconductor device described in Patent Document 1, if the delay of the expected value data and the comparison enable signal is 11 nsec (over cycle, cycle shift), the FF 20 does not capture “1”. Therefore, it is determined that the product is a non-defective product (PASS). That is, there is a risk of erroneous determination regarding the delay time delay of the output data of the RAM.

  Therefore, it is an object to be able to detect a clock cycle shift in the output data signal output from the memory circuit to the self test circuit, or the comparison enable signal or the expected value signal in the self test circuit.

A semiconductor device according to one aspect of the present invention includes:
A semiconductor device comprising a memory circuit and a self-test circuit for testing the memory circuit,
The self-test circuit outputs a bit value included in a bit string obtained by inverting a part of bit values included in an expected value bit string in each clock cycle of an output data signal output from the memory circuit in each clock cycle. Test pattern generation means for generating a comparison enable signal that enables comparison of the output data signal and the pseudo expected value signal in each clock cycle,
The output data signal output from the memory circuit, and the pseudo expected value signal and the comparison enable signal output from the test pattern generation means are received, and each of the periods within a period in which the comparison enable signal is in an active state A comparison means for comparing the output data signal with the pseudo expectation value signal in a clock cycle and generating a comparison result signal representing a comparison result;
Error holding means for receiving the comparison result signal from the comparison means and holding a bit value in each clock cycle of the received comparison result signal.

  According to the semiconductor device of the present invention, it is possible to detect a clock cycle shift in the output data signal output from the memory circuit to the self test circuit, or the comparison enable signal or the expected value signal in the self test circuit.

It is a block diagram which shows the structure of the semiconductor device which concerns on this invention as an example. FIG. 6 is a timing chart showing an example of the operation of the semiconductor device according to the present invention. It is a block diagram which shows the structure of the semiconductor device which concerns on this invention as an example. It is a block diagram which shows the structure of the semiconductor device which concerns on this invention as an example. 1 is a block diagram showing an example of a configuration of a semiconductor device according to a first embodiment. 1 is a block diagram illustrating an example of a configuration of a holding circuit in a semiconductor device according to a first embodiment. FIG. 6 is a timing diagram illustrating an operation of the semiconductor device according to the first embodiment as an example. FIG. 6 is a timing diagram illustrating an operation of the semiconductor device according to the first embodiment as an example. It is a block diagram which shows the structure of the semiconductor device which concerns on 2nd Embodiment as an example. FIG. 10 is a timing diagram illustrating an operation of the semiconductor device according to the second embodiment as an example. FIG. 10 is a timing diagram illustrating an operation of the semiconductor device according to the second embodiment as an example. It is a block diagram which shows the structure of the semiconductor device which concerns on 3rd Embodiment as an example. FIG. 9 is a timing diagram illustrating an operation of a semiconductor device according to a third embodiment as an example. FIG. 9 is a timing diagram illustrating an operation of a semiconductor device according to a third embodiment as an example. It is a block diagram which shows the structure of the semiconductor device which concerns on 4th Embodiment as an example. It is a block diagram which shows the structure of the semiconductor device which concerns on 4th Embodiment as an example. 10 is a block diagram illustrating a configuration of a semiconductor device described in Patent Document 1. FIG. 10 is a block diagram schematically showing a configuration of a semiconductor device described in Patent Document 1. FIG. 10 is a timing chart showing an operation of the semiconductor device described in Patent Document 1. FIG. 10 is a timing chart showing an operation of the semiconductor device described in Patent Document 1. FIG.

  First, the outline of the present invention will be described. Note that the reference numerals of the drawings attached to this summary are merely examples for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device according to the present invention. Referring to FIG. 1, the semiconductor device includes a memory circuit (20) and a self-test circuit. The self-test circuit includes a test pattern generating means (11), a comparing means (12), and an error holding means (13). The test pattern generation means (11) generates a pseudo expected value signal and a comparison enable signal. The “pseudo-expected value signal” is a bit value included in a bit string obtained by inverting a part of bit values included in an expected value bit string with respect to a bit value in each clock cycle of the output data signal output from the memory circuit (20). Take at each clock cycle. The comparison enable signal enables comparison of the output data signal and the pseudo expected value signal in each clock cycle. The comparison means (12) receives the output data signal output from the memory circuit (20) and the pseudo expected value signal and the comparison enable signal output from the test pattern generation means (11), and the comparison enable signal is activated. The output data signal is compared with the pseudo-expected value signal in each clock cycle within the state period, and a comparison result signal representing the comparison result is generated. The error holding means (13) receives the comparison result signal from the comparison means (12) and holds the bit value in each clock cycle of the received comparison result signal (development mode 1). In the semiconductor device, for example, a single or a plurality of semiconductor chips are sealed in a single package with a resin or the like, and are mounted on a wiring board together with other electronic components. The memory circuit and the logic circuit may be provided on the same semiconductor chip in a single package, or may be provided on different chips.

  The comparison means (12) may have a comparator (CMP1) and an AND gate (AND1). The comparator (CMP1) obtains an exclusive OR between the output data signal and the pseudo expected value signal. The AND gate (AND1) generates a logical product between the exclusive OR output from the comparator (CMP1) and the comparison enable signal as a comparison result signal (deployment mode 2).

  Further, the error holding means (13) may be a shift register that holds a bit value in each clock cycle of the comparison result signal (development mode 3).

  FIG. 2 is a timing chart showing an example of the operation of the semiconductor device shown in FIG. In FIG. 2, the memory circuit 20 is a RAM, and the error holding means (13) is a shift register. As shown in FIG. 2, the test pattern generation means (11) generates a pseudo expectation value signal that intentionally reverses the expectation value of the RAM output data. That is, the test pattern generation means (11) generates a pseudo expectation value signal as a test pattern in which the output of the comparison means (12) changes (becomes a unique bit string including changes from 0 to 1, 1 to 0). To do. In the part indicated by the thick broken line in FIG. 2, the pseudo expected value signal takes a value obtained by inverting the expected value of the RAM output data signal. The shift register acquires the output of the comparison means (12) every clock cycle.

  At this time, if both the signal in the self-test circuit (comparison enable signal, pseudo-expected value signal) and the signal received from the RAM by the self-test circuit (RAM output data signal) cause a cycle shift at the same time, The acquired bit string is shifted by 1 bit.

  Specifically, according to the test pattern shown in FIG. 2, when there is a cycle shift at the timing when the shift register holds “01010001010000000” when there is no cycle shift, the shift register holds “00101001010000”. Will do.

  Therefore, according to the semiconductor device of the present invention, it is possible to detect that a cycle shift (in this case, simultaneous cycle shift) has occurred. Note that the test pattern generation means (11) is an output data signal output from the memory circuit (20) to the self test circuit, and any combination of the three signals of the comparison enable signal and the expected value signal in the self test circuit. It is preferable to generate a test pattern that can detect a cycle shift.

  In the semiconductor device according to the present invention, the test pattern generating means (11) intentionally reverses the expected value to generate a pattern in which the comparison result for each clock cycle changes from 0 to 1 and from 1 to 0. In addition, a shift register for acquiring the comparison result for each cycle is provided, and the shift operation / holding operation is controlled by the test pattern generation circuit (11).

  According to the semiconductor device of the present invention, unlike the semiconductor device described in Patent Document 1, it is possible to detect that a cycle shift has occurred. More specifically, the determination result for each clock cycle generated by the comparison means (12) is taken into an error holding means (13) (for example, a shift register) in which a delay fault is unlikely to occur, thereby detecting a cycle shift.

  The test pattern generation means (11) generates a pattern in which 0 and 1 are mixed in the fail determination result. The fail determination result “1” is realized by intentionally inverting the expected value. By fetching the fail determination result into the shift register and collating the information stored in the shift register with the expected bit string, the RAM test including the test of the self test circuit itself can be performed.

  According to the semiconductor device of the present invention, at least the shift register itself operates normally (that is, there is no clock cycle shift), the clock cycle shift of other parts of the self-test circuit and the clock cycle of the read access of the RAM. Deviation can be detected, and a highly reliable RAM test can be performed.

  As described above, when the MBIST circuit is mounted on the same chip for testing an internal RAM such as SoC, the semiconductor device described in Patent Document 1 may cause an erroneous determination due to voltage, temperature conditions, and the like. . That is, even if the RAM access time exceeds the system clock cycle, it may be determined as PASS. At this time, it becomes difficult to select good and defective semiconductor devices.

  However, according to the semiconductor device of the present invention, the output data signal output from the memory circuit (20) (for example, RAM), and the comparison enable signal and the expected value signal output from the test pattern generation means (11). When a cycle shift occurs in at least one of the signals, it is possible to detect this.

  FIG. 3 is a block diagram showing a configuration of a modification of the semiconductor device of FIG. Referring to FIG. 3, the semiconductor device further includes flag holding means (14) for holding failure information. 3 has a function of suppressing the hold function of the flag holding means (14) and operating as a pipeline register.

  That is, the semiconductor device of FIG. 3 includes flag holding means (14) that detects mismatch information in the comparison result for each cycle and holds it as flag information, and functions as a pipeline register while suppressing the flag holding function. Have Further, the error holding means (13) (for example, shift register) acquires the output of the flag holding means (14) every cycle.

  Specifically, referring to FIG. 3, the flag holding means (14) receives the hold enable signal output from the test pattern generating means (11) and the comparison result signal output from the comparing means (12). When the hold enable signal is in the active state, the bit value indicating whether or not the comparison result signal has changed is held. In other cases, the error holding means (13) without holding the comparison result signal. (Deployment form 4).

  The flag holding means (14) may include a flip-flop (FF2), an AND gate (AND2), and an OR gate (OR2). The AND gate (AND2) generates a logical product of the hold enable signal (HOLDEN) and the output signal of the flip-flop (FF2). The OR gate (OR2) generates a logical sum of the comparison result signal and the output signal of the AND gate (AND2). The flip-flop (FF2) latches the output signal of the OR gate (deployment form 5).

  As described above, the semiconductor device shown in FIG. 3 is a semiconductor integrated device including a memory circuit (for example, RAM) and a self-test circuit for testing the memory circuit, and the self-test circuit receives a fail determination signal for each test clock cycle. Is stored as flag information (failure presence / absence information). Here, the flag holding circuit (14) has a register circuit (for example, flip-flop FF2). The flag holding circuit (14) has a function of suppressing the holding function and operating the register circuit (FF2) as a pipeline register for a fail determination signal. Further, the self-test circuit includes a test pattern generation means (11). The test pattern generation means (11) generates a test pattern so as to include a state in which the fail determination signal changes from “0 to 1” and “1 to 0”. The self-test circuit includes error holding means (13) (for example, a serial shift register) for storing a fail determination signal output from the register (pipeline register). Here, switching between the shift operation and the holding operation of the serial shift register is controlled by the test pattern generating means (11).

  According to the semiconductor device shown in FIG. 3, the failure of the memory circuit is detected by activating the hold enable signal and outputting the expected value of the output data of the memory circuit (20) as the pseudo expected value signal. be able to. On the other hand, by deactivating the hold enable signal and outputting a signal obtained by inverting a part of the expected value of the output data of the memory circuit (20) as the pseudo expected value signal, the output data signal, the pseudo expected value It is possible to detect that a cycle shift has occurred in at least one of the signal and the comparison enable signal. That is, according to the semiconductor device of FIG. 3, it is possible to realize both the test of the memory circuit (20) and the detection of the cycle shift.

  FIG. 4 is a block diagram showing a configuration of a further modification of the semiconductor device shown in FIG. According to the semiconductor device shown in FIG. 4, the error holding means (13) (for example, shift register) can be shared by a plurality of memory circuits (20a, 20b) (for example, RAM).

  In order to share the error holding means (13) among the plurality of memory circuits (20a, 20b), an OR gate (OR3) is provided at the serial input of the error holding means (13).

  Referring to FIG. 4, the semiconductor device includes a first comparison unit (12a), a second comparison unit (12b), a first flag holding unit (14a), a second flag holding unit (14b), and An OR gate (OR3) is provided. The first comparison means (12a) includes a first output data signal output from the first memory circuit (20a), a pseudo expected value signal and a comparison enable signal output from the test pattern generation means (11). And the first output data signal and the pseudo expectation value signal are compared in each clock cycle within the period in which the comparison enable signal is active, and a first comparison result signal representing the comparison result is generated. On the other hand, the second comparing means (12b) includes the second output data signal output from the second memory circuit (20b), the pseudo expected value signal output from the test pattern generating means (11), and the comparison. The enable signal is received, the second output data signal is compared with the pseudo expectation value signal in each clock cycle within the period in which the comparison enable signal is active, and a second comparison result signal representing the comparison result is generated. . The first flag holding means (14a) receives the hold enable signal (HOLDEN) output from the test pattern generation means (11) and the first comparison result signal output from the first comparison means (12a). When the hold enable signal (HOLDEN) is in an active state, the bit value indicating whether or not the first comparison result signal has changed is held, the held bit value is output, and otherwise Outputs the first comparison result signal as it is. On the other hand, the second flag holding means (14b) receives the hold enable signal (HOLDEN) and the second comparison result signal output from the second comparison means (12b), and receives the hold enable signal (HOLDEN). Is in the active state, the bit value indicating whether or not the second comparison result signal has changed is held and the held bit value is output. In other cases, the second comparison result signal is Output as is. The OR gate (OR3) obtains a logical sum of the output signal of the first flag holding means (14a) and the output signal of the second flag holding means (14b) and outputs the logical sum to the error holding means (13). Form 6).

  The first comparison means (12a) includes a comparator (CMP1a) that obtains an exclusive OR between the first output data signal and the pseudo expected value signal, and the obtained exclusive OR and the comparison enable signal. An AND gate (AND1a) that generates a logical product between them as a first comparison result signal may be included. Similarly, the second comparison means (12b) includes a comparator (CMP1b) that obtains an exclusive OR between the second output data signal and the pseudo expected value signal, and the obtained exclusive OR and comparison enable signal. And an AND gate (AND1b) that generates a logical product between the two as a second comparison result signal (expanded form 7).

  Further, the first flag holding means (14a) may include a first flip-flop (F2a), a first AND gate (AND2a), and a first OR gate (OR2a). The first AND gate (AND2a) generates a logical product of the hold enable signal (HOLDEN) and the output signal of the first flip-flop (FF2a). The first OR gate (OR2a) generates a logical sum of the first comparison result signal and the output signal of the first AND gate (AND2a). The first flip-flop (FF2a) latches the signal output from the first OR gate (OR2a). Similarly, the second flag holding means (14b) may include a second flip-flop (FF2b), a second AND gate (AND2b), and a second OR gate (OR2b). The second AND gate (AND2b) generates a logical product of the hold enable signal (HOLDEN) and the output signal of the second flip-flop (FF2b). The second OR gate (OR2b) generates a logical sum of the second comparison result signal and the output signal of the second AND gate (AND2b). The second flip-flop (FF2b) latches the signal output from the second OR gate (OR2b) (deployment mode 8).

  In the semiconductor device shown in FIG. 4, the flag holding means (14a, 14b) holds a fail flag for each memory circuit (for example, RAM). According to such a semiconductor device, it is possible to prevent an increase in the area of the self-test circuit by sharing the error holding means (13) by the plurality of memory circuits (20a, 20b).

  Referring to FIG. 5, the comparison means (12) in the semiconductor device of FIG. 1 is connected to the output data signal output from each data output terminal (Dout [0] to Dout [3]) of the memory circuit (for example, RAM 40). A plurality of XOR gates (G1) for obtaining an exclusive OR with the expected value signal (EXPDATA), an OR gate (G20) for obtaining a logical sum of output signals of the plurality of XOR gates (G1), and an OR gate (G20) And an AND gate (A20) for obtaining a logical product of the output signal and the comparison enable signal and outputting the result as the comparison result signal (development mode 9).

  Referring to FIG. 9, the comparison means (12) in the semiconductor device of FIG. 1 may include a plurality of comparison / flag holding circuits (V0 to V3). The comparison / flag holding circuits (V0 to V3) are respectively output data signals output from the data output terminals (Dout [0] to Dout [3]) of the memory circuit (for example, the RAM 40) and the pseudo expected value signal. An XOR gate (G1) for obtaining an exclusive OR, an AND gate (A30) for obtaining a logical product of the output signal of the XOR gate (G1) and the comparison enable signal (COMPEN), and an output from the test pattern generation circuit (31) When the hold enable signal (HOLDEN) and the output signal of the AND gate (A30) are received and the hold enable signal (HOLDEN) is in an active state, a bit value indicating whether or not the output signal has changed is Hold and output the held bit value, otherwise output without holding the output signal That flag holding means (AND gates A31, OR gate G31, the flip-flop FF30) and may have a. At this time, the logical sum of the output signals of the respective flag holding means of the comparison / flag holding circuit (V0 to V3) is used as the comparison result signal (development mode 10).

  Referring to FIG. 12, the semiconductor device includes an OR gate (G20) for obtaining a logical sum of signals output from the respective flag holding means of the comparison / flag holding circuit (V0 to V3), and a test pattern generating circuit (32). When the hold enable signal (HOLDEN2) and the output signal of the OR gate (G20) received from the output signal are received and the hold enable signal (HOLDEN2) is in an active state, a bit indicating whether or not the output signal has changed Flag holding means for holding the value and outputting the held bit value as the comparison result signal, otherwise outputting the comparison result signal without holding the output signal (AND gate A21, OR A gate G21 and a flip-flop FF20) (deployment form 11).

  Hereinafter, semiconductor devices according to first to fourth embodiments will be described with reference to the drawings.

<Embodiment 1>
The semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 5 is a block diagram showing an example of the configuration of the semiconductor device of this embodiment. Referring to FIG. 5, the semiconductor device includes a RAM 40 and a self test circuit for testing the RAM 40. The self-test circuit includes a test pattern generation circuit 31, comparison circuits U0 to U3, an OR gate G20, AND gates A20 and A21, an OR gate G21, a flip-flop FF20, and a shift register 33.

  Each of the comparison circuits U0 to U3 includes an XOR gate G1. The XOR gate obtains an exclusive OR of the output data signal DO [#] output from each data output terminal (Dout [0] to Dout [3]) of the RAM 40 and the pseudo expected value signal EXP [#]. The OR gate G20 calculates the logical sum of the output signals of the XOR gates G1 of the comparison circuits U0 to U3. The AND gate A20 calculates a logical product of the OR gate G20 and the comparison enable signal COMPEN.

  The AND gate A21 generates a logical product of the hold enable signal HOLDEN and the output signal of the flip-flop FF20. The OR gate OR21 generates a logical sum of the output signal of the AND gate A20 and the output signal of the AND gate A21. The flip-flop FF20 latches the output signal of the OR gate OR21.

  The shift register 33 holds the output signal from the flip-flop FF20.

  In the semiconductor device of this embodiment, an AND gate A21 is provided so that the holding function of the fail flag signal FAILFLAG output from the OR gate G21 can be controlled. The test pattern generation circuit 31 generates a hold enable signal for controlling this holding function. A hold enable signal HOLDEN output from the test pattern generation circuit 31 is connected to the AND gate A21.

  In the semiconductor device of this embodiment, the shift register 33 is provided as an error information acquisition circuit for capturing the fail flag signal FAILFLAG. The test pattern generation circuit 31 generates a shift enable signal CAPEN that controls capture of the fail flag signal FAILFLAG. A shift enable signal CAPEN output from the test pattern generation circuit 31 is connected to the shift register 33.

  FIG. 6 is a block diagram illustrating the configuration of the shift register 33 as an example. As an example, the shift register 33 may be a shift register with enable control as shown in FIG. Referring to FIG. 6, the shift register 33 includes registers SR [0] to SR [13] that are connected to each other so that the output signal of the previous-stage register is used as the input signal of the subsequent-stage register. Here, as an example, the number of shift register stages is 14, but the number of shift register stages is not limited thereto.

  Each of the registers SR [0] to SR [13] includes a selector SEL80 and a flip-flop FF80. The selector SEL80 selects the data signal D and outputs it to the flip-flop FF80 when the shift enable signal EN is 1, and outputs the output signal Q of the flip-flop FF80 when the shift enable signal EN is 0. Select and output to flip-flop FF80. The flip-flop FF80 latches the output signal of the selector SEL80 according to the clock signal CLK.

  The result of the cycle shift test is shifted in and stored in the shift register 33 for each cycle from the shift data input terminal SI when the shift enable signal is EN = 1. The test result is serially output from the shift data output terminal SO at the end of the test. At this time, the clock signal CLK may be operated at a low speed (large cycle time).

  The semiconductor device of this embodiment performs the same operation as the semiconductor device described in Patent Document 1 (FIG. 18) when the hold enable signal is HOLDEN = 1. Therefore, when the hold enable signal is HOLDEN = 1, the RAM 40 can be tested, but the cycle shift of the signals (output data signal from RAM 40, expected value signal, comparison enable signal) cannot be detected ( (Refer FIG. 19, FIG. 20).

  On the other hand, in the semiconductor device of this embodiment, when the hold enable signal is HOLDEN = 0, the cycle shift can be detected as described later, but the RAM 40 cannot be tested.

  That is, according to the semiconductor device of the present embodiment, the RAM 40 is used by combining the cycle shift test performed when the hold enable signal is HOLDEN = 0 and the RAM test performed when the hold enable signal is HOLDEN = 1. In addition, a highly reliable test including a self-test circuit can be performed.

  FIG. 7 is a timing chart at the time of normal operation of the semiconductor device of the present embodiment (when there is no signal clock cycle shift). In FIG. 7, “d” and “p” are mutually inverted data. Referring to FIG. 7, the test pattern generation circuit 31 generates a pseudo expected value signal EXPDATA obtained by inverting some bits of the expected value of the output data signal Dout output from the RAM 40.

  Since the state of the output data signal DO from the RAM 40 is “d” and the state of the pseudo expected value signal EXP is “p” at the time of the rising edge of the clock signal CLK at the beginning of the fourth cycle, the two do not match. It becomes. However, since the AND gate A20 has received the inactive comparison enable signal COMPEN at this time, it outputs a low level error signal ERR.

  Next, at the time of the rising edge of the clock signal CLK at the start of the fifth cycle, the state of the output data signal DO from the RAM 40 is “d”, and the state of the pseudo expected value signal EXP is “p”. Both are inconsistent. At this time, the AND gate A20 outputs the high-level error signal ERR because it receives the comparison enable signal COMPEN in the active state.

  Next, at the time of the rising edge of the clock signal CLK at the beginning of the sixth cycle, the state of the output data signal DO from the RAM 40 is “d”, and the state of the pseudo expected value signal EXP is “p”. Both are inconsistent. However, since the AND gate A20 has received the inactive comparison enable signal COMPEN at this time, it outputs a low level error signal ERR.

  Next, at the time of the rising edge of the clock signal CLK at the beginning of the seventh cycle, the state of the output data signal DO from the RAM 40 is “d”, and the state of the pseudo expected value signal EXP is “p”. Both are inconsistent. At this time, the AND gate A20 outputs the high-level error signal ERR because it receives the comparison enable signal COMPEN in the active state.

  Next, at the time of the rising edge of the clock signal CLK at the beginning of the eighth cycle, the state of the output data signal DO from the RAM 40 is “d”, and the state of the pseudo expected value signal EXP is “d”. Both agree. At this time, the AND gate A20 outputs a low level error signal ERR. Similarly, the comparison between the output data signal DO from the RAM 40 and the pseudo expected value signal EXP from the test pattern generation circuit 31 is performed during the period in which the comparison enable signal COMPEN is in the active state.

  Since the hold enable signal is HOLDEN = 0, the AND gate A21 always outputs 0, and the OR gate G21 outputs the error signal ERR output from the AND gate A20 to the flip-flop FF20 as it is. The flip-flop FF20 delays the signal received from the OR gate G21 by one cycle and outputs it to the shift register 33.

  Finally, the shift register 33 holds “01010010000000” as the values s [0] to s [13] in the period of the clock cycle 18.

  On the other hand, FIG. 8 is a timing chart at the time of an abnormal operation of the semiconductor device of the present embodiment (when there is a signal clock cycle shift). FIG. 8 shows an example in which the output data signal DO from the RAM 40 causes a cycle shift (thick dashed arrow in FIG. 8), and at the same time, the pseudo expected value signal EXPDATA and the comparison enable signal COMPEN also shift in cycle (thick solid arrow in FIG. 8). ) Is a timing diagram when the problem occurs.

  The output signal of the AND gate A20 in this case is a signal delayed by one clock cycle as compared with the case where there is no clock cycle shift (FIG. 7). Finally, the shift register 33 holds “00101001010000” as values s [0] to s [13] in the period of the clock cycle 18.

  As shown in FIGS. 7 and 8, the values s [0] to s [13] stored in the shift register 33 change depending on the presence / absence of a clock cycle shift of the signal. That is, when a shift shift occurs as shown in FIG. 8, “00101001010000” is stored in the shift register 33 as values s [0] to s [13]. This value is shifted by 1 bit when compared with “010101001000000” which is the values s [0] to s [13] stored in the shift register 33 when no shift shift occurs (FIG. 7). Therefore, according to the semiconductor device of the present embodiment, it is possible to detect the clock cycle shift of the signal, and to accurately determine whether the semiconductor device is good or defective.

<Embodiment 2>
A semiconductor device according to a second embodiment will be described with reference to the drawings. The semiconductor device of this embodiment corresponds to a case where the present invention is applied to the semiconductor device described in FIG. In Patent Document 2, the fail signal is expressed by negative logic, but in this embodiment (FIG. 9), it is expressed by positive logic.

  FIG. 9 is a block diagram showing an example of the configuration of the semiconductor device of this embodiment. Referring to FIG. 9, the semiconductor device includes a RAM 40 and a self-test circuit for testing the RAM 40. The self test circuit includes a test pattern generation circuit 31, comparison / flag holding circuits V 0 to V 3, an OR gate G 20, and a shift register 33.

  Each of the comparison / flag holding circuits V0 to V3 includes an XOR gate G1, AND gates A30 and A31, an OR gate G31, and a flip-flop FF30.

  The XOR gate G1 obtains an exclusive OR of the output data signal output from each data output terminal (Dout [0] to Dout [3]) of the RAM 40 and the pseudo expected value signal. The AND gate A30 calculates a logical product of the output signal of the XOR gate G1 and the comparison enable signal COMPEN. The flag holding means (AND gate A31, OR gate G31, flip-flop FF30) receives the hold enable signal HOLDEN output from the test pattern generation circuit 31 and the output signal of the AND gate A30, and the hold enable signal HOLDEN is activated. In the state, the bit value indicating whether or not the output signal has changed is held, and the held bit value is output. In other cases, the output signal is output without being held. The OR gate G20 calculates the logical sum of the output signals of the flag holding means of the comparison / flag holding circuit (V0 to V3) and outputs the logical sum to the shift register 33.

  The semiconductor device according to the first embodiment is provided with a flip-flop FF30 and an OR gate G31 so that fail flag information for each data I / O bit can be held. It is different from 5). In addition, the semiconductor device of this embodiment is provided with an AND gate A31 for the purpose of performing a “cycle shift test”.

  In the semiconductor device of this embodiment, the comparison / flag holding circuits V0 to V3 each hold a fail flag for each I / O of the RAM 40. The semiconductor device further includes an OR gate G20 that performs a logical OR operation on fail flag information for each I / O and creates fail flag information in RAM units. The serial shift register 33 for storing test results holds a fail flag for each RAM.

  Next, the operation of the semiconductor device of this embodiment will be described. First, in a normal RAM test, the hold enable signal is set to HOLDEN = 1, and fail flag information for each data I / O bit is held in the flip-flop FF30. The fail flag information (DATAFLAG [0] to [3]) for each data I / O bit is ORed by the OR gate G20 and becomes a fail information signal ERR for the RAM 40. When the hold enable signal is HOLDEN = 1, the fail information signal ERR represents a fail flag of the RAM 40.

  On the other hand, in the cycle shift test, the hold enable signal is set to HOLDEN = 0. The determination result DATAERR for each data I / O bit becomes a DATAFLAG signal delayed by one cycle via the flip-flop FF30. At this time, since the hold enable signal is HOLDEN = 0, the fail flag information is not held in the flip flip FF 30. The fail flag information (DATAFLAG [0] to [3]) for each data I / O bit is ORed by the OR gate G20 and becomes a fail information signal ERR for the RAM 40. The fail information signal ERR is taken into the shift register 33 as in the case of the first embodiment.

  10 and 11 show waveforms of the cycle shift test operation of the semiconductor device of this embodiment. FIG. 10 shows the operation during normal operation (when there is no signal cycle shift). On the other hand, FIG. 11 shows the operation at the time of abnormal operation (when there is a signal cycle shift).

  As shown in FIGS. 10 and 11, the values s [0] to s [13] stored in the shift register 33 change depending on the presence / absence of a clock cycle shift of the signal. That is, when a shift shift occurs as shown in FIG. 11, “00101001010000” is stored in the shift register 33 as values s [0] to s [13]. This value is shifted by 1 bit as compared with the values s [0] to s [13] stored in the shift register 33 when there is no shift shift (FIG. 10), that is, “010110001000000”. Therefore, according to the semiconductor device of the present embodiment, it is possible to detect a clock cycle shift of the signal as in the semiconductor device of the first embodiment.

  Further, according to the semiconductor device of the present embodiment, the fail flag information (DATAFLAG) for each I / O is added to the redundant relief information by adding a serial shift function as shown in Patent Documents 1 and 2. Can be used as

<Embodiment 3>
A semiconductor device according to a third embodiment will be described with reference to the drawings. FIG. 12 is a block diagram illustrating a configuration of the semiconductor device according to the present embodiment as an example. The semiconductor device of this embodiment is configured by adding a fail flag register for each RAM in the semiconductor device of the first embodiment (FIG. 5) to the semiconductor device of the second embodiment (FIG. 9). Have

  In the semiconductor device of this embodiment, the comparison / flag holding circuits V0 to V3 each hold a fail flag for each I / O of the RAM 40. The OR gate G20 performs a logical OR operation on the I / O fail flag information. The RAM fail flag holding circuit (AND gate A21, OR gate G21, flip-flop FF20) receives the OR operation output from the OR gate G20 and holds a fail flag for each RAM. The test result storage serial shift register 33 stores the output of the register of the RAM fail flag holding circuit.

  Next, the operation of the semiconductor device of this embodiment will be described. First, in a normal RAM test, the hold enable signal is set to HOLDEN = 1, and fail flag information for each data I / O bit is held in the flip-flop FF30. The fail flag information (DATAFLAG [0] to [3]) for each data I / O bit is ORed by the OR gate G20 and becomes a fail information signal ERR for the RAM 40. The fail information signal ERR is taken into the flip-flop FF20. When the hold enable signal is HOLDEN2 = 1, the fail information signal ERR is held as fail flag information for each RAM by a feedback circuit passing through the AND gate A21 and the OR gate G21.

  On the other hand, in the cycle shift test, the hold enable signal is set to HOLDEN = 0 and HOLDEN2 = 0. The determination result DATAERR for each data I / O bit becomes a DATAFLAG signal delayed by one cycle via the flip-flop FF30. At this time, since the hold enable signal is HOLDEN = 0, the fail flag information is not held in the flip-flop FF30. The fail flag information (DATAFLAG [0] to [3]) for each data I / O bit is ORed by the OR gate G20 and becomes a fail information signal ERR for the RAM 40. The fail information signal ERR becomes a fail flag signal FAILFLAG delayed by one cycle via the flip-flop FF20. Since the hold enable signal is HOLDEN2 = 0, the fail information signal ERR is not held in the flip-flop FF20 as a fail flag.

  In the semiconductor device of the present embodiment, the FAILFLAG signal is delayed by one cycle compared to the semiconductor device of the second embodiment (FIG. 9). Therefore, in this embodiment, the shift register 33 is controlled using the shift enable signal CAPEN2 that is delayed by one cycle of the shift enable signal CAPEN. The flip-flop FF70 delays the shift enable signal CAPEN by one cycle and outputs it as the shift enable signal CAPEN2.

  13 and 14 show waveforms of the cycle shift test operation of the semiconductor device of this embodiment. FIG. 13 shows the operation during normal operation (when there is no signal cycle shift). On the other hand, FIG. 14 shows the operation at the time of abnormal operation (when there is a signal cycle shift).

  As shown in FIGS. 13 and 14, the values s [0] to s [13] stored in the shift register 33 change depending on the presence / absence of a clock cycle shift of the signal. That is, when a shift shift occurs as shown in FIG. 14, “00101001010000” is stored in the shift register 33 as values s [0] to s [13]. This value is shifted by 1 bit as compared with the values s [0] to s [13] stored in the shift register 33 when there is no shift shift (FIG. 13), that is, “01010010010000”. Therefore, according to the semiconductor device of the present embodiment, it is possible to detect the clock cycle shift of the signal as in the first and second embodiments.

  Further, according to the semiconductor device of this embodiment, the fail flag information (DATAFLAG) for each I / O can be used as redundant relief information, as in the semiconductor device of the second embodiment. Furthermore, according to the semiconductor device of this embodiment, fail flag information in units of RAM can be used as redundant relief information.

<Embodiment 4>
A semiconductor device according to a fourth embodiment will be described with reference to the drawings. The semiconductor device of this embodiment includes a plurality of RAMs, and shares a shift register 33 among a plurality of FAILFLAG signals.

  15 and 16 are block diagrams illustrating an example of the configuration of the semiconductor device according to the present embodiment.

  FIG. 15A shows a case where the shift register 33 is shared among a plurality of fail flag signals FAILFLAG in the semiconductor device of the first embodiment. The flip-flop FF20 [0] holds or outputs a fail flag signal FAILFLAG [0] for the first RAM, and the flip-flop FF20 [1] holds or outputs a fail flag signal FAILFLAG [1] for the second RAM. In this case, an OR gate G70 for obtaining a logical sum of a plurality of fail flag signals is inserted.

  FIG. 15B shows a case where the shift register 33 is shared among a plurality of fail information signals ERR (fail flag signal FAILFLAG) in the semiconductor device of the second embodiment. In FIG. 15B, the lower comparison / flag holding circuit generates and holds or outputs a fail information signal ERR [2] for the first RAM, and the upper comparison / flag holding circuit fails for the second RAM. Information signal ERR [3] is generated and held or output. In this case, an OR gate G70 for obtaining the logic of a plurality of fail information signals ERR is inserted.

  Further, FIG. 15C shows a case where the shift register 33 is shared among a plurality of fail flag signals FAILFLAG in the semiconductor device of the third embodiment. The flip-flop FF20 [4] holds or outputs a fail flag signal FAILFLAG [0] for the first RAM, and the flip-flop FF20 [5] holds or outputs a fail flag signal FAILFLAG [1] for the second RAM. In this case, an OR gate G70 for obtaining a logical sum of a plurality of fail flag signals FAILFLAG is inserted.

  As shown in FIGS. 15A to 15C, in a semiconductor device having a plurality of RAMs, the OR gate G70 performs OR operation on fail flag information for each of the plurality of RAMs corresponding to each RAM, and stores the test results. Serial shift register 33 stores the output signal of OR gate G70.

  FIG. 16 shows a case where the shift register 33 is shared among a plurality of FAILFLAG signals when the semiconductor devices of the first to third embodiments coexist. In the case shown in FIG. 16, flip-flops FF80 [0] to FF80 [4] and an OR gate G70 are added.

  FAILFLAG [0], [1] in the semiconductor device of the first embodiment and FAILFLAG [2], [3] in the semiconductor device of the second embodiment are FAILFLAG [0] of the semiconductor device of the third embodiment. 4), advanced by one cycle compared to [5]. Therefore, after flip-flops FF80 [0] to FF80 [3] are inserted and the cycle is adjusted, an OR operation is performed by the OR gate G70. That is, the semiconductor device of FIG. 16 further includes a cycle adjustment circuit that adjusts the cycle of fail flag information for each of a plurality of RAMs.

  15 and FIG. 16, as an example, a configuration in which an OR operation is performed between several fail flag signals FAILFLAG is shown, but an OR operation may be performed on the fail flag signals FAILFLAG of several tens to several hundreds. .

  According to the semiconductor device of the present embodiment (FIGS. 15 and 16), sharing the shift register 33 provides an effect of reducing the circuit scale.

  Various modifications can be made to the semiconductor devices according to the first to fourth embodiments.

  Although not clearly shown in the semiconductor device of the second embodiment (FIG. 9) and the semiconductor device of the third embodiment (FIG. 12), FIG. 2 of Patent Document 1 or FIG. 29, a function of serially connecting flip-flops for fail flags for each data I / O bit may be added. As a result, the failure I / O position can be determined. Moreover, it becomes possible to carry out redundant relief of the RAM based on this determination result.

  Further, in the semiconductor device of the third embodiment (FIG. 12), the hold enable signals HOLDEN and HOLDEN2 may be shared.

  Further, when the shift register is shared by a plurality of RAMs, the OR gate G70 may be a pipelined OR operation circuit including a flip-flop. In this case, the shift enable signal CAPEN or CAPEN2 is delayed according to the number of pipeline stages.

  It should be noted that the disclosures of prior art documents such as the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

11 Test pattern generation means 12, 12a, 12b Comparison means 13 Error holding means 14, 14a, 14b Flag holding means 20, 20a, 20b Memory circuit 31, 32 Test pattern generation circuit 33 Shift register 40 RAM
111 Test pattern generation circuit 112 RAM
120 pattern generator 140 comparison circuit A20, A21, A30, A31 AND gate AND1, AND1a, AND1b AND gate AND2, AND2a, AND2b AND gate CMP1, CMP1a, CMP1b comparators FF2, FF2a, FF2b flip-flops FF20, FF30, FF70, FF80, FF89 Flip-flop G1, G2 XOR gates G20, G21, G31, G70 OR gates OR1, OR2, OR2a, OR2b, OR3 OR gates SR [0] to SR [13] Register SEL80 Selector U0 to U3 Comparison circuits V0 to V3 Comparison / flag holding circuit

Claims (11)

A semiconductor device comprising a memory circuit and a self-test circuit for testing the memory circuit,
The self-test circuit outputs a bit value included in a bit string obtained by inverting a part of bit values included in an expected value bit string in each clock cycle of an output data signal output from the memory circuit in each clock cycle. Test pattern generation means for generating a comparison enable signal that enables comparison of the output data signal and the pseudo expected value signal in each clock cycle,
The output data signal output from the memory circuit, and the pseudo expected value signal and the comparison enable signal output from the test pattern generation means are received, and each of the periods within a period in which the comparison enable signal is in an active state A comparison means for comparing the output data signal with the pseudo expectation value signal in a clock cycle and generating a comparison result signal representing a comparison result;
An error holding means for receiving the comparison result signal from the comparison means and holding a bit value in each clock cycle of the received comparison result signal.   The comparison means obtains an exclusive OR between the output data signal and the pseudo expectation value signal, and generates a logical product between the exclusive OR and the comparison enable signal as the comparison result signal. The semiconductor device according to claim 1, wherein the semiconductor device is characterized.   3. The semiconductor device according to claim 1, wherein the error holding unit is a shift register that holds a bit value in each clock cycle of the comparison result signal.   When the hold enable signal output from the test pattern generation means and the comparison result signal output from the comparison means are received, and the hold enable signal is in an active state, the change of the comparison result signal is changed. 4. The method according to claim 1, further comprising flag holding means for holding a bit value indicating presence / absence, and otherwise outputting to said error holding means without holding said comparison result signal. The semiconductor device according to any one of the above. The flag holding means includes a flip-flop, an AND gate, and an OR gate,
The AND gate generates a logical product of the hold enable signal and the output signal of the flip-flop;
The OR gate generates a logical sum of the comparison result signal and the output signal of the AND gate,
The semiconductor device according to claim 4, wherein the flip-flop latches an output signal of the OR gate. The first output data signal output from the first memory circuit and the pseudo expectation value signal and the comparison enable signal output from the test pattern generation means are received, and the comparison enable signal is in an active state. First comparison means for comparing the first output data signal with the pseudo expectation value signal in each clock cycle within a period and generating a first comparison result signal representing a comparison result;
The second output data signal output from the second memory circuit and the pseudo expected value signal and the comparison enable signal output from the test pattern generation means are received, and the comparison enable signal is in an active state. Second comparing means for comparing the second output data signal with the pseudo-expected value signal in each clock cycle within a period and generating a second comparison result signal representing a comparison result;
When the hold enable signal output from the test pattern generation unit and the first comparison result signal output from the first comparison unit are received, and the hold enable signal is in an active state, Holds a bit value indicating whether or not the first comparison result signal has changed, outputs the held bit value, and otherwise outputs the first comparison result signal as it is. Means,
When the hold enable signal and the second comparison result signal output from the second comparison means are received and the hold enable signal is in an active state, a change in the second comparison result signal Second flag holding means for holding a bit value representing the presence or absence of the output and outputting the held bit value; otherwise, outputting the second comparison result signal as it is;
2. An OR gate that obtains a logical sum of an output signal of the first flag holding means and an output signal of the second flag holding means and outputs the logical sum to the error holding means. A semiconductor device according to 1. The first comparing means obtains an exclusive OR between the first output data signal and the pseudo expectation value signal, and calculates a logical product between the exclusive OR and the comparison enable signal. As a comparison result signal
The second comparison means obtains an exclusive OR between the second output data signal and the pseudo expectation value signal, and calculates a logical product between the exclusive OR and the comparison enable signal. The semiconductor device according to claim 6, wherein the semiconductor device is generated as a comparison result signal. The first flag holding means includes a first flip-flop, a first AND gate, and a first OR gate,
The first AND gate generates a logical product of the hold enable signal and the output signal of the first flip-flop,
The first OR gate generates a logical sum of the first comparison result signal and the output signal of the first AND gate,
The first flip-flop latches a signal output from the first OR gate,
The second flag holding means includes a second flip-flop, a second AND gate, and a second OR gate,
The second AND gate generates a logical product of the hold enable signal and the output signal of the second flip-flop;
The second OR gate generates a logical sum of the second comparison result signal and the output signal of the second AND gate,
The semiconductor device according to claim 6, wherein the second flip-flop latches a signal output from the second OR gate. The comparing means includes a plurality of XOR gates for obtaining an exclusive OR of the output data signal output from each data output terminal of the memory circuit and the pseudo expected value signal;
An OR gate for obtaining a logical sum of output signals of the plurality of XOR gates;
The AND gate according to claim 1, further comprising: an AND gate that obtains a logical product of the output signal of the OR gate and the comparison enable signal and outputs the logical product as the comparison result signal. Semiconductor device. The comparison means includes a plurality of comparison / flag holding circuits,
Each of the plurality of comparison / flag holding circuits includes an XOR gate that obtains an exclusive OR of an output data signal output from each data output terminal of the memory circuit and the pseudo expected value signal;
An AND gate for obtaining a logical product of the output signal of the XOR gate and the comparison enable signal;
When the hold enable signal output from the test pattern generation means and the output signal of the AND gate are received and the hold enable signal is in an active state, a bit value indicating whether or not the output signal has changed is Holding a first bit holding means for outputting the held bit value, and otherwise outputting the output signal without holding the output signal.
4. The semiconductor device according to claim 1, wherein a logical sum of output signals of the first flag holding means of each of the plurality of comparison / flag holding circuits is used as the comparison result signal. An OR gate for obtaining a logical sum of signals output from the respective flag holding means of the plurality of comparison / flag holding circuits;
When the hold enable signal output from the test pattern generation means and the output signal of the OR gate are received, and the hold enable signal is in an active state, a bit value indicating whether or not the output signal has changed A second flag holding unit that holds and outputs the held bit value as the comparison result signal, and otherwise outputs the comparison result signal without holding the output signal. The semiconductor device according to claim 10, wherein:

Images