JP5711212B2 - Chip fuse - Google Patents

Description

  The present invention relates to a chip fuse.

Japanese Patent Publication No. 55-5847 (Patent Document 1) and Japanese Patent Application Laid-Open No. 7-122406 (Patent Document 2) disclose a chip-like fuse resistor in which a Ni—P—Fe film is formed on an insulating substrate by electroless plating . And a conventional example of a resistor is disclosed.

Japanese Patent Publication No.55-5847 Japanese Patent Laid-Open No. 7-122406

  The melting temperature of the Ni—P—Fe film is as high as about 800 ° C. to 1000 ° C. Therefore, in the circuit protection element described in Patent Document 1, there is a problem that the Ni-P-Fe film (fuse element) may not be blown at a small current value, and it is difficult to set the fuse blowing condition. Further, in the circuit protection element described in Patent Document 2, a small amount of tungsten or molybdenum is added to the Ni—P—Fe film to increase the stress of the plating film so that cracks are easily formed in the plating film. . However, the circuit protection element of Patent Document 2 has a problem in that a Ni-P-Fe film (fuse element) may not have a necessary and sufficient crack, and the Ni-P-Fe film does not break reliably. .

  An object of the present invention is to provide a chip fuse that uses a Ni-P-Fe plated layer and that is more reliably fused than in the past.

  Another object of the present invention is to provide a chip fuse that uses a fuse element that can be blown with a smaller current than the conventional one, in a chip fuse that uses a plated layer of Ni-P-Fe.

  The chip fuse of the present invention includes an insulating substrate, a pair of surface electrodes formed on both ends of the substrate surface of the insulating substrate, a Ni—P—Fe plating layer, a Sn plating layer, and an overcoat layer. . The Ni—P—Fe plating layer is formed on the substrate surface by an electroless plating method so as to straddle the pair of surface electrodes. The tin plating layer is formed on the Ni—P—Fe plating layer by electrolytic plating. In the present invention, the fuse element is constituted by the plated layer of Ni—P—Fe and the plated layer of Sn. The Ni—P—Fe plating layer needs to be heated to a considerably high temperature in order to melt it alone. Therefore, in the present invention, by forming Sn plating on the Ni—P—Fe plating layer, the fusing temperature of the fuse element using the Ni—P—Fe plating layer is made lower than that of the prior art. The principle that the fusing temperature is lowered has not been completely clarified, but the Ni-P-Fe plating layer has a higher resistance value than the Sn plating layer, so the temperature of the Ni-P-Fe plating layer is low. The Sn plating layer is first melted by the heat generated in the Ni—P—Fe plating layer, and the molten Sn plating layer touches Ni and Fe in the Ni—P—Fe plating layer. As a result, an alloy having a melting point of about 500 ° C. is formed particularly when Fe and Sn come into contact with each other. Therefore, it is presumed that the fusing temperature of the Ni—P—Fe plating layer that has melted only at 1000 ° C. or more alone can be lowered. The overcoat layer is formed by an insulating resin material such as epoxy or silicon so as to cover the Sn plating layer.

  Specifically, the thickness of the Ni—P—Fe plating layer is 0.4 to 0.8 μm, the thickness of the Sn plating layer is 1.0 to 5.0 μm, and the Ni—P—Fe plating is performed. It is preferable that the layer has a composition of Fe: 11 to 13% by weight, P: 7 to 13% by weight, and the balance of Ni.

  With this configuration, for example, in a 1005-size chip fuse with a length of 1.0 mm and a width of 0.5 mm with a rated current of 0.35 A, an internal maximum resistance of 650 mΩ, a rated voltage of 24 VDC, and a breaking current of 35 A, the fusing performance is determined as The melting time can be set to 200% of 5% and within 5 seconds. The chip fuse of the present invention is not limited to the above-mentioned standard, and for example, a resistance value range of 300 to 1000 mΩ, a rated current of 0.3 to 0.5 A, a rated voltage of 24 VCD, and a cutoff current of 35 A. it can. The size of the chip fuse may be a 1608 size having a length of 1.6 mm and a width of 0.8 mm.

It is sectional drawing of the chip fuse of embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an example of an embodiment of a chip fuse of the present invention. In addition, in order to make an understanding easy, in FIG. 1, the thickness dimension of each part is exaggerated and drawn. As shown in FIG. 1, the chip fuse 20 has a substantially rectangular insulating substrate 1. In the present embodiment, the chip-like insulating substrate 1 is formed of an alumina substrate (ceramic substrate).

  For the substrate surface 1 a of the insulating substrate 1, a pair of surfaces having substantially the same width dimension along the longitudinal direction of the insulating substrate 1, using an Ag—Pd-containing glaze paste formed by kneading Ag and Pd powder in a glass paste Electrodes 3 and 3 are formed. In this example, surface electrodes 3 and 3 having a thickness of about 8 μm were formed by screen printing using an Ag—Pd-containing glaze paste. The firing temperature of the Ag—Pd-containing glaze paste is about 850 ° C.

  On the substrate back surface 1b of the insulating substrate 1, a pair of back surface electrodes 5 and 5 having substantially the same width dimension along the longitudinal direction of the insulating substrate 1 is formed using an Ag-containing glaze paste. The back electrodes 5 and 5 are formed by screen printing, and the thickness is about 8 μm, which is the same as the surface electrode. The firing temperature of the Ag-containing glaze paste is about 850 ° C.

  The side electrodes 7 and 7 are formed so as to cover part of the surface electrodes 3 and 3 and part of the back electrodes 5 and 5 and straddle the surface electrodes 3 and 3 and the back electrodes 5 and 5. As a result, both end surfaces 1 c in the longitudinal direction of the insulating substrate 1 are also covered with the side electrodes 7, 7. The side electrodes 7, 7 are formed using a nickel-chromium alloy thin film containing a nickel-chromium alloy and a copper thin film. This thin film is formed by sputtering. However, the side electrodes 7 and 7 may be formed of Ag resin paste (fired at about 200 ° C.).

  As shown in FIG. 1, the side electrodes 7 and 7 are covered with a nickel plating layer (internal plating) 9 together with a part of the front electrodes 3 and 3 and a part of the back electrodes 5 and 5. The nickel plating layer 9 is entirely covered with a Sn plating layer 11 (external plating).

  A plating layer 15 made of Ni—P—Fe is formed on the substrate surface 1a. Ni-P-Fe has high bonding properties. Therefore, when Ni—P—Fe is used as the fuse element, a chip fuse having a high anti-pulse property can be obtained. The plated layer 15 made of Ni—P—Fe is formed to a thickness of 0.4 to 0.8 μm by an electroless plating method. In this example, the composition of Ni—P—Fe is such that Fe is 11 to 13 wt%, P is 7 to 13 wt%, and the balance is Ni. The thickness and composition of the Ni—P—Fe plating layer 15 are not limited to these, but if the composition ratio of Fe is high, the resistance value increases and the plating film is easily oxidized. Oxidation of the plating film involves problems such as deterioration of the adhesion of masking in the next process, destabilization of Sn deposition, and insufficient masking peeling. Moreover, when the composition ratio of Fe is low, sufficient fusing characteristics cannot be obtained. Therefore, the composition ratio and resistance value of Fe need to be in an appropriate range. The plated layer 15 made of Ni—P—Fe is formed by an electroless plating method and then heat-treated at 270 ° C. to 310 ° C.

  On the Ni—P—Fe plating layer 15, a plating layer 17 made of Sn is formed. The Sn plating layer 17 is formed to a thickness of 1.0 to 2.0 μm by electrolytic plating. It is preferable to mask the edge portion of the chip fuse 20 unit before forming the Sn plating layer 17. By masking, it is possible to prevent Sn from being deposited on the edge portion. When Sn is deposited on the edge portion, Sn adheres to the conductor. Therefore, the conductor may be cut off when reflowing. This can be prevented by masking.

  In the present invention, the Ni—P—Fe plating layer 15 and the Sn plating layer 17 constitute a fuse element 18. When a voltage is applied between the surface electrodes 3 and 3, a current flows through both the Ni—P—Fe plating layer 15 and the Sn plating layer 17. The Ni—P—Fe plating layer 15 needs to be 1000 ° C. in order to be melted alone. Since the Ni-P-Fe plating layer 15 has a higher resistance value than the Sn plating layer 17, the temperature of the Ni-P-Fe plating layer 15 is increased, and the Ni-P-Fe plating layer 15 is generated. The transferred heat is transferred to the Sn plating layer 17. Since the Sn plating layer 17 melts at about 230 ° C., it is melted by the heat transferred from the Ni—P—Fe plating layer 15. When the molten Sn plating layer 17 comes into contact with the Ni—P—Fe plating layer 15, Ni and Fe are melted. In particular, it is presumed that an alloy having a melting point of about 500 ° C. is formed by mixing Fe and Sn. Therefore, in the present embodiment, the Ni—P—Fe plating layer 15 that has melted only at 1000 ° C. alone melts at about 500 ° C. Therefore, the fuse element 18 of the present embodiment is melted at about 500 ° C.

  In particular, in the present embodiment, the Ni—P—Fe plating layer 15 has a thickness of 0.4 to 0.8 μm, and the Sn plating layer 17 has a thickness of 1.0 to 5.0 μm. Further, the composition of the Ni—P—Fe plating layer 15 is Fe: 11-13 wt%, P: 7-13 wt%, and the balance is Ni. Therefore, if the chip fuse of this embodiment is a rated current of 0.35A, an internal maximum resistance of 650 mΩ, a rated voltage of 24 VDC, a cutoff current of 35 A, a length of 1.0 mm, and a width of 0.55 mm, it will blow out. The performance can be 200% of the rated current and a fusing time within 5 seconds. Note that the chip fuse of the present invention is not limited to the above-mentioned standard, and for example, a resistance value range of 300 to 1000 mΩ, a rated current of 0.3 to 0.5 A, a rated voltage of 24 VDC, and a cutoff current of 35 A. it can. Further, the size of the chip fuse may be a 1608 size having a length of 1.6 mm and a width of 0.8 mm.

  An overcoat layer 19 is formed on the Sn plating layer 17 formed by electrolytic plating. In the present embodiment, the overcoat layer 19 is formed using epoxy which is an insulating resin material whose firing temperature is lower than the heat treatment temperature of the Ni—P—Fe plating layer 15 formed by electroless plating. Yes. The used epoxy firing temperature is about 200 ° C. The overcoat layer 19 is also formed by screen printing and firing.

  What is necessary is just to manufacture the chip fuse 20 of the said embodiment in the following order. First, a pair of front surface electrodes 3 and 3 and a pair of back surface electrodes 5 and 5 are formed on both ends of the substrate surface and the back surface of the insulating substrate 1. Next, side electrodes 7 are formed. Next, in order to deposit a plating layer formed by an electroless plating method on the substrate surface positioned between the pair of surface electrodes 3 and 3 and the pair of surface electrodes 3 and 3, A base for electroless deposition is formed between the surface electrodes 3 and 3. The base for electroless deposition functions as a base for depositing electroless plating, and is formed by screen printing and baking. The base material for the electroless deposition film is arbitrary, and in this example, it is formed of a glaze paste material (catalyst paste) containing Pd as a conductive material. The firing temperature of the base for electroless deposition made of a glaze paste material containing Pd is about 600 ° C. The electroless deposition base is formed between the surface electrodes 3 and 3 after the pair of surface electrodes 3 and 3 is formed. Incidentally, the electroless film deposition base is not formed with a layer in which only a small amount of Pd of 0.1 μm or less is scattered on the ceramic substrate in the finished chip fuse of the present invention.

  Next, a Ni—P—Fe plating layer 15 is formed on the pair of surface electrodes 3 and 3 and the cater paste on the substrate surface by an electroless plating method. Next, the Ni—P—Fe plating layer 15 is heat-treated. Next, a masking paste is printed and baked. Next, an Sn plating layer 17 is formed on the Ni—P—Fe plating layer 15 by electrolytic plating. Thereafter, the masking is removed. Then, trimming is performed as necessary to obtain a necessary resistance value. Trimming is not always necessary. Finally, an overcoat layer 19 that covers the Sn plating layer 17 is formed of an insulating resin material. After the overcoat layer 19 is formed, the plating layers 9 and 11 are formed across the side electrodes 7 and 7, the front electrodes 3 and 3, and the back electrodes 5 and 5.

  In this embodiment, the insulating substrate is made of a ceramic substrate, the overcoat layer is made of epoxy, and the undercoat layer is made of a metal glaze paste containing Pd. However, it is used when the present invention is applied. The substrate material, overcoat material, and undercoat layer to be used are not limited to these materials.

  According to the present invention, the fuse element can be surely blown at a lower temperature than in the prior art.

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 3 Front surface electrode 5 Back surface electrode 7 Side surface electrode 9 Internal plating 11 External plating 15 Ni-P-Fe plating layer 17 Sn plating layer 18 Fuse element 19 Overcoat layer 20 Chip fuse

Claims (1)

An insulating substrate;
A pair of surface electrodes formed at both ends of the substrate surface of the insulating substrate;
A plating layer of Ni-P-Fe formed on the substrate surface so as to straddle between the pair of surface electrodes;
A Sn plating layer formed on the Ni-P-Fe plating layer;
An overcoat layer made of an insulating resin material formed on the Sn plating layer ,
The Ni—P—Fe plating layer has a thickness of 0.4 to 0.8 μm, the Sn plating layer has a thickness of 1.0 to 2.0 μm,
The composition of the Ni-P-Fe plating layer is Fe: 11-13 wt%, P: 7-13 wt%, and the balance is Ni.

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