JP5703910B2 - Mask pattern data generation method, mask manufacturing method, mask, and mask pattern data generation program - Google Patents

Description

  The present invention relates to a mask pattern data generation method, a mask manufacturing method, and a mask manufacturing method for improving overlay accuracy between patterns in a plurality of photomask patterns (hereinafter referred to as masks) used for pattern formation of a semiconductor device. The present invention relates to a mask and mask pattern data generation program using a manufacturing method.

  Along with the high integration and miniaturization of semiconductor devices, the miniaturization of patterns of semiconductor devices formed on a wafer has progressed, and the positional accuracy between patterns and pattern layers (layers) has become important. Usually, a semiconductor device is formed by superposing a plurality of different pattern layers (layers), but it has become difficult to ensure the overlay accuracy between different pattern layers (layers) due to the miniaturization of patterns.

  Various exposure techniques and correction techniques have been studied and put into practical use for fine pattern formation of semiconductor devices, but with regard to pattern position accuracy related to overlay accuracy, a mask exposure apparatus or a semiconductor exposure apparatus used for transfer It depends on the actual situation. Under such circumstances, many proposals have been made for the projection lens distortion of the exposure apparatus related to the pattern position accuracy.

  For example, Patent Document 1 discloses a technique for providing a mask in which a positional deviation amount depending on a pattern due to distortion of a projection lens of an exposure apparatus used for transfer is predicted and measured in advance, and the pattern position is corrected. FIG. 19 is a perspective view showing a configuration of a semiconductor light exposure apparatus described in Patent Document 1, using an aperture 194 that uniformly converges incident light into a specific shape, and a mask 196 through a lens 195. , And a pattern drawn on the mask 196 is projected to generate a projection image. The projection image is reduced by a reduction lens 197 configured by combining a plurality of lenses and printed on the wafer 191. FIG. 20 is a diagram showing a pattern exposed by the above-described light exposure apparatus. Due to the optical characteristics of the reduction lens 197, the actually exposed pattern is shown by a solid line with respect to the design pattern shown by a broken line. The shape is distorted.

  Further, as shown in FIG. 21, Patent Document 2 has a lens aberration of an exposure apparatus as a database, extracts a pattern that affects transfer by the presence or absence of lens aberration, corrects a mask pattern, A technique is disclosed in which a mask is produced using mask creation data and a pattern is transferred by an optical exposure apparatus.

  As described above, many means for solving the lens distortion problem of the exposure apparatus have been proposed, and at present, the lens distortion problem is approaching to be solved. Therefore, as a factor other than lens distortion related to overlay accuracy, improvement in mask pattern position accuracy is increasingly demanded. In particular, with the recent adoption of double patterning (double exposure) technology in semiconductor device manufacturing, improvement in mask pattern overlay accuracy has become an important issue in mask manufacturing.

  Until now, the positional accuracy in the mask has been generally managed by the amount of deviation from the reference lattice on the mask, and FIG. 18 shows an example of a reference lattice and mask position error in conventional mask manufacturing. The reference grid is usually a square ideal grid. As shown in FIG. 18A, a reference grid 181 is formed on the mask based on the design pattern, and the grid points are set as position measurement points 182a. The lattice spacing can be set to an arbitrary distance on the mask, and is set to, for example, several mm to several tens mm. Next, as shown in FIG. 18B, the coordinates of the lattice point (position measurement point) 182b of the manufactured mask pattern (solid line) are measured by a coordinate measuring device, and the deviation amount (position) from the reference lattice (dashed line) is measured. Error) 183 is measured, and it has been managed that the deviation amount is within a predetermined specification value.

JP-A-11-307424 JP 2001-68398 A

  As described above, with the miniaturization of the mask pattern, the mask pattern overlay accuracy becomes extremely strict, and a specification value with a deviation amount (position error) from the reference grid based on the design pattern within several nanometers is also required. It has become. However, in order to make the position error within several nanometers, the stage position accuracy of the electron beam lithography apparatus used for mask manufacturing may be a value close to that, and it is difficult to ensure the position accuracy. .

  The mask position error caused by the conventional mask pattern data generation method is such that a layer serving as a reference for overlaying (hereinafter referred to as a reference layer) at the time of transferring the mask pattern to a wafer and a layer for performing overlay (hereinafter referred to as a layer to be matched). Error) is managed and operated via a reference grid. In this conventional method, there is a problem that the position errors of the reference layer and the layer to be combined are reflected in the transfer position error.

  Therefore, the present invention has been made in view of the above problems. That is, the object of the present invention is to increase the margin for overlay design by focusing on the mask pattern data generation method regarding the pattern position accuracy in semiconductor fabrication, which has been conventionally dependent on the mask drawing apparatus or semiconductor exposure apparatus, By providing a mask pattern data generation method that improves the overlay accuracy between different pattern layers (layers), a mask manufacturing method using this pattern data generation method, a mask using the manufacturing method, and a mask pattern data generation program is there.

In order to solve the above problems, a mask pattern data generation method according to the first aspect of the present invention is a mask for generating mask pattern data of a plurality of layers necessary for mask fabrication from design data of a semiconductor device. A pattern data generation method, comprising: selecting whether the predetermined layer of the design data is a reference layer that is a reference or a reference layer when a plurality of layers are superimposed, and the reference layer In the selected layer, a reference grid based on the design data of the layer that is the reference layer is selected as a coordinate reference for mask drawing of the layer that is the reference layer, and the design data of the layer that is the reference layer is used as mask drawing data. Using the mask drawing data, the step of converting, and the mask of the layer that is the reference layer on a predetermined mask blank Drawing a pattern, processing the mask blank, producing a mask of the layer that is the reference layer, measuring the positional accuracy of the mask pattern of the layer that is the reference layer of the produced mask, and measuring the reference A step of setting a position coordinate of a mask pattern of a layer that is a layer as a second reference lattice, and using the position information of the mask pattern of the layer that is the reference layer in a layer that is not the reference layer , as the coordinate reference of the mask drawing of the non-reference layer layer, select the second reference grating, it viewed including the the steps of converting the design data of the non-reference layer layer to mask drawing data, wherein the reference layer is These are a plurality of reference layers of the same layer .

  A mask pattern data generation method according to a second aspect of the present invention is the mask pattern data generation method according to the first aspect, wherein the layer selected as the reference layer is the design data of the semiconductor device. It is characterized by having two layers inside.

  According to the mask pattern data generation method of the present invention, the overlay accuracy of the reference layer at the time of exposure and the layer to be formed formed on the reference layer is improved. In addition, by overlapping the other layers to be combined using the positional accuracy of the reference layer, the margin for the overlay design increases. In addition, the overlay reference layer is often a layer used in the initial process of semiconductor device manufacture, mask accuracy is relaxed by improving overlay accuracy, and the difficulty of device manufacture using this mask is reduced, The time required for processing (TAT) can be improved. There is an effect that it is easy to superimpose double patterning (double exposure) in manufacturing semiconductor devices.

  According to the mask manufacturing method of the present invention, a plurality of masks with high positional accuracy can be obtained by superimposing other layers to be bonded using the positional accuracy of the reference layer.

  According to the mask of the present invention, a plurality of masks with high positional accuracy can be obtained, and the overlay margin between layers at the time of transfer can be expanded. As a result, the yield of mask manufacturing and device manufacturing is improved. Is possible.

  According to the mask pattern data generation program of the present invention, it is possible to automatically generate mask pattern data with high alignment accuracy by executing generation of mask pattern data using a computer.

It is a flowchart which shows the mask manufacture procedure of this invention including the mask pattern data generation method of this invention. It is explanatory drawing which shows the setting of the reference | standard grating | lattice and 2nd reference | standard grating | lattice (effective reference | standard grating | lattice) in this invention. It is a figure which shows the positional error comparison example at the time of superposing | stacking two manufactured masks using the 2nd reference | standard grating | lattice (effective reference | standard grating | lattice) of this invention. It is a figure which shows the wafer shot image at the time of applying the mask pattern data generation method of this invention, and carrying out two-layer transfer with the two real masks shown in FIG. It is a figure which shows the position accuracy of the 2nd layer mask to which this invention is applied, and the deviation | shift from a reference | standard grating | lattice. It is a figure which shows the position error amount at the time of the transfer by this invention, and the position error at the time of transfer from a reference | standard grating | lattice. It is a flowchart which shows the mask manufacture procedure containing the conventional mask pattern data generation method. It is a figure which shows the example of the position error measurement at the time of manufacturing the mask of the 1st layer and the 2nd layer using the conventional reference | standard grating | lattice. It is a figure which shows the positional error comparison example of the superimposition of the two masks which carried out the mask manufacture by the conventional mask pattern data generation method. It is a figure which shows the positional error amount of two masks by a prior art, and the positional error at the time of transcription | transfer. It is the figure which compared the positional error amount at the time of transcription | transfer with this invention and a prior art. In the embodiment of the present invention, the measurement data of the positional error (nm) between the X coordinate and the Y coordinate when the first layer mask is used as an effective reference lattice and the second layer mask is transferred to the wafer. The transfer position error from the reference lattice (ideal lattice) of the second layer mask when it is created in accordance with the first layer is shown. In the comparative example by a prior art, it is measurement data of the positional error amount (nm) of the X coordinate of the 1st layer mask with respect to a reference | standard grating | lattice, and a Y coordinate. In a comparative example, it is the measurement data of the position error (nm) at the time of the transfer to the wafer of a 1st layer mask and a 2nd layer mask. In this invention, it is explanatory drawing which shows the 1st example in case a reference layer is made into two layers. In this invention, it is explanatory drawing which shows the 2nd example in case a reference | standard layer is made into two layers. It is an example of the reference | standard grating | lattice and mask position error of the mask manufacture in a prior art. It is a perspective view which shows the structure of the conventional optical exposure apparatus for semiconductors. It is a figure which shows the pattern exposed with the optical exposure apparatus shown in FIG. It is a flowchart which shows one Embodiment of the conventional pattern formation method.

  Hereinafter, based on the drawings, a mask pattern data generation method according to an embodiment of the present invention, a mask manufacturing method using the mask pattern data generation method, a mask and a mask pattern data generation program used for the mask pattern data generation method, This will be described in detail in comparison with a conventional mask pattern data generation method.

  FIG. 1 is a flowchart showing a mask manufacturing procedure of the present invention including a mask pattern data generation method of the present invention. First, as shown in FIG. 1, design data of a semiconductor device is prepared (S10). A semiconductor device is composed of, for example, a plurality of layers such as an element isolation layer, a gate layer, a wiring layer, and a contact hole layer. Usually, only one layer composed of a pattern of one layer is disposed on one mask. Then, a plurality of mask patterns on which patterns of each layer are formed are sequentially aligned and transferred on the wafer to manufacture a device.

  Next, it is selected whether the predetermined layer of the design data is a reference layer or a reference layer that serves as a reference when a plurality of layers are overlaid (aligned) (S11). Which layer is used as a reference layer is determined in advance depending on the device to be manufactured and the manufacturing process thereof. Usually, the overlay reference layer is often used in the initial process of device manufacture.

  In the layer selected as the reference layer, the design data of the layer used as the reference layer is converted into mask drawing data (S12). At this time, a reference lattice based on the design data of the layer serving as the reference layer is selected as a coordinate reference for mask drawing of the layer serving as the reference layer (S13).

  The reference lattice in step S13 is preferably an ideal lattice (also referred to as a standard reference lattice) having a square shape based on design data of a layer serving as a reference layer. FIG. 2 is an explanatory diagram showing the setting of the reference grating and the second reference grating in the present invention (hereinafter, the second reference grating is also referred to as an effective reference grating in the present invention), and FIG. These are figures which show the reference | standard grating | lattice as an ideal grating | lattice. In FIG. 2A, each lattice point of the reference lattice 21 is a position measurement point 22, and the lattice interval is usually set to several mm to several tens mm on the mask.

  Next, using the above mask drawing data, a mask pattern of a layer as a reference layer is drawn on a predetermined mask blank coated with an electron beam resist (S14) and developed to form a resist pattern. The mask blank is etched to produce a layer mask as a reference layer (S15). The produced mask is subjected to inspections such as appearance defect inspection and dimension inspection (S16).

  Next, as shown in FIG. 2B, the positional accuracy of the mask pattern of the layer serving as the reference layer is measured by a coordinate measuring device, and the position error (deviation amount) of the pattern of the layer serving as the reference layer with respect to the reference lattice is measured. ) 23 is calculated. If the deviation amount 23 is within the allowable specification value, the position coordinates of the mask pattern of the layer serving as the reference layer are set as the second reference lattice (effective reference lattice) 24 as shown in FIG. (S17).

  Next, in the layer selected as not the reference layer, the positional information of the mask pattern of the layer that is the reference layer is obtained (S18), and the design data of the layer that is not the reference layer is converted into mask drawing data (S19). . At this time, the second reference lattice (effective reference lattice) 24 is selected as a coordinate reference for mask drawing of a layer that is not the reference layer (S20).

  Next, using the converted mask drawing data, a mask pattern of a layer that is not a reference layer is drawn on a predetermined mask blank coated with an electron beam resist (S21), and developed to form a resist pattern. Then, the mask blank is etched to produce a mask for a layer that is not a reference layer (S22). The produced mask is subjected to inspections such as appearance defect inspection and dimension inspection (S23).

  Next, the positional accuracy of the mask pattern of the layer that is not the reference layer is measured, and the amount of positional deviation from the second reference lattice (effective reference lattice) is calculated to obtain the overlay accuracy between layers (S24). FIG. 3 is a diagram (FIG. 3B) showing an example of a positional error in overlaying the second mask when the second reference grating (effective reference grating) 24 shown in FIG. 3A is used. is there.

  The mask of the layer that is not the reference layer for which the positional accuracy measurement has been completed undergoes a shipping inspection together with the mask of the layer that is used as the reference layer (S25), and is shipped to the semiconductor device manufacturing process (S26).

  FIG. 4 shows the chip shape when the mask pattern data generation method of the present invention is applied and two real mask patterns are transferred onto the wafer by the two-layer mask image shown in FIG. It is an image figure (Drawing 4 (b)) shown.

  As shown in FIG. 1 and described above, in the mask manufacturing method of the present invention, the amount of positional deviation with respect to the reference lattice (ideal lattice) of the mask pattern of the layer used for the overlay reference layer of the semiconductor device to be manufactured is measured, The coordinates of the layer used for the reference layer having the amount of displacement are selected as the second reference lattice (effective reference lattice), the same semiconductor device and the mask pattern for the next process are created, and the mask is manufactured. This makes it possible to manufacture a mask having a two-layer overlay accuracy that is higher than the overlay accuracy between two layers via a conventional reference lattice.

  According to the mask according to the mask manufacturing method of the present invention, by obtaining a plurality of masks with high positional accuracy, the overlay margin between layers at the time of transfer can be expanded, and as a result, the yield of semiconductor device manufacturing is improved. It becomes possible to do.

  Furthermore, the mask pattern data generation method of the present invention is used as a program and is executed using a computer, so that mask pattern data with high alignment accuracy can be automatically generated.

  In the above description of the present invention, the case where one layer is selected as the reference layer when determining the second reference lattice (effective reference lattice) has been described. However, in the present invention, the reference layer may be two layers. . In this case, since two layers are considered as the reference layer, it is possible to further improve the overlay accuracy when manufacturing the semiconductor device.

  Here, an example in which the reference layer is two layers is shown. There are two types of legends with two reference layers. The first example is an example in which the superposition during wafer transfer extends over two layers. For example, when a contact hole is formed in the device structure as shown in FIGS. 16A to 16C, the Y direction may be aligned with the A layer and the X direction may be aligned with the B layer. The A layer is compared to the active layer (FIG. 16- (d)), and the B layer is compared to the gate layer (FIG. 16- (e)). The planar design of the contact hole layer to be formed is shown in FIG. In general, the active layer and the gate layer intersect each other and are often orthogonal. In this case, as in the device cross-sectional image shown in FIG. 16- (b), the contact hole connected from the active layer to the upper layer is in contact with the active layer and is connected to the upper layer through the pattern of the gate layer. Therefore, a better structure can be obtained by aligning the Y direction in the short period direction of the active layer and aligning the X direction in the short period direction of the gate layer. In such a case, the second reference lattice (effective reference lattice) of the contact hole layer is aligned with the reference layer of the A layer (for example, active layer) in the Y direction and the B layer (for example, gate layer) in the X direction. By matching with the reference layer, the effect of the present invention can be obtained.

  The second example is a case where the upper and lower two layers are used as a reference. The device structure as shown in FIGS. 17- (a) to (c) is taken as an example. For example, the contact hole (FIG. 17- (e)) is used for one purpose to connect the lower layer and the upper layer, but the positional information of the lower layer (FIG. 17- (d)) and the upper layer (FIG. 17- (f)). If the second reference grating (effective reference grating) is set based on the above, the lower layer and the upper layer can be connected with better accuracy. As a result, not only problems such as an increase in resistance due to displacement of the contact hole are improved, but also the design margin can be reduced, and as a result, the chip size can be reduced.

  In the mask pattern generation method of the present invention, it is also preferable to create a plurality of reference layers of the same layer in advance. When a plurality of reference layers of the same layer are created in advance, an effective reference lattice that takes into account the pattern positions of the plurality of reference layers can be used to realize multiple lines when manufacturing the same semiconductor device.

  For example, a memory product such as a DRAM has a larger amount of chips manufactured than a logic product. Therefore, in the stage of mass production, a plurality of masks used for transfer are produced and manufactured because they are produced in parallel by a plurality of exposure apparatuses.

  Accordingly, there are a plurality of masks for the first layer. For example, it is assumed that three masks A, B, and C are produced for the first layer. The amount of positional deviation of the three masks with respect to the reference grating is measured, and an effective reference grating is obtained from the results of the three sheets. As a result, the second and subsequent masks matched to the effective reference lattice can be superimposed with higher accuracy on any of the reference layers A to C.

Here, the necessity of mass production of memory such as DRAM is cited as the reason for possessing a plurality of reference layers, but there are cases where a plurality of reference layers are also possessed for other reasons. For example, the case where it owns as a backup mask with respect to damage and contamination by long-term use is mentioned.
Next, the present invention will be described in more detail by way of examples while comparing with a conventional mask pattern data generation method.

(Example)
This will be described with reference to the mask manufacturing flow diagram of the present invention shown in FIG. First, as shown in FIG. 1, design data of a semiconductor device was prepared (S10). This semiconductor device is composed of a plurality of layers such as an active layer, a gate layer, a wiring layer, and a contact hole layer. When the above layers of the active layer of the design data are overlaid (aligned), the plurality of layers are aligned. Was selected as a reference layer (S11). The other layers were non-reference layers.

  Next, the design data of the first active layer layer as the reference layer is converted into mask drawing data (S12). At this time, in the layer of the active layer selected as the reference layer, a reference lattice based on the design data of the active layer as the reference layer was selected as a coordinate reference for mask drawing (S13). As shown in FIG. 2A, the reference lattice is a square ideal lattice with a lattice interval of 16 mm on the mask as a unit.

  Next, the mask pattern of the active layer layer is drawn with an electron beam on a 6-inch square chrome mask blank coated with an electron beam resist using the above mask drawing data (S14), and developed to form a resist pattern. The mask blank was dry-etched with a mixed gas of chlorine and oxygen to produce a first layer mask of the active layer layer as a reference layer (S15). The produced mask was subjected to inspections such as appearance defect inspection and dimension inspection (S16).

  Next, as shown in FIG. 2B, the position accuracy of the mask pattern of the active layer layer as the reference layer was measured using a coordinate measuring device, and the position error (deviation amount) with respect to the reference lattice was calculated. (S17). Since the deviation amount is within the allowable specification value, as shown in FIG. 2C, the position coordinate of the mask pattern of the first active layer layer as the reference layer is set to the second reference lattice (effective reference grid). Grid).

  Next, in the second gate layer, which is another layer selected as not being the reference layer, the position information of the mask pattern of the active layer, which is the reference layer, is obtained (S18), and the design of the gate layer is performed. The data was converted into mask drawing data (S19). At this time, the second reference lattice (effective reference lattice) is selected as a coordinate reference for mask drawing of the gate layer (S20).

  Next, using the converted mask drawing data, the mask pattern of the second gate layer is drawn with an electron beam on a 6 inch square chrome mask blank coated with an electron beam resist (S21) and developed. After forming a resist pattern, dry etching was performed to prepare a mask for the second gate layer (S22). The manufactured mask was subjected to inspections such as appearance defect inspection and dimension inspection (S23).

  Next, the positional accuracy of the mask pattern of the gate layer was measured, and the amount of positional deviation from the second reference lattice (effective reference lattice) was calculated to obtain the overlay accuracy between layers (S24). FIG. 3B shows an example of the positional error of mask overlay of the gate layer when the second reference grating (effective reference grating) shown in FIG. 3A is used.

  FIG. 5 is a diagram showing a positional error (shift) from the reference lattice (ideal lattice) of the mask of the second gate layer using the pattern data generation method of the present invention for reference.

  Hereinafter, in the same manner as the mask fabrication for the second gate layer, a mask composed of other layers that are not selected as the reference layer is created in sequence, and the mask of the layer that is not the reference layer after the positional accuracy measurement is completed After shipping inspection (S25) as a set with the layer mask as a layer, it was shipped to the semiconductor device manufacturing process (S26).

  FIG. 12 shows an embodiment using the pattern data generation method of the present invention, a first layer mask (active layer layer mask) as an effective reference lattice, and a second layer using an effective reference lattice based on this mask. This is measurement data of X-axis and Y-coordinate position errors (nm) when transferring the mask (mask of the gate layer) to the wafer, and shows measured values at 6 points for X and Y. FIG. 13 shows, for reference, a transfer position error (nm) from the reference lattice (ideal lattice) of the second layer mask when it is prepared according to the first layer. The results of FIGS. 12 and 13 are summarized in Table 1.

  As shown in Table 1, (a) the position error during transfer of the first layer mask using the effective reference lattice is 0, and (b) the position error during transfer of the second layer mask is a relatively small value. is there. In the second layer mask, the position error of the first layer mask and the position error of the second layer mask are added together (transferred by (a) + (b)). By using the second reference grating (effective reference grating), the position error of the first layer is canceled out to zero.

  FIG. 6 shows the results of Table 1 above using the pattern data generation method of the present invention, and shows the position error amount at the time of transfer and the position error at the time of transfer from the reference grid.

(Comparative example)
On the other hand, for comparison, as a mask manufacturing procedure including a conventional mask pattern data generation method, a mask was manufactured based on the flowchart shown in FIG. The design data was the same as in the example, and for comparison, the first mask pattern was the active layer layer and the second mask pattern was the gate layer layer as in the example. A standard coordinate reference lattice (ideal lattice) is selected as a drawing coordinate reference, and the above-mentioned standard coordinate reference lattice is used for measuring the positional accuracy of the mask produced. A mask was prepared.

  FIG. 8 shows, in the comparative example, using the conventional reference grating 81 shown in FIG. 8A, the mask position error (FIG. 8B) of the first active layer layer with respect to the reference grating, and the reference grating FIG. 8C is a diagram showing a mask position error (FIG. 8C) of the second gate layer with respect to FIG.

  FIG. 9 is a diagram showing a positional error comparison example of the overlaying of two masks manufactured by the conventional mask pattern data generation method shown in FIG.

  FIG. 14 shows a positional error (nm) between the X coordinate and the Y coordinate of the first layer mask (mask of the active layer layer) with respect to the reference lattice in the comparative example using the pattern data generation method using the reference lattice of the prior art. ) And measured values at 6 points each of X and Y. FIG. 15 shows (e) (f) the first mask and 2 based on the positional error amount (nm) of the X coordinate and the Y coordinate of the second layer mask (gate layer layer mask) with respect to the reference lattice. It is the measurement data of the position error (nm) at the time of transfer to the wafer by the mask of the layer. The results of FIGS. 14 and 15 are summarized in Table 2.

  As shown in Table 2 (f), the position error of the pattern transferred by the first layer mask and the second layer mask is a relatively large value.

  FIG. 10 illustrates the results of Table 2 above, and is a diagram illustrating the positional error amount of the two masks of the comparative example according to the prior art and the positional error at the time of transfer.

(Differences between the examples of the present invention and comparative examples)
Table 3 shows an example of using the pattern data generation method of the present invention shown in Table 1 and a comparative example using the pattern data generation method using the conventional reference grid shown in Table 2 at the time of transfer. The position error (nm) of the coordinate and the Y coordinate is compared.

  FIG. 11 illustrates the results of Table 3 above, and is a diagram comparing the amount of positional error during transfer between the example of the present invention and the comparative example according to the prior art. By using the pattern data generation method of the present invention, the position error range is reduced to a ratio of about 0.6 for the X coordinate and about 0.8 for the Y coordinate as compared with the prior art.

  As shown in Table 3 and FIG. 11, by using a mask manufactured using the mask pattern data generation method according to the embodiment of the present invention, the mask pattern data generation method according to the comparative example of the prior art was manufactured. It has been shown that the overlay accuracy of pattern transfer onto the wafer is improved compared to using a mask.

21 Reference grid 22 Position measurement point 23 Position error 24 Second reference grid (effective reference grid)
51 Reference grid 52 Position measurement point 81 Reference grid 82 Position measurement point 91 Reference grid 92 Position measurement point 181 Reference grids 182a and 182b Position measurement point 183 Position error 191 Wafer 194 Aperture 195 Lens 196 Mask 197 Reduction lens

Claims (2)

A mask pattern data generation method for generating mask pattern data of a plurality of layers necessary for mask production from design data of a semiconductor device,
Selecting whether the predetermined layer of the design data is a reference layer or a reference layer that serves as a reference when superposing a plurality of layers;
In the layer selected as the reference layer,
Selecting a reference grid based on the design data of the layer that is the reference layer as a coordinate reference for mask drawing of the layer that is the reference layer, and converting the design data of the layer that is the reference layer into mask drawing data;
Using the mask drawing data, drawing a mask pattern of the layer that is the reference layer on a predetermined mask blank, processing the mask blank, and producing a mask of the layer that is the reference layer;
Measuring the positional accuracy of the mask pattern of the layer that is the reference layer of the produced mask, and setting the position coordinates of the mask pattern of the layer that is the reference layer as a second reference lattice, and
In the layer selected as not the reference layer,
Using the position information of the mask pattern of the layer that is the reference layer, the second reference grid is selected as the coordinate reference for mask drawing of the layer that is not the reference layer, and the design data of the layer that is not the reference layer is mask drawing data Converting to
Only including,
The mask pattern data generation method , wherein the reference layer is a plurality of reference layers of the same layer .   2. The mask pattern data generation method according to claim 1, wherein the layer selected as the reference layer is two layers in the design data of the semiconductor device.

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