JP5797534B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board for mounting a semiconductor integrated circuit element.

  Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting a semiconductor integrated circuit element. FIG. 7 is a schematic cross-sectional view showing an example of a conventional wiring board formed by the build-up method, and FIG. 8 is a schematic top view of the main part of the wiring board shown in FIG.

  As shown in FIG. 7, the conventional wiring board 30 has a plurality of buildup insulating layers 22 and buildup wiring layers 23 alternately stacked on the upper and lower surfaces of the core substrate 21, and a semiconductor integrated circuit at the center of the upper surface. A mounting portion 30a for mounting the circuit element S is provided.

  A core conductor layer 24 made of copper foil or a copper plating layer is deposited on the upper and lower surfaces of the core substrate 21. Also, a large number of through holes 25 are formed in a grid-like arrangement from the upper surface to the lower surface of the core substrate 21 to which a copper plating layer that functions as a part of the core conductor layer 24 is deposited.

  A plurality of via holes 26 are formed in each of the build-up insulating layers 22, and a build-up wiring layer 23 made of a copper plating layer is deposited on the surface of each build-up insulating layer 22 including the via holes 26. Yes. The build-up wiring layer 23 is electrically connected to the through-hole 25 while the upper and lower layers are connected to each other through the via hole 26. Further, a part of the buildup wiring layer 23 deposited on the surface of the outermost buildup insulating layer 22 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 30a. Circular semiconductor element connection pads 27 to be connected are formed, and these semiconductor element connection pads 27 are formed in a lattice shape corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. Yes. In addition, a part of the outermost buildup insulating layer 22 on the lower surface side that is attached to the surface is a circular external connection pad 28 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of pads 28 are formed in a lattice shape corresponding to the through holes 25 and arranged side by side.

  Further, a solder resist layer 29 for exposing the semiconductor element connection pads 27 and the external connection pads 28 is deposited on the outermost buildup insulating layer 22 and the buildup wiring layer 23 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 27, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 28 via the solder ball. Are electrically connected.

  By the way, the semiconductor integrated circuit element S is provided with a large number of electrode terminals T for grounding and power supply alternately in the central portion of the lower surface in order to ensure sufficient power supply from the wiring board 30 and on the outer peripheral portion of the lower surface. Increasing use is made of a terminal arrangement in which a large number of signal electrode terminals are provided. When such a semiconductor integrated circuit element S is mounted, the arrangement of the semiconductor element connection pads 27 on the wiring board 30 is also set at the center of the mounting portion 30a corresponding to the electrode terminal T of the semiconductor integrated circuit element S and for power supply. A large number of semiconductor element connection pads 27 are arranged, and a large number of signal semiconductor element connection pads 27 are arranged on the outer peripheral portion of the mounting portion 30a.

  FIG. 9 is a top view showing only the grounding and power supply semiconductor element connection pads 27 at the center of the mounting portion 30a. In FIG. 9, the uppermost buildup wiring layer 23 under the solder resist layer 29 is indicated by a broken line. In FIG. 9, the semiconductor element connection pad 27 indicated by G is a semiconductor element connection pad 27G for grounding, and the semiconductor element connection pad 27 indicated by P is a semiconductor element connection pad 27P for power supply. As shown in FIG. 9, the semiconductor element connection pads 27G for grounding and the semiconductor element connection pads 27P for power supply are alternately arranged in a grid-like arrangement so as to form a diagonal row. At the same time, the semiconductor element connection pads 27 in each row are integrated one by one as a band-like integrated pattern.

  Then, these semiconductor element connection pads 27 for grounding and power supply are electrically connected to the through holes 25 via the buildup wiring layer 23 and the core conductor layer 24 on the upper surface side as shown in FIG. Yes. FIG. 10 is a perspective view showing a part of the semiconductor element connection pads 27 in FIG. 9 and the corresponding build-up wiring layer 23 and core conductor layer 24 on the upper surface side in FIG. The position of the via 26 connected to the lower layer is shown, and the cross indicates the position where the via 26 from the upper layer is connected.

  The next build-up wiring layer 23 to which the semiconductor element connection pad 27 is connected is mainly a ground plane 23G, in which a via land 23L connected to the power supply semiconductor element connection pad 27P is arranged via a clearance 23C. It is installed. The via lands 23L are arranged in a one-to-one manner so as to form a row at a position corresponding to the power supply semiconductor element connection pad 27P of each row, and the clearance 23C of each row of the via land 23L is connected to one. Therefore, the ground plane 23G is in a state of being separated in a strip shape so as to correspond to each row of the grounding semiconductor element connection pads 27G by a single clearance 23C. The grounding semiconductor element connection pad 27G is connected to the band-shaped portion sandwiched by the clearance 23C of the ground plane 23G via the via 26 from each grounding semiconductor element connection pad 27G, and the semiconductor element connection for power supply The pads 27P are connected to the corresponding via lands 23L via the vias 26 on a one-to-one basis.

  The lower build-up wiring layer 23 is mainly a power plane 23P, and a via land 23L connected to the upper ground plane 23G is disposed therethrough via a clearance 23C. The via lands 23L are arranged in a one-to-one manner so as to form a row at a position corresponding to the grounding semiconductor element connection pad 27G in each row, and in the same manner as in the upper build-up wiring layer 23, each via land 23L has a row. The clearance 23C is connected to one. Therefore, the power supply plane 23P is in a state of being separated in a band shape so as to correspond to each row of the power supply semiconductor element connection pads 27 by a single clearance 23C. The upper ground plane 23G is connected to the via land 23L corresponding to the ground semiconductor element connection pad 27G via the via 26, and is connected to the power semiconductor element connection pad 27P. The via land 23L is connected to a band-like portion sandwiched by the clearance 23C of the power plane 23P via a via 26 from the upper via land 23L.

  The lower core conductor layer 24 is mainly a ground plane 24G, and the ground plane 24G is connected to a grounding through hole 25G and a through hole land 24L connected to a power supply through hole 25P therein. Is disposed via a clearance 24C. The upper via land 23L connected to the ground plane 23G is connected to the ground plane 24G via the via 26, and the upper power plane 23P is connected to the through-hole land 24L via the via 26. As a result, the grounding semiconductor element connection pad 27G is electrically connected to the grounding through hole 25G, and the power supply semiconductor element connection pad 27P is electrically connected to the power supply through hole 25P. Become.

  Further, as shown in FIG. 11, the grounding through hole 25G and the power supply through hole 25P are respectively connected to the grounding external connection pads via the core conductor layer 24 and the buildup wiring layer 23 on the lower surface side. 28G and the external connection pad 28P for power supply are electrically connected. 11 is a perspective view showing the core conductor layer 24 and the build-up wiring layer 23 on the lower surface side corresponding to FIG. 10, and the small circles in each layer indicate the positions of the vias 26 connected to the lower layer. , X indicates the position where the via 26 from the upper layer is connected.

  The core conductor layer 24 on the lower surface side is mainly a power plane 24P, and the power plane 24P is connected to a power through hole 25P and a through hole land 24L connected to a ground through hole 25G therein. Is disposed via a clearance 24C.

  The lower buildup wiring layer 23 is mainly a ground plane 23G, in which via lands 23L connected to the upper power supply plane 24P are arranged via a clearance 23C. The power plane 24P in the core conductor layer 24 on the lower surface side is connected to the via land 23L via the via 26, and the through-hole land 24L is connected to the ground plane 23G via the via 26.

  The lower build-up wiring layer 23 is mainly a power plane 23P, and a via land 23L connected to the upper ground plane 23G via a via 26 is disposed therethrough via a clearance 23C. The via land 23L in the upper buildup wiring layer 23 is connected to the power supply plane 23P via the via 26.

  The outermost buildup wiring layer 23 on the lower surface side is mainly a ground plane 23G, and has a region to be an external connection pad 28G for grounding, and the external connection pad 28P for power supply has a clearance 23C. It is arranged via. The ground plane 23G forming the ground external connection pad 28G is connected to the upper via land 23L via the via 26, and the power external connection pad 28P is connected to the upper power plane 23P via the via 26. Has been.

  With the connection as described above, the grounding through hole 25G and the corresponding grounding external connection pad 28G and the power supply throughhole 25P are electrically connected to the corresponding power supply external connection pad 28P. Is done. The via 26 and the via land 23L that connect the grounding through hole 25G, the corresponding grounding external connection pad 28G and the power supply throughhole 25P, and the corresponding power supply external connection pad 28P are: Each of the four via holes 25G and 25P is connected to the corresponding external connection pads 28G and 28P, and four via lands 23L of each set are formed independently.

  However, since the pitch of the through holes 25 is generally larger than the pitch of the semiconductor element connection pads 27, for example, a row of power supply semiconductor element connection pads 27P indicated by an arrow A in FIG. 9 is taken as an example. The power through-hole 25P is not located below the band-like portion of the power plane 23P connected to the semiconductor element connection pad 27P in this column. As a result, in this portion, the current path to the power supply through hole 25P largely bypasses the clearance 23C of the power supply plane 23P. Since a large number of vias 26 for connection to the power source semiconductor element connection pads 27P of the column A are connected to this portion, a large current flows in a concentrated manner in this largely detoured current path. As a result, sufficient power cannot be supplied to the semiconductor element connection pads 27P for power supply in the column A through this current path, and good operation of the semiconductor integrated circuit element S is impaired.

  Therefore, the applicant of the present application previously described in Japanese Patent Application No. 2010-2222989 a core having a plurality of first through holes connected to the first potential and a plurality of second through holes connected to the second potential. An insulating substrate formed by laminating a plurality of insulating layers having at least a first insulating layer on the upper surface of the substrate, and one or a plurality of them alternately arranged in a grid pattern on the upper surface of the insulating substrate. A first pad group electrically connected to the first through hole and a second pad group electrically connected to the second through hole; and the first pad group A first layer disposed between insulating layers and electrically connected to the first pad group via a first via group connected to a position corresponding to each column of the first pad group. Each of the power plane and the second pad group And a via land group that is electrically connected to the second pad group through a second via group connected to a position corresponding to the first power plane and surrounded by the first power plane through a clearance. A wiring board, wherein a plurality of adjacent via groups in the second via group form a plurality of via groups gathered at a pitch narrower than the pitch of the second pad, and the adjacent via groups The first power plane is interposed between the connected via lands, and conduction from each column of the first pad group to the first through hole through the first power plane between the via lands. A wiring board on which a path was formed was proposed.

According to the wiring board proposed in Japanese Patent Application No. 2010-222989, in the above configuration, a plurality of via groups in which the plurality of adjacent vias in the second via group are gathered together at a pitch narrower than the pitch of the second pads are arranged. The first power supply plane is interposed between via lands connected to the adjacent via group, and the first pad group is formed through the first power supply plane between the via lands. Since a conductive path from each row to the first through hole is formed, a large number of power supply paths from the first through hole to the first pad are secured, which is sufficient for the semiconductor integrated circuit element. The semiconductor integrated circuit device can be operated satisfactorily by supplying a sufficient power.

  However, in the wiring board proposed in Japanese Patent Application No. 2010-222989, the current path on the upper surface side of the core substrate is considered, but the power supply on the lower surface side of the core substrate is not considered. In the future, in order to suppress the power consumption of the semiconductor integrated circuit element, the operating voltage of the semiconductor integrated circuit element is expected to become increasingly lower. In a wiring board on which such a semiconductor integrated circuit element having a low operating voltage is mounted, it is necessary to further improve the power supply characteristics.

JP 2011-159773 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board capable of satisfactorily operating a semiconductor integrated circuit element by sufficiently supplying power even to a semiconductor integrated circuit element having a low operating voltage. .

A wiring substrate according to the present invention includes a core substrate having a plurality of first through holes connected to a first potential and a plurality of second through holes connected to a second potential, and upper and lower surfaces of the core substrate. A plurality of build-up insulating layers stacked in layers, and a plurality of layers arranged alternately in a grid pattern on the surface of the uppermost uppermost build-up insulating layer. A first semiconductor element connection pad electrically connected to the first through hole and a second semiconductor element connection pad electrically connected to the second through hole; Electrically connected to the first semiconductor element connection pad via a first via group disposed between the build-up insulating layers and connected to a position corresponding to each column of the first semiconductor element connection pad. Connected first power supply pre And electrically connected to the second semiconductor element connection pad through a second via group connected to a position corresponding to each column of the second semiconductor element connection pad and via a clearance. The via land group surrounded by the first power plane and the surface of the build-up insulating layer on the outermost surface on the lower surface side are arranged corresponding to the first through hole and electrically connected to the first through hole. A first external connection pad and a second external connection pad disposed corresponding to the second through hole and electrically connected to the second through hole, and a lower surface side The first or second via the plurality of sets of third vias disposed between the build-up insulating layers and connected to a position corresponding to one of the first or second external connection pads. Via a second power supply plane electrically connected to one of the external connection pads and a plurality of sets of fourth vias connected to positions corresponding to the other of the first or second external connection pads A wiring board having a second via land connected to the other of the first or second external connection pads and surrounded by the second power plane through a clearance. A plurality of adjacent via groups in the via group form a plurality of via groups gathered at a pitch narrower than the pitch of the second semiconductor element connection pads, and between via lands connected to the adjacent via groups. The first power plane is interposed between the first semiconductor element connection pads and the first power plane through the first power plane between the via lands. A conductive path to one through hole is formed, and the second via land is connected to one portion corresponding to the set of the fourth vias. .

According to the wiring board of the present invention, in the above configuration, a plurality of via groups in which a plurality of adjacent ones in the second via group are gathered together at a pitch narrower than the pitch of the second semiconductor element connection pads are formed. And the first power plane is interposed between the via lands connected to the adjacent via groups, and the first semiconductor element connection pads are connected through the first power plane between the via lands. Since a conductive path from each row to the first through hole is formed, a large number of power supply paths from the first through hole to the first semiconductor element connection pad can be secured. Further, since the second via land corresponds to one set of the fourth via, the second via land is connected to the first via hole through the second via land. Power supply to the external connection pads can be performed satisfactorily. Therefore, it is possible to satisfactorily operate the semiconductor integrated circuit element by supplying sufficient power to the semiconductor integrated circuit element operating at a low voltage.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 3 is an enlarged view of a main part of FIG. FIG. 4 is an exploded perspective view of main parts of the wiring board shown in FIGS. 1 and 2. FIG. 5 is an exploded perspective view of a main part of the wiring board shown in FIGS. 1 and 2. FIG. 6 is an enlarged view of a main part of FIG. FIG. 7 is a schematic sectional view showing a conventional wiring board. FIG. 8 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 9 is an enlarged view of a main part of FIG. FIG. 10 is an exploded perspective view of the main part of the wiring board shown in FIGS. FIG. 11 is an exploded perspective view of a main part of the wiring board shown in FIGS.

  Next, an example of an embodiment of the wiring board according to the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of the wiring board of this example formed by the build-up method, and FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. 3 is an enlarged view of a main part in FIG. 2, and FIGS. 4 and 5 are exploded perspective views of the main part of the wiring board shown in FIGS. 1 and 2, respectively. Further, FIG. 6 is an enlarged view of a main part of FIG.

  As shown in FIG. 1, a wiring board 10 of this example has build-up insulating layers 2 and build-up wiring layers 3 alternately stacked on the upper and lower surfaces of a core substrate 1, and a semiconductor integrated circuit element at the center of the upper surface. A mounting portion 10a for mounting S is provided.

  The core substrate 1 has a thickness of about 50 to 800 μm, and is made of an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. A large number of core conductor layers 4 made of copper foil or copper plating layers are deposited on the upper and lower surfaces, and copper plating layers that function as a part of the core conductor layers 4 are deposited from the upper surface to the lower surface of the insulating substrate. A through hole 5 is formed. The diameter of the through hole 5 is about 100 to 300 μm, and the inside is filled with resin.

  The build-up insulating layer 2 is made of an insulating material containing a thermosetting resin such as an epoxy resin, and a plurality of via holes 6 are formed in each, and the surface of each build-up insulating layer 2 including the via holes 6 is plated with copper. A build-up wiring layer 3 composed of layers is deposited. The build-up wiring layer 3 is electrically connected to the through hole 5 while being connected to each other through the via hole 6. Further, a part of the buildup wiring layer 3 deposited on the outermost buildup insulating layer 2 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 10a. The circular semiconductor element connection pads 7 are formed, and these semiconductor element connection pads 7 are formed in a lattice arrangement corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . The semiconductor element connection pads 7 have a large number of grounding and power supply semiconductor element connection pads 7 arranged at the center of the mounting part 10a, and a large number of signal semiconductor element connection pads 7 arranged at the outer periphery of the mounting part 10a. ing. Also, a part of the lower surface side deposited on the outermost buildup insulating layer 2 is a circular external connection pad 8 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of grids 8 are formed in a grid.

  Further, a solder resist layer 9 for exposing the semiconductor element connection pads 7 and the external connection pads 8 is deposited on the outermost buildup insulating layer 2 and the buildup wiring layer 3 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 9, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 8 via the solder ball. Are electrically connected.

  FIG. 3 shows only the grounding and power supply semiconductor element connection pads 7 in the center of the mounting portion 10a. In FIG. 3, the uppermost buildup wiring layer 3 under the solder resist layer 9 is indicated by a broken line. In FIG. 3, the semiconductor element connection pad 7 indicated by G is a semiconductor element connection pad 7G for grounding, and the semiconductor element connection pad 7 indicated by P is a semiconductor element connection pad 7P for power supply. As shown in FIG. 3, the semiconductor element connection pads 7G for grounding and the semiconductor element connection pads 7P for power supply are alternately arranged in a grid-like arrangement so as to form diagonal rows. At the same time, the semiconductor element connection pads 7 in each row are integrated as a single band-like pattern one row at a time.

  These grounding semiconductor element connection pads 7G and power supply semiconductor element connection pads 7P are electrically connected to the through holes 5 through the underlying buildup wiring layer 3 as shown in FIG. Yes. FIG. 4 is a perspective view showing a part of the semiconductor element connection pads 7 in FIG. 3 and the corresponding build-up wiring layer 3 and core conductor layer 4 corresponding to the extracted semiconductor element connection pads 7. The position of the via 6 to be connected to is indicated, and the mark x indicates the position to which the via 6 from the upper layer is connected. By the way, in this example, as shown in the plan view of the main part in FIG. 6, two vias 6 connected to each semiconductor element connection pad 7 are provided in each row of the semiconductor element connection pads 7. A plurality of via groups 6A are formed by gathering at a pitch P2 narrower than the pitch P1 of 7. For this reason, the gaps between the via groups 6A are wider than the pitch P1 of the semiconductor element connection pads 7.

  The next build-up wiring layer 3 to which the semiconductor element connection pad 7 is connected is mainly the ground plane 3G, in which the via land 3L connected to the semiconductor element connection pad 7P for power supply via the via group 6A is provided. It is disposed via a clearance 3C. The via lands 3L are arranged in rows corresponding to the via groups 6A connected to the power supply semiconductor element connection pads 7P in each row, and the clearance 3C of each row is grounded between the via lands 3L. The planes 3G are independent so as to intervene. For this reason, the ground plane 3G is connected to one another so as to pass between the clearances 3C surrounding the via land 3L. In such a configuration, the pitch P2 of the vias 6 in the via group 6A is narrower than the pitch P1 of the semiconductor element connection pads 7, and the interval between the via groups 6A is wider than the pitch P1 of the semiconductor element connection pads 7. Thus, it is realized by securing a sufficient area for interposing the ground plane 3G between the via lands 3L connected to each via group 6A. On the other hand, the grounding semiconductor element connection pads 7G are connected to the power supply plane 3G via via groups 6A connected to the semiconductor element connection pads 7G in each column. Further, the via group 6B arranged at the same pitch as the via group 6A at a position slightly deviated from the via group 6A from the via land 3L and the ground plane 3G in the buildup wiring layer 3 is a buildup wiring layer 3 below the via group 6A. It is formed so as to connect to.

  The lower build-up wiring layer 3 is mainly a power plane 3P, and a via land 3L connected to the upper ground plane 3G via a via group 6B is disposed via a clearance 3C. The via lands 3L are arranged in rows at positions corresponding to the via groups 6B connected to the grounding semiconductor element connection pads 7G in each row, and the clearance 3C of each row has a power supply between the via lands 3L. It is independent so that the plane 3P is interposed. Therefore, the power planes 3P are connected together so as to pass between the clearances 3C surrounding the via land 3L. In such a configuration, the pitch P2 of the vias 6 in the via group 6B is narrower than the pitch P1 of the semiconductor element connection pads 7, and the interval between the via groups 6B is wider than the pitch P1 of the semiconductor element connection pads 7. Thus, it is realized by securing a sufficient area for interposing the power supply plane 3G between the via lands 3L connected to each via group 6B. On the other hand, the power plane 3P is connected to an upper via land 3L via a via group 6B.

  The lower core conductor layer 4 is mainly a ground plane 4G. The ground plane 4G is connected to a grounding through hole 5G, and a through hole land 4L connected to a power supply through hole 5P therein. Is disposed via a clearance 4C. The upper via land 3L connected to the ground plane 3G is connected to the ground plane 4G via the via 6, and the upper power plane 3P is connected to the through-hole land 4L via the via 6. As a result, the grounding semiconductor element connection pad 7G is electrically connected to the grounding through hole 5G, and the power supply semiconductor element connection pad 7P is electrically connected to the power supply through hole 5P. Become.

  Further, as shown in FIG. 5, the grounding through-hole 5G and the power-supplying through-hole 5P are respectively connected to the grounding external connection pads via the core conductor layer 4 and the buildup wiring layer 3 on the lower surface side. 8G and the external connection pad 8P for power supply are electrically connected. FIG. 5 is a perspective view showing the core conductor layer 4 and the build-up wiring layer 3 on the lower surface side corresponding to FIG. 4, and the small circles in each layer indicate the positions of the vias 6 connected to the lower layer. , X indicates the position where the via 6 from the upper layer is connected.

  The core conductor layer 4 on the lower surface side is mainly a power plane 4P, and the power plane 4P is connected to a power through hole 5P and a through hole land 4L connected to a ground through hole 5G therein. Is disposed via a clearance 4C.

  The lower buildup wiring layer 3 is mainly a ground plane 3G, in which via lands 3L connected to the upper power supply plane 4P are arranged via a clearance 3C. The power plane 4P in the core conductor layer 4 on the lower surface side is connected to the via land 3L via the via 6, and the through-hole land 4L is connected to the ground plane 3G via the via 6.

  The lower build-up wiring layer 3 is mainly a power plane 3P, and a via land 3L connected to the upper ground plane 3G via a via 6 is disposed via a clearance 3C. The via land 3L in the upper buildup wiring layer 3 is connected to the power plane 3P via the via 6.

  The outermost buildup wiring layer 3 on the lower surface side is mainly a ground plane 3G, and has a region to be an external connection pad 8G for grounding, and the external connection pad 8P for power supply has a clearance 3C. It is arranged via. The ground plane 3G forming the external connection pad 8G for grounding is connected to the upper via land 3L via the via 6, and the external connection pad 8P for power supply is connected to the upper power plane 3P via the via 6. Has been.

  With the connection as described above, the grounding through hole 5G and the corresponding grounding external connection pad 8G and the power supply throughhole 5P are electrically connected to the corresponding power supply external connection pad 8P. Is done. Each of the grounding through hole 5G and the corresponding grounding external connection pad 8G and the power supply throughhole 5P and the corresponding power supply external connection pad 8P have four vias 6 respectively. Each of the through holes 5G, 5P and the corresponding external connection pads 8G, 8P are connected as a set. In the present invention, the via land 3L connected to each set of four vias is formed in a pattern in which the portions corresponding to the four vias are connected to one. As a result, the current path is well distributed between the four vias 6 connected to the via land 3L via the via land 3L.

In the wiring board of this example, as described above, the pitch P2 of the vias 6 in the via group 6B connected from the upper ground plane 3G to the ground via land 3L provided in the power plane 3P is set to the semiconductor. By making the interval between the via groups 6B wider than the pitch P1 of the semiconductor element connection pads 7 as being narrower than the pitch P1 of the element connection pads 7, the via lands 3L connected to the adjacent via groups 6B It is important that the power plane 3P is interposed between the two. With such a configuration, a conductive path is formed from each column of the pad group of the semiconductor element connection pads 7P for power supply to the through hole 5P for power supply through the power supply plane 3P between the via lands 3L. Further, the via land 3L provided in the ground plane 3G or the power plane 3P in the build-up wiring layer 3 on the lower surface side is connected to one via land corresponding to the four vias 6. The power supply from the through holes 5G, 5P to the external connection pads 8G, 8P through 3L can be satisfactorily performed. Therefore, the semiconductor integrated circuit element S can be satisfactorily operated by supplying sufficient power to the semiconductor integrated circuit element S operating at a low voltage.

  According to the result of the simulation performed by the present inventor using the DC current density simulator, the analysis model using the wiring board 10 in the present application is more semiconductor than the analysis model using the wiring board 10 in the previously filed Japanese Patent Application No. 2010-2222989. It was confirmed that the voltage drop when a transient current flows in the power supply to the integrated circuit element S was improved by about 15%. Needless to say, the present invention is also applied to the case where the grounding potential and the power supply potential are interchanged. Further, the same structure as the build-up wiring layer 3 on the lower surface side of the present application may be applied to the build-up wiring layer 13 on the lower surface side of the wiring board 20 in Japanese Patent Application No. 2010-222989 filed earlier. In this case as well, the voltage drop when a transient current flows in the power supply to the conductor integrated circuit element S can be similarly improved by about 15%.

  By the way, the same structure as the build-up wiring layer 3 on the lower surface side of the wiring board 10 of the present application is applied to the analysis model of the wiring board 30 which is the prior art of the present application and the build-up wiring layer 23 on the lower surface side of the wiring board 30. In the analysis model, the voltage drop when a transient current flows in the power supply to the semiconductor integrated circuit element S was improved only by 0.3%. Therefore, when a current path in the build-up wiring layer on the upper surface side is not sufficiently secured, the semiconductor integrated circuit element can be applied even if the same structure as the build-up wiring layer 3 on the lower surface side in the wiring substrate 10 of the present application is applied. It can be seen that the voltage drop when the transient current flows in the power supply to S can hardly be improved.

DESCRIPTION OF SYMBOLS 1 Core substrate 2 Build-up insulating layer 3 Build-up wiring layer 3L Via land 3C Clearance 5 Through hole 5G Ground through hole 5P Power through hole 6 Via 7 Semiconductor element connection pad 7G Ground semiconductor element connection pad 7P For power supply Semiconductor device connection pad 8 External connection pad 8G External connection pad for grounding 8P External connection pad for power supply

Claims (1)

A core substrate having a plurality of first through holes connected to the first potential and a plurality of second through holes connected to the second potential, and a plurality of layers are laminated on the upper and lower surfaces of the core substrate. A large number of build-up insulating layers and a plurality of one-by-one in a lattice-like arrangement are arranged on the surface of the uppermost layer of the build-up insulating layer on the upper surface side so as to be alternately arranged. A first semiconductor element connection pad electrically connected to the through hole, a second semiconductor element connection pad electrically connected to the second through hole, and the buildup insulating layer on the upper surface side. And a first power supply electrically connected to the first semiconductor element connection pad via a first via group connected to a position corresponding to each column of the first semiconductor element connection pad. Plain and said second The first power supply plane is electrically connected to the second semiconductor element connection pad via a second via group connected to a position corresponding to each row of the conductor element connection pads and via a clearance. A via land group surrounded by the first through hole and a surface of the buildup insulating layer on the outermost surface on the lower surface side corresponding to the first through hole and electrically connected to the first through hole. Between the second external connection pad disposed corresponding to the first external connection pad and the second through hole and electrically connected to the second through hole, and the build-up insulating layer on the lower surface side The first or second external connection pad is disposed through a plurality of sets of third vias that are arranged and connected to positions corresponding to one of the first or second external connection pads. Through the second power supply plane electrically connected to the other side and the plurality of sets of fourth vias connected to positions corresponding to the other of the first or second external connection pads. A wiring board having a second via land connected to the other of the second external connection pads and surrounded by the second power plane through a clearance, and adjacent to the second via group. A plurality of via groups are formed such that each of the plurality of via groups gathers at a pitch narrower than the pitch of the second semiconductor element connection pads, and the first land is connected between the via lands connected to the adjacent via groups. A power plane is interposed, and each row of the first semiconductor element connection pads is connected to the first through hole through the first power plane between the via lands. A wiring board characterized in that a conductive path is formed, and the second via land is connected to one portion corresponding to the set of the fourth vias.

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