JP5782510B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a dynamic circuit.

  Conventionally, a semiconductor memory device as shown in FIG. 15 is known as a semiconductor integrated circuit. In this semiconductor memory device, one of a plurality of word lines WL <0>... WL <n> (n is an integer of 1 or more) is selected by the word driver 600, and the selected word line becomes active. As a result, the data in the memory cell 610 is output to the bit lines BIT <0> and NBIT <0>. The data output to the bit lines BIT <0> and NBIT <0> is amplified by the sense amplifier 620 and output to the outside as the output signal DO <0>. Which word line is selected is determined by the address signal Address and the output of the row decoder 630. If noise occurs in the output of the row decoder 630, there is a possibility that the word line is selected multiple times. When a plurality of word lines are selected, data output from the memory cells 610 connected to each word line collide with each other on the bit line, so that the semiconductor memory device malfunctions.

  In the row decoder, a dynamic circuit is often used for speeding up the output, but using the dynamic circuit has a drawback that noise tends to occur in the output. Therefore, in order to reduce noise generated in the output of the row decoder, there is a row decoder using a dynamic circuit provided with a holding circuit that holds the voltage of the output node (see, for example, Patent Document 1).

JP 2003-318727 A

  In recent years, due to changes in technological trends in semiconductor memory devices, semiconductor memory devices in which noise generated in the output of a decoder is allowed to some extent are being used. For example, as shown in FIG. 16, global bit lines GBL <0>, NGBL <0> and local bit lines LBL <0>, NLBL <0> in the bank 640 are connected via a bank selection circuit 650. A semiconductor memory device having a hierarchical bit line structure is known.

  This semiconductor memory device is configured not to malfunction even when an unselected word line WL_BLK1_ <0> other than the selected word line WL_BNK0_ <0> becomes active due to noise generated at the output of the bank decoder 660. Even when the non-selected word line WL_BLK1_ <0> becomes active, the bank selection signal BNK <1> is not affected by noise, so the bank selection circuit 650 does not operate and the local bit connected to the non-selected bank. This is because the lines LBL <0> and NLBL <0> are not connected to the global bit lines GBL <0> and NGBL <0>.

  In such a semiconductor memory device, although output noise of the decoder is allowed to some extent, there is a possibility of malfunction if the output becomes an error. Therefore, it seems effective to use the semiconductor integrated circuit of Patent Document 1 for the decoder of the semiconductor memory device. However, using the technique of Patent Document 1, it is possible to reduce the noise of the output signal, but it is possible to increase the speed of the output signal such that the timing of the logic transition of the output signal is delayed or the speed of the logic transition is delayed. Be disturbed. As a result, problems such as a slow reading speed of data from the memory cell occur in the semiconductor memory device.

  In view of the above, it is an object of the present invention to quickly remove noise in an output signal and to increase the speed of the output signal in a semiconductor integrated circuit.

  In order to solve the above problems, the present invention has taken the following solutions. For example, the semiconductor integrated circuit includes a first dynamic circuit that receives a plurality of input signals and a first clock signal and controls a level of the first dynamic node, a second dynamic node, and a first power supply. A first transistor, which is provided between the first dynamic node and the conduction of which is controlled according to the level of the first dynamic node; and between the second dynamic node and the first power supply; A second transistor whose conduction is controlled in accordance with a second clock signal; and a second dynamic circuit that outputs an output signal having a logic value corresponding to a level of the second dynamic node. When the plurality of input signals are in the first state, the first dynamic circuit maintains the level of the first dynamic node at the first level for conducting the first transistor, while the plurality of input signals are In the second state other than the first state, the level of the first dynamic node is set to the first level in accordance with the first clock signal and the second level that does not cause the first transistor to conduct. Switch to. The second dynamic circuit is provided between the second dynamic node and the second power supply, the plurality of input signals are in the second state, and the level of the first dynamic node is other than the first level. The second dynamic node is connected to the second power source to compensate the level of the second dynamic node.

  According to this, when the first and second transistors are turned on, the second dynamic node is connected to the first power supply. The first transistor is turned off when the level of the first dynamic node is the second level. The compensation circuit operates when the plurality of input signals are in the second state and the level of the first dynamic node is other than the first level, and the second dynamic node, the second power source, Connect.

  Here, it is assumed that the level of the second dynamic node is the level indicated by the second power supply, and the second transistor is in a conductive state. In this case, if the plurality of input signals are in the second state, the first transistor is conductive until the level of the first dynamic node is completely switched from the first level to the second level. The second dynamic node is connected to the first power source. Therefore, the level of the second dynamic node changes. At this time, since the level of the first dynamic node is in a state between the first and second levels, the compensation circuit operates to compensate the level of the second dynamic node. Therefore, the level of the second dynamic node immediately returns to the state before the change. In other words, noise generated by the change in the level of the second dynamic node is removed in a short time, so that the output signal does not cause an error.

  Further, when the first and second transistors are in a conductive state and the second dynamic node and the first power supply are connected, the compensation circuit does not operate. In this case, since the voltage is not supplied from the second power source to the second dynamic node, the level of the second dynamic node is indicated by the first power source from the level indicated by the second power source. It takes less time to switch to a higher level. That is, the timing at which the logical value of the output signal changes becomes earlier, and the speed of the change can be increased.

  Preferably, the semiconductor integrated circuit is provided between the first dynamic node and the second power supply, and when the level of the first dynamic node is the first level, the level of the first dynamic node Is held at the first level.

  According to this, it is possible to suppress the level of the first dynamic node from slightly changing from the first level due to the occurrence of noise or the like in the first dynamic node. Therefore, since the conduction state of the first transistor can be stabilized, the time until the level of the second dynamic node changes from the level indicated by the second power supply to the level indicated by the first power supply is shortened. can do. As a result, the output signal can be further increased in speed.

  According to the present invention, noise in the output signal can be quickly removed and the output signal can be speeded up.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit according to the first embodiment. FIG. 3 is a circuit diagram showing a comparative example of the semiconductor integrated circuit of the first embodiment. FIG. 4 is a timing chart showing the operation of the semiconductor integrated circuit of FIG. FIG. 5 is a timing chart showing another operation of the semiconductor integrated circuit of FIG. FIG. 6 is a circuit diagram showing a modification of the semiconductor integrated circuit according to the first embodiment. FIG. 7 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment. FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment. FIG. 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment. FIG. 10 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment. FIG. 11 is a circuit diagram showing a modification of the semiconductor integrated circuit according to the fifth embodiment. FIG. 12 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the sixth embodiment. FIG. 13 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the seventh embodiment. FIG. 14 is a circuit diagram showing a modification of the semiconductor integrated circuit according to the seventh embodiment. FIG. 15 is a circuit diagram showing a configuration of a general semiconductor memory device. FIG. 16 is a circuit diagram showing a configuration of a semiconductor memory device having a hierarchical bit line structure.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment. The semiconductor integrated circuit of FIG. 1 is an address decoder, for example, and outputs a signal OUT having a desired logical value in response to a plurality of input address signals. Specifically, when the address signals AD [0], AD [1], and AD [2] are all LOW (first state) and the clock signal CLK changes from LOW to HIGH, the output signal OUT changes from LOW. Change to HIGH. On the other hand, if any one of the address signals AD [0], AD [1], AD [2] is HIGH (second state), the output signal OUT is kept LOW. The address decoder includes a first dynamic circuit 10, an NMOS transistor TJ1 as a first transistor, an NMOS transistor TD2 as a second transistor, a second dynamic circuit 20, a holding circuit 30, and an inverter 40. And.

  The first dynamic circuit 10 can be composed of a first precharge circuit 100 that precharges the first dynamic node ML1, an NMOS parallel circuit 110, and an NMOS transistor TD1.

  The first precharge circuit 100 includes a PMOS transistor TPC1 that is connected between a power supply voltage that is a second power supply and the first dynamic node ML1 and that is conductively controlled in synchronization with the clock signal CLK.

  The NMOS parallel circuit 110 is connected between the first dynamic node ML1 and the NMOS transistor TD1, and is NMOS transistor whose conduction is controlled according to the address signals AD [0], AD [1], AD [2]. It has TIN1, TIN2, and TIN3.

  The NMOS transistor TD1 is connected between the NMOS parallel circuit 110 and the ground potential which is the first power supply, and is conduction controlled in synchronization with the clock signal CLK.

  As described above, in the first dynamic circuit 10, when the address signals AD [0], AD [1], AD [2] are all LOW, the level of the first dynamic node ML1 is HIGH (first Level). On the other hand, when any one of the address signals AD [0], AD [1], and AD [2] is HIGH, the first dynamic node ML1 is LOW (second output) when the clock signal CLK is HIGH. Level) and becomes HIGH when the clock signal CLK becomes LOW.

  The NMOS transistors TJ1 and TD2 are connected in series between the second dynamic node ML2 and the ground potential. The NMOS transistor TJ1 is conductively controlled according to the level of the first dynamic node ML1. The NMOS transistor TD2 is conduction controlled in synchronization with the clock signal CLK. The NMOS transistor TJ1 may be connected between the second dynamic node ML2 and the NMOS transistor TD2.

  The second dynamic circuit 20 includes a second dynamic node ML2, a compensation circuit 200, and a second precharge circuit 210. The compensation circuit 200 can be configured by a PMOS transistor TECU, which is a third transistor, connected between the power supply voltage and the second dynamic node ML2. The PMOS transistor TECU is subjected to conduction control in response to the result of logical operation of the address signals AD [0], AD [1], AD [2] by the NOR circuit 202. That is, the PMOS transistor TECU is turned on when any one of the address signals AD [0], AD [1], and AD [2] is HIGH.

  The second precharge circuit 210 precharges the second dynamic node ML2 to HIGH. For example, the second precharge circuit 210 is connected between the power supply voltage and the second dynamic node ML2, and is synchronized with the clock signal CLK. , A PMOS transistor TPC2 whose conduction is controlled.

  The holding circuit 30 can be composed of three PMOS transistors 306 to 310 connected in series between the power supply voltage and the first dynamic node ML1. The PMOS transistors 306, 308, and 310, which are the fifth transistors, are conduction controlled in accordance with the address signals AD [0], AD [1], and AD [2], respectively. Each of the PMOS transistors 306 to 310 only needs to be connected in series. Further, the fifth transistor may be composed of one PMOS transistor. In this case, the output of the NOR circuit that receives the address signals AD [0], AD [1], AD [2] may be input to the gate of the PMOS transistor.

  The inverter 40 outputs an output signal OUT having a logical value obtained by inverting the level of the second dynamic node ML2.

  Next, the operation of the address decoder shown in FIG. 1 will be described with reference to FIG. It is assumed that any one of the address signals AD [0], AD [1], and AD [2] is HIGH during the period from the time t0 to the time t2, and all of them are LOW during the other periods. That is, during the period from time t0 to time t2, the address is missed, and after time t2, the address is hit.

  Prior to time t0, the NMOS transistors TIN1, TIN2, and TIN3 are all non-conductive. Before time t0, since the clock signal CLK is LOW, the NMOS transistor transistors TD1 and TD2 are in a non-conductive state, and the PMOS transistors TPC1 and TPC2 are in a conductive state. Accordingly, the first and second dynamic nodes ML1 and ML2 are precharged to HIGH, respectively. As a result, the output signal OUT is LOW. Further, since the first dynamic node ML1 is kept HIGH, the NMOS transistor TJ1 is in a conductive state.

  When the clock signal CLK becomes HIGH at time t0, the NMOS transistor TD1 becomes conductive. At time t0, any one of the NMOS transistors TIN1, TIN2, and TIN3 is turned on. Accordingly, the first dynamic node ML1 is discharged from HIGH to LOW. Almost at the same time, the NMOS transistor TD2 becomes conductive, so that the second dynamic node ML2 starts to be discharged. As a result, the charge of the second dynamic node ML2 is extracted, so that the level becomes LOW, and noise is generated in the second dynamic node ML2. As a result, noise appears in the output signal OUT.

  When the level of the first dynamic node ML1 changes from HIGH to LOW, the NMOS transistor TJ1 is turned off, and the discharge of the second dynamic node ML2 is stopped. Further, since any one of the address signals AD [0], AD [1], and AD [2] is HIGH during the period from the time t0 to the time t2, the power supply voltage is applied to the second dynamic node ML2 by the compensation circuit 200. Is supplied. As a result, since the level of the second dynamic node ML2 is compensated and returns to HIGH immediately, noise is eliminated in a short time. That is, even if noise occurs in the second dynamic node ML2, the output signal OUT does not cause an error.

  When the clock signal CLK becomes LOW at time t1, the NMOS transistors TD1 and TD2 are turned off, so that the levels of the first and second dynamic nodes ML1 and ML2 are both maintained high.

  When the address signals AD [0], AD [1], and AD [2] are all LOW at time t2, all of the NMOS transistors TIN1, TIN2, and TIN3 are turned off. Then, since the NMOS transistor TD2 becomes conductive, the discharge of the second dynamic node ML2 is started. At this time, since the address signals AD [0], AD [1], and AD [2] are all LOW, the compensation circuit 200 does not operate. Accordingly, since the second dynamic node ML2 is discharged smoothly, the level immediately becomes LOW. That is, the timing at which the output signal OUT undergoes a logic transition and the speed of the logic transition increase. Thereafter, while the address is hit, the second dynamic node ML2 and the output signal OUT logically transition according to the clock signal CLK.

  FIG. 3 is a circuit diagram showing a configuration of an address decoder which is a comparative example of FIG. The common reference numerals in FIG. 1 and FIG. 3 indicate the same components, and the description thereof is omitted.

  In FIG. 3, the NMOS transistor TKP1 corresponds to the holding circuit 30 shown in FIG. In the configuration of FIG. 3, the connection order of the NMOS transistors TJ1 and TD2 is opposite to that of the configuration of FIG. Further, in the configuration of FIG. 3, a holding circuit 220 for holding the level of the second dynamic node ML2 is provided instead of the compensation circuit 200 shown in FIG. The holding circuit 220 is the same as the circuit employed in the configuration disclosed in Patent Document 1, and is intended to reduce noise generated in the second dynamic node ML2. Specifically, the holding circuit 220 includes a PMOS transistor TKP2 that is connected between the power supply voltage and the second dynamic node ML2 and that is controlled to be conductive according to the output of the inverter 40. The advantages of the configuration of FIG. 1 regarding these differences will be described later.

  In the address decoder shown in FIG. 3, the noise generated in the second dynamic node ML2 can be further reduced by increasing the size of the PMOS transistor TKP2. Here, the operation when the size of the NMOS transistor TKP2 is increased will be described with reference to FIG. In FIG. 4, the states of the address signals AD [0], AD [1], AD [2] and the timing at which the clock signal CLK logically transitions are the same as in FIG.

  Since the clock signal CLK is LOW until time t0, the first and second dynamic nodes ML1 and ML2 are each precharged to HIGH. Therefore, the output signal OUT is LOW. Both the PMOS transistor TKP2 and the NMOS transistor TJ1 are in a conductive state.

  When the clock signal CLK becomes HIGH at time t0, the first and second dynamic nodes ML1 and ML2 are discharged. The second dynamic node ML2 is discharged until the level of the first dynamic node ML1 becomes LOW. However, since the PMOS transistor TKP2 is conductive, the change of the second dynamic node ML2 is small. Eventually, when the level of the first dynamic node ML1 becomes LOW and the NMOS transistor TJ1 becomes non-conductive, the discharge of the second dynamic node ML2 is stopped and the level returns to the original level. Thus, since the level change of the second dynamic node ML2 is small and level inversion does not occur, no noise appears in the output signal OUT.

  When the clock signal CLK becomes LOW at time t1, the NMOS transistors TD1 and TD2 become non-conductive, so that the level of the first dynamic node ML1 becomes HIGH and the level of the second dynamic node ML2 remains HIGH. Maintained. Since the second dynamic node ML2 is HIGH, the holding circuit 220 continues to operate.

  At time t2, the NMOS transistors TIN1, TIN2, and TIN3 are all turned off, and when the clock signal CLK becomes HIGH, the second dynamic node ML2 starts to be discharged. At this time, since the PMOS transistor TKP2 is conductive, it takes time for the charge of the second dynamic node ML2 to be extracted. That is, as compared with the configuration of FIG. 1, the timing of the logic transition of the output signal OUT and the speed of the logic transition are slow. Therefore, when the address decoder shown in FIG. 3 is applied to a semiconductor memory device, the data reading speed is reduced.

  Further, in the address decoder of FIG. 3, for example, when performing a low voltage operation, if the size of the PMOS transistor TKP2 is increased, the level of the second dynamic node ML2 is not inverted after time t2 and may malfunction. .

  As described above, the address decoder shown in FIG. 3 has a problem when the size of the PMOS transistor TKP2 is increased.

  On the other hand, the operation when the size of the PMOS transistor TKP2 of the address decoder shown in FIG. 3 is reduced will be described with reference to FIG. 4 and 5, the timing at which the address signals AD [0], AD [1], AD [2] and the clock signal CLK logically change is the same.

  When the clock signal CLK becomes HIGH at time t0, discharging of the second dynamic node ML2 is started. While the level of the second dynamic node ML2 is HIGH, the power supply voltage is supplied to the second dynamic node ML2 via the PMOS transistor TKP2, but since the size of the PMOS transistor TKP2 is small, the second dynamic node ML2 Immediately becomes LOW. When the level of the second dynamic node ML2 becomes LOW, the PMOS transistor TKP2 is completely turned off, and the level cannot be returned to HIGH. In other words, the level of the second dynamic node ML2 that should originally be kept HIGH becomes LOW for a while, so that the output signal OUT remains HIGH and an error occurs.

  When the clock signal CLK becomes HIGH again at time t2, the second dynamic node ML2 is discharged. At this time, since the size of the PMOS transistor TKP2 is small and its capability is low, the level of the second dynamic node ML2 becomes LOW relatively quickly. Therefore, the output signal OUT is relatively speeded up as compared with the case of FIG.

  As described above, in the address decoder of FIG. 3, when the size of the PMOS transistor TKP2 is reduced, there is a problem that the output signal OUT becomes an error. In FIG. 3, the timing chart when the load capacity of the first dynamic node ML1 is large is the same as FIG.

  As described above, in the address decoder of FIG. 3 that employs the technique of Patent Document 1, an attempt to reduce the noise hinders the speeding up of the output signal OUT, while an attempt to speed up the output signal OUT results in an error. There is a problem of becoming, and these are in a trade-off relationship.

  In contrast, in the address decoder according to the present embodiment, as described above, although noise appears in the output signal OUT, the output signal OUT does not cause an error, and the output signal OUT can be speeded up. . That is, the address decoder according to this embodiment can solve the above-described trade-off problem, and is particularly suitable for a noise care-free semiconductor memory device as shown in FIG.

  Note that the address decoder shown in FIG. 1 may be provided with the holding circuit 220 shown in FIG. In the address decoder of FIG. 3, after any one of the address signals AD [0], AD [1], AD [2] is HIGH, the level of the second dynamic node ML2 becomes LOW, A holding circuit 220 is required to return the level to HIGH. However, in the address decoder of FIG. 1, when any one of the address signals AD [0], AD [1], AD [2] is HIGH, the level of the second dynamic node ML2 is compensated by the compensation circuit 200. Therefore, the holding circuit 220 illustrated in FIG. 3 may be omitted.

  Generally, as the address signals AD [0], AD [1], and AD [2], an address signal input to the semiconductor memory device is a signal latched by a latch circuit. As described above, the address signals AD [0], AD [1], and AD [2] may be used as they are. In this case, since the timing of the falling edge of the output signal OUT can be adjusted by the address signals AD [0], AD [1], and AD [2], the pulse width of the output signal OUT can be adjusted. It is.

  Further, in the present embodiment, the noise generated in the output signal OUT by the compensation circuit 200 may be about glitch, so the gate width of the NMOS transistor TD2 may be increased and the threshold voltage may be lowered. As a result, the operating current of the NMOS transistor TD2 can be increased, so that the output signal OUT can be further increased in speed.

  Further, since the level of the second dynamic node ML2 is reliably compensated by the compensation circuit 200, it is possible to operate the second dynamic node ML2 by reducing the voltage to some extent before the NMOS transistor TD2 becomes conductive. It becomes. As a result, the amount of charge to be extracted from the second dynamic node ML2 is reduced, so that the output signal OUT can be further increased in speed. Further, by connecting a low power supply voltage to the PMOS transistor TPC2 and precharging the second dynamic node ML2 to a low voltage in advance, the amount of charge related to charging / discharging of the second dynamic node ML2 is reduced. Electricity can be realized.

  In FIG. 1, the clock signal CLK input to the NMOS transistors TD1 and TD2 and the clock signal CLK input to the PMOS transistors TPC1 and TPC2 are not necessarily the same signal. For example, it may be a signal output from a different clock generation circuit or the like.

  In the configuration shown in FIG. 3, the PMOS transistor TKP1 that is a holding circuit is connected to the second dynamic node ML2, but in the configuration shown in FIG. 1, the holding circuit 30 is connected to the second dynamic node ML2. Absent. Therefore, in the configuration shown in FIG. 1, the load capacity of the second dynamic node ML2 can be reduced as compared with the configuration shown in FIG. Therefore, the logic transition from HIGH to LOW at the level of the second dynamic node ML2 can be further accelerated.

  In the configuration shown in FIG. 3, the PMOS transistor TKP1 is susceptible to the noise of the second dynamic node ML2, and may malfunction due to the noise generated at the second dynamic node ML2. If noise occurs in the second dynamic node ML2, the PMOS transistor TKP1 may be turned on, and the level of the first dynamic node ML1 that should be originally kept low may become HIGH. On the other hand, in the configuration of FIG. 1, the holding circuit 30 is conduction controlled by the address signals AD [0], AD [1], and AD [2], so that the influence of noise of the second dynamic node ML2 is affected. I will not receive it. Therefore, according to the configuration of FIG. 1, the possibility of malfunction as described above is reduced. That is, the reliability of the output signal OUT can be improved.

  Further, when the address signals AD [0], AD [1], and AD [2] are all LOW and the first dynamic node ML1 needs to be kept HIGH, the configuration shown in FIG. Compared to the configuration shown, noise due to coupling or the like occurring in the first dynamic node ML1 can be prevented. Therefore, since the gate of the NMOS transistor TJ1 can be stably kept at HIGH, the level of the second dynamic node ML2 can be quickly changed from HIGH to LOW.

  In the configuration shown in FIG. 1, the NMOS transistor TD2 whose conduction is controlled by the clock signal CLK is arranged closer to the second dynamic node ML2 than the NMOS transistor TD2 shown in FIG. As a result, when the clock signal CLK changes from LOW to HIGH, the level of the second dynamic node ML2 can be changed quickly, so that the output signal OUT can be speeded up.

  In the configuration of FIG. 3, when the load capacity of the first dynamic node ML1 is large, the level of the first dynamic node ML1 that should be LOW is unlikely to become LOW when the NMOS transistor TD2 becomes conductive. Become. In this case, a large noise is generated in the second dynamic node ML2, and the PMOS transistor TKP2 of the holding circuit 220 is completely turned off and malfunctions. That is, the output signal OUT becomes an error.

  On the other hand, in the configuration of FIG. 1, even when a large noise occurs in the second dynamic node ML2, the noise is immediately removed as shown in FIG. Therefore, since many logic circuits can be incorporated in the first dynamic node ML1, the circuit scale can be reduced and the number of logic stages can be reduced. As a result, it is possible to simultaneously reduce the area of the address decoder, increase the operation speed, and reduce the power consumption.

  In the configuration shown in FIG. 3, the holding circuit 220 is configured so that the level of the second dynamic node ML2 is HIGH, that is, a period from time t0 to time t2 in FIG. 4 and a part of time after time t2. Works on. On the other hand, in the configuration shown in FIG. 1, the compensation circuit 200 operates when any one of the address signals AD [0], AD [1], and AD [2] is HIGH. That is, the compensation circuit 200 shown in FIG. 1 operates when the level of the first dynamic node ML1 is other than HIGH during the period from the time t0 to the time t2 in FIG. 2, and thus the NMOS transistor TD2 and the NMOS transistor TJ1 Since there is no current path that flows between the ground potential and the power supply voltage via, power consumption can be reduced.

  Further, in the configuration of FIG. 1, there is no holding circuit 220 shown in FIG. 3, and when the NMOS transistor TD2 and the NMOS transistor TJ1 are in a conductive state, there is no transistor that connects the power supply voltage and the second dynamic node ML2. There is no malfunction during low voltage operation. Further, it is possible to operate at a lower voltage during the low voltage operation.

  As shown in FIG. 6, a latch circuit 230 may be connected to the second dynamic node ML2 instead of the second precharge circuit 210. Thus, the level of the second dynamic node ML2 can be held by the latch circuit 230. Therefore, by using the held level, a reset operation for returning the level of the second dynamic node ML2 becomes unnecessary, so that power consumption can be reduced.

<Second Embodiment>
FIG. 7 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment. The common reference numerals in FIG. 1 and FIG. 7 indicate the same components, and thus the description thereof is omitted. The difference between FIG. 1 and FIG. 7 is that a holding circuit 30A is provided instead of the holding circuit 30 of FIG. 1, and the conduction control of the holding circuit 30A is performed by an input signal to the compensation circuit 200.

  Specifically, the holding circuit 30A can be configured by a PMOS transistor TECUC2 as a fifth transistor and a NOT circuit 302A. The PMOS transistor TECUC2 is connected between the power supply voltage and the first dynamic node ML1.

  The PMOS transistor TECU2 is subjected to conduction control in response to a signal obtained by inverting the input signal to the PMOS transistor TECU by the NOT circuit 302A. Therefore, the PMOS transistor TECU2 is turned on when the PMOS transistor TEUC is in a non-conductive state.

  As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, according to the present embodiment, the load capacity of the address signals AD [0], AD [1], AD [2] can be reduced as compared with the configuration of FIG.

<Third Embodiment>
FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment. The common reference numerals in FIGS. 1 and 8 indicate the same components, and thus the description thereof is omitted. In the configuration shown in FIG. 8, one of the address signals AD [0], AD [1], AD [2] is changed to the reset signal RESET, and the second precharge circuit 210 is omitted. Is different from the configuration of FIG. In FIG. 8, the holding circuit 30 shown in FIG. 1 is shown in a simplified manner.

  The PMOS transistor TECU conducts when the reset signal RESET is active. The reset signal RESET becomes active at a timing at which the level of the second dynamic node ML2 should be set to the initial value HIGH.

  As described above, according to the present embodiment, since the load capacity of the second dynamic node ML2 is reduced, the amount of charge to be extracted from the second dynamic node ML2 is reduced. Therefore, the output signal OUT can be speeded up and the power consumption of the semiconductor integrated circuit can be reduced. Further, since the second precharge circuit 210 shown in FIG. 1 is omitted, the area of the semiconductor integrated circuit can be reduced. Further, since the second precharge circuit 210 is not provided, the load capacity of the clock signal CLK can be reduced, and further reduction in power consumption can be realized.

<Fourth Embodiment>
FIG. 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment. The common reference numerals in FIG. 1 and FIG. In FIG. 9, the circuit configuration of the compensation circuit 200A is different from that of the compensation circuit 200 of FIG. In FIG. 9, the holding circuit 30 shown in FIG. 1 is shown in a simplified manner.

  The compensation circuit 200A includes PMOS transistors TECUC1, TEUC2, and TECU3 connected in parallel, which are third transistors.

  The PMOS transistor TECU1 is subjected to conduction control by receiving NAD [2], which is an inverted signal of the address signal AD [2], at its gate. The PMOS transistor TECUC2 receives NAD [1], which is an inverted signal of the address signal AD [1], at its gate and is controlled for conduction. The PMOS transistor TECU3 receives NAD [0], which is an inverted signal of the address signal AD [0], at its gate and is controlled for conduction. Note that an address signal input to another address decoder may be used as the inverted signals NAD [0], NAD [1], and NAD [2].

  This eliminates the need to newly generate the inverted signals NAD [0], NAD [1], and NAD [2]. Therefore, in the compensation circuit 200A, the overhead of the circuit area due to using the inverted signals NAD [0], NAD [1], and NAD [2] does not occur.

  Further, in the compensation circuit 200A shown in FIG. 9, the NOR circuit 202 in the compensation circuit 200 shown in FIG. 1 is not necessary, so that the circuit area of the compensation circuit 200A can be reduced.

  In the compensation circuit 200A shown in FIG. 9, the PMOS transistors TECU1, TEUC2, and TECU3 are connected to the second dynamic node ML2 via the PMOS transistor TECD that is the fourth transistor and the NOT circuit 204, thereby dynamically The load capacity of the node ML2 can be reduced.

  Further, the third transistor may be composed of one PMOS transistor. In this case, the output of the OR circuit that receives the inverted signals NAD [0], NAD [1], and NAD [2] may be input to the gate of the PMOS transistor.

<Fifth Embodiment>
FIG. 10 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment. The common reference numerals in FIG. 1 and FIG. In FIG. 10, the circuit configuration of the compensation circuit 200B is different from that of the compensation circuit 200 of FIG. In FIG. 10, the holding circuit 30 shown in FIG. 1 is shown in a simplified manner.

  The compensation circuit 200B includes a PMOS transistor TEC1 (third transistor) connected between the power supply voltage and the second dynamic node ML2. The first dynamic node ML1 is connected to the gate of the PMOS transistor TEC1. Therefore, the PMOS transistor TEC1 becomes conductive when any one of the address signals AD [0], AD [1], and AD [2] is HIGH, that is, when the first dynamic node ML1 is LOW.

  As described above, according to the present embodiment, the compensation circuit 200B can have a simpler configuration, so that the circuit area of the semiconductor integrated circuit can be further reduced.

  Here, even if the address signals AD [0], AD [1], and AD [2] are all LOW and the NMOS parallel circuit 110 is in a non-conducting state, the first dynamic node ML1 is caused by a leakage current or the like. There is a possibility that the electric charge will be lost. In the present embodiment, when the charge of the first dynamic node ML1 is lost and the level becomes LOW, the PMOS transistor TEC1 may be turned on. However, since the holding circuit 30 is provided, the level of the first dynamic node ML1 can be maintained high, and a malfunction in which the PMOS transistor TEC1 is erroneously turned on can be prevented.

  In each of the above-described embodiments, the connection order of the NMOS transistor TD2 and the NMOS transistor TJ1 may be switched.

  For example, as shown in FIG. 11, the NMOS transistor TJ1 may be connected between the second dynamic node ML2 and the NMOS transistor TD2.

<Sixth Embodiment>
FIG. 12 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the sixth embodiment. The common reference numerals in FIG. 10 and FIG. 12 indicate the same components, and thus the description thereof is omitted. In FIG. 12, the circuit configuration of the holding circuit 30B is different from the holding circuit 30 of each embodiment described above.

  Specifically, the holding circuit 30B can be configured by a PMOS transistor TKP1 connected between the power supply voltage and the first dynamic node ML1. The PMOS transistor TKP1 is conductively controlled according to the level of the second dynamic node ML2, and is conductive when the level of the second dynamic node ML2 is LOW.

  As described above, according to the present embodiment, since the holding circuit 30B can have a simpler configuration, the circuit area of the semiconductor integrated circuit can be further reduced. In the present embodiment, the connection order of the NMOS transistor TJ1 and the NMOS transistor TD2 may be switched.

<Seventh Embodiment>
FIG. 13 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the seventh embodiment. The common reference numerals in FIG. 12 and FIG. 13 indicate the same components, and thus the description thereof is omitted. The semiconductor integrated circuit shown in FIG. 13 is a comparator that compares address signals, for example. In FIG. 13, the compensation circuit 200B is shown in a simplified manner.

  In the comparator shown in FIG. 13, the address signals AD_A [0] and AD_B [0], AD_A [1] and AD_B [1], AD_A [2] and AD_B [2] are logically operated by the EOR circuit 42, respectively. Result is input.

  Since a general comparator is not provided with the compensation circuit 200B shown in FIG. 13, it is necessary to suppress noise of the output signal OUT as a comparison result of the comparator. Therefore, conventionally, a margin is provided at the timing of starting the circuit corresponding to the NMOS transistor TD2. Therefore, it is difficult to increase the speed of the output signal OUT with a general comparator.

  On the other hand, in the comparator shown in FIG. 13, even when an error in the comparison result occurs or noise occurs in the second dynamic node ML2, error correction and noise can be quickly removed. it can. Therefore, the reliability of the comparison result is improved, and it is not necessary to provide the above-described extra margin, so that the output signal OUT can be speeded up.

  The comparator may be configured as shown in FIG. FIG. 14 is a modification of the comparator shown in FIG. In FIG. 14, the NMOS parallel circuit 110A and the logic circuit 42A are equivalent to the NMOS parallel circuit 110 and the EOR circuit 42 shown in FIG.

  According to the comparator shown in FIG. 14, the number of parts of the circuit can be reduced as compared with the configuration of FIG. 13, so that the circuit area can be reduced.

  The above embodiments have been described by taking the address decoder and the comparator as examples. However, the present invention can have various configurations other than those described above, and can be applied to various circuits. In this embodiment, the connection order of the NMOS transistor TJ1 and the NMOS transistor TD2 may be switched.

  In each of the above embodiments, the holding circuits 30, 30A, and 30B may be omitted. Further, although the first power supply has been described as the ground potential and the second power supply as the power supply voltage, these may be reversed. Further, the second state may be set when all of the address signals AD [0], AD [1], and AD [2] are LOW, and the first state may be set when any one of them is HIGH. The first dynamic node ML1 may be set to the second level when the level is HIGH and the first level when the level is LOW. Further, the level of the second dynamic node ML2 may be made to have an inverse logic to the level described in each embodiment. In these cases, each component of the semiconductor integrated circuit according to each embodiment may be operated in the reverse logic to the operation described above.

  In addition, each component of the semiconductor integrated circuit according to each embodiment may be replaced with an equivalent circuit. For example, the NMOS transistor TJ1 may be replaced with a PMOS transistor and a NOT circuit connected to the gate of the PMOS transistor.

  The semiconductor integrated circuit according to each of the above embodiments is suitable for the semiconductor memory device shown in FIG. 16, but may be applied to the semiconductor memory device as shown in FIG.

  The semiconductor integrated circuit according to the present invention is useful for semiconductor memory devices and the like because noise can be quickly removed from the output signal and the output signal can be speeded up.

DESCRIPTION OF SYMBOLS 10 1st dynamic circuit 30,30A, 30B Holding circuit 20 2nd dynamic circuit 200,200A, 200B Compensation circuit 230 Latch circuit TJ1 1st transistor TD2 2nd transistor TEC1, TECU 3rd transistor TECU1, TECU2, TECU3 3rd transistor TECD 4th transistor TKP1, TECU2 5th transistor 306, 308, 310 5th transistor ML1 1st dynamic node ML2 2nd dynamic node CLK 1st clock signal, 2nd clock signal OUT output signals AD [0], AD [1], AD [2], AD_A [0], AD_B [0], AD_A [1], AD_B [1], AD_A [2], AD_B [2] Address signal ( Multiple input signals )

Claims (15)

A first dynamic circuit that receives a plurality of input signals and a first clock signal and controls a level of the first dynamic node;
A first transistor provided between a second dynamic node and a first power supply, the conduction of which is controlled according to the level of the first dynamic node;
A second transistor provided in series with the first transistor between the second dynamic node and the first power supply, the conduction of which is controlled according to a second clock signal;
A second dynamic circuit that outputs an output signal having a logical value corresponding to the level of the second dynamic node;
The first dynamic circuit includes:
When the plurality of input signals are in the first state, the level of the first dynamic node is maintained at a first level for conducting the first transistor, while the plurality of input signals are in the first state. When the second state other than the first state is established, the first dynamic node is set to a level at which the first transistor is not conducted with the first level in accordance with the first clock signal. To switch to the level of
The second dynamic circuit includes:
Provided between the second dynamic node and a second power supply, the plurality of input signals are in the second state, and the level of the first dynamic node is other than the first level A semiconductor integrated circuit comprising: a compensation circuit for compensating a level of the second dynamic node by connecting the second dynamic node to the second power source. The semiconductor integrated circuit according to claim 1.
The compensation circuit includes:
Provided between the second dynamic node and the second power supply, and controlled to conduct according to the state of the plurality of input signals, and conducts when the plurality of input signals are in the second state. A semiconductor integrated circuit including a third transistor. The semiconductor integrated circuit according to claim 1.
The compensation circuit is provided between the second dynamic node and the second power supply, and conduction control is performed according to a level of the first dynamic node, and the first dynamic node is the second dynamic node. A semiconductor integrated circuit comprising a third transistor that conducts when the level is reached. The semiconductor integrated circuit according to claim 1.
The compensation circuit includes:
Provided between the second dynamic node and the second power supply, and controlled to conduct according to the state of the inverted signal of the plurality of input signals, the inverted signal being the second input signal being the second input signal. A semiconductor integrated circuit comprising: a third transistor that is conductive when in the state. The semiconductor integrated circuit according to claim 4.
The compensation circuit includes:
Between the second dynamic node and the second power supply, it is provided in series with the third transistor, and conduction control is performed according to the first clock signal, and the first clock signal is A semiconductor integrated circuit, comprising: a fourth transistor that conducts when the level of the first dynamic node is the second level. The semiconductor integrated circuit according to claim 2.
Provided between the first dynamic node and the second power supply, controlled in conduction according to an input signal to the gate of the third transistor, and when the third transistor is non-conductive, A semiconductor integrated circuit comprising a holding circuit having a fifth transistor which is conductive. The semiconductor integrated circuit according to claim 2.
The plurality of input signals include a reset signal for returning the level of the second dynamic node to an initial level,
The semiconductor integrated circuit, wherein the third transistor is turned on when the reset signal is active. The semiconductor integrated circuit according to claim 1.
The level of the first dynamic node is set between the first dynamic node and the second power source, and the level of the first dynamic node is set to the first level when the level of the first dynamic node is the first level. A semiconductor integrated circuit comprising a holding circuit for holding at a level of 1. The semiconductor integrated circuit according to claim 8.
The holding circuit is provided between the first dynamic node and the second power supply, and is conductively controlled according to a level of the second dynamic node, and the second dynamic node is the first dynamic node. A semiconductor integrated circuit including a fifth transistor which is conductive when connected to a power source. The semiconductor integrated circuit according to claim 8.
The holding circuit is
Provided between the first dynamic node and the second power supply, and controlled to conduct according to the state of the plurality of input signals, and conducts when the plurality of input signals are in the first state. A semiconductor integrated circuit including a fifth transistor. The semiconductor integrated circuit according to claim 1.
The semiconductor integrated circuit, wherein the second transistor is connected between the second dynamic node and the first transistor. The semiconductor integrated circuit according to claim 1.
A semiconductor integrated circuit comprising a latch circuit for latching the level of the second dynamic node. The semiconductor integrated circuit according to claim 1.
The semiconductor integrated circuit according to claim 1, wherein the first and second clock signals are the same signal. The semiconductor integrated circuit according to claim 1 is an address decoder,
The semiconductor integrated circuit, wherein each of the plurality of input signals is an address signal. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a comparator.

Images