JP5766412B2 - Display device - Google Patents

Description

  The present invention relates to a display device including one or a plurality of scanning line groups configured by n scanning lines.

  Display devices such as organic EL display devices have a display area for displaying images. The display area includes a plurality of pixel rows, and each pixel row includes a plurality of pixel circuits. The display device further includes a plurality of scanning lines corresponding to each pixel row and a plurality of video signal lines for inputting a video signal to each pixel circuit.

  Each pixel row is assigned an address period, and the scanning line corresponding to each pixel row outputs a scan signal in accordance with the timing of the assigned address period. The scanning signal output from each scanning line is generated by supplying power from two power sources that output a high potential and a low potential, respectively.

  Patent Document 1 describes a display device that can improve contrast as compared with a conventional pixel circuit and can suppress deterioration of an electro-optical element. FIG. 6 is a diagram illustrating an example of a pixel circuit in a conventional display device, and FIG. 7 is a diagram illustrating scanning input to each scanning signal line Gi, Wi, Ui, Ri of the pixel circuit illustrated in FIG. It is a timing chart which shows an example of a signal. In the display device disclosed in Patent Document 1, each pixel circuit in a display area for displaying an image has the same circuit structure.

International Publication WO2006 / 137295

  Here, when the power supply capability of the two power supplies for outputting the scanning signal is insufficient, a display defect may occur.

  Such a display defect occurs when, for example, a video signal input from most video signal lines varies greatly between a writing period of a predetermined pixel row and a writing period immediately before the writing period. is there.

  Parasitic capacitance is present at the intersection of the video signal line and the scanning line, and the load applied to all the scanning lines that intersect with the video signal line varies due to fluctuations in the potential of the video signal line. Furthermore, when the potential applied to most of the video signal lines varies greatly, the potentials of all the scanning lines also vary greatly. If the power supply capacity is insufficient when such potential fluctuation occurs, the potential of the scanning line is not stabilized during the input of the video signal in the predetermined pixel row, and the video written to each pixel circuit in the predetermined pixel row The signal fluctuates and a display defect occurs.

  FIG. 8 is a diagram illustrating an example in which a display failure has occurred due to insufficient power supply capability. In the example of FIG. 8, writing is sequentially performed from the first pixel row, and a black rectangle is displayed at the center of the white screen. For this reason, the video signal hardly fluctuates in the pixel rows from the first row to the m−1th row. However, when the mth pixel row is written, the potential applied to about half of the video signal lines is greatly reduced. In the example of FIG. 8, during the input of the video signal in the m-th row, the potential of the scanning line is not stabilized due to insufficient power supply capability, and a display defect occurs in the entire m-th pixel row.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that prevents display defects caused by insufficient power supply capacity of a power supply that supplies power to scanning lines.

  In order to solve the above problems, a display device according to the present invention includes one or more scanning line groups each including n scanning lines, and a high potential that supplies power to the one or more scanning line groups. Display device having two power supplies on the side and low potential side and n pixel rows each composed of a plurality of pixel circuits, each comprising n lines that constitute each of the one or more scanning line groups Each of the scanning lines is associated with each of the n pixel rows, and each of the one or more scanning line groups includes scanning lines connected to switching elements that perform common control in the pixel circuits. In the predetermined one scanning line group among the one or plural scanning line groups, of the n scanning lines included in the predetermined one scanning line group, The scanning line of the unit outputs the potential from the power source on the high potential side, thereby causing the switch elements to be connected to perform the common control, and the remaining scanning lines are potentials from the power source on the low potential side. Is output to cause each of the connected switch elements to perform the common control.

  In the display device according to the aspect of the invention, the one or more scanning line groups may include one or more first scanning line groups, one or more second scanning line groups, and one or more first scanning line groups. A plurality of scanning line groups, each of the one or more first scanning line groups, a part of the n scanning lines included in the first scanning line group. The scanning lines output the potential from the high-potential side power supply, thereby causing the switching elements to be connected to perform the common control, and the remaining scanning lines receive the potential from the low-potential side power supply. By outputting, each of the connected switch elements performs the common control, and in each of the n pixel rows, a video signal is input to each pixel circuit in the pixel row. In a period other than the write period, a potential from the power source on the low potential side is input from the scanning lines belonging to the one or more second scanning line groups and to the one or more third scanning line groups. A potential from the power source on the high potential side may be input from a scanning line to which the scanning line belongs.

  In the display device according to the aspect of the invention, the second scanning line group and the third scanning line group may have the same number of groups.

  In the display device according to the aspect of the invention, the one or more scanning line groups may have an odd number of groups of 3 or more, and the one or more first scanning line groups may have one group number. It may be characterized by that.

  Further, in one aspect of the display device according to the present invention, the display device is an organic EL display device, a display region is configured including the n pixel rows, and the predetermined one scanning line group is defined. Each of the switch elements connected to the n scanning lines that constitutes each is a light emission control switch that controls whether or not the organic EL element included in each pixel circuit emits light, and the display area is an image of one frame. One frame period for displaying the image signal includes n writing periods for inputting a video signal to the n pixel rows and a non-light emission period for turning off the light emitting elements of the pixel circuits in the display region. Each of the light emission control switches may cause the light emitting element to emit light after the writing period ends and turn off the light emitting element during the non-light emitting period.

  In one embodiment of the display device according to the present invention, the part of the scanning lines outputs a signal that changes to a potential of the high-potential side power source using a potential of the low-potential side power source as a reference potential, Each of the switch elements to be connected performs the common control, and the remaining part of the scanning lines is a signal that changes to a potential by the low-potential side power source using a potential by the high-potential side power source as a reference potential. May be output to cause each of the connected switch elements to perform the common control.

  In the display device according to the aspect of the invention, each of the switch elements connected to the part of the scanning lines is an NMOS element, and the NMOS element is turned on by a potential from the power source on the high potential side. The NMOS element is turned off by the potential of the low-potential-side power supply, and each of the switch elements connected to the remaining part of the scanning lines is a PMOS element, and the high-potential-side power supply The PMOS element may be turned off by the potential of the power supply, and the PMOS element may be turned on by the potential of the power supply on the low potential side.

  In the display device according to the aspect of the invention, the partial scanning lines may be half of the n scanning lines, and the remaining scanning lines may be the remaining half of the n scanning lines. The scanning line may be a feature.

  In one embodiment of the display device according to the present invention, the partial scanning lines and the remaining scanning lines may be associated with the n pixel rows so as to be alternated.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which prevented the display defect produced by the power supply capability shortage of the power supply which supplies electric power to a scanning line can be provided.

It is a figure which shows the mode on the TFT substrate of the display apparatus which concerns on 1st this embodiment. 3 is a diagram illustrating a pixel circuit PX1 included in an odd-numbered pixel row PL1 in the first embodiment. FIG. FIG. 3 is a diagram illustrating a pixel circuit PX2 included in an even-numbered pixel row PL2 in the first embodiment. 6 is a timing chart showing scanning signals output from scanning lines GA to GC in the first embodiment. It is a figure which shows pixel circuit PX1 which odd-numbered pixel row PL1 in 2nd Embodiment has. It is a figure which shows the pixel circuit PX2 which the pixel row PL2 of the even-numbered row in 2nd Embodiment has. It is a timing chart which shows the scanning signal output from each scanning line GA-GD in 2nd Embodiment. It is a figure which shows an example of the pixel circuit in the conventional display apparatus. 7 is a timing chart illustrating an example of a scanning signal input to each scanning signal line of the pixel circuit illustrated in FIG. 6. It is a figure which shows the example which the display defect resulting from the lack of power supply capability generate | occur | produced.

  Embodiments according to the present invention will be described below with reference to the drawings. However, in the following description, the same reference numerals are given to the same components in the respective embodiments, and repeated descriptions of the same components will be omitted. It goes without saying that the present invention can be modified as appropriate without departing from the technical idea of each embodiment described below.

[First Embodiment]
The display device according to this embodiment includes an organic EL display device including a TFT substrate in which a plurality of organic EL elements are arranged on a glass substrate, and a sealing substrate bonded to the TFT substrate with a sealing material. It is.

  FIG. 1 is a diagram showing a state on the TFT substrate of the display device according to the present embodiment. As shown in the figure, the display region DP on the TFT substrate has a plurality of pixel rows PL, and the display region DP of the present embodiment has n pixel rows PL1 to PLn. (In the present specification, n is an integer of 1 or more). In the display area DP, a plurality of video signal lines DL are laid along the vertical direction in the figure at intervals, and a plurality of first scanning lines GA, a plurality of second scanning lines GB, and a plurality of The third scanning line GC is laid along the horizontal direction in the drawing at intervals. As shown in the figure, a scanning line driving circuit GDR and a video signal line driving circuit DDR are mounted around the display area DP.

  In the present embodiment, n first scanning lines GA1 to GAn, n second scanning lines GB1 to GBn, and n third scanning lines GC1 to GCn are laid in the display region DP. These are associated one by one with each of the pixel rows PL1 to PLn. Specifically, as shown in FIG. 1, the first scanning line GA, the second scanning line GB, and the third scanning line GC are associated with each pixel row one by one.

  Further, the scanning line driving circuit GDR in the present embodiment includes a power source (high potential side power source) for outputting an H level potential to each scanning line and a power source for outputting an L level potential to each scanning line. 2 power sources (low potential side power source). The scanning line driving circuit GDR outputs the scanning signals for selecting the pixel rows PL1 to PLn to each scanning line in turn by using the two power supplies. When selecting a pixel row, the scanning line driving circuit GDR outputs scanning signals to the first to third scanning lines GA to GC associated with the pixel row, respectively, and the video signal line driving circuit DDR is selected. A video signal is output to each video signal line DL corresponding to the pixel row.

  In particular, in the present embodiment, among the pixel rows PL1 to PLn, the odd-numbered pixel row PL has a plurality of pixel circuits PX1, and the even-numbered pixel row PL has a plurality of pixel circuits PX2. ing. For this reason, the pixel circuit PX1 and the pixel circuit PX2 are mixed in the display area DP.

  FIG. 2A is a diagram illustrating a pixel circuit PX1 included in a pixel row PL1 that is an odd-numbered row in the present embodiment, and FIG. 2B is a diagram illustrating a pixel circuit PX2 included in a pixel row PL2 that is an even-numbered row in the present embodiment. is there. As shown in the figure, the pixel circuit PX1 and the pixel circuit PX2 include an organic EL element Oled, one of input switches Q1a and Q1b, a reset switch Q2, a light emission control switch Q3, a drive switch Q4, and a cancel capacitor. C1 and a storage capacitor C2. As shown in these drawings, the second scan line GB is connected to the gate electrode of the reset switch Q2, the third scan line GC is connected to the gate electrode of the light emission control switch Q3, and the odd-numbered first scan line GA is connected. Is connected to the gate electrode of the input switch Q1a, and the first scanning lines GA in the even rows are connected to the gate electrode of the input switch Q1b.

  As shown in FIGS. 2A and 2B, each of the pixel circuit PX1 and the pixel circuit PX2 is provided with an organic EL element Oled as a light emitting element, and its cathode end is connected to a common electrode. The anode end of the organic EL element Oled is connected to one end of the light emission control switch Q3, and the other end of the light emission control switch Q3 is connected to one end of the drive switch Q4. Further, the other end of the drive switch Q4 is connected to the power supply line Voled. The power line Voled is laid substantially parallel to the video signal line DL in the display area DP and supplies a current to the organic EL element Oled.

  A reset switch Q2 is connected between the other end of the light emission control switch Q3 and the gate electrode of the drive switch Q4. A storage capacitor C2 is connected between the other end of the drive switch Q4 and the gate electrode of the drive switch Q4. Furthermore, one end of a cancel capacitor C1 is also connected to the gate electrode of the drive switch Q4. The other end of the cancel capacitor C1 is connected to the video signal line DL via the input switch Q1a in the pixel circuit PX1, and is connected to the video signal line DL via the input switch Q1b in the pixel circuit PX2. In the present embodiment, the first scanning line GA, the second scanning line GB, and the third scanning line GC have two potentials: an H level potential by a high potential side power source and an L level potential by a low potential side power source. When the potential level is input, on / off of the switch element connected to each scanning line is switched.

  Here, the input switch Q1a connected to the odd-numbered first scanning lines GA receives the input of the H level potential and performs control in the pixel circuit PX1 and the input connected to the even-numbered first scanning lines GA. Controls performed by the switch Q1b in the pixel circuit PX2 upon receiving an L-level potential are common to each other. In the present embodiment, specifically, the input switches Q1a and Q1b perform control for transmitting the potential of the video signal line DL to the cancel capacitor C1. That is, the first scanning lines GA1 to GAn are connected to switch elements (input switches Q1a or Q1b) that perform common control in each pixel circuit. In this embodiment, the odd-numbered input switches Q1a are NMOS elements that are turned on when a potential from the high-potential side power supply is input, and the even-numbered input switches Q1b are the potentials from the low-potential side power supply. This is a PMOS element that is turned on when.

  In the pixel circuits PX1 and PX2 of the present embodiment, as described above, the switch elements connected to the first scanning line GA are PMOS elements and NMOS elements, but the input switches Q1a and Q1b are connected to the respective pixel circuits. The control to be performed is common to each other. For this reason, the potential output as the scanning signal is different between the first scanning line GA1 as an odd row and the first scanning line GA2 as an even row. In the following, the control in the pixel circuit PX1 and the pixel circuit PX2 will be further described, but the pixel circuit PX1 and the pixel circuit PX2 are substantially the same except for the points described above. Therefore, in the following description, the pixel circuit PX1 will be mainly described while omitting the description of the pixel circuit PX2 in terms of being the same as the pixel circuit PX1.

  FIG. 3 is a timing chart showing scanning signals output from the scanning lines GA to GC in the present embodiment. The writing period shown in FIG. 3 is a period assigned to each pixel row for inputting a video signal. During the writing period of a predetermined pixel row, the input of the scanning signal of each scanning line associated with the predetermined pixel row starts and ends. In the scanning lines GA to GC of this embodiment, during a period other than the writing period of the connected pixel row, one of the binary potential levels of the H level potential and the L level potential is set as a reference potential. And outputs a rectangular wave from the one potential to the other potential as a scanning signal within the writing period.

  As shown in FIG. 3, first, the emission control switch Q3 is turned off by outputting an off signal to the third scanning line GC1. Next, when the scanning signal is output from the first scanning line GA1 and the input switch Q1a is turned on, scanning signals are further output from the second scanning line GB1 and the third scanning line GC1, and the reset switch Q2 is turned on. The light emission control switch Q3 is turned on. As a result, the signal voltage of the reference level input to the video signal line DL is input to one end of the cancel capacitor C1, and when the reset switch Q2 is turned on, the drive switch Q4 is diode-connected, and the light emission control is performed. When the switch Q3 is turned on, a current flows through the organic EL element Oled, and a precharge voltage (a potential at which the drive switch Q4 is turned on) is applied to the gate of the drive switch Q4. Thereafter, when the light emission control switch Q3 is turned off, the drive switch Q4 becomes a diode connection whose drain side is opened, and the gate voltage of the drive switch Q4 gradually goes to the threshold voltage Vth. The reset switch Q2 is a switch for resetting the luminance information written in the pixel circuit PX.

  Thereafter, when the output of the scanning signal from the second scanning line GB1 is completed, the reset switch Q2 is turned off, and the threshold voltage Vth of the drive switch Q4 is written to one end of the cancel capacitor C1. Then, after the output of the scanning signals of the second scanning line GB1 and the third scanning line GC1 is completed, the scanning signal of the first scanning line GA1 is being output (the input switch Q1a is in the on state and the reset switch Q2 is in the off state) When the light emission control switch Q3 is in an OFF state), a video signal having a voltage level corresponding to given luminance information is input from the video signal line DL. As a result, the gate voltage of the drive switch Q4 changes by a voltage corresponding to the voltage level input from the video signal line DL with reference to the voltage at the time of reset.

  When the output of the scanning signal of the first scanning line GA1 is completed, the gate voltage of the drive switch Q4 maintains this changed voltage, and the state in which charges corresponding to the luminance information are accumulated in the storage capacitor C2 (that is, The luminance information is written in the pixel circuit PX1). When the light emission control switch Q3 is turned on, a current flows to the organic EL element Oled through the light emission control switch Q3 in accordance with the change in the gate voltage of the drive switch Q4, and according to the luminance information of the storage capacitor C2. Thus, the organic EL element Oled emits light.

  As described above, when the writing period 1 assigned to the pixel row PL1 ends, the writing periods (writing period 2 to writing period n) assigned after the pixel row PL2 start in order. The timing chart of FIG. 3 shows a part of one frame period in which the display area DP displays an image of one screen. After the writing period n ends, the entire display area DP emits light and an image of one screen is displayed. Is displayed. In particular, in FIG. 3, as described above, the first scanning line GA associated with the odd-numbered pixel rows PL outputs a scanning signal that changes to an H-level potential using the L-level potential as a reference potential. The first scanning line GA associated with the pixel row PL outputs a scanning signal that changes to an L level potential using the H level potential as a reference potential. In this way, the odd-numbered first scanning lines GA and the even-numbered first scanning lines GA have control (cancellation) common to each of the switch elements (input switches Q1a and Q1b) connected to each other in each pixel circuit. The capacitor C1 is controlled to transmit the potential of the video signal line DL).

  As described above, the n first scanning lines GA1 to GAn are connected to the switch elements that perform common control in the pixel circuits, and the n first scanning lines GA1 to GAn include A scanning line that outputs an H level potential as a scanning signal and a scanning line that outputs an L level potential as a scanning signal are mixed. Hereinafter, in this specification, first, n scanning lines connected to switch elements that perform common control in each pixel circuit are referred to as a scanning line group. Further, some of the n scanning lines constituting the scanning line group are scanning lines that output the potential from the power source on the high potential side as a scanning signal, and the remaining scanning lines are on the low potential side. In this specification, a scanning line that outputs a potential from the power source as a scanning signal is referred to as a first scanning line group. Therefore, in the present embodiment, one first scanning line group is configured by the n first scanning lines GA1 to GAn.

  The second scan lines GB1 to GBn are also connected to a reset switch Q2 that performs common control in each pixel circuit, and the third scan lines GC1 to GCn are also connected to a light emission control switch Q3 that performs common control in each pixel circuit. Connected. In the present embodiment, the reset switch Q2 connected to each of the second scanning lines GB1 to GBn and the light emission control switch Q3 connected to each of the third scanning lines GC1 to GCn are independent of odd rows and even rows. , An NMOS device.

  Further, in this specification, each of the n scanning lines constituting the scanning line group is a scanning line that outputs a potential from a power source on the low potential side as a reference potential in a period other than the writing period. It is called a line group. Further, each of the n scanning lines constituting the scanning line group is a scanning line that outputs the potential from the power source on the high potential side as a reference potential in a period other than the writing period, which is called a third scanning line group. And Therefore, in the present embodiment, the second scanning line group is configured by the n second scanning lines GB1 to GBn, and the third scanning line group is configured by the n third scanning lines GC1 to GCn.

  In this embodiment, the power source used for outputting the scanning signal of the first scanning line GA is different between the even-numbered row and the odd-numbered row, and the power source for supplying power to the first scanning lines GA1 to GAn is used. To be distributed. Specifically, in an odd row, an L level potential is output from the first scanning line GA in a period other than the writing period, and in an even row, the first scanning line GA outputs an H level in a period other than the writing period. Is output. As a result, as shown in FIG. 3, the power used for the output of the first scanning lines GA1 to GAn is distributed at a predetermined timing within one frame period. In this way, it is improved that the power source for supplying power to the first scanning lines GA1 to GAn is biased to one of the two, and display defects caused by insufficient power source capability are less likely to occur.

  Further, as shown in FIG. 3, each of the second scanning lines GB1 to GBn belonging to the second scanning line group is connected to a pixel row to which an L-level potential by a low-potential-side power supply is connected, except during each writing period. Each of the third scanning lines GC1 to GCn belonging to the third scanning line group inputs an H level potential from the power source on the high potential side to the connected pixel row, except during each writing period. As a result, the power source used for the output of the second scanning line group and the power source used for the output of each scanning line of the third scanning line group are distributed at a predetermined timing within one frame period. ing. By doing so, display defects due to insufficient power supply capability are further less likely to occur.

  When the number of scanning line groups is an odd number as in this embodiment, one of the scanning line groups is set as the first scanning line group, and the other half is set as the second scanning line group. By using the third scanning line group, the power source for supplying power is more efficiently distributed.

  In the present embodiment, one scanning line group is configured by the scanning lines in the first scanning lines GA1 to GAn, and scanning lines that output an H level potential as a scanning signal and scanning an L level potential are performed. Scanning lines that are output as signals are mixed. Further, three first scanning line groups may be configured by the first scanning lines GA1 to GAn, the second scanning lines GB1 to GBn, and the third scanning lines GC1 to GCn.

[Second Embodiment]
Next, a display device according to a second embodiment of the present invention will be described. The display device according to the second embodiment is an organic EL display device similarly to the display device according to the first embodiment. However, in the display region DP, a plurality of fourth scan lines GD are further separated from other scan lines. It is laid similarly. In the following description, the display device according to the second embodiment will be described with a focus on portions that are different from the display device according to the first embodiment, and portions that are the same as those of the first embodiment will be described. Description is omitted.

  FIG. 4A is a diagram illustrating the pixel circuit PX1 included in the odd-numbered pixel row PL in the second embodiment, and FIG. 4B illustrates the pixel circuit PX2 included in the even-numbered pixel row PL in the second embodiment. FIG. As shown in the drawing, first, the pixel circuits PX1 and PX2 include a precharge switch Q5, and the gate electrode of the precharge switch Q5 is connected to the fourth scanning line GD in the first embodiment. Is different. The precharge switch Q5 is connected between one end of the drive switch Q4 and the video signal line DL. In the odd rows, the third scan line GC is connected to the gate electrode of the light emission control switch Q3a, and in the even rows, the third scan line GC is connected to the gate electrode of the light emission control switch Q3b. The second embodiment is different from the first embodiment.

  That is, in the second embodiment, two first scan line groups are configured by the n first scan lines GA1 to GAn and the n third scan lines GC1 to GCn. The n second scanning lines GB1 to GBn constitute one second scanning line group, and the n fourth scanning lines GD1 to GDn constitute one third scanning line group.

  Here, in the second embodiment, the odd-numbered light emission control switches Q3a are NMOS elements that are turned on when a potential from the power source on the high potential side is input, and the even-numbered light emission control switches Q3b are low. The PMOS element is turned on when a potential from the power supply on the potential side is input. In addition, the precharge switch Q5 is a PMOS element that is turned on when a potential from the power source on the low potential side is input regardless of the odd-numbered row and the even-numbered row.

  FIG. 5 is a timing chart showing scanning signals output from the scanning lines GA to GD in the second embodiment. In the second embodiment, a non-light emission period is assigned to all pixel rows after the writing period of all pixel rows is completed.

  As shown in FIG. 5, first, the light emission control switch Q3a is turned off by outputting a scanning signal from the third scanning line GC1. Next, when the scanning signal is output from the first scanning line GA1 and the input switch Q1a is turned on, scanning signals are further output from the fourth scanning line GD1 and the second scanning line GB1, and the precharge switch Q5 is turned on. The on / reset switch Q2 is turned on. As a result, the signal voltage of the reference level input to the video signal line DL is input to one end of the cancel capacitor C1, and the drive switch Q4 is diode-connected by turning on the reset switch Q2, and the power line Voled Current flows through the drive switch Q4 and the precharge switch Q5 to the video signal line DL. At this time, a precharge voltage (a potential at which the drive switch Q4 is turned on) is applied to the gate of the drive switch Q4. Thereafter, when the precharge switch Q5 is turned off, the drive switch Q4 becomes a diode connection with its drain side open, and the gate voltage of the drive switch Q4 gradually goes to the threshold voltage Vth.

  Thereafter, when the scanning signal of the second scanning line GB1 is finished, the reset switch Q2 is turned off, and the threshold voltage Vth of the driving switch Q4 is written to one end of the cancel capacitor C1. While the scanning signal of the first scanning line GA1 is being output, a video signal having a voltage level corresponding to given luminance information is input from the video signal line DL. As a result, the gate voltage of the drive switch Q4 changes by a voltage corresponding to the voltage level input from the video signal line DL with reference to the voltage at the time of reset. The gate voltage of the drive switch Q4 maintains this changed voltage, and the storage capacitor C2 is in a state where charges corresponding to the luminance information are accumulated (that is, the luminance information is written in the pixel circuit PX1). .

  When the output of the scanning signal of the first scanning line GA1 is finished and the output of the scanning signal of the third scanning line GC1 is finished and the light emission control switch Q3a is turned on, the light emission control switch Q3 is connected to the organic EL element Oled. A current flows, and the organic EL element Oled emits light according to the luminance information of the storage capacitor C2.

  As described above, when the writing period 1 assigned to the pixel row PL1 ends, the writing periods (writing period 2 to writing period n) assigned after the pixel row PL2 start in order. After the end of the writing period n, the entire display area DP emits light to display an image, and a non-emission period is assigned to all the pixel rows PL. In this non-light-emission period, the odd-numbered light emission control switches Q3a and the even-numbered light emission control switches Q3b are turned off, and are controlled to turn off each organic EL element Oled in the display region DP. After the non-light emission period, the odd-numbered light emission control switches Q3a and the even-numbered light emission control switches Q3b are turned on again to control each organic EL element Oled in the display region DP to emit light.

  In particular, in FIG. 5, as described above, the third scanning line GC associated with the odd-numbered pixel rows PL outputs a scanning signal that changes to an L-level potential using the H-level potential as a reference potential, and The third scanning line GC associated with the pixel row PL outputs a scanning signal that changes to an H level potential using the L level potential as a reference potential. In this way, the odd-numbered third scanning lines GC and the even-numbered third scanning lines GC cause each of the connected switch elements to perform control common to each pixel circuit.

  As in the second embodiment, when the display device has a non-light emission period in one frame period, the n number of light emission control switches connected to each light emission control switch for controlling whether or not the organic EL element Oled emits light. The three scanning lines GC are made into one first scanning line group. Specifically, in the present embodiment, the odd-numbered third scanning lines GC output a scanning signal that changes to an L-level potential using the H-level potential as a reference potential, and the even-numbered third scanning lines GC The scanning signal that changes to the H level potential is output using the L level potential as the reference potential. By doing in this way, the power source for supplying electric power to the third scanning lines GC1 to GCn is dispersed even in the non-light emitting period.

  In the display device according to the second embodiment, the number of scanning line groups is an even number, and two first scanning line groups, one second scanning line group, and one third scanning line group. And have. Then, one of the first scanning line groups is constituted by n scanning lines of the third scanning lines GC1 to GCn, and the power is distributed even in the non-light emitting period. Here, in the second embodiment, another first scanning line group is the first scanning lines GA1 to GAn, but instead of the first scanning lines GA1 to GAn, the second scanning lines GB1 to GB or The fourth scanning lines GD1 to GDn may be a first scanning line group.

  In the first scanning line group of each of the embodiments described above, the odd-numbered and even-numbered rows have half the number of scanning lines that output an H level potential as a scanning signal and the number of scanning lines that output an L level potential as a scanning signal. They are mixed together. As in each of the above embodiments, it is desirable to mix half by half. However, one or more scanning lines that are part of the n scanning lines of the first scanning line group output an H level potential as a scanning signal, and the remaining scanning lines output an L level potential as a scanning signal. Even when all the n scanning lines output one potential as a scanning signal, the bias of the power source for supplying power is improved.

  In the display device according to the second embodiment, there are two first scanning line groups, and even-numbered pixel rows have a first scanning line GA that outputs an H level potential as a scanning signal, and L A third scanning line GC that outputs a level potential as a scanning signal is associated, and an odd-numbered pixel row is scanned with a first scanning line GA that outputs an L level potential as a scanning signal and an H level potential. The third scanning line GC that is output as a signal is associated with the third scanning line GC. However, the partial scanning lines and the remaining scanning lines in one first scanning line group, and the partial scanning lines and the remaining scanning lines in another first scanning line group are independent of each other. It may be associated with each pixel row.

  In the first scanning line group of each of the above embodiments, the scanning lines that output the H level potential as the scanning signal and the scanning lines that output the L level potential as the scanning signal alternately in the odd and even rows. Are mixed. In order to improve the image quality of the display image, it is desirable to mix them alternately. For example, a part of the scanning line on the upper side of the display area DP is a scanning line that outputs an H level potential as a scanning signal. Even if the remaining scanning line on the side is a scanning line that outputs an L-level potential as a scanning signal, the bias of the power supply for supplying power is improved.

  Further, since the on state (on resistance) differs depending on the source voltage at the same channel width channel length between the NMOS and the PMOS, the channel width channel length may be changed so as to be the same on state. Specifically, the light emission control switches Q3a and Q3b in FIGS. 4A and 4B are set such that W / L = 4/4 μm in the case of NMOS and W / L = 8/4 μm in the case of PMOS.

  In the present embodiment, the scanning signal output by the scanning lines of each scanning line group during the writing period is a rectangular wave signal. However, even a signal having a waveform other than the rectangular wave may be a signal that can drive the switch element connected to the scanning line in common in each pixel circuit.

  In each of the above embodiments, the organic EL display device has been described as an example of a display device, but other display devices such as a liquid crystal display device may be used.

  DDR video signal line drive circuit, GDR scan line drive circuit, DL video signal line, GA1 to GAn first scan line, GB1 to GBn second scan line, GC1 to GCn third scan line, GD1 to GDn fourth scan line, PL1-PLn pixel row, PX1, PX2 pixel circuit, Voled power line, Old organic EL element, Q1a, Q1b input switch, Q2 reset switch, Q3, Q3a, Q3b light emission control switch, Q4 drive switch, Q5 precharge switch, C1 Cancel capacitor, C2 memory capacitor.

Claims (8)

One or more scan line groups each consisting of n scan lines;
Two power supplies on the high potential side and the low potential side for supplying power to the one or more scanning line groups;
A display device having n pixel rows each composed of a plurality of pixel circuits,
N scanning lines constituting each of the one or more scanning line groups are associated one by one with the n pixel rows,
Each of the one or more scanning line groups is a group consisting of scanning lines connected to electrodes for switching on and off switching elements that perform common control in each pixel circuit,
In one predetermined scanning line group among the one or more scanning line groups, some of the n scanning lines included in the predetermined one scanning line group are on the high potential side. By outputting the potential by the power supply, the switch elements to be connected are controlled in common, and the remaining scanning lines are connected by outputting the potential by the power supply on the low potential side. Let each of the elements perform the common control,
Each of the scanning lines in the predetermined scanning line group outputs a signal to only one pixel row ,
The one or more scanning line groups are a plurality of scanning line groups, and the plurality of scanning line groups include one or more first scanning line groups, one or more second scanning line groups, One or more third scan line groups, and
In each pixel circuit, the scanning lines belonging to the first scanning line group, the scanning lines belonging to the second scanning line group, and the scanning lines belonging to the third scanning line group respectively turn on and off different switch elements. Connected to the electrode to be switched, and
In each of the one or more first scanning line groups, some of the n scanning lines included in the first scanning line group output a potential from the power source on the high potential side. Therefore, each of the switch elements to be connected performs the common control, and the remaining scanning lines output the potential from the power source on the low potential side, thereby causing the common to each of the switch elements to be connected. Let control
In each of the n pixel rows, the scanning lines belonging to the one or more second scanning line groups in a period other than an address period assigned for inputting a video signal to each pixel circuit in the pixel row. In addition, a potential from the power source on the low potential side is input, and a potential from the power source on the high potential side is input from a scanning line belonging to the one or a plurality of third scanning line groups.
A display device characterized by that. The display device according to claim 1 ,
In each of the n pixel rows, the number of scanning lines belonging to the one or more second scanning line groups is equal to the number of scanning lines belonging to the one or more third scanning line groups.
A display device characterized by that. A display device according to claim 2 ,
In each of the n pixel rows, the number of scanning lines belonging to the one or more first scanning line groups, the number of scanning lines belonging to the one or more second scanning line groups, and the one or more The total number of scanning lines belonging to the third scanning line group is an odd number,
In each of the n pixel rows, the number of scanning lines belonging to the first scanning line group is one.
A display device characterized by that. The display device according to claim 1,
The display device is an organic EL display device,
A display region is configured including the n pixel rows,
Each of the switching elements connected to the n scanning lines constituting the predetermined scanning line group is a light emission control switch that controls whether or not the organic EL element included in each pixel circuit emits light. ,
One frame period in which the display region displays an image of one frame includes n writing periods for inputting video signals to the n pixel rows, and the light emitting elements of the pixel circuits in the display region. A non-light-emitting period that turns off,
Each of the light emission control switches causes the light emitting element to emit light after the writing period ends, and turns off the light emitting element during the non-light emitting period.
A display device characterized by that. The display device according to claim 1,
The part of the scanning lines outputs a signal that changes to a potential of the high-potential side power source using a potential of the low-potential side power source as a reference potential, and the common control is performed on each of the connected switch elements. Let
The remaining part of the scanning lines outputs a signal that changes to the potential of the low-potential side power supply using the potential of the high-potential-side power supply as a reference potential, and is common to each of the switch elements to be connected To control
A display device characterized by that. The display device according to claim 1,
Each of the switch elements connected to the part of the scanning lines is an NMOS element, and the NMOS element is turned on by a potential from the power source on the high potential side, and the switch element is turned on by the potential from the power source on the low potential side. The NMOS device is turned off,
Each of the switch elements connected to the remaining part of the scanning lines is a PMOS element, and the PMOS element is turned off by the potential of the power source on the high potential side, and the potential by the power source of the low potential side This turns on the PMOS device.
A display device characterized by that. The display device according to claim 1,
The partial scanning lines are half of the n scanning lines,
The remaining scanning lines are the remaining half of the n scanning lines.
A display device characterized by that. The display device according to claim 7 ,
The partial scan lines and the remaining scan lines are associated with the n pixel rows in an alternating manner.
A display device characterized by that.

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