JP5621533B2 - Noise reduction device and power conversion device including the same - Google Patents

Description

  The present invention relates to a noise reduction device for reducing a noise terminal voltage generated between the power conversion circuit and the ground due to the operation of the power conversion circuit, and a power conversion device including the noise reduction device.

  FIG. 8 shows a noise reduction device applied to a system in which a three-phase induction motor is driven by a three-phase inverter circuit. For example, the noise reduction device is substantially the same as that described in Patent Document 1.

  In FIG. 8, 1a is an AC power source, 2a is a rectifier circuit having a diode bridge structure, 3 is a capacitor, 4 is an example of a power conversion circuit, semiconductor switching elements Q1 to Q6 such as IGBT (insulated gate bipolar transistor), and these Inverter circuit composed of diodes D1 to D6 connected in reverse parallel to each other, 5 is an induction motor whose casing is connected to ground and is driven as a load of inverter circuit 4, 6 is a DC power source, and 7 is a zero phase composed of an annular core A leakage current detector such as a current transformer, 8 is an inverter control circuit for generating a signal for PWM control of the semiconductor switching elements Q1 to Q6 of the inverter circuit 4, 9 is a noise reduction circuit, and 10 is a noise reduction control circuit. . In the above description, the noise reduction device includes the leakage current detector 7, the noise reduction circuit 9, and the noise reduction control circuit 10.

  The AC input terminal of the rectifier circuit 2a is connected to the AC output terminal of the AC power source 1a. On the other hand, the positive DC output terminal of the rectifier circuit 2 a is connected to the positive DC input terminal of the inverter circuit 4. Let this connection point be P. The negative DC output terminal of the rectifier circuit 2 a is connected to the negative DC input terminal of the inverter circuit 4. Let this connection point be N.

  The capacitor 3 is connected between the DC output terminals P and N of the rectifier circuit 2a. The voltage of the AC power supply 1a is full-wave rectified by the rectifier circuit 2a and then smoothed by the capacitor 3. Here, the rectifier circuit 2a and the capacitor 3 constitute a DC power source.

  The inverter circuit 4 includes a U-phase arm composed of semiconductor switching elements Q1 and Q4 connected in series between DC input terminals P and N, a V-phase arm composed of semiconductor switching elements Q2 and Q5, and semiconductor switching elements Q3 and Q6. And a W-phase arm. Here, a connection midpoint between the semiconductor switching elements Q1 and Q4, a connection midpoint between the semiconductor switching elements Q2 and Q5, and a connection midpoint between the semiconductor switching elements Q3 and Q6 are respectively output terminals of the inverter circuit 4. U, V, W.

  The control circuit 8 generates a switching signal for ON / OFF control of the semiconductor switching elements Q1 to Q6 of the inverter circuit 4. This signal is generally PWM modulated. The DC voltage smoothed by the capacitor 3 is converted into a desired AC voltage by the on / off operation of the semiconductor switching elements Q1 to Q6 of the inverter circuit 4. The AC voltage converted by the inverter circuit 4 is output from the output terminals U to W and supplied to the induction motor 5.

  The noise reduction circuit 9 includes a power transformer T1 having a primary winding connected to both ends of the AC power source 1a, a rectifier circuit Rf having an AC input terminal connected to a secondary winding of the power transformer T1, and a DC of the rectifier circuit Rf. The voltage across the capacitors C2 and C3 and the capacitors C2 and C3, which are connected in series between the output terminals and whose midpoint of connection is connected to the negative DC input terminal N of the inverter circuit 4, is applied as the operating voltage and leaks to the ground. Transistors Tr1 and Tr2 as current control elements through which a compensation current for canceling the current flows, and a capacitor C1 connected between the connection midpoint of the transistors Tr1 and Tr2 and the ground are provided. The transistor Tr1 is an NPN type, and the transistor Tr2 is a PNP type transistor.

  Incidentally, a stray capacitance Cs exists between the winding of the induction motor 5 and the housing as shown by a broken line in FIG. On the other hand, a rectangular wave pulse voltage PWM-modulated by the inverter circuit 4 is applied to the winding of the induction motor 5. This pulse voltage is applied across the stray capacitance Cs. As a result, a pulsed current I1 that charges and discharges the stray capacitance Cs flows between the winding of the induction motor 5 and the ground.

  The pulsed current I1 is represented by I1 = Cs × (dv / dt). Here, dv / dt is the time change rate of the rectangular wave pulse voltage applied to the winding of the induction motor 5 by the switching operation of the semiconductor switching elements Q1 to Q6 of the inverter circuit 4.

  In FIG. 8, when the noise reduction circuit 9 does not function, the pulse current I1 leaks to the ground at the rise and fall timings of the rectangular wave pulse voltage applied to the winding of the induction motor 5. Flowing as.

  For example, when the winding voltage of the induction motor 5 increases stepwise with respect to the voltage of the casing, a leakage current I1 flows from the winding of the induction motor 5 toward the ground. On the other hand, when the winding voltage of the induction motor 5 decreases stepwise, a leakage current I1 flows from the ground toward the winding of the induction motor 5.

  This leakage current I1 returns to the DC input terminal of the inverter circuit 4 through the ground and the DC power supply 6. If this leakage current I1 flows to the ground, it becomes a noise current, which may cause an electric shock or malfunction of the leakage breaker, and must be removed.

  Therefore, Patent Document 1 discloses a noise reduction device that cancels the leakage current I1 by injecting into the ground a current having the same polarity and the same polarity as the leakage current I1 detected by the leakage current detector 7 ( (See FIG. 8.)

Specifically, the noise reduction control circuit 10 adds the signal generated based on the switching signals of the semiconductor switching elements Q1 to Q6 and the signal detected by the leakage current detector 7 to drive the transistors Tr1 and Tr2. A control signal S _B is generated. Control signal _{S B} of the transistors Tr1, Tr2, by the switching signal of the semiconductor switching element Q1~Q3 is the upper arm of the inverter circuit 4 subtracts the switching signal of the semiconductor switching element Q4~Q6 a lower arm for adding can get.

Control signal S _B noise reduction control circuit 10 generates is supplied to both the base terminal of the transistor Tr1, Tr2 (control terminal) on amplified by the base signal amplifier Amp. Transistors Tr1 and Tr2 is, the reverse operation to each other in accordance with the control signal _{S B,} to inject current I2 to cancel the leakage current I1.

Patent Document 2 discloses a noise reduction device that compensates for a current leaking to the power supply side by canceling the common mode voltage.
This noise reduction device detects the voltage across the ground capacitor connected to the main circuit line between the AC power supply 1a and the rectifier circuit 2a, and generates a canceling voltage having the opposite polarity and the same magnitude as the detected voltage. ing. This canceling voltage is superimposed between the AC power supply 1a and the connection point of the grounding capacitor via the common mode transformer.

Japanese Patent No. 3650314 JP 2010-57268 A

  According to the technique disclosed in Patent Document 1, the noise reduction circuit 9 is configured by a power transformer T1 and a rectifier circuit Rf as a canceling voltage power source that supplies the operating voltage V2 of the transistors Tr1 and Tr2. . This is to ensure normal operation of the noise reduction device by insulating the AC power supply 1a and the canceling voltage power supply with the power transformer T1.

  However, since the AC power supply 1a is a power supply of commercial frequency, if the canceling voltage power supply is configured in this way, a large power transformer T1 is required, and there is a problem that the noise reduction device is increased in size.

  Further, according to the technique disclosed in Patent Document 2, a common mode transformer is required as means for superimposing the canceling voltage between the AC power supply 1a and the connection point of the grounding capacitor. However, the common mode transformer for allowing the main circuit current to flow between the AC power source 1a and the rectifier circuit 2a is large, and there is a problem that the noise reduction device is increased in size.

  Further, the switching operation of the semiconductor switching elements Q1 to Q6 generates a noise terminal voltage between the DC input terminal of the inverter circuit 4 and the ground. The noise terminal voltage propagates through the main circuit line of the inverter circuit 4 to the AC power supply 1a side. The propagated noise terminal voltage becomes noise that adversely affects other devices connected to the system of the AC power supply 1a. However, the noise reduction device disclosed in Patent Document 1 and Patent Document 2 cannot reduce the noise terminal voltage.

  The present invention is intended to solve the problem of such a conventional noise reduction device, and cancels a fluctuation component (hereinafter referred to as a noise voltage) of a voltage across a grounding capacitor, which will be described later. Accordingly, an object of the present invention is to provide a low-cost and small-sized noise reduction device that can reduce the noise terminal voltage generated between the input terminal of the power conversion circuit and the ground.

In order to achieve the above object, a noise reduction device provided by the present invention is a noise reduction device for a power conversion circuit that converts a voltage of a DC power source or an AC power source into an AC voltage by a switching operation of a semiconductor switching element. A first grounding capacitor and a second capacitor connected in series between a connection point of a capacitor connected in series between the main circuit lines disposed between the power conversion circuit and a DC power supply or an AC power supply and the ground. A grounding capacitor series circuit including a grounding capacitor, a canceling voltage generating circuit for generating a canceling voltage having a polarity opposite to a noise voltage generated at both ends of the first grounding capacitor, and a primary winding connected to the canceling voltage generating circuit And a secondary winding is connected across the second ground capacitor to transform the cancellation voltage to the same magnitude as the noise voltage. Comprising a vessel, the said when the noise voltage is generated at both ends of the first grounding capacitor, which comprises suppressing the variation in the voltage across the grounding capacitor series circuit to generate the offset voltage.

  The noise voltage generated at both ends of the first grounding capacitor is approximately equal to the noise terminal voltage generated between the main circuit line disposed between the power conversion circuit and the DC power supply or AC power supply and the ground. The noise terminal voltage can be reduced by canceling this voltage with a voltage having the opposite polarity and the same magnitude.

  The noise reduction device provided by the present invention also has a capacitor in series between the second grounding capacitor and the secondary winding of the cancellation transformer or between the primary winding of the cancellation transformer and the cancellation voltage generation circuit. It is characterized by being connected to.

  As a result, the DC component and low-frequency component of the voltage output from the cancellation voltage generation circuit are removed, and only the high-frequency component corresponding to the noise voltage is applied to the cancellation transformer. Therefore, the canceling transformer can be reduced in size, and further, the noise reduction device can be reduced in price and size.

  Also, the cancellation voltage generation circuit of the noise reduction device includes a cancellation voltage power source as an operating power source, and a capacitor connected in series to both ends of the cancellation voltage power source and having a midpoint of connection connected to one end of the primary winding of the cancellation transformer It is characterized by comprising a series circuit and a voltage control element series circuit connected in series to both ends of the canceling voltage power source and having a connection midpoint connected to the other end of the primary winding of the canceling transformer.

  Furthermore, the power conversion circuit includes a current detector that detects the output current, and is based on the polarity of the output current of the power conversion circuit detected by the current detector and the signal that switches the semiconductor switching element of the power conversion circuit. A control signal for the voltage control element series circuit is generated.

  Further, the control signal of the voltage control element series circuit is such that the semiconductor switching element connected to the positive input terminal of the power conversion circuit is switched from the non-conductive state to the conductive state during the period when the power conversion circuit outputs a positive current. The semiconductor switching element connected to the positive input terminal of the power conversion circuit during the first timing when the switching signal of the semiconductor switching element changes in order to achieve the above and the period during which the power conversion circuit outputs a positive current The negative input terminal of the power conversion circuit during the second timing when the switching signal of the semiconductor switching element changes in order to change the switching state of the semiconductor switching element from the conduction state to the non-conduction state and the period during which the power conversion circuit outputs a negative current In order to switch the semiconductor switching element connected to the non-conductive state to the conductive state, The semiconductor switching element connected to the negative input terminal of the power conversion circuit is changed from the conductive state to the nonconductive state in the third timing when the signal changes and the period in which the power conversion circuit outputs a negative current. Therefore, the switching timing of the semiconductor switching element changes at the fourth timing when the switching signal changes.

  As a result, the canceling voltage can be generated in synchronization with the generation of the noise terminal voltage. Therefore, it is possible to effectively reduce the noise terminal voltage generated between the main circuit line disposed between the power conversion circuit and the DC power source or the AC power source and the ground.

Moreover, the power converter device includes a noise reduction device provided by the present invention.
Accordingly, it is possible to provide a power conversion device that can effectively reduce the noise terminal voltage while being inexpensive and small.

  According to the present invention, since the frequency of the cancellation voltage generated by the cancellation voltage generation circuit corresponds to the switching frequency of the semiconductor switching element included in the power conversion circuit, the cancellation transformer can be reduced in size and the noise reduction device can be reduced. Price and size can be reduced.

  In addition, since the cancellation voltage can be generated in synchronization with the generation timing of the noise terminal voltage, the noise terminal voltage can be effectively reduced.

It is a figure for demonstrating 1st Embodiment of the power converter device provided with the noise reduction apparatus which concerns on this invention. FIG. 2 is a block diagram for explaining an example of a noise reduction control circuit shown in FIG. 1. It is a figure for demonstrating the relationship of the switching signal of the semiconductor switching element of a power converter circuit. (A) A diagram showing a path through which a positive U-phase current flows during period 1, (b) a diagram showing a path through which a positive U-phase current flows during period 2, and (c) during period 3 FIG. 6 is a diagram showing a path through which a positive U-phase current flows, and (d) a diagram showing a path through which a positive U-phase current flows during a period 4. (A) A diagram showing a path through which a negative polarity U-phase current flows during period 1, (b) a diagram showing a path through which a negative polarity U phase current flows during period 2, and (c) during period 3 FIG. 4 is a diagram illustrating a path through which a negative polarity U-phase current flows, and (d) a diagram illustrating a path through which a negative polarity U-phase current flows during a period 4. It is a figure for demonstrating other embodiment of the power converter device provided with the noise reduction apparatus which concerns on this invention. It is a figure for demonstrating other embodiment of the power converter device provided with the noise reduction apparatus which concerns on this invention. It is a figure for demonstrating the power converter device provided with the conventional noise reduction apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. In FIG. 1 to FIG. 7, the same reference numerals are given to components common to the power conversion device and the noise reduction device shown in FIG. 8, and description thereof is omitted.

FIG. 1 is a diagram for explaining a first embodiment of a power conversion device including a noise reduction device according to the present invention. In FIG. 1, 1c is a DC power supply, 3a and 3b are capacitors connected in series to both ends of the DC power supply 1c, 4 is an inverter circuit, 5 is an induction motor as a load of the inverter circuit 4, and 8 is controlling the inverter circuit 4. inverter control circuit, 9a noise reduction circuit, 10a is the noise reduction control circuit for generating a control signal S _B of the noise reduction circuit 9a, it is 31 to 33 is a current detector for detecting an output current of the inverter circuit 4.

The configuration and operation of the noise reduction circuit 9a and the noise reduction control circuit 10a will be described below.
The noise reduction circuit 9a includes a first ground capacitor Co1, a second ground capacitor Co2, and a second ground capacitor Co2 that are connected in series between the connection midpoint of the capacitor series circuit including the capacitors 3a and 3b and the ground. Between the DC output terminals of the canceling transformer T2 having a secondary winding connected to both ends thereof, a capacitor C1 having one end connected to one end of the primary winding of the canceling transformer T2, the canceling voltage power supply Vd, and the canceling voltage power supply Vd Is connected in series to the other end of the primary winding of the cancellation transformer T2, and the voltage across the capacitor series circuit composed of the capacitors C2 and C3 is applied as the operating voltage. The connection midpoint includes transistors Tr1 and Tr2 connected in series to the other end of the capacitor C1.

The transistors Tr1 and Tr2 are voltage control elements, which are an NPN transistor and a PNP transistor, respectively. Transistors Tr1, Tr2 is the reverse operation to each other in response to the control signal S _B, to apply the offset voltage to the primary winding of the cancellation transformer T2. On the other hand, the canceling transformer T2 transforms the canceling voltage applied to the primary winding to the same magnitude as the noise voltage generated at both ends of the first grounding capacitor.

Next, the relationship between the inverter control circuit 8 and the noise reduction control circuit 10a will be described with reference to FIG.
The inverter control circuit 8 includes U, V, and W phase PWM (pulse width modulation) controllers 81 to 83 and switching signal generators 84 to 86. The inverter control circuit 8 receives the switching signals G1 to G6 of the semiconductor switching elements Q1 to Q6. Generate.

  The U-phase switching signal generator 84 generates the switching signals G1 and G4 of the semiconductor switching elements Q1 and Q4 constituting the U-phase of the inverter circuit 4 based on the signal output from the U-phase PWM controller 81. The output signal G1 of the U-phase switching signal generator 84 is “1” when the semiconductor switching element Q1 is turned on, and is “0” when it is turned off. The switching signal G4 of the semiconductor switching element Q4 is a signal obtained by inverting “1” and “0” of the switching signal G1. However, in order to prevent the semiconductor switching elements Q1 and Q4 from being turned on at the same time, a pause period in which the switching signals G1 and G4 are both “0” is provided.

  V-phase switching signal generator 85 and W-phase switching signal generator 86 generate switching signals G3 to G6 of semiconductor switching elements Q2 and Q5 and semiconductor switching elements Q3 and Q6 in the same manner as U-phase switching signal generator 84. .

  On the other hand, the noise reduction control circuit 10a includes current polarity determination units 101 to 103, logical inversion operators 111 to 113, logical product operators (AND) 121 to 126, and a control signal generation unit 131.

  First, the U-phase current polarity determination unit 101 determines the polarity of the U-phase current by, for example, comparing the U-phase current signal Iu input from the current detector 31 with the reference value 0 [A]. To do. As a result of determining the current polarity, the current polarity determination unit 101 outputs “1” when the U-phase current is larger than 0 [A], and outputs “0” when it is smaller.

The logic inversion operator 111 generates a signal obtained by inverting “1” and “0” with respect to the signal input from the current polarity determination unit 101.
The AND operator 121 performs an AND operation between the switching signal G1 of the semiconductor switching element Q1 and the output signal of the current polarity determination unit 101, and outputs the result. On the other hand, the logic inversion operator 111 inverts and outputs the signal input from the current polarity determination unit 101. The logical product operator 122 performs a logical product operation between the switching signal G4 of the semiconductor switching element Q4 and the signal output from the logical inversion operator 111, and outputs the result.

  As a result of the above logical operation, the output signal of the AND operator 121 becomes “1” when the semiconductor switching element Q1 is in the ON state in the period in which the U-phase current of the inverter circuit 4 is positive, and the other period In this case, it is “0”. On the other hand, the output signal of the logical product operator 122 becomes “1” when the semiconductor switching element Q4 is in the ON state in the period in which the U-phase current of the inverter circuit 4 is negative, and “ 0 ".

  Similar arithmetic processing is performed between the V-phase current and the switching signals G2 and G5 of the V-phase semiconductor switching elements Q2 and Q5. Similar calculation processing is also performed between the W-phase current and the switching signals G3 and G6 of the W-phase semiconductor switching elements Q3 and Q6. Each operation result is output from the logical product operators 123 to 126.

  That is, the output signal of the V-phase AND operator 123 is “1” only when the switching signal of the semiconductor switching element Q2 is on during the period when the V-phase current of the inverter circuit 4 is positive. It becomes “0” during the period. Further, the output signal of the AND operator 124 is “1” only when the switching signal of the semiconductor switching element Q5 is ON during the period in which the V-phase current of the inverter circuit 4 is negative, and during other periods. Becomes “0”.

  Further, the output signal of the W-phase AND operator 125 becomes “1” only when the switching signal of the semiconductor switching element Q3 is ON during the period when the W-phase current of the inverter circuit 4 is positive. It becomes “0” during the period. Further, the output signal of the AND operator 126 becomes “1” only when the switching signal of the semiconductor switching element Q6 is ON during the period in which the W-phase current of the inverter circuit 4 is negative, and during the other periods Becomes “0”.

The control signal generation unit 131 adds signals output from the logical product operators 121, 123, and 125, and subtracts and outputs signals output from the logical product operators 122, 124, and 126.
Signal output from the control signal generator 131, a signal _{S B} for controlling the transistors Tr1 and Tr2 of the noise reduction circuit 9a.

With the above logical operation, the noise reduction control circuit 10a changes at a timing that coincides with the voltage change timing generated in the winding of the induction motor 5 when the semiconductor switching elements Q1 to Q6 of the inverter circuit 4 are turned on / off. The control signal S _B to be output can be output.

Here, with reference to FIGS. 3 to 5, the control change timing of the signal S _B is described that matches the timing of the voltage change that occurs in the winding of the induction motor 5.
First, the switching signals of the U-phase semiconductor switching elements Q1 and Q4 have four periods (period 1 to period 4) shown in FIG. Period 1 is a period in which the semiconductor switching element Q1 is on and the semiconductor switching element Q4 is off. Period 3 is a period during which semiconductor switching element Q4 is turned on and semiconductor switching element Q1 is turned off. Periods 2 and 4 are idle periods provided so that the semiconductor switching elements Q1 and Q4 do not turn on at the same time, and are periods in which both of the semiconductor switching elements Q1 and Q4 are off.

  Next, in the period 1 to the period 4, the relationship between the path through which the positive polarity U-phase current flows and the voltage of the output terminal U will be specifically described with reference to FIGS. 4A, since the semiconductor switching element Q1 is on, a U-phase current flows from the DC input terminal P toward the induction motor 5 via the semiconductor switching element Q1. In the period 2 of FIG. 4B, since the semiconductor switching elements Q1 and Q4 are off, a U-phase current flows from the DC input terminal N toward the induction motor 5 via the diode D4. In the period 3 of FIG. 4C, since the semiconductor switching element Q1 is OFF, the U-phase current flows from the DC input terminal N toward the induction motor 5 via the diode D4. In the period 4 of FIG. 4D, since the semiconductor switching elements Q1 and Q4 are off, the U-phase current flows from the DC input terminal N to the induction motor 5 via the diode D4 as in the period 2. It flows toward.

  That is, when the polarity of the U-phase current is positive, the voltage of the output terminal U becomes the voltage V1 [V] of the DC input terminal P only during the period 1 in which the semiconductor switching element Q1 is on. Therefore, when the polarity of the U-phase current is positive, the voltage at the output terminal U changes from the voltage 0 [V] at the DC input terminal N to the voltage V1 [V at the DC input terminal P when the period 4 shifts to the period 1. ] Changes. When the period 1 is shifted to the period 2, the voltage at the output terminal U changes from the voltage V1 [V] at the DC input terminal P to the voltage 0 [V] at the DC input terminal N. This change in voltage is synchronized only with the on / off operation of the semiconductor switching element Q1.

  On the other hand, when shifting from the period 2 to the period 3 and when shifting from the period 3 to the period 4, the voltage of the output terminal U is equal to the voltage 0 [DC of the DC input terminal N regardless of the on / off operation of the semiconductor switching element Q 4. V], and no voltage change occurs.

  Next, when the polarity of the U-phase current is negative (when the current flows from the induction motor 5 toward the inverter circuit 4), the switching signals of the U-phase semiconductor switching elements Q1 and Q4 are similarly shown in FIG. There are four periods shown. 5A to 5D, the relationship between the path through which the negative-polarity U-phase current flows during period 1 to period 4 and the voltage at output terminal U will be described in detail.

  In the period 1 of FIG. 5A, since the semiconductor switching element Q4 is OFF, a U-phase current flows from the induction motor 5 toward the DC input terminal P via the diode D1. In the period 2 of FIG. 5B, since the semiconductor switching elements Q1 and Q4 are off, the U-phase current flows from the induction motor 5 toward the DC input terminal N via the diode D1 as in the period 1. Flowing. In period 3 of FIG. 5C, since the semiconductor switching element Q4 is on, the U-phase current flows from the induction motor 5 toward the DC input terminal N via the semiconductor switching element Q4. In the period 4 of FIG. 5D, since the semiconductor switching elements Q1 and Q4 are off, the U-phase current flows from the induction motor 5 to the DC input terminal N via the diode D1 as in the period 2. It flows toward.

  That is, when the polarity of the U-phase current is negative, the voltage of the output terminal U becomes the voltage 0 [V] of the DC input terminal N only during the period 3 in which the semiconductor switching element Q4 is on. Therefore, when the polarity of the U-phase current is negative, the voltage at the output terminal U changes from the voltage V1 [V] at the DC input terminal P to the voltage 0 [V at the DC input terminal N when the period 2 shifts to the period 3. ] Changes. Further, when the period 3 is shifted to the period 4, the voltage at the output terminal U changes from the voltage 0 [V] at the DC input terminal N to the voltage V1 [V] at the DC input terminal P. This change in voltage is synchronized only with the on / off operation of the semiconductor switching element Q4.

  On the other hand, when the period 4 shifts to the period 1 and when the period 1 shifts to the period 2, the voltage of the output terminal U is equal to the voltage V1 [ V], and no voltage change occurs.

  As described above, the voltage change timing of the output terminal U coincides with the change timing of the switching signal G1 of the U-phase semiconductor switching element Q1 when the U-phase current is positive, and when the U-phase current is negative. This coincides with the change timing of the switching signal G4 of the U-phase semiconductor switching element Q4.

  Similarly, the change timing of the voltage at the output terminal V coincides with the change timing of the switching signal G2 of the V-phase semiconductor switching element Q2 when the V-phase current is positive, and when the V-phase current is negative. This coincides with the timing at which the switching signal G5 of the V-phase semiconductor switching element Q5 changes. The voltage change timing of the output terminal W coincides with the timing at which the switching signal G3 of the W-phase semiconductor switching element Q3 changes when the W-phase current is positive, and W when the W-phase current is negative. This coincides with the timing at which the switching signal G6 of the phase semiconductor switching element Q6 changes.

Therefore, the timing at which the control signal S _B generated by the noise reduction control circuit 10a is changed, the output terminal U of the inverter circuit 4, V, coincides with the timing of the W voltage changes.
Returning to FIG. 1, the transistors Tr1 and Tr2 of the noise reduction circuit 9a, operates in accordance with the control signal _{S B.} Due to the operation of the transistors Tr1 and Tr2, the polarity of the secondary winding of the canceling transformer T2, that is, both ends of the second grounding capacitor Co2, is opposite to that of the noise voltage ΔVco1 generated at both ends of the first grounding capacitor Co1. Are induced by the equal voltage Vco2. As a result, the noise terminal voltage generated in the DC input line of the inverter circuit 4 can be canceled.

  For example, when a positive polarity U-phase current is flowing from the inverter circuit 4 toward the induction motor 5, when the semiconductor switching element Q1 changes from an off state to an on state, the voltage at the output terminal U of the U-phase arm is DC. The voltage changes from 0 [V] at the input terminal N to V1 [V] at the DC input terminal P. At this time, a voltage change of dv / dt occurs at both ends of the stray capacitance Cs of the induction motor 5, and a leakage current I1 flows from the induction motor 5 to the ground. When the leakage current I1 charges or discharges the ground capacitor Co1, a noise voltage ΔVco1 substantially equal to the noise terminal voltage is generated at both ends of the ground capacitor Co1.

On the other hand, the control signal S _B outputted from the noise reduction control circuit 10a, the value of the signal "1" is added to the output logical product operator 121, stepwise changes. When the control signal S _B is stepwise increased, the operating state of the transistors Tr1 and Tr2 changes in the noise reduction circuit 9a, offset voltage corresponding to the control signal S _B to the primary winding of the cancellation transformer T2 is applied. The cancellation voltage applied to the primary winding of the cancellation transformer T2 is transformed and induced as a voltage Vco2 in the secondary winding of the cancellation transformer T2.

  As a result, the voltage across the grounded capacitor series circuit composed of the first grounded capacitor Co1 and the second grounded capacitor Co2 is kept constant. Thereby, the noise terminal voltage generated in the DC input line of the inverter circuit 4 can be reduced.

Capacitor C1 is a coupling capacitor for removing a DC component and a low-frequency component from the voltage generated by the operation of transistors Tr1 and Tr2.
Moreover, the voltage of the frequency according to the switching frequency of the semiconductor switching elements Q1-Q6 of the inverter circuit 4 is applied to the cancellation | transformation transformer T2 by operation | movement of transistor Tr1, Tr2. The switching frequency of the semiconductor switching elements Q1 to Q6 is generally several kHz to several tens kHz, which is higher than the commercial frequency of 50 Hz or 60 Hz.

  Therefore, the canceling transformer T2 can be significantly reduced in size as compared with the power transformer T1 to which a commercial frequency voltage is applied. As a result, the noise reduction device can be reduced in size and cost.

Next, another embodiment according to the present invention will be described with reference to FIGS. 6 and 7.
FIG. 6 shows an embodiment in which a single-phase AC power source 1a and a rectifier circuit 2a constitute a DC power source, and a capacitor series circuit composed of capacitors 41 and 42 is provided between the AC input terminals of the rectifier circuit 2a. A first ground capacitor Co1 and a second ground capacitor Co2 are connected in series between the connection midpoint of the capacitors 41 and 42 and the ground. Further, the secondary winding of the cancellation transformer T2 is connected in parallel to both ends of the second ground capacitor Co2. Other components are the same as those in the embodiment shown in FIG.

  Even with this configuration, the canceling voltage Vco2 for canceling the noise voltage ΔVco1 generated at both ends of the first ground capacitor Co1 can be generated at both ends of the second ground capacitor. As a result, the voltage across the ground capacitor series circuit can be stabilized, and the noise terminal voltage can be reduced. In addition, the offset transformer T2 can be significantly reduced in size. As a result, the noise reduction device can be reduced in size and cost.

  Next, FIG. 7 is an embodiment in the case where the AC power supply has three phases. In the present embodiment, a three-phase AC power source 1b and a three-phase rectifier circuit 2b constitute a DC power source. Capacitors 41 to 43 are connected in a star shape between the AC input terminals of the rectifier circuit 2b. A first ground capacitor Co1 and a second ground capacitor Co2 are connected in series between the neutral point of the star-connected capacitors 41 to 43 and the ground. Further, the secondary winding of the cancellation transformer T2 is connected in parallel to both ends of the second ground capacitor Co2. Other components are the same as those in the embodiment shown in FIG.

  Even with this configuration, the canceling voltage Vco2 for canceling the noise voltage ΔVco1 generated at both ends of the first ground capacitor Co1 can be generated at both ends of the second ground capacitor. As a result, the voltage across the ground capacitor series circuit can be stabilized, and the noise terminal voltage can be reduced. In addition, the offset transformer T2 can be significantly reduced in size. As a result, the noise reduction device can be reduced in size and cost.

  In the above-described embodiment, the capacitance value of the ground capacitor series circuit formed of the first ground capacitor Co1 and the second ground capacitor Co2 is the total value of the capacitances of the capacitors 3a and 3b or the capacitors 41 to 41. It is preferable to set it to about 1/10 times the total value of the capacitance of 43. By setting the capacitance value of the ground capacitor series circuit in this way, a voltage corresponding to about 90% of the noise terminal voltage generated at the input terminal of the inverter circuit 4 is generated at both ends of the ground capacitor series circuit.

  The capacitance value of the first ground capacitor Co1 is preferably set to about 100 times the capacitance value of the stray capacitance Cs of the induction motor 5. By setting the capacitance value of the grounded capacitor series circuit in this way, the noise voltage ΔVco1 generated at both ends of the first grounded capacitor Co1 is about the potential that varies between the winding of the induction motor 5 and the ground. The voltage is 1/100.

  As described above, the canceling voltage generated by the noise reduction device 9a can be made extremely low with respect to the voltage V1 of the DC power supply. Thereby, the noise reduction apparatus 9a can be further reduced in size.

  For example, when the voltage V1 of the DC power supply is 600 [V], the maximum value of the noise voltage ΔVco1 generated across the first ground capacitor Co1 is about 6 [V]. If the maximum value of the noise voltage ΔVco1 is about 6 [V], the circuit voltage of the noise reduction device 9a may be about 10 [V].

  Therefore, the noise reduction device can be composed of transistors Tr1 and Tr2 having a withstand voltage between terminals of several tens of volts, capacitors C1 to C3, and the like. By using such a low withstand voltage component, an inexpensive and small noise reduction device can be provided.

  Furthermore, in general, low withstand voltage components are excellent in high frequency characteristics, and therefore, a noise reduction device constituted by such low withstand voltage components can effectively reduce high frequency noise terminal voltages. .

  DESCRIPTION OF SYMBOLS 1a, 1b ... AC power source, 1c ... DC power source, 2a, 2b ... Rectifier circuit, 3, 3a, 3b ... Capacitor, 4 ... Inverter circuit, 5 ... Induction motor, 6 ... DC power supply, 7 ... Leakage current detector, 8 ... Inverter control circuit, 9, 9a ... Noise reduction circuit, 10, 10a ... Noise reduction control circuit, 31-33 ... Current detector, 41 to 43, capacitor, 81, U phase PWM control unit, 82, V phase PWM control unit, 83, W phase PWM control unit, 84, U phase switching signal Generation unit, 85 ... V-phase switching signal generation unit, 86 ... W-phase switching signal generation unit, 101 to 103 ... current polarity determination unit, 111 to 113 ... logic inversion operator, 121 to 126 ... AND operator, 131 ... Control signal Component, Amp ... base signal amplifier, C1-C3 ... capacitor, Co1 ... first ground capacitor, Co2 ... second ground capacitor, Cs ... stray capacitance, D1-D6. .. Diodes, Q1 to Q6... Semiconductor switching elements, Rf... Rectifier circuit, T1... Power transformer, T2 .. cancellation transformer, Tr1, Tr2.・ Cancellation voltage power supply

Claims (7)

A noise reduction device for a power conversion circuit that converts a voltage of a DC power supply or an AC power supply into an AC voltage by a switching operation of a semiconductor switching element,
The noise reduction device is:
A first ground capacitor and a second capacitor connected in series between a connection point of a capacitor connected in series between a main circuit line disposed between the power conversion circuit and a DC power source or an AC power source and the ground. A grounded capacitor series circuit comprising a grounded capacitor;
A canceling voltage generating circuit for generating a canceling voltage having a polarity opposite to a noise voltage component generated at both ends of the first grounding capacitor by a switching operation of the semiconductor switching element;
A canceling transformer having a primary winding connected to the cancellation voltage generating circuit and a secondary winding connected to both ends of the second grounded capacitor to transform the cancellation voltage to the same magnitude as the noise voltage;
With
A noise reduction apparatus characterized in that, when the noise voltage is generated in the first ground capacitor, the canceling voltage is generated to suppress the fluctuation of the voltage across the ground capacitor series circuit.   The noise reduction device according to claim 1, wherein a capacitor is connected in series between the second grounding capacitor and the secondary winding of the cancellation transformer.   The noise reduction device according to claim 1, wherein a capacitor is connected in series between a primary winding of the cancellation transformer and the cancellation voltage generation circuit. The canceling voltage generation circuit of the noise reduction device,
The cancellation voltage power supply as its operating power supply,
A capacitor series circuit connected in series to both ends of the canceling voltage power source, the connection midpoint of which is connected to one end of the primary winding of the canceling transformer;
A voltage control element series circuit connected in series to both ends of the canceling voltage power source, the connection midpoint of which is connected to the other end of the primary winding of the canceling transformer;
The noise reduction device according to any one of claims 1 to 3, further comprising: The power conversion circuit includes a current detector for detecting the output current,
The canceling voltage generating circuit is
The polarity of the output current of the power conversion circuit detected by the current detector;
A signal for switching the semiconductor switching element of the power conversion circuit;
The noise reduction device according to claim 4, wherein a control signal for the voltage control element series circuit is generated based on The control signal of the voltage control element series circuit is:
In the period in which the power conversion circuit outputs a positive current, the semiconductor switching element connected to the positive input terminal of the power conversion circuit is switched from a non-conductive state to a conductive state. A first timing at which the switching signal changes;
In the period in which the power conversion circuit outputs a positive current, the semiconductor switching element connected to the positive input terminal of the power conversion circuit is switched from a conductive state to a non-conductive state. A second timing at which the switching signal changes;
In the period in which the power conversion circuit outputs a negative current, the semiconductor switching element is connected to the negative input terminal of the power conversion circuit to change the semiconductor switching element from a non-conductive state to a conductive state. A third timing at which the switching signal changes;
In the period in which the power conversion circuit outputs a negative current, the semiconductor switching element connected to the negative input terminal of the power conversion circuit is switched from a conductive state to a non-conductive state. A fourth timing at which the switching signal changes;
The noise reduction device according to claim 5, wherein The power converter device provided with the noise reduction apparatus of any one of Claim 1 thru | or 6.