JP5609950B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a MIS (metal-insulating film-semiconductor) type semiconductor device having a trench gate structure and a method for manufacturing the same.

FIG. 48 is a cross-sectional view showing the configuration of a MIS field effect transistor (FET) having a conventional trench gate structure. As shown in FIG. 48, in the conventional vertical trench gate type n-channel MISFET, the p base region 2, the n ⁺ source region 3 and the p ⁺ contact region are arranged on the first main surface side with the n drift region 1 interposed therebetween. 4 is formed, and an n ⁺ drain region 5 is formed on the second main surface side. Gate insulating film 6 and gate electrode 7 are formed in trench 8 that reaches p-type base region 2 and reaches n drift region 1 from the first main surface.

Source electrode 9 is electrically connected to n ⁺ source region 3 and p ⁺ contact region 4 and insulated from gate electrode 7 by interlayer insulating film 10. Further, the drain electrode 11 is electrically connected to the n ⁺ drain region 5. In FIG. 48, a broken line indicated by reference numeral 12 in the p base region 2 and a broken line indicated by reference numeral 13 in the n drift region 1 indicate the ends of the depletion layer when the MISFET is in the OFF state, respectively.

  FIG. 49 is a characteristic diagram schematically showing the electric field intensity distribution along A-A ′ in FIG. 48. In the vertical axis of FIG. 49, B1, B2, and B3 are the depletion layer end 12 (B1) in the p base region 2 and the pn junction of the p base region 2 and the n drift region 1 respectively in AA ′ of FIG. It corresponds to the surface 14 (B2) and the end 13 (B3) of the depletion layer in the n drift region 1. The breakdown voltage of the MISFET corresponds to the area of the electric field distribution when the maximum electric field strength reaches the critical electric field strength in the characteristic diagram shown in FIG.

By the way, in order to reduce the capacitance between the gate and the drain, a MIS type semiconductor device in which thick SiO ₂ is provided at the bottom of the trench is known (for example, see Patent Document 1). In addition, in a MISFET having a super junction structure in which a p-type impurity layer is provided adjacent to the n drain drift region, an oxide film is provided under the gate electrode in order to reduce the gate-drain capacitance. (For example, refer to Patent Document 2). Also known is a semiconductor device in which a field forming region made of SiO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , SrTiO ₃ or BaTiO ₃ is provided across the n drain drift region forming the pn junction and the p body. (For example, refer to Patent Document 3).

Further, a semiconductor device having a structure in which SiO ₂ is filled in the lower half of the trench and a gate electrode is provided in the upper half of the trench is known (see, for example, Patent Document 4). A transistor having a structure in which a dielectric layer of SiO ₂ or Si ₃ N ₄ is provided under the gate electrode and a field plate is provided adjacent to the dielectric is known (see, for example, Patent Document 5). .

US Patent Application Publication No. 2004/0166636 (FIG. 3) U.S. Patent No. 5981996 (Fig. 1) International Publication No. 2004/102670 Pamphlet (FIG. 7) Japanese Patent Laying-Open No. 2005-302925 (FIG. 1) JP 2003-204064 A (FIGS. 4 and 5K)

MIS power semiconductor devices such as power MOS (metal-oxide film-semiconductor) FETs and IGBTs (insulated gate bipolar transistors) are required to have low on-resistance. However, in the semiconductor device disclosed in Patent Document 1, it is clear from the same document that SiO ₂ having a thick trench bottom does not contribute to reduction of on-resistance. Therefore, even if the N epitaxial layer (drift region) is elongated and reduced in concentration, the ratio of the resistance of the N epitaxial layer (drift region) to the entire on-resistance increases, so the number of gate electrodes is reduced to a trench gate structure. Even if the number is increased, there is a problem that a sufficiently low on-resistance cannot be achieved as a whole device.

  Further, in the semiconductor device disclosed in Patent Document 2, the p-type impurity layer adjacent to the n drain drift region is provided to reduce the on-resistance, and the oxide film under the gate electrode reduces the on-resistance. Does not contribute. When an imbalance occurs in the number of carriers in the n drain drift region and the p-type impurity layer, the depletion layer is not sufficiently expanded by the carriers remaining in the off state, and the breakdown voltage is reduced. In order to achieve the desired complete depletion, it is necessary to precisely control the impurity concentrations of the n drain drift region and the p-type impurity layer.

  In the semiconductor device disclosed in Patent Document 3, since the field formation region is an ineffective region where no on-current flows, the provision of the field formation region increases the width of the unit element and hinders integration. There is a problem. Moreover, when manufacturing this semiconductor device, it is necessary to form a trench for a gate electrode and a trench for a field formation region deeper than that closely, and to bury these trenches separately. There is also the problem that it is very difficult to do.

  Furthermore, Patent Document 3 discloses a simulation result in the diode structure (FIG. 4 of the same document). However, according to our research, FIG. In the structure shown in FIG. 7, it has been found that it is difficult to obtain the same effect as the simulation result. The reason for this difficulty is as follows.

  FIG. In the structure shown in 3A, since the pn junction is formed by the p region and the n region having the same concentration, the depletion layer sufficiently spreads in both the p region and the n region in the off state. On the other hand, FIG. In the structure shown in FIG. 7, the pn junction is formed by the high-concentration p body and the low-concentration n drain drift region, so that the depletion layer spreads only on the n drain drift region side.

  Even if the depletion layer is forcibly expanded on the p body side, punch-through occurs because the depletion layer reaches the source region. In order to avoid this, even if the range where the depletion layer can be sufficiently expanded by extending the p body side, the equipotential surface is n around the gate electrode on the surface opposite to the field formation region of the pn junction. Since it is pushed into the drain drift region side, it is not possible to expect the depletion layer to expand to match the extension on the p body side. On the contrary, there is a problem that the electric field concentrates around the gate electrode, which causes a breakdown voltage to decrease, and a problem that the channel becomes longer as the p body extends, thereby increasing the on-resistance. Occurs.

  Further, in the semiconductor device disclosed in Patent Document 4, it is necessary to increase the thickness of the drift layer in order to increase the source-drain breakdown voltage. In order to maintain or lower the on-resistance even when the drift layer is thick, the gate drive voltage needs to be equal to or higher than the breakdown voltage between the source and drain. Further, the semiconductor device disclosed in Patent Document 5 has a problem that integration is hindered because a field plate is provided.

  The present invention provides a semiconductor device that can secure a withstand voltage without changing the thickness of the drift layer and can reduce the on-resistance without applying a high gate drive voltage in order to eliminate the above-described problems caused by the prior art. For the purpose. Another object of the present invention is to provide a manufacturing method for easily manufacturing a semiconductor device having such characteristics.

In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a first main surface sandwiching the drift region between a first conductivity type drift region and a second main surface. The drift region is sandwiched between the base region of the second conductivity type formed on the side, the source region of the first conductivity type formed in the surface layer of the base region, and the first main surface. A drain region of a first conductivity type formed on the second main surface side, and a trench reaching the drain region through the base region and the drift region from the first main surface in contact with the source region A high dielectric material embedded in the second main surface side of the junction surface between the base region and the drift region in the trench, and the first main surface and the high dielectric material in the trench. Gate insulating film formed between the body and An insulating gate structure comprising a gate electrode, wherein the high dielectric has a relative dielectric constant larger than that of the silicon oxide film, and a first high portion of an outer portion of the high dielectric along the inner wall surface of the trench is formed. a dielectric than said first high dielectric have a different dielectric constant than the second high dielectric the inner portion, the junction surface between the high dielectric and the gate electrode, said drift region It is characterized in that it is located closer to the first main surface than the junction surface with the drain region .

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type source region formed on the surface layer of the base region, and a first main surface formed between the first main surface and the drift region between the first main surface and the first main surface. A drain region of one conductivity type; a trench that is in contact with the source region and extends from the first main surface through the base region and the drift region to the drain region; and the base region in the trench and the base region A high dielectric embedded on the second main surface side of the junction surface with the drift region, and a gate insulating film formed between the first main surface and the high dielectric in the trench And an insulated gate structure comprising a gate electrode; A dielectric constant of the high dielectric material is larger than that of the silicon nitride film; and a first high dielectric material of the high dielectric material at an outer portion along an inner wall surface of the trench, and the first high dielectric material. It has a different dielectric constant than the second high dielectric in the inner portion than the bonding surface between the gate electrode and the high dielectric, the first than the junction surface between the drift region and the drain region 1 on the main surface side .

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type emitter region formed on the surface layer of the base region, and a first main surface formed on the second main surface side with the drift region interposed between the first main surface and the first main surface. A collector region of two conductivity types, a trench that contacts the emitter region and penetrates the base region and the drift region from the first main surface to the collector region , and the base region and the base in the trench A high dielectric embedded on the second main surface side of the junction surface with the drift region, and a gate insulating film formed between the first main surface and the high dielectric in the trench Gate structure comprising a gate electrode The dielectric constant of the high dielectric material is larger than that of the silicon oxide film, and the first high dielectric material in the outer portion along the inner wall surface of the trench of the high dielectric material, and the first high dielectric material, than the dielectric have a different dielectric constant than the second high dielectric the inner portion, the junction surface between the high dielectric and the gate electrode, than the junction surface between the drift region and the collector region It is located on the first main surface side .

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type emitter region formed on the surface layer of the base region, and a first main surface formed on the second main surface side with the drift region interposed between the first main surface and the first main surface. A collector region of two conductivity types, a trench that contacts the emitter region and penetrates the base region and the drift region from the first main surface to the collector region , and the base region and the base in the trench A high dielectric embedded on the second main surface side of the junction surface with the drift region, and a gate insulating film formed between the first main surface and the high dielectric in the trench Gate structure comprising a gate electrode A dielectric constant of the high dielectric material is larger than that of the silicon nitride film, and a first high dielectric material in an outer portion along an inner wall surface of the trench of the high dielectric material, and the first high dielectric material, than the dielectric have a different dielectric constant than the second high dielectric the inner portion, the junction surface between the high dielectric and the gate electrode, than the junction surface between the drift region and the collector region It is located on the first main surface side .

  In the semiconductor device according to the present invention as set forth in the invention described above, the high dielectric is in contact with the drain region. In the semiconductor device according to the present invention, the high dielectric is in contact with the collector region in the above-described invention. The semiconductor device according to the present invention is characterized in that, in the above-described invention, the deepest portion of the high dielectric is deeper than an end of the depletion layer extending in the drift region in the off state. In the semiconductor device according to the present invention, the high dielectric is in contact with the gate electrode in the above-described invention.

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type source region formed on the surface layer of the base region, and a first main surface formed between the first main surface and the drift region between the first main surface and the first main surface. A drain region of one conductivity type; a trench that is in contact with the source region and extends from the first main surface through the base region and the drift region to the drain region; and the base region in the trench and the base region A plurality of high dielectrics embedded on the second main surface side of the junction surface with the drift region; and the first main surface and the plurality of high dielectrics in the trench. Between the high dielectric provided at the position of the main surface of 1 An insulating gate structure including a formed gate insulating film and a gate electrode, wherein a relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon oxide film, a first high dielectric outer portion along the inner wall surface of the trench, have a different dielectric constant than the second high dielectric of the inner portion than the first high dielectric, the gate The bonding surface between the electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the first bonding surface between the drift region and the drain region. It is located in the main surface side of this.

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type source region formed on the surface layer of the base region, and a first main surface formed between the first main surface and the drift region between the first main surface and the first main surface. A drain region of one conductivity type; a trench that is in contact with the source region and extends from the first main surface through the base region and the drift region to the drain region; and the base region in the trench and the base region A plurality of high dielectrics embedded on the second main surface side of the junction surface with the drift region; and the first main surface and the plurality of high dielectrics in the trench. Between the high dielectric provided at the position of the main surface of 1 An insulating gate structure including a formed gate insulating film and a gate electrode, wherein a relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon nitride film, a first high dielectric outer portion along the inner wall surface of the trench, have a different dielectric constant than the second high dielectric of the inner portion than the first high dielectric, the gate The bonding surface between the electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the first bonding surface between the drift region and the drain region. It is located in the main surface side of this.

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type emitter region formed on the surface layer of the base region, and a first main surface formed on the second main surface side with the drift region interposed between the first main surface and the first main surface. A collector region of two conductivity types, a trench that contacts the emitter region and penetrates the base region and the drift region from the first main surface to the collector region , and the base region and the base in the trench A plurality of high dielectrics embedded on the second main surface side of the junction surface with the drift region; and the first main surface and the plurality of high dielectrics in the trench. A high dielectric provided at a position on the main surface side of An insulating gate structure comprising a gate insulating film and a gate electrode formed therebetween, wherein at least one of the plurality of high dielectrics has a relative dielectric constant larger than that of the silicon oxide film, and the plurality of high dielectrics of, it has a different dielectric constant than the second high dielectric of the first high dielectric and said first inner portion than the high dielectric outer portion along the inner wall surface of the trench, The bonding surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the bonding surface between the drift region and the collector region. It is located on the first main surface side .

The semiconductor device according to the present invention includes a second conductivity type base formed on the first main surface side with the drift region interposed between the first conductivity type drift region and the second main surface. A first conductive type emitter region formed on the surface layer of the base region, and a first main surface formed on the second main surface side with the drift region interposed between the first main surface and the first main surface. A collector region of two conductivity types, a trench that contacts the emitter region and penetrates the base region and the drift region from the first main surface to the collector region , and the base region and the base in the trench A plurality of high dielectrics embedded on the second main surface side of the junction surface with the drift region; and the first main surface and the plurality of high dielectrics in the trench. A high dielectric provided at a position on the main surface side of An insulating gate structure including a gate insulating film and a gate electrode formed therebetween, wherein at least one of the plurality of high dielectrics has a relative dielectric constant larger than that of the silicon nitride film, and the plurality of high dielectrics of, it has a different dielectric constant than the second high dielectric of the first high dielectric and said first inner portion than the high dielectric outer portion along the inner wall surface of the trench, The bonding surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the bonding surface between the drift region and the collector region. It is located on the first main surface side .

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, one of the plurality of high dielectrics is in contact with the drain region. The semiconductor device according to the present invention is characterized in that, in the above-described invention, one of the plurality of high dielectrics is in contact with the collector region. The semiconductor device according to the present invention is characterized in that, in the above-described invention, one of the plurality of high dielectrics is in contact with the gate electrode. The semiconductor device according to the present invention is characterized in that, in the above-described invention, one of the plurality of high dielectrics is a silicon oxide film. In the semiconductor device according to the present invention, the deepest portion of the high dielectric provided in the deepest position among the plurality of high dielectrics is in the drift region when the deepest portion is in the off state. It is characterized by being deeper than the edge of the spreading depletion layer.

The semiconductor device manufacturing method according to the present invention is a method for manufacturing the above-described semiconductor device, wherein the second conductivity type is formed on the first conductivity type first semiconductor layer serving as the first conductivity type drift region. a second semiconductor layer of a second conductivity type serving as a conductivity type of the base region are provided, that pass transmembrane the semiconductor layer and the first semiconductor layer of the second from the surface of the second semiconductor layer trench Forming a trench, forming a first high dielectric covering the inner wall surface of the trench, and forming an inner portion of the first high dielectric in the trench A second high-dielectric formation step of filling the second main surface side with a second high-dielectric material with respect to the junction surface between the base region and the drift region, and the first high-dielectric formation step in the trench. A gate electrode is embedded on the second high dielectric in the inner part of the high dielectric It characterized in that it comprises a chromatography gate electrode forming step. The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the gate electrode forming step forms the gate electrode by filling with the second high dielectric while doping impurities. To do.

  According to the above-described invention, the shape of the electric field distribution when the maximum electric field strength reaches the critical electric field strength in the off state due to the influence of the polarization charge by the high dielectric region under the gate electrode is a triangular shape (see FIG. 49). ) Approaches a rectangular shape (see FIG. 2). Accordingly, the area of the electric field distribution is increased, and this area corresponds to the breakdown voltage, so that the breakdown voltage is improved. Therefore, even if the impurity concentration in the drift region is the same as the conventional one, a higher breakdown voltage can be obtained. That is, in the case of the same withstand voltage class as in the conventional case, the on-resistance is reduced. Conventionally, it has not been easy to embed a high dielectric having a relative dielectric constant higher than that of the silicon nitride film under the gate electrode. However, according to the above-described invention, the high dielectric is formed in the lower half of the trench. A gate electrode is formed in the upper half of the same trench.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the withstand voltage can be secured without changing the thickness of the drift layer, and the on-resistance can be reduced without applying a high gate drive voltage. In addition, according to the method for manufacturing a semiconductor device according to the present invention, a semiconductor device having such characteristics can be easily manufactured.

It is sectional drawing which shows the structure of the trench gate type MISFET concerning Embodiment 1 of this invention. It is a characteristic view which shows typically the electric field strength distribution in C-C 'of FIG. It is sectional drawing which shows the structure of MISFET used for the simulation for investigating the characteristic of MISFET of FIG. FIG. 4 is a characteristic diagram showing a simulation result of a relationship between a relative permittivity εr of a high dielectric and an on-resistance RonA in the MISFET of FIG. 3. FIG. 4 is a characteristic diagram showing a simulation result of a relationship between a relative permittivity εr of a high dielectric, an on-resistance RonA, and a withstand voltage BV in the MISFET of FIG. 3. It is a characteristic view which shows the simulation result of the relationship between the dielectric constant (epsilon) r of a high dielectric material and electric field distribution in the MISFET of FIG. FIG. 4 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 1 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing potential simulation results when the relative dielectric constant εr is set to 3.9 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 7 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 12 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing a simulation result of potential when the relative permittivity εr is 40 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing potential simulation results when the relative dielectric constant εr is 100 in the MISFET of FIG. 3. FIG. 4 is a cross-sectional view showing a potential simulation result when the relative permittivity εr is 300 in the MISFET of FIG. 3. It is sectional drawing which shows the structure of the trench gate type MISFET concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of MISFET used for the simulation for investigating the characteristic of MISFET of FIG. FIG. 16 is a partial enlarged cross-sectional view for explaining the reason why the trench is deepened in the MISFET shown in FIG. 15. FIG. 16 is a partial enlarged cross-sectional view for explaining the reason why the trench is deepened in the MISFET shown in FIG. 15. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric and the on-resistance RonA in the MISFET of FIG. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric, the on-resistance RonA, and the breakdown voltage BV in the MISFET of FIG. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric and the electric field distribution in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 1 in the MISFET of FIG. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative permittivity εr is set to 3.9 in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 7 in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative permittivity εr is 12 in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 40 in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative dielectric constant εr is 100 in the MISFET of FIG. 15. FIG. 16 is a cross-sectional view showing a simulation result of potential when the relative permittivity εr is 300 in the MISFET of FIG. 15. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the breakdown voltage BV in the MISFET of FIG. 15. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the on-resistance RonA in the MISFET of FIG. 15. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the electric field distribution when the relative dielectric constant εr of the high dielectric 37 in the inner part of the MISFET of FIG. 15 is set to 3.9. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the electric field distribution when the relative dielectric constant εr of the high dielectric 37 in the inner part of the MISFET of FIG. 15 is set to 12. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the electric field distribution when the relative dielectric constant εr of the high dielectric 37 in the inner portion of the MISFET of FIG. 15 is set to 40. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the electric field distribution when the relative dielectric constant εr of the high dielectric 37 in the inner portion of the MISFET of FIG. 15 is set to 100. FIG. 16 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the electric field distribution when the relative dielectric constant εr of the high dielectric 37 in the inner portion of the MISFET of FIG. 15 is set to 300. It is sectional drawing which expands and shows typically the part enclosed with the broken line of FIG. It is sectional drawing which expands and shows typically the part enclosed with the broken line of FIG. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing method of the trench gate type MISFET concerning Embodiment 4 of this invention. It is sectional drawing which shows the structure of the conventional trench gate type MISFET. FIG. 49 is a characteristic diagram schematically showing an electric field intensity distribution at A-A ′ in FIG. 48.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + attached to n or p means that the impurity concentration is higher than that of a layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
1 is a cross-sectional view showing a configuration of a trench gate type MISFET according to a first embodiment of the present invention. FIG. 1 shows a half cell of the main part of the semiconductor device. The actual overall configuration of the semiconductor device is a configuration in which the configuration of the half cell shown in FIG. 1 is continuous with both ends thereof as axes of line symmetry (the same applies to FIG. 14).

As shown in FIG. 1, in the vertical trench gate type n-channel MISFET according to the first embodiment, a p base region 22 is formed on the first main surface side with the n drift region 21 interposed therebetween, and the second An n ⁺ drain region 25 is formed on the main surface side. The n ⁺ source region 23 and the p ⁺ contact region 24 are formed adjacent to each other on the surface layer of the p base region 22.

The trench 28 is adjacent to the n ⁺ source region 23 and penetrates the p base region 22 and the n drift region 21 from the first main surface to reach the n ⁺ drain region 25. The lower half of the trench 28, specifically, the region below the pn junction surface 34 composed of the p base region 22 and the n drift region 21 is filled with a high dielectric 35. The relative permittivity of the high dielectric 35 is higher than that of the silicon oxide film (SiO ₂ , relative permittivity: 3.9).

For example, as the high dielectric 35, silicon nitride film (Si ₃ N ₄ , relative dielectric constant: ˜7), Al ₂ O ₃ (relative dielectric constant: 8.5-10), silicate (ZrAlxOy, relative dielectric constant: 10) To 20), aluminate (HfAlxOy, relative permittivity: 10 to 20), ZrO ₂ (relative permittivity: 11 to 18.5), HfO ₂ (relative permittivity: 24), Ta ₂ O ₅ (relative permittivity) _{: ~25), La 2 O 3} ( dielectric constant: 27), CoTiO ₃ (dielectric constant: 40), SrTiO ₃ (dielectric constant: 300) or BaTiO ₃ (relative dielectric constant: 5000), and the like However, it is not limited to these. Preferably, the high dielectric 35 is preferably a material having a higher relative dielectric constant than the silicon nitride film.

The gate insulating film 26 is provided along the side wall surface of the portion of the trench 28 that is in contact with the p base region 22. An inner portion of the gate insulating film 26 in the trench 28 is filled with a gate electrode 27. The gate electrode 27 is in contact with the high dielectric 35. The high dielectric 35 may not be in contact with the gate electrode 27 or the n ⁺ drain region 25, but if the high dielectric 35 is in contact with one or both of the gate electrode 27 and the n ⁺ drain region 25, Since the potential of the portion is fixed, the potential distribution in the high dielectric 35 and consequently the n drift region 21, that is, the electric field distribution is stabilized, which is preferable.

Source electrode 29 is electrically connected to n ⁺ source region 23 and p ⁺ contact region 24. The source electrode 29 is insulated from the gate electrode 27 by the interlayer insulating film 30. Further, the drain electrode 31 is electrically connected to the n ⁺ drain region 25. In FIG. 1, the broken line indicated by reference numeral 32 in the p base region 22 and the broken line indicated by reference numeral 33 in the n drift region 21 indicate the ends of the depletion layer when the MISFET is in the OFF state, respectively.

Since the high dielectric 35 is provided, in the off state, the polarization charge dominantly determines the electric field distribution. Therefore, as shown in FIG. It stretches downward near 35, that is, pulled toward the lower end side of the high dielectric 35. Therefore, when the depth (d ₁ ) of the depletion layer in the semiconductor region far from the high dielectric 35 and the depth (d ₂ ) of the deepest portion of the high dielectric 35 are compared, d ₂ is deeper than d _1. It becomes the design which becomes.

If it is such a design, d ₂ may be deep enough that the deepest portion of the high dielectric 35 remains in the n drift region 21. However, since it is effective to shorten the drift region in order to reduce the on-resistance, the deepest portion of the high dielectric 35 reaches the n ⁺ drain region 25 as shown in FIG. Is good.

Note that d ₂ may be designed to be shallower than d ₁ . In that case, compared with the same breakdown voltage (same d ₁ ), the length of the portion of the n drift region 21 facing the side wall of the high dielectric 35 is shortened, so that an improvement in gate charge characteristics can be expected due to a reduction in parasitic capacitance. . When (d ₁ −d ₂ ) / d ₁ ≦ 0.1, the portion of the n drift region 21 having a thickness (d ₁ −d ₂ ) that does not face the high dielectric 35 serves as a buffer layer. There is breakdown voltage higher than when d ₂ is deeper than d ₁ to fulfill, also the thickness (d ₁ -d ₂₎ amount corresponding RonA the width of the n drift region 21 is expanded [Ω · cm ^2] is slightly reduced The trade-off between breakdown voltage and RonA is improved. However, in the case of (d ₁ −d ₂ ) / d ₁ > 0.1, electric field concentration occurs at the interface between the n drift region 21 at the corner of the trench 28 and the high dielectric 35, and the ratio (d ₂ / d ₁ ) Undesirably, the pressure resistance deteriorates in proportion to the decrease.

  FIG. 2 is a characteristic diagram schematically showing the electric field intensity distribution at C-C ′ in FIG. 1. 2, E1, E2, and E3 are the depletion layer end 32 (E1) in the p base region 22 in CC ′ of FIG. 1, and the pn junction of the p base region 22 and the n drift region 21, respectively. It corresponds to the surface 34 (E2) and the end 33 (E3) of the depletion layer in the n drift region 21. As shown in FIG. 2, the shape of the electric field distribution when the maximum electric field strength reaches the critical electric field strength approaches a rectangular shape. Accordingly, since the area of the electric field distribution (corresponding to the withstand voltage) when the maximum electric field strength reaches the critical electric field intensity is larger than that in the conventional case (see FIG. 49), the withstand voltage is improved as compared with the conventional case.

In addition, M.M. According to “Analysis of silicon carbide power device performance” by Bhatnagar et al. (Proc. ISPSD (1991), p. 176-180), the so-called silicon limit of on-resistance is given by the following equation: Given. Note that Ron [Ω] is an on-resistance, and A [cm ² ] is a chip surface area.
RonA = 5.93 × 10 ⁻⁹ · Vb ^2.5 [Ω · cm ² ]

  When a material having a high relative dielectric constant is used as the high dielectric 35, the on-resistance may fall below the silicon limit. When the on-resistance is lower than the silicon limit, it is not necessary to provide a field plate unlike the semiconductor device disclosed in Patent Document 5, and thus a smaller semiconductor device can be obtained. Further, unlike the semiconductor device disclosed in Patent Document 4, it is not necessary to apply a high gate drive voltage.

  Next, a description will be given of the result of simulation of the characteristics of the MISFET configured as shown in FIG. FIG. 3 is a cross-sectional view showing a half cell of the MISFET used in this simulation. In FIG. 3, the high dielectric 35 has a double structure of an outer portion along the side wall and bottom surface of the trench 28 and an inner portion filled therein, but the outer portion and the inner portion are the same material. It is made of and is substantially integrated. That is, the configuration shown in FIG. 3 is the same as the configuration shown in FIG.

The breakdown voltage class is 60V. As shown in FIG. 3, the depth Xj1 from the first main surface to the pn junction surface 34, the depth Xj2 from the pn junction surface 34 to the interface between the n drift region 21 and the n ⁺ drain region 25, and the n drift region 21 And the depth from the interface of n ⁺ drain region 25 to the second main surface, that is, thickness XjN of n ⁺ drain region 25 are 0.8 μm, 3.1 μm, and 0.1 μm, respectively. The depth Dt from the first main surface to the bottom of the trench 28 (the deepest part of the high dielectric 35) is 3.9 μm. The thickness of the gate insulating film 26 is 500 angstroms. The gate electrode 27 is doped polysilicon. The impurity concentration of the p base region 22 is 2 × 10 ¹⁷ cm ⁻³ .

FIG. 4 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric and the on-resistance RonA. In FIG. 4, a rough broken line across the characteristic diagram is the silicon limit, and a fine broken line in the range where the relative dielectric constant εr is larger than 1000 is obtained by extrapolating a line in the range of 1000 or less. The simulation result shown in FIG. 4 is a result when the withstand voltage is set to 60 V by adjusting the concentration of the n drift region 21. FIG. 4 shows that when the withstand voltage class is 60V, if the relative dielectric constant of the high dielectric 35 is about 40 or more, it is below the silicon limit. Therefore, in the case of this breakdown voltage class, it is more preferable that the relative dielectric constant of the high dielectric 35 is 40 or more. For example, as the high dielectric 35, CoTiO ₃ , SrTiO ₃ , BaTiO ₃ or the like is appropriate.

FIG. 5 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric material, the on-resistance RonA, and the breakdown voltage BV. The simulation results shown in FIG. 5 are the results when the concentration of the n drift region 21 is 2 × 10 ¹⁶ cm ⁻³ , the gate-source voltage is 10 V, and the drain-source voltage is 0.1 V. (The same applies to the simulation results shown in FIGS. 6 to 13). FIG. 5 shows that by increasing the relative dielectric constant εr of the high dielectric 35, the breakdown voltage can be increased and the on-resistance RonA can be reduced. Therefore, even if the thickness and concentration of the n drift region 21 and the gate drive voltage are the same as the conventional one, it is possible to increase the breakdown voltage and reduce the on-resistance RonA.

  FIG. 6 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric material and the electric field distribution. In FIG. 6, E4, E2, and E5 are the first main surface (E4), the pn junction surface 34 (E2) of the p base region 22 and the n drift region 21, and the second main surface, respectively. This corresponds to (E5). Hereinafter, the first main surface and the second main surface are referred to as a substrate front surface and a substrate back surface, respectively. From FIG. 6, by increasing the relative dielectric constant εr of the high dielectric 35, the electric field in the H portion in the vicinity of the pn junction surface 34 (E2) is relaxed, and the electric field strength distribution is uniform in the trench depth direction. You can see that That is, as described with reference to FIG. 2, when the relative permittivity εr increases, the shape of the electric field distribution approaches a rectangular shape and the area of the electric field distribution increases, so that the breakdown voltage is improved as compared with the conventional case. In the ON state, for the same reason, when the relative dielectric constant εr increases, the potential gradient between the drain and the source is relaxed, so that the ON resistance RonA decreases.

  7, 8, 9, 10, 11, 12, and 13 are MISFETs when the relative dielectric constant εr is set to 1, 3.9, 7, 12, 40, 100, and 300, respectively. It is sectional drawing which shows the simulation result of the inside potential. Each figure shows a potential distribution when a withstand voltage BV is applied between the source electrode and the drain electrode. In the n drift region 21 and the p base region 22, both ends of the equipotential line 40 are both ends of the depletion layer. 7 to 13 that the depletion layer expands in the depth direction of the trench 28 as the relative dielectric constant εr of the high dielectric 35 increases. Therefore, it can be seen that the breakdown voltage is improved even if the thickness and concentration of the n drift region 21 are the same as the conventional one. Further, it can be seen that in the ON state, the potential gradient between the drain and the source is relaxed, and the ON resistance RonA is lowered.

Embodiment 2. FIG.
FIG. 14 is a sectional view showing the configuration of a half cell of a trench gate type MISFET according to the second embodiment of the present invention. As shown in FIG. 14, the MISFET according to the second embodiment is different from the first embodiment in that the high dielectric 35 buried under the gate electrode 27 is composed of a high dielectric 36 in the outer portion and a high dielectric 36 in the inner portion. That is, the dielectric 37 has a double structure. Since other configurations are the same as those of the first embodiment, the same reference numerals are given and description thereof is omitted.

The relative dielectric constant of each of the high dielectrics 36 and 37 in the outer portion and the inner portion is higher than that of the silicon oxide film (SiO ₂ ), preferably higher than that of the silicon nitride film (Si ₃ N ₄ ). For example, as the high dielectrics 36 and 37, various materials exemplified in the first embodiment can be mentioned, but the high dielectrics 36 and 37 are not limited thereto. Further, either one of the high dielectrics 36 and 37 in the outer portion and the inner portion may be a silicon oxide film (SiO ₂ ). It is to be noted that the first embodiment is obtained by configuring the high dielectric 36 in the outer portion and the high dielectric 37 in the inner portion with the same high dielectric.

  The electric field strength distribution at J-J ′ in FIG. 14 is the same as the characteristic diagram schematically shown in FIG. 2. Also in the second embodiment, when at least one of the high dielectrics 36 and 37 is made of a material having a high relative dielectric constant, the on-resistance may be lower than the silicon limit. In that case, since it is not necessary to provide a field plate unlike the semiconductor device disclosed in Patent Document 5, a smaller semiconductor device can be obtained. Further, unlike the semiconductor device disclosed in Patent Document 4, it is not necessary to apply a high gate drive voltage.

  Next, the results of simulation of the characteristics of the MISFET configured as shown in FIG. 14 will be described. FIG. 15 is a cross-sectional view showing a half cell of the MISFET used in this simulation. The breakdown voltage class is 60V.

As shown in FIG. 15, the depth Xj1 from the substrate surface (first main surface) to the pn junction surface 34, the depth Xj2 from the pn junction surface 34 to the interface between the n drift region 21 and the n ⁺ drain region 25, The depth from the interface between the n drift region 21 and the n ⁺ drain region 25 to the back surface (second main surface) of the substrate, that is, the thickness XjN of the n ⁺ drain region 25 is 0.8 μm, 3.1 μm, and 6 μm, respectively. .4 μm. The depth Dt from the first main surface to the bottom of the trench 28 (the deepest portion of the high dielectric 36 in the outer portion) is 10.2 μm. The thickness of the gate insulating film 26 is 500 angstroms. The gate electrode 27 is doped polysilicon. The impurity concentration of the p base region 22 is 2 × 10 ¹⁷ cm ⁻³ . The high dielectric 36 in the outer portion is a silicon oxide film (SiO ₂ ).

Here, the reason why the trench 28 is deepened is as follows. As shown in FIG. 16, when the trench 28 is shallowed, the equipotential lines 41, 42, 43 near the end of the depletion layer among the equipotential lines 41, 42, 43, 44, 45 become the high dielectric 36 in the outer portion. Therefore, the electric field concentration occurs here and the breakdown voltage is lowered. On the other hand, as shown in FIG. 17, when the trench 28 is made sufficiently deep so as to extend into the n ⁺ drain region 25, the equipotential lines 41, 42, 43 near the depletion layer end become high dielectrics in the outer portion. Since the body 36 does not reach the bottom portion of the trench 28, electric field concentration can be avoided and high breakdown voltage can be maintained. 16 and 17 show simulation results when the high dielectric 37 in the inner portion is made of SrTiO ₃ .

  FIG. 18 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric in the inner portion and the on-resistance RonA. In FIG. 18, a rough broken line across the characteristic diagram is the silicon limit, and a fine broken line in the range where the relative dielectric constant εr is larger than 300 is obtained by extrapolating a line in the range of 300 or less. The simulation results shown in FIG. 18 are results when the withstand voltage is set to 60 V by adjusting the concentration of the n drift region 21. As is clear from the comparison between FIG. 18 and FIG. 4, the same tendency as in the first embodiment is observed in the relative dielectric constant εr dependency of the on-resistance RonA when the withstand voltage class is 60V.

In the second embodiment, it can be seen that if the relative dielectric constant of the high dielectric 37 in the inner portion is about 40 or more, it is below the silicon limit. Therefore, in the case of this breakdown voltage class, it is more preferable that the relative dielectric constant of the high dielectric 37 in the inner portion is 40 or more. For example, CoTiO ₃ , SrTiO ₃ , BaTiO ₃ or the like is suitable as the high dielectric 37 in the inner part.

FIG. 19 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric material in the inner portion, the on-resistance RonA, and the breakdown voltage BV. The simulation results shown in FIG. 19 are the results when the concentration of the n drift region 21 is 2 × 10 ¹⁶ cm ⁻³ , the gate-source voltage is 10 V, and the drain-source voltage is 0.1 V. (The same applies to the simulation results shown in FIGS. 20 to 27). As apparent from the comparison between FIG. 19 and FIG. 5, the same tendency as in the first embodiment is observed in the relative permittivity εr dependency of the on-resistance RonA and the withstand voltage BV.

FIG. 20 is a characteristic diagram showing a simulation result of the relationship between the relative dielectric constant εr of the high dielectric at the inner portion and the electric field distribution. 20, K1, K2, and K3 are the substrate surface (K1) in FIG. 15, the pn junction surface 34 (K2) of the p base region 22 and the n drift region 21, and the n drift region 21 and the n ⁺ drain, respectively. This corresponds to the interface (K3) of the region 25. As apparent from the comparison between FIG. 20 and FIG. 6, the same tendency as in the first embodiment is observed in the relationship between the relative dielectric constant εr of the high dielectric 37 in the inner portion and the electric field distribution.

  FIGS. 21, 22, 23, 24, 25, 26, and 27 show the relative dielectric constant εr of the high dielectric 37 in the inner portion as 1, 3.9, 7, 12, 40, 100, respectively. 6 is a cross-sectional view showing the simulation result of the potential in the MISFET when set to 300 and 300. FIG. Each figure shows a potential distribution when a withstand voltage BV is applied between the source electrode and the drain electrode. In the n drift region 21 and the p base region 22, both ends of the equipotential line 40 are both ends of the depletion layer. From FIG. 21 to FIG. 27, it can be seen that the depletion layer expands in the depth direction of the trench 28 as the relative dielectric constant εr of the high dielectric 37 in the inner portion increases. Therefore, it can be seen that the breakdown voltage is improved even if the thickness and concentration of the n drift region 21 are the same as the conventional one. Further, it can be seen that in the ON state, the potential gradient between the drain and the source is relaxed, and the ON resistance RonA is lowered.

FIG. 28 is a characteristic diagram showing a simulation result of the relationship between the impurity concentration of the n drift region and the breakdown voltage BV. From FIG. 28, it can be seen that as the relative dielectric constant εr of the high dielectric 37 in the inner portion increases, the impurity concentration of the n drift region 21 where the withstand voltage BV reaches a peak shifts to the high concentration side. For example, when the relative dielectric constant εr of the high dielectric 37 in the inner portion is 100, the impurity concentration of the n drift region 21 (hereinafter referred to as the drift concentration) is 0.5 × 10 ¹⁶ cm ^−3. The breakdown voltage BV peaks. In contrast, when the relative dielectric constant εr of the high dielectric 37 in the inner portion is 300, the breakdown voltage BV peaks when the drift concentration is 2 × 10 ¹⁶ cm ⁻³ and the relative dielectric constant εr. Is shifted to a higher density side than when 100 is 100. FIG. 29 is a characteristic diagram showing a simulation result of the relationship between the drift concentration and the on-resistance RonA.

  Here, a mechanism in which the withstand voltage BV has a peak will be described. 30, FIG. 31, FIG. 32, FIG. 33 and FIG. 34 show the drift concentration when the relative dielectric constant εr of the high dielectric 37 in the inner part is set to 3.9, 12, 40, 100 and 300, respectively. It is a characteristic view which shows the simulation result of the relationship with electric field distribution. Hereinafter, the drift concentration when the breakdown voltage reaches a peak is referred to as a breakdown voltage peak concentration.

  When the drift concentration is lower than the withstand voltage peak concentration, as shown in FIGS. 30 to 34, when the drift concentration is increased, the electric field intensity at the L portion maintains a critical value up to the withstand voltage peak value. On the other hand, the electric field strength of the M part increases. This acts in the direction of increasing the breakdown voltage. Then, the area increase of the electric field distribution due to the increase of the electric field intensity of the M part is superior to the area reduction of the electric field distribution due to the decrease of the electric field intensity of the L part, and thereby the breakdown voltage increases as the drift concentration is increased. When the drift concentration is higher than the withstand voltage peak concentration, the area reduction of the electric field distribution due to the decrease in the electric field strength of the L part is superior to the area increase of the electric field distribution due to the increase of the electric field intensity of the M part, and therefore the breakdown voltage is reduced To do. When the drift concentration is further increased, the electric field strength in the M portion reaches a critical level, and the depletion layer also stops at a shallow portion of the trench 28, so that the breakdown voltage is further reduced.

  Here, the tendency of the electric field strength of the L part and the M part will be described. As shown in FIGS. 30 to 34, if the relative dielectric constant εr of the high dielectric 37 in the inner portion is the same, the lower the drift concentration, the higher the electric field strength in the L portion. In addition, even when the drift concentration is the same, the higher the relative dielectric constant εr of the high dielectric 37 in the inner portion, the higher the electric field strength in the L portion (the reason will be described later), so the electric field strength in the L portion maintains a critical value. The limit of drift concentration shifts to the higher concentration side. As for the electric field strength of the M portion, the electric field strength decreases as the relative dielectric constant εr of the high dielectric 37 in the inner portion increases even at the same drift concentration. This is because the electric field is relaxed by the high dielectric 37.

  From the above, as the relative dielectric constant εr of the high dielectric 37 in the inner portion is higher, the peak of the breakdown voltage BV is shifted to the higher concentration side of the drift concentration. When the drift concentration is lower than the withstand voltage peak concentration, the withstand voltage increases significantly as the relative dielectric constant εr of the high dielectric 37 in the inner portion increases. This is because, as described above, the higher the relative dielectric constant εr, the lower the electric field strength of the M portion, so that the breakdown voltage can be increased until the critical electric field strength is reached.

  Here, the reason why the electric field strength in the L portion increases as the relative dielectric constant εr of the high dielectric 37 in the inner portion increases even at the same drift concentration will be described. For this explanation, in FIGS. 22 and 27, the maximum depth of the equipotential line at the end of the depletion layer in the high dielectric 37 in the inner portion is a1, and the distance from the substrate surface to the end of the depletion layer in the n drift region 21 is shown. Let the distance be a2. As is clear from the comparison between FIG. 22 and FIG. 27, the higher dielectric constant εr of the inner high dielectric 37 (FIG. 27, relative dielectric constant εr: 300) is lower (FIG. 22, relative dielectric constant εr). : 3.9), it can be seen that the difference between a1 and a2 is larger.

  FIGS. 35 and 36 are cross-sectional views schematically showing enlarged portions surrounded by broken lines in FIGS. 22 and 27, respectively. As is clear from the comparison between FIG. 35 and FIG. 36, the higher dielectric constant εr of the high dielectric 37 in the inner portion (FIG. 36, relative dielectric constant εr: 300) is lower (FIG. 35, relative dielectric constant εr). : 3.9), it can be seen that the bending of the equipotential lines 46, 47 and 48 at the interface between the n drift region 21 and the high dielectric 36 in the outer portion is larger. As shown in FIG. 36, when the relative dielectric constant εr of the high dielectric 37 in the inner part is high, the equipotential lines 46, 47, and 48 are parallel to the trench sidewalls in the high dielectric 36 in the outer part. Since the electric field tends to concentrate, the electric field strength in the L portion increases.

Embodiment 3 FIG.
37 to 44 are cross-sectional views showing a method of manufacturing a trench gate type MISFET according to the third embodiment of the present invention. First, an n semiconductor layer that becomes an n drift region 21 is epitaxially grown on an n ⁺ substrate that becomes an n ⁺ drain region 25. Subsequently, for example, boron is ion-implanted as a p-type impurity on the surface of the epitaxial growth layer and thermally diffused, thereby providing a p semiconductor layer that becomes the p base region 22 (FIG. 37).

Next, trenches reaching the n ⁺ substrate from the surface of the p semiconductor layer are formed by reactive ion etching (FIG. 38). Next, the inner peripheral surface of the trench 28 is covered with a silicon oxide film (SiO ₂ ) by thermal oxidation (FIG. 39). This silicon oxide film becomes the high dielectric 36 in the outer portion in the MISFET of the second embodiment. By covering the inner peripheral surface of the trench 28 with a silicon oxide film, the trench side wall is chemically stabilized. Further, when completed as a MISFET, the gate-drain capacitance is reduced.

  The trench 28 is then filled with the high dielectric 37 of the inner portion by depositing a high dielectric material (FIG. 40). Next, the upper half of the high dielectric 36 in the outer portion and the high dielectric 37 in the inner portion are removed by dry etching (FIG. 41). Next, thermal oxidation is performed to form the gate insulating film 26 on the side wall surface of the upper half of the trench 28 (FIG. 42). Next, the inner part of the gate insulating film 26 of the trench 28 is refilled with polysilicon doped with impurities at a high concentration to form the gate electrode 27 (FIG. 43).

Finally, as an n-type impurity and a p-type impurity, for example, arsenic and boron are ion-implanted and thermally diffused to provide an n ⁺ source region 23 and a p ⁺ contact region 24. Subsequently, the source electrode 29, the interlayer insulating film 30 and the drain electrode 31 are formed by the same process as that of the ordinary method for manufacturing a semiconductor device (FIG. 44), and the MISFET of the second embodiment shown in FIG. 14 is completed. In the step shown in FIG. 39, if the same material as the high dielectric 37 in the inner part is used as the high dielectric 36 in the outer part, the MISFET of the first embodiment shown in FIG. 1 is completed.

Embodiment 4 FIG.
45 to 47 are sectional views showing a method of manufacturing a trench gate type MISFET according to the fourth embodiment of the present invention. First, similarly to the third embodiment, the steps shown in FIGS. 37 to 39 are performed to cover the inner peripheral surface of the trench 28 with a silicon oxide film (SiO ₂ ) (FIG. 39). The lower half of the trench 28 is then filled with the inner portion of the high dielectric 37 by depositing a high dielectric material. At this time, the deposition of the high dielectric 37 is stopped halfway so that the gate electrode formation region is not filled. On the upper half of the trench 28, that is, on the trench sidewall in the region where the gate electrode is to be formed, the silicon oxide film which is the high dielectric 36 in the outer portion remains, but this becomes the gate insulating film 26 (FIG. 45).

  Next, the inner part of the gate insulating film 26 in the trench 28 is filled with the same material as that of the high dielectric 37 in the inner part to fill the upper half of the trench 28. At that time, by doping the impurity at a high concentration, conductivity is imparted to the high dielectric 37 buried in the upper half portion of the trench 28 to function as the gate electrode 27 (FIG. 46). In this way, there is an advantage that the high dielectric 37 and the gate electrode 27 in the inner part can be manufactured in a continuous process. Further, there is an advantage that the gate electrode 27 and the high dielectric 37 in the inner part are integrated, and stress at the boundary between them is reduced.

Finally, n ⁺ source region 23, p ⁺ contact region 24, source electrode 29, interlayer insulating film 30 and drain electrode 31 are formed in the same manner as in the third embodiment (FIG. 47), and the implementation shown in FIG. The MISFET of form 2 is completed. In the step shown in FIG. 39, if the same material as the high dielectric 37 in the inner part is used as the high dielectric 36 in the outer part, the MISFET of the first embodiment shown in FIG. 1 is completed.

For example, a high dielectric 37 in the inner portion when forming the SrTiO _3, to form a SrTiO ₃ doped with niobium (Nb) as the gate electrode 27.

As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds. In addition, the high dielectric region under the gate electrode may be formed of a plurality of materials. In that case, a relative dielectric such as a silicon oxide film is partially provided around or inside the material having a relatively high relative dielectric constant. Low rate materials may be mixed. The present invention is applicable not only to MISFETs but also to IGBTs. When applied to an IGBT, in the above description, the n ⁺ source region 23 and the n ⁺ drain region 25 may be read as an n ⁺ emitter region and a p ⁺ collector region, respectively. Further, an n ⁺ buffer region may be formed between the drift region and the p ⁺ collector region.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for MIS type semiconductor devices having a trench gate structure, and in particular, power semiconductor devices such as MISFETs and IGBTs that require a high breakdown voltage and a large current capacity. Suitable for

21 drift region 22 base region 23 source region 25 drain region 26 gate insulating film 27 gate electrode 28 trench 33 end of depletion layer 35, 36, 37 high dielectric

Claims (19)

A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
A source region of a first conductivity type formed in a surface layer of the base region;
A drain region of a first conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the source region and extends from the first main surface through the base region and the drift region to the drain region ;
A high dielectric embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
An insulated gate structure comprising a gate insulating film and a gate electrode formed between the first main surface and the high dielectric in the trench;
With
The dielectric constant of the high dielectric is larger than that of the silicon oxide film,
The first dielectric having an outer portion along the inner wall surface of the trench and the second dielectric having a dielectric constant different from that of the second dielectric in the inner portion of the first dielectric are different from each other. Yes, and
The semiconductor device according to claim 1, wherein a junction surface between the gate electrode and the high dielectric is located closer to the first main surface than a junction surface between the drift region and the drain region . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
A source region of a first conductivity type formed in a surface layer of the base region;
A drain region of a first conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the source region and extends from the first main surface through the base region and the drift region to the drain region ;
A high dielectric embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
An insulated gate structure comprising a gate insulating film and a gate electrode formed between the first main surface and the high dielectric in the trench;
With
The dielectric constant of the high dielectric is larger than that of the silicon nitride film,
The first dielectric having an outer portion along the inner wall surface of the trench and the second dielectric having a dielectric constant different from that of the second dielectric in the inner portion of the first dielectric are different from each other. Yes, and
The semiconductor device according to claim 1, wherein a junction surface between the gate electrode and the high dielectric is located closer to the first main surface than a junction surface between the drift region and the drain region . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
An emitter region of a first conductivity type formed in a surface layer of the base region;
A collector region of a second conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the emitter region and extends from the first main surface through the base region and the drift region to the collector region ;
A high dielectric embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
An insulated gate structure comprising a gate insulating film and a gate electrode formed between the first main surface and the high dielectric in the trench;
With
The dielectric constant of the high dielectric is larger than that of the silicon oxide film,
The first dielectric having an outer portion along the inner wall surface of the trench and the second dielectric having a dielectric constant different from that of the second dielectric in the inner portion of the first dielectric are different from each other. Yes, and
The semiconductor device according to claim 1, wherein a junction surface between the gate electrode and the high dielectric is located closer to the first main surface than a junction surface between the drift region and the collector region . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
An emitter region of a first conductivity type formed in a surface layer of the base region;
A collector region of a second conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the emitter region and extends from the first main surface through the base region and the drift region to the collector region ;
A high dielectric embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
An insulated gate structure comprising a gate insulating film and a gate electrode formed between the first main surface and the high dielectric in the trench;
With
The dielectric constant of the high dielectric is larger than that of the silicon nitride film,
The first dielectric having an outer portion along the inner wall surface of the trench and the second dielectric having a dielectric constant different from that of the second dielectric in the inner portion of the first dielectric are different from each other. Yes, and
The semiconductor device according to claim 1, wherein a junction surface between the gate electrode and the high dielectric is located closer to the first main surface than a junction surface between the drift region and the collector region .   The semiconductor device according to claim 1, wherein the high dielectric is in contact with the drain region.   The semiconductor device according to claim 3, wherein the high dielectric is in contact with the collector region.   The semiconductor device according to claim 1, wherein a deepest portion of the high dielectric is deeper than an end of a depletion layer that extends into the drift region in an off state.   The semiconductor device according to claim 1, wherein the high dielectric is in contact with the gate electrode. A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
A source region of a first conductivity type formed in a surface layer of the base region;
A drain region of a first conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the source region and extends from the first main surface through the base region and the drift region to the drain region ;
A plurality of high dielectric materials embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
A gate insulating film and a gate formed between the first main surface and the high dielectric provided at a position closest to the first main surface among the plurality of high dielectrics in the trench An insulated gate structure comprising electrodes;
With
A relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon oxide film;
The ratio of the first high dielectric in the outer portion along the inner wall surface of the trench and the second high dielectric in the inner portion of the plurality of high dielectrics are different from each other. It has a dielectric constant,
The junction surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the junction surface between the drift region and the drain region. A semiconductor device which is located on the first main surface side . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
A source region of a first conductivity type formed in a surface layer of the base region;
A drain region of a first conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the source region and extends from the first main surface through the base region and the drift region to the drain region ;
A plurality of high dielectric materials embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
A gate insulating film and a gate formed between the first main surface and the high dielectric provided at a position closest to the first main surface among the plurality of high dielectrics in the trench An insulated gate structure comprising electrodes;
With
A relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon nitride film;
The ratio of the first high dielectric in the outer portion along the inner wall surface of the trench and the second high dielectric in the inner portion of the plurality of high dielectrics are different from each other. It has a dielectric constant,
The junction surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the junction surface between the drift region and the drain region. A semiconductor device which is located on the first main surface side . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
An emitter region of a first conductivity type formed in a surface layer of the base region;
A collector region of a second conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the emitter region and extends from the first main surface through the base region and the drift region to the collector region ;
A plurality of high dielectric materials embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
A gate insulating film and a gate formed between the first main surface and the high dielectric provided at a position closest to the first main surface among the plurality of high dielectrics in the trench An insulated gate structure comprising electrodes;
With
A relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon oxide film;
The ratio of the first high dielectric in the outer portion along the inner wall surface of the trench and the second high dielectric in the inner portion of the plurality of high dielectrics are different from each other. It has a dielectric constant,
The bonding surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the bonding surface between the drift region and the collector region. A semiconductor device which is located on the first main surface side . A drift region of a first conductivity type;
A base region of a second conductivity type formed on the first main surface side with the drift region sandwiched between the second main surface;
An emitter region of a first conductivity type formed in a surface layer of the base region;
A collector region of a second conductivity type formed on the second main surface side with the drift region interposed between the first main surface and the first main surface;
A trench that contacts the emitter region and extends from the first main surface through the base region and the drift region to the collector region ;
A plurality of high dielectric materials embedded in the second main surface side of the junction surface between the base region and the drift region in the trench;
A gate insulating film and a gate formed between the first main surface and the high dielectric provided at a position closest to the first main surface among the plurality of high dielectrics in the trench An insulated gate structure comprising electrodes;
With
A relative dielectric constant of at least one of the plurality of high dielectrics is larger than that of the silicon nitride film;
The ratio of the first high dielectric in the outer portion along the inner wall surface of the trench and the second high dielectric in the inner portion of the plurality of high dielectrics are different from each other. It has a dielectric constant,
The bonding surface between the gate electrode and the high dielectric provided at the position closest to the first main surface among the plurality of high dielectrics is more than the bonding surface between the drift region and the collector region. A semiconductor device which is located on the first main surface side .   11. The semiconductor device according to claim 9, wherein one of the plurality of high dielectrics is in contact with the drain region.   13. The semiconductor device according to claim 11, wherein one of the plurality of high dielectrics contacts the collector region.   The semiconductor device according to claim 9, wherein one of the plurality of high dielectrics is in contact with the gate electrode.   The semiconductor device according to claim 9, wherein one of the plurality of high dielectrics is a silicon oxide film.   The deepest portion of the high dielectric provided at the deepest position among the plurality of high dielectrics is deeper than an end of a depletion layer that extends into the drift region in an off state. The semiconductor device according to any one of 9 to 16. A method for manufacturing a semiconductor device according to claim 1,
A second conductivity type second semiconductor layer serving as a second conductivity type base region is provided on the first conductivity type first semiconductor layer serving as the first conductivity type drift region. from the surface of the second semiconductor layer and the trench forming step of forming a trench that passes transmural the semiconductor layer and the first semiconductor layer of the second,
A first high dielectric formation step of forming a first high dielectric covering the inner wall surface of the trench;
In the trench, a second high dielectric that fills the second main surface side of the inner portion of the first high dielectric with respect to the junction surface between the base region and the drift region with the second high dielectric. A dielectric formation step;
A gate electrode forming step of burying a gate electrode on the second high dielectric in the inner portion of the first high dielectric in the trench;
A method for manufacturing a semiconductor device, comprising:   19. The method of manufacturing a semiconductor device according to claim 18, wherein in the gate electrode forming step, the gate electrode is formed by burying with the second high dielectric while doping impurities.

Images