JP5604844B2 - Storage device and operation method of storage device - Google Patents
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Description
本発明は、電気抵抗の状態により、情報を記憶・保持する記憶素子を用いて、メモリセルが構成された記憶装置に係わる。 The present invention relates to a memory device in which a memory cell is configured using a memory element that stores and holds information depending on the state of electrical resistance.
不揮発性メモリの分野においては、フラッシュメモリを筆頭に、強誘電体メモリ（Ferbam）、MRAM（Magnetic RAM）、OUM（Ovonic Unified Memory）等の研究が盛んである。不揮発メモリにおいては、より多くの記録容量や記録密度を実現することが求められている。これを実現する構成として、多値記録、即ちひとつのメモリセルに対して２ビット以上のデータを記録することが可能な構成の、不揮発性メモリが提案されている。このとき、例えば２ビットのデータが記録できるという場合には、メモリセルを構成する記憶素子が４つの状態の保持が可能であることを意味する。 In the field of non-volatile memory, research on ferroelectric memory (Ferbam), MRAM (Magnetic RAM), OUM (Ovonic Unified Memory), etc. is active, with flash memory at the top. In the nonvolatile memory, it is required to realize a larger recording capacity and recording density. As a configuration for realizing this, there has been proposed a non-volatile memory having a configuration capable of recording multi-value recording, that is, data of 2 bits or more in one memory cell. At this time, for example, when 2 bits of data can be recorded, it means that the memory element constituting the memory cell can hold four states.
このような、多値化技術を実現するメモリとしては、フラッシュメモリが知られているが、最近、これらの従来の不揮発性メモリと異なる抵抗変化型不揮発メモリ（ReRAM：Resistance RAM）が提案されている（非特許文献１）。この非特許文献１に記載されている抵抗変化型不揮発メモリは、電圧パルスの印加によってメモリセルの抵抗変化層の抵抗値を設定することにより情報を書き込むことができ、かつ情報の非破壊読み出しを行うことができる不揮発性メモリである。非特許文献１では、抵抗変化層としては、PCMO（Pr0.7Ca0.3MnO3）及びYBCO（Yba２Cu3Oy）が用いられている。 A flash memory is known as a memory that realizes such multi-value technology, but recently, a resistance variable nonvolatile memory (ReRAM: Resistance RAM) different from these conventional nonvolatile memories has been proposed. (Non-Patent Document 1). The variable resistance nonvolatile memory described in Non-Patent Document 1 can write information by setting a resistance value of a variable resistance layer of a memory cell by applying a voltage pulse, and can perform nondestructive reading of information. It is a non-volatile memory that can be performed. In Non-Patent Document 1, PCMO (Pr 0.7 Ca 0.3 MnO 3 ) and YBCO (Yba 2 Cu 3 Oy) are used as the resistance change layer.
抵抗変化型不揮発性メモリについては、他の提案もなされている（非特許文献２、非特許文献３）。非特許文献２では、抵抗変化層として約50nmの多結晶NiOx（x＝１〜１．５）が用いられている。 Other proposals have been made for variable resistance nonvolatile memories (Non-Patent Document 2 and Non-Patent Document 3). In Non-Patent Document 2, approximately 50 nm of polycrystalline NiOx (x = 1 to 1.5) is used as the resistance change layer.
また、抵抗変化型不揮発メモリを用いた多値動作の方法としては、低抵抗状態の抵抗値を制御して、多値記憶を可能にした記憶装置が提案されている（特許文献１）。従来技術によると、記憶素子としてCu、Ag、あるいはZnなどを含有した希土類酸化物を電極で挟んだ構造を用い、記憶素子の抵抗値が高い状態から低い状態へ変化させる動作を行う際に、記憶素子と直列に接続した電界効果型トランジスタの飽和電流値を制御することで、低抵抗状態の抵抗値を３値以上に制御することを特徴としている。 As a method of multi-value operation using a resistance variable nonvolatile memory, a storage device has been proposed that enables multi-value storage by controlling the resistance value in a low resistance state (Patent Document 1). According to the prior art, using a structure in which a rare earth oxide containing Cu, Ag, Zn, or the like is sandwiched between electrodes as a memory element, when performing an operation of changing the resistance value of the memory element from a high state to a low state, By controlling the saturation current value of the field effect transistor connected in series with the memory element, the resistance value in the low resistance state is controlled to three or more.
また、特許文献２では、抵抗値のバラツキを改善するために、抵抗値が低い状態の複数レベルのうち、最も抵抗値の低いレベル以外のレベルから高抵抗化する際には、前記最も抵抗値の低いレベルへ変化させる過程が行われてから、前記抵抗値が高い状態に変化させる過程が行われている。 Further, in Patent Document 2, in order to improve the resistance value variation, when the resistance value is increased from a level other than the lowest resistance value level among the plurality of levels having a low resistance value, the highest resistance value is obtained. After the process of changing to a low level is performed, the process of changing the resistance value to a high state is performed.
ところで、従来の抵抗変化型メモリの多値化方法を、遷移金属酸化物と遷移金属酸化物を挟んだ金属電極からなる構造の抵抗変化型記憶素子に適用した場合、以下の様になる。 By the way, when the conventional multi-value method of the resistance change type memory is applied to a resistance change type memory element having a structure composed of a transition metal oxide and a metal electrode sandwiching the transition metal oxide, the following is obtained.
図１は制御トランジスタ（nFET）２を抵抗変化素子（ReRAM）１と直列に接続した1T1R型のメモリセルを示している。抵抗変化素子にはここでは、Ru/Ta2O5/TiO2/Ru積層構造を用いている。 FIG. 1 shows a 1T1R type memory cell in which a control transistor (nFET) 2 is connected in series with a resistance change element (ReRAM) 1. Here, the variable resistance element uses a Ru / Ta 2 O 5 / TiO 2 / Ru laminated structure.
本メモリ素子の典型的なDCスイッチング特性を図２に示す。なお、Formingとは初期状態の遷移金属酸化物層内に上下電極をつなぐ低抵抗の伝導パスを造る動作であり、最初の１回のみ行う。抵抗値が高い状態から抵抗値が低い状態へ変化させる動作及び変化後の状態を消去動作及び消去状態と定義し、前記記憶素子の抵抗値が低い状態から抵抗値が高い状態へ変化させる動作及び変化後の状態を書き込み動作及び書き込み状態と定義する。Forming及び消去動作は上部電極に正電圧を印加することで行った。 A typical DC switching characteristic of the memory device is shown in FIG. Forming is an operation of creating a low-resistance conduction path that connects the upper and lower electrodes in the transition metal oxide layer in the initial state, and is performed only once. An operation for changing the resistance value from a high resistance state to a low resistance value and a state after the change are defined as an erasing operation and an erasing state, and an operation for changing the resistance value of the memory element from a low resistance state to a high resistance value; The state after the change is defined as a write operation and a write state. Forming and erasing operations were performed by applying a positive voltage to the upper electrode.
図２中の（１）及び（３）で示すように、上部電極（VT.E.）印加電圧の増大に伴い電流の急激な上昇（ReRAMの低抵抗化スイッチ）が見られるが、制御トランジスタの飽和電流（Isat.）によって、電流上昇（低抵抗化）が制限されていることがわかる。通常、制御トランジスタのゲート印加電圧は2.5Vとし、このときの飽和電流は100μAである。書き込み動作は、上部電極に負電圧を印加することで行った。このとき、電流は上部電極/基板間を流れ、制御トランジスタによる電流制限は行わなかった。 As shown by (1) and (3) in FIG. 2, a rapid increase in current (ReRAM low resistance switch) is observed as the upper electrode (V TE ) applied voltage increases. It can be seen that the current rise (low resistance) is limited by the current (I sat. ). Usually, the gate application voltage of the control transistor is 2.5 V, and the saturation current at this time is 100 μA. The writing operation was performed by applying a negative voltage to the upper electrode. At this time, the current flowed between the upper electrode / substrate, and the current was not limited by the control transistor.
図２で示したように、Forming後の電流はReRAMと直列に接続したnFETの飽和電流（Isat.）で制御しており、消去動作時（低抵抗化）も同様の制御を行っている。書き換えサイクル中にnFETの飽和電流値を変更し、消去抵抗値（低抵抗状態の抵抗値）の多値動作化の実行可能性を検証した。図３は、消去抵抗（低抵抗状態）の書き換え回数及び制御電流（Isat.）依存性を示している。７回目までは、Isat.=100μAでSet動作を行い、８回目及び９回目はIsat.＝200μAに上げ、１０回目以降はIsat.=100μAに戻した。 As shown in FIG. 2, the current after forming is controlled by the saturation current (I sat. ) Of the nFET connected in series with ReRAM, and the same control is also performed during the erase operation (low resistance). . The saturation current value of the nFET was changed during the rewrite cycle, and the feasibility of multi-level operation of the erase resistance value (resistance value in the low resistance state) was verified. FIG. 3 shows the dependence of the erase resistance (low resistance state) on the number of rewrites and the control current (Isat.). Up to the 7th time, the Set operation was performed at I sat. = 100 μA, the 8th and 9th times were increased to I sat. = 200 μA, and the 10th and subsequent times were returned to I sat. = 100 μA.
その結果、Isat.を100μAから200μAに増加することで、消去抵抗値を約2kΩから約0.6kΩに下げることができ、Isat.を100μA に戻すことで消去抵抗値を約0.6kΩから約2kΩに上げることができた。しかし、１８回目以降の消去抵抗値が示すように、書き換えを繰り返すうちに抵抗値が目的値（〜2kΩ）、よりも低くなり、９回目、１０回目で行った低抵抗の消去状態（約0.6kΩ）に近づいてしまう傾向があることがわかった。これは、Set抵抗の低抵抗化はフィラメントの数もしくは太さが増えることで起きているが、一度増えたフィラメントの数もしくは太さは消去動作で元に戻りにくいことを示している。つまり、金属電極によって遷移金属酸化物を挟んだ構造の抵抗変化型記憶素子では低抵抗状態における多値動作は、原理的に困難であることがわかる。 As a result, by increasing I sat. From 100 μA to 200 μA, the erase resistance can be lowered from about 2 kΩ to about 0.6 kΩ, and by returning I sat. To 100 μA, the erase resistance can be reduced from about 0.6 kΩ to about 0.6 kΩ . It was possible to increase to 2kΩ. However, as shown by the erase resistance value after the 18th time, the resistance value becomes lower than the target value (˜2 kΩ) as the rewrite is repeated, and the low resistance erase state (about 0.6 is performed at the 9th time and the 10th time). It has been found that there is a tendency to approach kΩ). This indicates that the lowering of the Set resistance is caused by an increase in the number or thickness of the filaments, but once the number or thickness of the filaments is increased, it is difficult to return to the original state by the erasing operation. That is, it can be understood that multi-value operation in a low resistance state is difficult in principle in a resistance change type memory element having a structure in which a transition metal oxide is sandwiched between metal electrodes.
本発明の課題の一つは、書き替え動作を繰り返し行っても、高抵抗状態への書き込みレベルを所望の抵抗値に制御することが可能な記憶装置、及び記憶装置の動作方法を提供することにある。 One of the objects of the present invention is to provide a memory device that can control a write level to a high resistance state to a desired resistance value even when a rewrite operation is repeatedly performed, and an operation method of the memory device. It is in.
上記課題を解決するために、本発明においては、電気抵抗の状態により情報を記憶・保持する遷移金属酸化物と前記遷移金属酸化物を挟む上下電極からなる抵抗変化型記憶素子からメモリセルが構成され、前記記憶素子の抵抗値が高い状態から抵抗値が低い状態へ変化させる動作及び変化後の状態を消去動作及び消去状態と定義し、前記記憶素子の抵抗値が低い状態から抵抗値が高い状態へ変化させる動作及び変化後の状態を書き込み動作及び書き込み状態と定義したとき、前記書き込み状態の伝導機構は電流と電圧との関係を示す電流電圧特性が非線形なトンネル伝導であり、前記電流電圧特性の非線形度は前記記憶素子の抵抗値に依存し、前記抵抗値が大きいほど大きくなり、前記消去状態の伝導機構は前記電流電圧特性が線形なオーミック伝導であることを特徴としている。
In order to solve the above problems, in the present invention, a memory cell is composed of a transition metal oxide that stores and holds information according to the state of electrical resistance, and a resistance change memory element that includes upper and lower electrodes sandwiching the transition metal oxide. An operation for changing the resistance value of the memory element from a high state to a low resistance value and a state after the change are defined as an erasing operation and an erasing state, and the resistance value of the memory element is increased from a low resistance value. When the operation to change to the state and the state after the change are defined as the write operation and the write state, the conduction mechanism of the write state is a tunnel conduction in which the current-voltage characteristic indicating the relationship between current and voltage is nonlinear, and the current voltage nonlinearity of characteristics depends on the resistance value of the memory element, the result as the resistance value is larger increases, conduction mechanism of the erased state is linear the current-voltage characteristic Ohmi It is characterized in that a click conduction.
本発明は、従来の多値化方法と異なり、低抵抗状態から高抵抗状態に変化する過程で多値化を行っている。このとき、遷移金属酸化物中に上下電極をつなぐように形成したフィラメントを分断するようにトンネルバリアが生成することで高抵抗化させる。一方、前記トンネルバリアを消失することで低抵抗化させる為、フィラメント自身の数・太さに変化はない。つまり、本抵抗変化素子においては、書き替え動作を繰り返し行っても、高抵抗状態への書き込みレベルを所望の抵抗値に制御することが可能である。トンネル抵抗は、書き換え動作時の上下電極印加電圧によって制御され、印加電圧が高いほどトンネルバリアの幅が広がって高抵抗化し、多値動作が可能となる。また、トンネルバリアを用いて高抵抗状態を形成しているので、熱ストレスに対する高い信頼性が得られる。 Unlike the conventional multilevel method, the present invention performs multilevel processing in the process of changing from a low resistance state to a high resistance state. At this time, the resistance is increased by generating a tunnel barrier so as to divide the filament formed so as to connect the upper and lower electrodes in the transition metal oxide. On the other hand, since the resistance is reduced by eliminating the tunnel barrier, the number and thickness of the filament itself does not change. That is, in this variable resistance element, the write level to the high resistance state can be controlled to a desired resistance value even if the rewrite operation is repeated. The tunnel resistance is controlled by the voltage applied to the upper and lower electrodes during the rewriting operation, and the higher the applied voltage, the wider the tunnel barrier and the higher the resistance, allowing multi-value operation. Moreover, since the high resistance state is formed using the tunnel barrier, high reliability against thermal stress can be obtained.
以下、図面を参照して本発明の実施形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
本実施形態においては、電気抵抗の状態により情報を記憶・保持する遷移金属酸化物と前記遷移金属酸化物を挟む上下電極からなる記憶素子からメモリセルが構成され、前記記憶素子の抵抗値が高い状態から抵抗値が低い状態へ変化させる動作及び変化後の状態を消去動作及び消去状態と定義し、前記記憶素子の抵抗値が低い状態から抵抗値が高い状態へ変化させる動作及び変化後の状態を書き込み動作及び書き込み状態と定義したとき、前記書き込み状態の伝導機構がトンネル伝導であり、トンネル抵抗を変化させることで２値以上の書き込み状態にすることが可能である。また、前記トンネル抵抗は、トンネルバリアの幅を変化させることで制御する。このとき、前記トンネルバリアの幅は、書き込み動作時に前記上下電極に印加する電圧を変えることで制御する。例えば、書き込み動作時に、書き込みパルスを上下電極間に加えたあとで、記憶素子の抵抗値を読み出す動作を行い、所望の抵抗に達していなかったら、書き込みパルスの電圧を増大させて追加書き込み動作を行い、所望の抵抗値になるまで繰り返すように構成すると良い。 In the present embodiment, a memory cell is constituted by a memory element composed of a transition metal oxide that stores and holds information according to an electrical resistance state and upper and lower electrodes sandwiching the transition metal oxide, and the resistance value of the memory element is high. An operation for changing from a state to a low resistance value and a state after the change are defined as an erasing operation and an erasing state, and an operation for changing from a low resistance value of the memory element to a high resistance value and a state after the change Is defined as a writing operation and a writing state, the conduction mechanism of the writing state is tunnel conduction, and a writing state of two or more values can be obtained by changing the tunnel resistance. The tunnel resistance is controlled by changing the width of the tunnel barrier. At this time, the width of the tunnel barrier is controlled by changing the voltage applied to the upper and lower electrodes during the write operation. For example, after a write pulse is applied between the upper and lower electrodes during a write operation, an operation of reading the resistance value of the memory element is performed.If the desired resistance is not reached, the write pulse voltage is increased to perform an additional write operation. It is good to comprise so that it may carry out and it may repeat until it becomes desired resistance value.
本実施形態においては、制御トランジスタ（nMOSFET：電界効果型トランジスタの一例）を抵抗変化素子と直列に接続した1T1R型のメモリセルを用いた。なお、抵抗変化素子として、ここでは、Ta2O5/TiO2積層構造を用いたが、ZrO2、ZrOx、TiO2、TiOx、Ta2O5、TaOxを１種類以上少なくとも含む積層膜であっても良い。抵抗変化素子の電極としては、ここではRuを用いたが、Pt、Ni、Ta、TaN、Ti、TiN、RuOであっても良い。 In this embodiment, a 1T1R type memory cell in which a control transistor (nMOSFET: an example of a field effect transistor) is connected in series with a resistance change element is used. As the variable resistance element, here, was used Ta 2 O 5 / TiO 2 multilayer structure, there in ZrO 2, ZrOx, TiO 2, TiOx, Ta 2 O 5, at least comprising the laminated film of one or more of TaOx May be. Here, Ru is used as the electrode of the variable resistance element, but it may be Pt, Ni, Ta, TaN, Ti, TiN, or RuO.
まず、初期状態から、上下電極間に電圧を印加して上下電極間にフィラメントを形成してから（Forming動作）、書き込み消去を行った。なお、Forming及び消去動作は上部電極に正電圧を印加することで行った。Forming及び消去時は、制御トランジスタの飽和電流（Isat.）によって、電流上昇（低抵抗化）を制限し抵抗値が2kΩ程度になるように制御した。通常、制御トランジスタのゲート印加電圧は2.5Vとし、このときの飽和電流は100μAである。書き込み動作は、上部電極に負電圧を印加することで行った。 First, from the initial state, a voltage was applied between the upper and lower electrodes to form a filament between the upper and lower electrodes (Forming operation), and then writing and erasing were performed. The forming and erasing operations were performed by applying a positive voltage to the upper electrode. At the time of forming and erasing, the resistance value was controlled to be about 2 kΩ by limiting the current rise (lower resistance) by the saturation current (I sat. ) Of the control transistor. Usually, the gate application voltage of the control transistor is 2.5 V, and the saturation current at this time is 100 μA. The writing operation was performed by applying a negative voltage to the upper electrode.
図４は書き込み状態と消去状態の電流−電圧特性を示したものである。それぞれ、0.5Vの電流値で規格化してある。消去状態の電流は電圧に対して線形であり、オーミックな伝導機構であることがわかる。一方、書き込み状態の伝導機構は非線形な伝導機構であり、消去状態と異なることがわかる。 FIG. 4 shows current-voltage characteristics in the written state and the erased state. Each is standardized with a current value of 0.5V. It can be seen that the current in the erased state is linear with respect to the voltage and is an ohmic conduction mechanism. On the other hand, the conduction mechanism in the written state is a non-linear conduction mechanism and is different from the erased state.
書き込み状態の電流電圧特性の温度依存性を図５に示すように詳細に解析した。図５において、挿入図は、ゼロバイアス近傍の拡大図である。温度は、4.5K〜300Kの間で変化させた。図５に示すように、全ての温度領域において、電流電圧特性は非線形性を示した。さらに、90K以下の温度領域では、折れ曲がり構造が見えた。この様な特徴的な折れ曲がり構造は、単一電子トンネリング現象が起こるときに観測されることが知られており（例えば、下記非特許文献３、４参照）、Reset状態においてトンネル障壁が生成されていることを示している。つまり、Reset状態における高抵抗化はトンネル障壁の生成によるフィラメントの断絶によるものである。
（非特許文献４）T. A. Fulton and G. J. Dolan, “Observation of Single-Electron Charging Effects in Small Tunnel Junctions”, Phys. Rev. Lett., Vol. 59, pp. 109-112
（非特許文献５）M. Amman, R. Wilkins, E. ben-Jacob, P. D. Maker, R. C. Jaklevic, “Analytic solution for the current-voltage characteristic of two mesoscopic tunnel junctions coupled in series”, Phys. Rev. B, Vol. 43, pp. 1146-1149, 1991
The temperature dependence of the current-voltage characteristics in the written state was analyzed in detail as shown in FIG. In FIG. 5, the inset is an enlarged view in the vicinity of the zero bias. The temperature was varied between 4.5K and 300K. As shown in FIG. 5, the current-voltage characteristics showed nonlinearity in all temperature regions. In addition, a bent structure was visible in the temperature range below 90K. It is known that such a characteristic bent structure is observed when a single electron tunneling phenomenon occurs (for example, see Non-Patent Documents 3 and 4 below), and a tunnel barrier is generated in the Reset state. It shows that. That is, the increase in resistance in the reset state is due to the breakage of the filament due to the generation of the tunnel barrier.
(Non-Patent Document 4) TA Fulton and GJ Dolan, “Observation of Single-Electron Charging Effects in Small Tunnel Junctions”, Phys. Rev. Lett., Vol. 59, pp. 109-112
(Non-Patent Document 5) M. Amman, R. Wilkins, E. ben-Jacob, PD Maker, RC Jaklevic, “Analytic solution for the current-voltage characteristic of two mesoscopic tunnel junctions coupled in series”, Phys. Rev. B , Vol. 43, pp. 1146-1149, 1991
単一電子トンネリング現象は、図６に示すような２重トンネル障壁モデルを用いて、説明される。２重トンネル障壁モデルを用いたシミュレーションを行った。その結果、図７の電流電圧特性に示すように、実験で得られた電流電圧特性の折れ曲がり構造を再現することができた。なお、図７の上図は中心電極の平均余剰電子数、挿入図はゼロバイアス近傍の拡大図を示している。この際、トンネル確率（遷移確率）および、電極の電子状態密度のエネルギー依存性は無いと仮定している。ゼロバイアス近傍の折れ曲がり構造（領域Ｉ）は、“中心電極から右側電極に出て、左側電極から中心電極に入る”プロセス、その外側の折れ曲がり構造（領域II）は、“左側電極から中心電極に入って、中心電極から右側電極に入る”プロセスに相当する。 The single electron tunneling phenomenon is explained using a double tunnel barrier model as shown in FIG. A simulation using a double tunnel barrier model was performed. As a result, as shown in the current-voltage characteristic of FIG. 7, the bent structure of the current-voltage characteristic obtained in the experiment could be reproduced. 7 shows the average surplus number of electrons in the center electrode, and the inset shows an enlarged view near the zero bias. At this time, it is assumed that there is no energy dependence of the tunnel probability (transition probability) and the electronic state density of the electrode. The bent structure in the vicinity of the zero bias (region I) is the process of “exiting from the center electrode to the right electrode and entering the center electrode from the left electrode”, and the outer bent structure (region II) is “from the left electrode to the center electrode. It corresponds to the process of “entering and entering the right electrode from the center electrode”.
なお、左側電極は下部電極側、右側電極は上部電極側に対応する。モデルによる折れ曲がり構造の再現から、トンネル障壁の諸情報（トンネル抵抗（R1+R2=3Gohm, R1/R2>1000）・静電容量（C1=0.304aF, C2=0.904aF））が得られた。中心電極の帯電エネルギーが電極との間の静電容量だけで決まると仮定すれば、単一電子帯電エネルギー（e2/2(C1+C2)）は66meVであるが、実際には、電極以外との容量もあるので、これよりも小さいと考えられる。実験値との比較によって得られたシミュレーションのモデルパラメータにおいて、上部電極側の障壁のトンネル抵抗は、下部電極側のそれと比較して、1000倍以上大きく、片方のバリアが支配的であることがわかる。 The left electrode corresponds to the lower electrode side, and the right electrode corresponds to the upper electrode side. From the reproduction of the bent structure by the model, various information of the tunnel barrier (tunnel resistance (R 1 + R 2 = 3Gohm, R 1 / R 2 > 1000), capacitance (C 1 = 0.304aF, C 2 = 0.904aF) )was gotten. Assuming the charge energy of the center electrode to be determined only by the capacitance between the electrodes, the single electron charging energy (e 2/2 (C 1 + C 2)) but is 66MeV, in fact, Since there is a capacity other than the electrode, it is considered to be smaller than this. In the simulation model parameters obtained by comparison with the experimental values, the tunnel resistance of the barrier on the upper electrode side is more than 1000 times larger than that on the lower electrode side, indicating that one barrier is dominant. .
以上に示したように、遷移金属酸化物と前記遷移金属酸化物を挟む上下電極からなる記憶素子においては、消去状態はオーミック伝導、書き込み状態はひとつのトンネルバリアが支配的なトンネル伝導、と異なる伝導機構である。 As described above, in the memory element composed of the transition metal oxide and the upper and lower electrodes sandwiching the transition metal oxide, the erased state is different from the ohmic conduction, and the writing state is different from the tunnel conduction dominant in one tunnel barrier. It is a conduction mechanism.
図８は、一試料に対して、-1.5Vから順次パルス電圧を上げて書き込みを行った際の、抵抗値の変化を示したものである。読み出し動作は、各パルス印加毎に行った。図８に示すように、-1.5Vの書き込みパルス（書き込み電圧パルス）を与えても、変化しなかった試料が、-2.0Vの書き込みパルスを与えることで抵抗値が増大した。次に、同電圧のResetパルスを印加しても抵抗値は変化せず、さらに高いResetパルスを印加することで抵抗値がさらに増大した。-2.0Vの書き込みパルスを与えた後で-2.5Vの書き込みパルスを与える際、最初の書き込みパルスによってある程度高抵抗化している為、書き込み電流はほとんど流れなかった。この傾向は、抵抗変化素子の高抵抗化機構として、書き込み時の電流によるジュールヒーティング効果ではなく、抵抗変化層膜中の電界効果によってスイッチしていることを示している。 FIG. 8 shows a change in resistance value when writing is performed by sequentially increasing the pulse voltage from −1.5 V to one sample. The read operation was performed for each pulse application. As shown in FIG. 8, even when a -1.5V write pulse (write voltage pulse) was applied, the sample that did not change increased the resistance value by applying a -2.0V write pulse. Next, the resistance value did not change even when a reset pulse of the same voltage was applied, and the resistance value further increased by applying a higher reset pulse. When giving a -2.5V write pulse after giving a -2.0V write pulse, the write current hardly flowed because the resistance was increased to some extent by the first write pulse. This tendency indicates that, as a mechanism for increasing the resistance of the variable resistance element, the switching is based on the electric field effect in the variable resistance layer film, not the Joule heating effect due to the current at the time of writing.
次に、図４の書き込み状態の電流電圧特性の0.4V〜0.5Vの領域をＩ＝Ｖｎの関数でフィッティングし、電流電圧特性の非線形度nを抵抗値(0.5Vで計算)に対してプロットした結果を図９に示す。図９に示すように、電流電圧特性の非線形度ｎは抵抗が大きいほど大きくなる傾向であることがわかる。この傾向は、トンネル障壁幅の変化によって得られる傾向と良く一致していた。ここで、トンネル障壁の高さが0.5eVもしくは1.0eVに固定し、障壁幅を変化させた際の、非線形度ｎと抵抗値の関係を、図９に点線（単一障壁モデルの障壁幅を変えた場合に期待される曲線）で示した。図９に示すように、２つの点線の間に収まっていることがわかる。これは抵抗変化素子の書き込み状態（高抵抗状態）の抵抗値がトンネル障壁幅に依存して変化することを示している。図１０に、抵抗変化素子の高抵抗化メカニズムを示す。図１０に示すように、トンネル障壁の幅の変化により素子の抵抗が変化する。 Next, a region of 0.4V~0.5V of the current-voltage characteristics of the written state of FIG. 4 fitting a function of I = V n, a nonlinearity n of the current-voltage characteristic with respect to the resistance value (calculated by 0.5V) The plotted results are shown in FIG. As can be seen from FIG. 9, the non-linearity n of the current-voltage characteristic tends to increase as the resistance increases. This trend was in good agreement with the trend obtained by changing the tunnel barrier width. Here, when the height of the tunnel barrier is fixed at 0.5 eV or 1.0 eV and the barrier width is changed, the relationship between the nonlinearity n and the resistance value is shown in FIG. Curves expected when changing). As shown in FIG. 9, it can be seen that it falls within the two dotted lines. This indicates that the resistance value in the write state (high resistance state) of the variable resistance element changes depending on the tunnel barrier width. FIG. 10 shows a mechanism for increasing the resistance of the variable resistance element. As shown in FIG. 10, the resistance of the element changes due to the change in the width of the tunnel barrier.
次に、0.1Vごとの電圧ステップによって書き込み状態のVerifyを行った際の抵抗分布を図１１に示す。図１１に示すように、書き込み電圧制御でVerifyを行うことで、Reset抵抗バラツキを抑制することができ、書き込み抵抗値の多値化（４値、２bit/cell）が可能であることがわかった。なお、書き換えを行う際は、抵抗変化素子に高電圧を印加してトンネルバリアを破壊し、オーミックな伝導パスを形成してから、書き込み動作によって再度トンネルバリアを形成する。また、抵抗値が低い書き込みレベルから消去動作を行う際には、最も抵抗の高い書き込みレベルに変化させる過程が行われてから、消去動作を行うことで、セル後とのスイッチング履歴が平準化され、繰り返し書き換え後のセル間のスイッチング特性バラツキを抑制することができる。 Next, FIG. 11 shows a resistance distribution when the write state is verified by a voltage step every 0.1V. As shown in FIG. 11, it was found that by performing verify by write voltage control, variation in reset resistance can be suppressed, and multi-value (4 values, 2 bits / cell) of write resistance values can be achieved. . When rewriting, a high voltage is applied to the variable resistance element to break the tunnel barrier to form an ohmic conduction path, and then the tunnel barrier is formed again by the write operation. In addition, when performing an erase operation from a write level with a low resistance value, the process of changing to the write level with the highest resistance is performed, and then the erase operation is performed to level the switching history with the cell. Thus, variation in switching characteristics between cells after repeated rewriting can be suppressed.
図１２は中間値の書き込み抵抗分布の熱ストレスによる変動を示したものである。図１２に示すように、この様にトンネルバリア幅制御で形成した書き込み状態はVerifyによって中間値のReset抵抗値とした場合も、熱ストレスによる変動量は小さく、信頼性を十分確保できることがわかった。 FIG. 12 shows the fluctuation of the intermediate value write resistance distribution due to thermal stress. As shown in FIG. 12, even when the write state formed by the tunnel barrier width control is set to an intermediate reset resistance value by Verify, the fluctuation amount due to the thermal stress is small, and it was found that sufficient reliability can be secured. .
また、本抵抗変化素子においては、書き替え動作を繰り返し行っても、トンネルバリア幅が可逆的に変化する為、高抵抗状態への書き込みレベルを所望の抵抗値に制御して複数回書き替えることが可能である。よって、本発明を用いることで、繰り返し耐性と熱耐性の高い抵抗変化素子を実現することができる。 In addition, in this variable resistance element, the tunnel barrier width changes reversibly even if the rewriting operation is repeated, so that the rewriting is performed multiple times by controlling the write level to the high resistance state to a desired resistance value. Is possible. Therefore, by using the present invention, it is possible to realize a resistance change element having high repetition resistance and high heat resistance.
なお、本実施の形態では、消去パルスが正電圧、書き込みパルスが負電圧のバイポーラ型の抵抗変化素子の場合を示したが、消去・書き込み動作を同じ極性の電圧印加で行うユニポーラ型の抵抗変化素子においても同様のことができる。この場合も同様に、書き込み電圧を上げることで、トンネルバリアの幅が増大し、書き込み状態の抵抗値を増大させることができる。また、Verifyを行うことで書き込み抵抗の多値化を行うことができる。 In this embodiment, a bipolar resistance change element in which an erase pulse is a positive voltage and a write pulse is a negative voltage is shown. However, a unipolar resistance change in which an erase / write operation is performed by applying a voltage of the same polarity. The same can be applied to the element. Similarly, in this case, by increasing the write voltage, the width of the tunnel barrier can be increased and the resistance value in the write state can be increased. In addition, the write resistance can be multivalued by performing Verify.
１ 抵抗変化素子
２ 制御トランジスタ（ｎMOSFET）
３ ゲート電圧（VG）
４ 下部電極電圧（VB.E.）
５ 上部電極電圧（VT.E.）
６ ソース電圧（VS）
1 Resistance change element 2 Control transistor (nMOSFET)
3 Gate voltage (V G )
4 Lower electrode voltage (V BE )
5 Upper electrode voltage (V TE )
6 Source voltage (V S )
Claims (5)
前記記憶素子の抵抗値が高い状態から抵抗値が低い状態へ変化させる動作及び変化後の状態を消去動作及び消去状態と定義し、前記記憶素子の抵抗値が低い状態から抵抗値が高い状態へ変化させる動作及び変化後の状態を書き込み動作及び書き込み状態と定義したとき、
前記書き込み状態の伝導機構は電流と電圧との関係を示す電流電圧特性が非線形なトンネル伝導であり、前記電流電圧特性の非線形度は前記記憶素子の抵抗値に依存し、前記抵抗値が大きいほど大きくなり、
前記消去状態の伝導機構は前記電流電圧特性が線形なオーミック伝導であることを特徴とする記憶装置。 A memory cell is composed of a resistance change memory element composed of a transition metal oxide that stores and holds information according to the state of electrical resistance and a metal electrode that sandwiches the transition metal oxide,
An operation for changing the resistance value of the memory element from a high state to a low resistance value and a state after the change are defined as an erasing operation and an erased state, and the resistance value of the memory element is changed from a low resistance value to a high resistance value. When the operation to be changed and the state after the change are defined as the write operation and the write state,
The conduction mechanism in the written state is tunnel conduction in which the current-voltage characteristic indicating the relationship between current and voltage is nonlinear. The nonlinearity of the current-voltage characteristic depends on the resistance value of the memory element, and the larger the resistance value, Grow,
The memory device, wherein the conduction mechanism in the erased state is ohmic conduction in which the current-voltage characteristic is linear.
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