JP5699772B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In order to protect electronic devices and computer systems from disasters, misuse, and unauthorized use, it is necessary to maintain the confidentiality, integrity, and availability of any hardware, software, and data, and various security measures have been taken. Yes.

  As one method for periodically changing the password to ensure security against misuse and unauthorized use, means using a one-time password or the like may be employed. For physical security of electronic devices and computers, secure devices that are equipped with security functions and can be carried, such as IC cards and USB memories, are used.

  The secure device mainly uses a non-volatile memory that does not require a power source for storing information, and examples of the non-volatile memory include an EEPROM, a flash memory, a ferroelectric memory (FeRAM), and a magnetoresistive memory (MRAM). . In particular, FeRAM and MRAM, which are examples of memories that combine both the high-speed operation and low-voltage operation characteristics of DRAM and the non-volatile characteristics of flash memory, are mass-produced as general-purpose memories and logic-embedded memories. .

  FeRAM is a non-volatile memory that uses the characteristics of ferroelectrics and has the features of high-speed writing, low power consumption, virtually unlimited number of rewrites, and byte rewriting, and written data is difficult to analyze physically. Therefore, it is also expected as an authentication LSI by taking advantage of its properties.

  In FeRAM, a 1T1C system that stores 1-bit data by one ferroelectric capacitor and one cell selection transistor, or 1-bit data by two ferroelectric capacitors and two cell selection transistors. A 2T2C method of storing is used.

  As another circuit of FeRAM, for example, the following circuit is known. The circuit has a structure in which one end of a plurality of ferroelectric capacitors is connected to a common node electrode and the other end is connected to different plate electrodes. Further, the gate of the gain transistor and the gate electrode of the readout switch are connected to the common node electrode, and one source / drain of the readout switch is connected to the common node electrode. In this case, a depletion state N-channel MOS transistor is used as a gain transistor connected to a plurality of ferroelectric capacitors.

JP 2004-227724 A

  In semiconductor devices, security is enhanced by encryption to cope with safety, but a device that can further prevent the security from being broken by electrical and physical analysis and ensure further safety Is desired.

  An object of the present invention is to provide a semiconductor device and a manufacturing method thereof for enhancing security.

According to one aspect, a first memory cell array including a first memory cell having a first transistor and a first capacitor having one electrode connected to the first transistor, and an off-current that is higher than that of the first transistor. A second memory cell array including a second memory cell having a high second transistor and a second capacitor having one electrode connected to the second transistor; the other electrode of the first capacitor and the other of the second capacitor And a plate line connected to the electrode .
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

  The off currents of the first and second transistors formed in the different memory cell arrays are made different so that the off leakage current of the second transistor is higher than that of the first transistor. As a result, data written to the second memory cell array is more easily lost than data written to the first memory cell array. As data written to the second memory cell array, for example, there is authentication data used temporarily.

FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to the embodiment. 2A and 2B are circuit diagrams illustrating examples of memory cells of the semiconductor device according to the embodiment. FIG. 3 is a diagram illustrating an example of characteristics of the MOS transistor in the semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating an example of the relationship between the applied voltage and the charge amount of the ferroelectric capacitor in the semiconductor device according to the embodiment. FIG. 5 is a plan view illustrating a part of a process of forming a MOS transistor in the semiconductor device according to the embodiment. FIG. 6 is a diagram illustrating an example of the relationship between the impurity dose of the MOS transistor and the off-current in the semiconductor device according to the embodiment. FIG. 7A to FIG. 7D are cross-sectional views illustrating a part of the process of forming the semiconductor device according to the embodiment. FIG. 8A to FIG. 8C are cross-sectional views illustrating a part of the process of forming the semiconductor device according to the embodiment. FIG. 9A and FIG. 9B are cross-sectional views illustrating a part of the process of forming the semiconductor device according to the embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

FIG. 1 is a circuit diagram showing a ferroelectric memory device which is an example of a semiconductor device according to the embodiment.
A ferroelectric memory device 1 shown in FIG. 1 has a first memory cell array region 2 and a second memory cell array region 3 formed on the same or different semiconductor substrates.

  In the first memory cell array region 2, a plurality of plate lines PL extending in the first direction X are formed at intervals in the second direction Y, and the plate lines PL are further arranged in the first direction X. 2 extending into the memory cell array region 3. Note that the first direction X and the second direction Y intersect each other.

  In the first memory cell array region 2, a plurality of word lines WL extending in the first direction X are formed at intervals in the second direction Y, and the word lines WL are further arranged in the first direction X. The second memory cell region 3 is formed so as to extend into the second memory cell region 3. Each word line WL has a plurality of bent portions 6 bent in a stepped manner in the first direction Y, and three-dimensionally intersects with one of bit lines BL1, BL2, BL3, BL4, which will be described later, at the bent portion 6.

  Further, in the first memory cell array region 2, a plurality of first and second bit lines BL1 and BL2 extending in the second direction Y are formed at intervals in the first direction X. The first bit line BL1 and the second bit line BL2 are alternately arranged.

  In the first memory cell array region 2, a plurality of first memory cells 4 are arranged in the first direction X and the second direction Y. The plurality of first memory cells 4 are arranged in a matrix, and the first direction X is the row direction and the second direction Y is the column direction.

  As illustrated in FIG. 2A, the first memory cell 4 has a 2T2C type structure including first and second MOS transistors 4a and 4c and first and second ferroelectric capacitors 4b and 4d. Have. In each of the word lines WL, the same number, for example, eight first memory cells 4 are connected to at least one of both sides of the bent portion 6 as a flange. As illustrated in FIG. 3, the first and second MOS transistors 4a and 4c have normally-off characteristics, that is, enhancement-type characteristics.

  The gate electrodes of the first MOS transistor 4a and the second MOS transistor 4c in the first memory cell 4 are connected to the same word line WL. One source / drain of the first MOS transistor 4a is connected to the first bit line BL1, and the other source / drain region is connected to the upper electrode of the first ferroelectric capacitor 4b.

  One source / drain of the second MOS transistor 4c is connected to the second bit line BL2, and the other source / drain region is connected to the upper electrode of the second ferroelectric capacitor 4d. Further, the lower electrodes of the first and second ferroelectric capacitors 4b and 4d are connected to the same plate line PL.

  In the second memory cell array region 3, a plurality of third and fourth bit lines BL3 and BL4 extending in the second direction Y are formed at intervals in the first direction X. The third bit line BL3 and the fourth bit line BL4 are alternately formed.

In the second memory cell array region 3, a plurality of second memory cells 5 are arranged in the first direction X and the second direction Y. A plurality of second memory cells 5, Ru are arranged in a matrix. The first direction X is the row direction, and the second direction Y is the column direction.

  As illustrated in FIG. 2B, the second memory cell 5 has a 2T2C type structure including third and fourth MOS transistors 5a and 5c and third and fourth ferroelectric capacitors 5b and 5d. Have. In each of the word lines WL, the same number, for example, eight second memory cells 5 are connected to at least one of both sides of the bent portion 6 as a flange.

The third and fourth MOS transistors 5a and 5c are the first and second MOS transistors 4a.
Compared to 4c, the threshold voltage of the gate voltage is lower and the off-leakage current is slightly higher, that is, a quasi-depletion type characteristic.

  The target threshold voltage needs to be adjusted to a characteristic in which a leak current of such a magnitude that data is not lost in the time required for data reading flows in the second memory cell array region 3, for example, the characteristic illustrated in FIG. There is. The MOS transistor having such characteristics is formed by adjusting the dose amount of the impurity concentration in the channel region as will be described later.

  The gate electrodes of the third MOS transistor 5a and the fourth MOS transistor 5c in the second memory cell 5 are connected to the same word line WL. One source / drain of the third MOS transistor 4a is connected to the third bit line BL3, and the other source / drain region is connected to the upper electrode of the third ferroelectric capacitor 5b.

  One source / drain of the fourth MOS transistor 5c is connected to the fourth bit line BL4, and the other source / drain region is connected to the upper electrode of the fourth ferroelectric capacitor 5d. Further, the lower electrodes of the third and fourth ferroelectric capacitors 5b and 5d are connected to the same plate line PL.

  The first and second memory cell array regions 2 and 3 are connected to a peripheral circuit 10 including a sense amplifier / write amplifier 7, a word line selector 8, a plate line driving circuit 9, and the like. For example, the first to fourth bit lines BL1, BL2, BL3, and BL4 are connected to the sense amplifier / write amplifier 7, the word line WL is connected to the word line selector 8, and the plate line PL is connected to the plate line driving circuit 9. Connected.

  In the first memory cell array region 2 described above, when data is written in the 2T2C type first memory cell 4, the first and second ferroelectric capacitors 4b and 4d are relatively polarized in opposite directions. ing. For example, in the state of data “0”, as illustrated in FIG. 2A, the first ferroelectric capacitor 4b has an upward polarization characteristic, and the second ferroelectric capacitor 4d has a downward polarization. Has characteristics. In the data “1”, the polarization is in the opposite direction.

  When reading data, the first and second MOS transistors 4a and 4c are turned on by setting the word line WL to a high voltage state. At this time, if the plate line PL connected to the lower electrodes of the first and second ferroelectric capacitors 4b and 4d is set to a high voltage state at the same time, the first ferroelectric capacitor 4b starts from the first ferroelectric capacitor 4b according to the stored data. The charge moves to the first bit line BL1, and the charge moves from the second ferroelectric capacitor to the second bit line BL2.

  When the data is “0”, the first ferroelectric capacitor 4b has an upward remanent polarization, and the second ferroelectric capacitor 4d has a downward remanent polarization. Therefore, the data is connected to the first MOS transistor 4a. Charges corresponding to J0 illustrated in FIG. 4 move to the first bit line BL1 thus formed, and J1 illustrated in FIG. 4 is connected to the second bit line BL2 connected to the second MOS transistor 4c. The charge corresponding to is moved.

  Since the potentials of the first and second bit lines BL1 and BL2 rise according to these charge amounts, the magnitude is compared by a sense amplifier to determine “0” or “1”. When the data is “0”, the potential of the first bit line BL1 is lower than the potential of the second bit line BL2, and when the data is “1”, the potential of the first bit line BL1 is the first potential. It becomes higher than the potential of the second bit line BL2.

  In FIG. 4, if the voltage applied to the lower electrode is zero after the state moves from point a to point c to read data “1”, the point c does not return to point a. Move to d. Therefore, after reading the data, the original data is written back so that the original value can be read again at the next reading. The read operation described above is the same for the second memory cell 5 in the second memory cell array region 3.

  When reading the data written in the first memory cell array region 2 as described above, it is placed in the same column as the first memory cell 4 selected as a read target in the first memory cell array region 2. In the second memory cell 5 in the second memory cell array region 3 connected to the same plate line PL, the following phenomenon occurs.

  That is, when the plate line PL is in a high voltage state, the word line WL connected to the second memory cell 5 and the third and fourth bit lines BL are both in a low voltage state. Accordingly, the gate electrodes of the third and fourth MOS transistors 5a and 5c are in the low voltage state and in the off state.

  In this state, since the third and fourth MOS transistors 5a and 5c are quasi-depletion type, a potential difference is generated between the two sources / drains of the third and fourth MOS transistors 5a and 5c. . As a result, the charges accumulated in the third and fourth ferroelectric capacitors 5b and 5d slightly leak through the third and fourth MOS transistors 5a and 5c and the third or fourth bit lines BL3 and BL4. become. However, when the plate line PL is at a low voltage, the potential difference between the two sources / drains of the third and fourth MOS transistors 5a and 5c is extremely small, so that the leakage current does not substantially flow.

  Therefore, by repeating the data reading and writing operations in the first memory cell array region 2, the charges accumulated in the third and fourth ferroelectric capacitors 3b and 3d in the second memory cell array region 3 are lost. Easy to break. That is, there is a high possibility that the written data is destroyed in the second memory cell array region 3.

  When security data is written in the second memory cell array region 3, for example, it is necessary to read the data once or a predetermined number of times. Therefore, the characteristics of the third and fourth MOS transistors 5a and 5c, for example, the off-current values are adjusted in advance so that the destruction of the data in the second memory cell array region 3 starts after the data is read the number of times. deep. This is because a plate voltage may be applied to the second memory cell 5 that is not selected.

Thus, for example, data necessary for security measures is written in the second memory cell array region 3, and after the data is read, the secure data is lost by writing or reading the data in the first memory cell array region 2. Become.

  By the way, when the data in the first memory cell array region 2 is read and written, the data written in the second memory cell array region 3 may be temporarily written in the first memory cell array region 2. By temporarily performing such data movement, it is possible to prevent the data in the second memory cell array region 3 from being lost. For example, secure data can be stored only for a specified period.

  In the semiconductor memory device as described above, the second memory cell array region 3 in which data is easily lost by the read operation and the write operation of the first memory cell array region 2 is provided. Thereby, the semiconductor memory device according to the present embodiment can be dealt with as a highly secure authentication semiconductor device, and physical and electrical analysis can be prevented.

  Next, the first MOS transistor 4a, the first ferroelectric capacitor 4b in the first memory cell array region 2, the third MOS transistor 5a in the second memory cell array region 3, the third strong transistor An example of the formation process of the dielectric capacitor 5b will be described. The first and second MOS transistors 4a and 4c are formed by the same method, and the first and second ferroelectric capacitors 4b and 4d are formed by the same method. Further, the third and fourth MOS transistors 5a and 5c are formed by the same method, and the third and fourth ferroelectric capacitors 5b and 5d are formed by the same method.

  7 to 9 are cross-sectional views showing an example of a process for forming a memory cell of the semiconductor memory device. Next, steps required until a structure illustrated in FIG.

  First, shallow trench isolation (STI) is formed as an element isolation layer 12 around a plurality of active regions of a silicon substrate 11 which is a semiconductor substrate. Note that an SOI substrate may be employed as the semiconductor substrate.

  In order to form the STI, first, a mask having a two-layer structure of a planar silicon oxide film and silicon nitride film having an opening in the element isolation region is formed on the silicon substrate 11. Thereafter, the silicon substrate 11 is etched through the opening of the mask to form a groove, and a silicon oxide film is embedded in the groove. As a result, an STI is formed. The embedded silicon oxide film on the mask is removed by a chemical mechanical polishing (CMP) method, and then the mask is removed. Note that the element isolation layer 12 may be formed by a LOCOS method.

Subsequently, boron ions are implanted as a p-type (second conductivity type) impurity into a plurality of active regions adjacent to the element isolation layer 12. As a result, a first P well 13 is formed in the active region of the first memory cell array region 2, and a second P well 14 is formed in the second memory cell array region 3 at the same time. Here, as boron ion implantation conditions, for example, the dose is about 3.0 × 10 ¹³ / cm ² and the acceleration energy is about 300 keV.

  Next, as shown in the cross-sectional view illustrated in FIG. 7B and the plan view illustrated in FIG. 5, a photoresist is applied on the silicon substrate 11, and this is exposed and developed, whereby a resist pattern 15. Is used as a mask. The resist pattern 15 covers a partial region 14a of the gate formation region (channel region) where the gate electrode 19g is to be formed among all the second P wells 14 in the second memory cell array region 3, and the other is exposed. Having an opening 15b. Further, the resist pattern 15 has an opening 15 a that exposes all the first P wells 14 in the first memory cell array region 2.

Subsequently, p-type impurity ions for first threshold voltage adjustment are implanted into the P wells 13 and 14 exposed from the openings 15a and 15b of the resist pattern 15 to form first threshold adjustment regions 16 and 17a. As conditions for implanting the p-type impurity ions, for example, the dose amount of boron ions is A ₁ × 10 ^z / cm ² and the acceleration energy is about 300 keV. Thereafter, the resist pattern 15 is removed with a solvent.

Further, as illustrated in FIG. 7C, p-type impurity ions for second threshold adjustment are implanted into the P wells 13 and 14 exposed from the element isolation layer 12. As p-type impurity ion implantation conditions, for example, the dose amount of boron ions is set to A ₂ × 10 ^z / cm ² , and the acceleration energy is set to about 300 keV.

As a result, the total dose of boron ions in the first threshold adjustment region 16 in the P well 13 in the first memory cell array region 2 is (A ₁ + A ₂ ) × 10 ^z / cm ² . In addition, in the P well 14 of the second memory cell array region 3, a partial region 14a of the channel region becomes a second threshold adjustment region 17b having a low dose amount of about A ₂ × 10 ^z / cm ² , and the remaining threshold value The dose of the adjustment region 17a becomes high (A ₁ + A ₂ ) × 10 ^z / cm ² . As the value of A _2, for example, to set the condition of the _{A 2 / (A 1 + A} 2) = 0.67~0.55.

Here, the length Lw of each of the gate electrode 18g of the first MOS transistor 4a and the gate electrode 19g of the third MOS transistor 5a illustrated in FIG. 5 is set to 10 μm, and the applied voltages of the gate electrodes 18g and 19g are set as follows. 3V. Under such conditions, the characteristics as illustrated in FIG. 6 are obtained by adjusting the impurity dose. That is, the off-state current of the first MOS transistor 4a is about 2 × 10 ¹¹ A to about 9 × 10 ¹³ A, while the threshold voltage of the third MOS transistor 5a is lowered and the off-current is about 10 ¹⁷ A units. The dose of the p-type impurity is adjusted so that

  Further, in the case where the on-state current of the first MOS transistor 4a is 1 μA, the threshold voltage of the third MOS transistor 5a is about 0.1V to 0.8V higher than the threshold voltage of the first MOS transistor 4a. Preferably, the characteristics are adjusted to be as low as about 0.3V to 0.6V.

  By the way, in order to adjust the off current, the length Lw of each of the first MOS transistor 4a and the third MOS transistor 5a may be varied instead of adjusting the impurity dose. For example, the length Lw of the gate electrode 19g of the third MOS transistor 5a may be longer than the length Lw of the gate electrode 18g of the first MOS transistor 4a.

Next, steps required until a structure shown in FIG.
First, thin gate insulating films 18a and 19a of about 3.0 nm, for example, are formed on the surfaces of the first and second P wells 13 and 14 by thermal oxidation or the like. Further, a polycrystalline silicon film having a film thickness of, for example, about 180 nm is formed on the gate insulating films 18a and 19a by a vapor deposition (CVD) method.

  Thereafter, the polycrystalline silicon film and the gate insulating films 18a and 19a are processed by lithography and subsequent dry etching, thereby forming gate electrodes 18g and 19g on the gate insulating films 18a and 19a. The gate electrodes 18g and 19g become part of the word line WL illustrated in FIG. A cap film (not shown) made of a silicon nitride film may be formed on the gate electrodes 18g and 19g.

  Subsequently, n-type (first conductivity type) impurities such as arsenic (As) ions are implanted into the first and second P wells 13 and 14 using the gate electrodes 18g and 19g as a mask. Thus, n-type extension regions 18b, 18c, 19b, and 19c are formed in the first and second P wells 13 and 14 on both sides of the gate electrodes 18g and 19g, respectively.

  Further, for example, a silicon oxide film is formed on the entire surface by the CVD method, and this silicon oxide film is etched back in a substantially vertical direction to leave a silicon oxide film on the side surfaces of the gate electrodes 18g and 19g. Used as wall 20.

  Further, n-type impurities such as phosphorus (P) ions are implanted into the P wells 13 and 14 using the gate electrodes 18g and 19g and the sidewalls 20 as a mask to form n-type source / drain regions 18s, 18d, 19s and 19d. To do. This ion implantation is set to a condition in which the impurity concentration is higher than that of the n-type extension regions 18b, 18c, 19b, and 19c.

Thereafter, a metal such as cobalt or nickel is formed on the silicon substrate 11 by sputtering, and annealed to form silicide layers 21a and 22a on the gate electrodes 18g and 19g. Silicide layers 21s, 21d, 22s, and 22d are also formed on the surfaces of the source / drain regions 18s, 18d, 19s, and 19d. Thereafter, unnecessary metal is removed.

  Thus, the basic structure of the first and third MOS transistors 4a and 4b is completed. Further, a silicon nitride film is formed as a protective insulating film 23 on the MOS transistors 4a and 5a and the element isolation layer 12 by a CVD method to a thickness of about 20 nm, for example.

Next, steps required until a structure shown in FIG.
First, a silicon oxide film is formed as a first interlayer insulating film 24 on the protective insulating film 23 by a CVD method to a thickness of about 1 μm, for example. Further, contact holes are formed on the n-type source / drain regions 18s, 18d, 19s, and 19d in the first interlayer insulating film 24 and the protective film 23 by photolithography and subsequent etching.

  Subsequently, a titanium nitride (TiN) film is formed as a barrier film in the contact hole by a sputtering method, and tungsten is buried as a main conductor film by a CVD method. Thereafter, the barrier film and the main conductor film on the first interlayer insulating film 24 are removed by a chemical mechanical polishing (CMP) method. Thereby, the barrier film and the main conductor film left in each contact hole are used as the contact plugs 25s, 25d, 26s, and 26d.

Further, on the contact plugs 25 s, 25 d, 26 s, 26 d and the first interlayer insulating film 24, a silicon oxide film and a silicon oxynitride film are formed as an antioxidant film 27 so as to have a thickness of about 130 nm and about 100 nm, respectively. Form by the method. Thereafter, an alumina (Al ₂ O ₃ ) film is formed as a base insulating film 28 on the antioxidant film 27 to a thickness of about 20 nm, for example, by sputtering.

Next, steps required until a structure illustrated in FIG.
First, a lower electrode film 29 and a ferroelectric film 30 are sequentially formed on the base insulating film 28. As the lower electrode film 29, for example, a platinum (Pt) film is formed to a thickness of, for example, about 150 nm by sputtering. Further, as the ferroelectric film 30, a film having a perovskite structure including Pb, Zr, Ti, and oxygen, for example, a PLSZT film is formed to a thickness of about 140 nm by RF sputtering. As the ferroelectric film 30, another ferroelectric material, for example, a bismuth-based material film or a barium titanate film may be formed.

Subsequently, the ferroelectric film 30 is subjected to RTA treatment in an oxygen-containing atmosphere, and the ferroelectric film 30 is crystallized. Further, an upper electrode layer 31 made of, for example, IrO ₂ which is a conductive oxide is formed on the ferroelectric film 30 to a thickness of about 250 nm by a reactive sputtering method. The material of the upper electrode layer 31 may be Ir, Ru, RuO ₂ , SrRuO ₃ , other conductive oxides, or a laminated structure thereof instead of IrO ₂ .

Next, steps required until a structure illustrated in FIG.
First, the upper electrode film 31 is processed into a plurality of electrode shapes by lithography and subsequent dry etching to form patterns of capacitor upper electrodes 31a and 31b. Subsequently, the base insulating film 28, the ferroelectric film 30, and the lower electrode film 29 are processed by lithography and subsequent dry etching to form lower electrodes 29a and 29b for capacitors that also serve as the plate lines PL. Each of the lower electrodes 29a and 29b has a stripe shape in which a plurality of upper electrodes 31a and 31b are overlaid thereon.

The lower electrode 29a in the first memory cell array region 2 is formed above the element isolation layer 12 on the side of the first MOS transistor 4a, and together with the ferroelectric film 30 and the upper electrode 31a, the first ferroelectric Capacitor 4b is formed. Similarly, the lower electrode 29b in the second memory cell array region 3 is formed above the element isolation layer 12 beside the third MOS transistor 5a, and the third strong electrode is formed together with the ferroelectric film 30 and the upper electrode 31b. The dielectric capacitor 5b is obtained.

  After that, recovery annealing is performed in order to eliminate damage to the first ferroelectric capacitor 4b and the third ferroelectric capacitor 5b that have been received by film formation and etching. As recovery annealing, furnace annealing is performed for 40 minutes at a temperature of about 650 ° C. in an oxygen atmosphere in an annealing furnace. Thereafter, an alumina film having a thickness of about 20 nm is formed as the protective film 32 on the first ferroelectric capacitor 4b, the third ferroelectric capacitor 5b, and the antioxidant film 27 by, for example, sputtering.

Further, a second interlayer insulating film 33 is formed on the protective film 32 and the base insulating film 28 so as to cover the ferroelectric capacitors 4b and 5b. Here, as the second interlayer insulating film 33, a silicon oxide film is formed by a plasma CVD method using, for example, TEOS. Further, the surface of the second interlayer insulating film 33 is polished by CMP. For example, N ₂ O plasma annealing may be performed after CMP for the purpose of dehydrating the second interlayer insulating film 33. Further, a silicon nitride film is formed as the antioxidant film 34 on the second interlayer insulating film 33 by the CVD method, and a silicon oxide film is further formed thereon as the wiring base insulating film 35 by the CVD method.

Next, a process for forming the structure illustrated in FIG.
First, the wiring base insulating film 35, the antioxidant film 34, the second interlayer insulating film 33 and the protective film 32 are patterned to form the lower electrodes 29a and 29b and the upper electrodes of the first and third ferroelectric capacitors 4b and 5b. Contact holes 3 reaching 31a and 31b are formed. After that, for example, annealing (recovery annealing) is performed in an oxygen-containing atmosphere, and the ferroelectric capacitor characteristics deteriorated by the etching process so far are recovered.

  Further, the wiring base insulating film 35, the antioxidant film 34, the second interlayer insulating film 33, the protective film 32, and the antioxidant film 27 are patterned, so that each of the first and second memory cell array regions 2 and 3 is patterned. Via holes are formed on the contact plugs 25s, 25d, 26s, and 26d. Subsequently, a TiN film is formed on the inner surfaces of the via holes in the first and second memory cell array regions 2 and 3 by using, for example, a sputtering method, and a tungsten film is embedded as a main conductor film in the via holes by using a CVD method. .

  Thereafter, the TiN film and the tungsten film on the second interlayer insulating film 33 are removed by CMP, and the TiN film and the tungsten film left in the contact holes are used as the via plugs 36a to 36h, respectively.

Next, steps required until a structure illustrated in FIG.
First, for example, a Ti / TiN film, an aluminum-copper alloy film (AlCu film), and a Ti / TiN film are sequentially stacked on the second interlayer insulating film 33 and the via plugs 36a to 36h, respectively, and patterned to form a first layer. First-layer wirings 37a, 37c, 37e, and 37f and conductive pads 37b and 37d are formed.

  In this case, one source / drain region 18d of the first MOS transistor 4a is connected to the upper electrode of the first ferroelectric capacitor 4b via the contact plug 25d, the via plug 36c, the first layer wiring 37a and the via plug 36a. Connected to 31a. Similarly, one source / drain region 19d of the third MOS transistor 5a is connected to the upper electrode of the first ferroelectric capacitor 5b via the contact plug 26d, the via plug 36g, the first layer wiring 37e, and the via plug 36e. 31b.

  The other source / drain region 18s of the first MOS transistor 4a is connected to the first-layer conductive pad 37b via a contact plug 25s and a via plug 36d. The other source / drain region 19s of the second MOS transistor 5a is connected to the first-layer conductive pad 37d through a contact plug 26s and a via plug 36h.

  The lower electrodes 29a and 29b of the first and third ferroelectric capacitors 4b and 5b, that is, the via plugs 36b and 36f connected to the plate line PL are shown in FIG. 1 through the first-layer wirings 37c and 37f, respectively. Connected to the example peripheral circuit 10.

  Subsequently, a third interlayer insulating film 38 is formed on the first-layer wirings 37a, 37c, 37e, and 37f, the conductive pads 37b and 37d, and the second interlayer insulating film 33. Further, the third interlayer insulating film 38 is formed. Among them, via holes are formed on the conductive pads 37b and 37d and the like, and a metal film is filled therein to form second-layer via plugs 39a and 39b.

  Further, second-layer wirings 40 a to 40 d are formed on the third interlayer insulating film 38. The second-layer wiring 40a connected to the second-layer via plug 39a electrically connected to the other source / drain region 18s of the first MOS transistor 4a is connected to the first MOS transistor 4a in FIG. It is connected to the exemplified bit line BL1. Similarly, the second-layer wiring 40c connected to the second-layer via plug 39b electrically connected to the other source / drain region 19s of the third MOS transistor 5a is connected to the other via the other wiring. Connected to bit line BL3.

  Thereafter, a fourth interlayer insulating film 41 is formed on the second-layer wirings 40a to 40d and the third interlayer insulating film 38, and a via plug (not shown) is formed therein. Third-layer wirings 42 a to 42 d are formed on the film 41. Further, similarly, the fifth interlayer insulating film 43, the fourth layer wirings 44a and 44b, the sixth interlayer insulating film 45, the fifth layer wirings 46 and 46b, the sixth layer interlayer insulating film 47, the cover film 48 etc. are formed.

  As described above, the memory cell array regions 2 and 3 of the semiconductor memory device shown in FIG. 1 are formed only by adding the step of changing the concentration of the impurity for adjusting the threshold voltage of the third MOS transistor 5a in a partial region. be able to.

  Although the above-described memory cell has been described as a 2T2C type memory cell, the present invention can be similarly applied to a 1T1C type memory cell using a MOS transistor as a memory selection element. That is, the secure data storage memory cell array region and the normal data storage memory cell array region have different MOS transistor threshold values, so that the secure data can be easily erased at the time of normal data reading and writing. be able to.

  In the above embodiment, the planar type is used as the ferroelectric capacitor, but a stacked type may be used. Further, the semiconductor device may be a system LSI in which a semiconductor memory device and a logic device are mounted together.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary note 1) a first memory cell array including a first memory cell having a first transistor and a first capacitor connected to the first transistor; a second transistor having a higher off-current than the first transistor; And a second memory cell array including a second memory cell having a second capacitor connected to the second transistor.
(Supplementary note 2) The semiconductor according to supplementary note 1, wherein the first transistor is a first conductivity type first MOS transistor, and the second transistor is a first conductivity type second MOS transistor. apparatus.
(Supplementary Note 3) The first dose of the second conductivity type impurity introduced into at least a part of the first semiconductor region below the gate electrode of the second MOS transistor is the first MOS transistor The semiconductor device according to appendix 2, wherein the semiconductor device is lower than a second dose amount of the second conductivity type impurity introduced into the second semiconductor region below the gate electrode.
(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the first conductivity type is an n-type, and the second conductivity type impurity is a p-type impurity.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein each of the first capacitor and the second capacitor is a ferroelectric capacitor.
(Supplementary Note 6) The first memory cell includes a third capacitor connected to a third transistor in addition to the first capacitor connected to the first transistor, and the second memory cell includes the first capacitor 6. The semiconductor device according to claim 1, further comprising a fourth capacitor connected to the fourth transistor in addition to the second capacitor connected to the two transistors.
(Supplementary Note 7) The first transistor is connected to one electrode of the first word line and the first capacitor, and the third transistor is connected to one electrode of the first word line and the third capacitor. The second transistor is connected between a second word line and one electrode of the second capacitor; the fourth transistor is connected to one electrode of the second word line and the fourth capacitor; 7. The semiconductor according to appendix 1 to appendix 6, wherein the other electrode of each of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor is connected to the same plate line. apparatus.
(Supplementary Note 8) A step of introducing a first conductivity type impurity for voltage adjustment into the first gate electrode formation region of the first transistor formation region of the semiconductor substrate in a first dose amount; Introducing the one conductivity type impurity at a second dose amount lower than the first dose amount into at least a partial region below the second gate electrode formation region; and the first transistor formation region in the first transistor formation region. Forming a first gate electrode above the first gate electrode formation region; forming a second gate electrode above the second gate electrode formation region in the second transistor formation region; and the first transistor. Forming a first source / drain region on both sides of the first gate electrode in the formation region; and a second source on both sides of the second gate electrode in the second transistor formation region. Forming a drain / drain region, forming a first capacitor connected to one of the first source / drain regions above the semiconductor substrate, and forming the second capacitor above the semiconductor substrate. Forming a second capacitor connected to one of the source / drain regions of the semiconductor device.
(Supplementary Note 9) The one-conductivity type impurity introduced into the first gate electrode formation region in the first transistor formation region is the part of the second gate electrode formation region in the second transistor formation region. 9. The method of manufacturing a semiconductor device according to appendix 8, wherein the first dose is introduced into a region other than the region.
(Supplementary note 10) The method for manufacturing a semiconductor device according to supplementary note 9, wherein the partial region of the second gate electrode formation region in the second transistor formation region is covered with a mask.
(Additional remark 11) The said 1st capacitor and the said 2nd capacitor are ferroelectric capacitors, respectively, The manufacturing method of the semiconductor device in any one of Additional remark 7 thru | or Additional remark 10 characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2, 3 Memory cell array 4, 5 Memory cell 4a, 4c MOS transistor 4b, 4d Ferroelectric capacitor 5a, 5c MOS transistor 5b, 5d Ferroelectric capacitor BL1-BL4 Bit line PL Plate line WL Word line 11 Silicon substrate 13, 14 P well 15 Resist pattern 18g Gate electrode 18s, 18d Source / drain region 19g Gate electrode 19s, 19d Source / drain region

Claims (5)

A first memory cell array including a first memory cell having a first transistor and a first capacitor having one electrode connected to the first transistor;
A second memory cell array including a second memory cell having a second transistor having an off-current higher than that of the first transistor and a second capacitor having one electrode connected to the second transistor;
A plate line connected to the other electrode of the first capacitor and the other electrode of the second capacitor;
A semiconductor device.   2. The semiconductor device according to claim 1, wherein the first transistor is a first conductivity type first MOS transistor, and the second transistor is a first conductivity type second MOS transistor.   The first dose amount of the second conductivity type impurity introduced into at least a part of the first semiconductor region below the gate electrode of the second MOS transistor is the amount of the first MOS transistor gate electrode. 3. The semiconductor device according to claim 2, wherein the semiconductor device is lower than a second dose amount of a second conductivity type impurity introduced into a lower second semiconductor region. Introducing one conductivity type impurity for voltage adjustment in a first dose amount into a first gate electrode formation region of a first memory cell formation region of a first memory cell array of a semiconductor substrate;
The one conductivity type impurity at a second dose amount lower than the first dose amount in at least a partial region of the second memory cell formation region of the second memory cell array of the semiconductor substrate below the second gate electrode formation region. A process of introducing
Forming a first gate electrode above the first gate electrode formation region in the first memory cell formation region;
Forming a second gate electrode above the second gate electrode formation region in the second memory cell formation region;
Forming first source / drain regions on both sides of the first gate electrode in the first memory cell formation region;
Forming second source / drain regions on both sides of the second gate electrode in the second memory cell formation region;
Forming a first capacitor having one electrode connected to one of the first source / drain regions above the semiconductor substrate;
Forming a second capacitor having one electrode connected to one of the second source / drain regions above the semiconductor substrate;
Forming a plate wire;
Have
The method of manufacturing a semiconductor device, wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to the plate line . The one conductivity type impurity introduced into the first gate electrode formation region in the first transistor formation region is different from the partial region in the second gate electrode formation region in the second transistor formation region. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the first dose is also introduced into the first region.

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