JP5695614B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  FIG. 7 is a cross-sectional view showing a conventional semiconductor device. In the semiconductor device 100, a SiGe epitaxial layer 102 and a silicon epitaxial layer 103 are sequentially stacked on a silicon substrate 101. Further, in the silicon epitaxial layer 103, an FET (field effect transistor) 110 composed of a source / drain region 111, a gate electrode 112, and the like is formed. The FET 110 is isolated from other elements by an STI (Shallow Trench Isolation) 104 formed in the periphery.

  In addition, patent document 1, 2 is mentioned as a prior art document relevant to this invention.

Japanese Patent Laid-Open No. 10-284722 US Pat. No. 6,121,100

  In the semiconductor device 100 described above, the SiGe epitaxial layer 102 applies biaxial stress to the silicon epitaxial layer 103, thereby causing lattice distortion in the silicon epitaxial layer 103. That is, in manufacturing the semiconductor device 100, a so-called strained silicon process is used. The wafer formed in this process is called a strained silicon wafer. By using such a strained silicon wafer, the carrier mobility in the FET can be increased.

  However, the semiconductor device 100 having the above configuration has a problem that crystal defects (dislocations) are likely to occur in the silicon epitaxial layer 103. In FIG. 7, the appearance of crystal defects is schematically indicated by line L1. One possible cause of crystal defects is as follows. That is, the strained silicon wafer is curved so as to relieve stress between the SiGe epitaxial layer 102 and the silicon epitaxial layer 103. Then, when the curved wafer is subjected to vacuum chucking or the like, an excessive force is applied to the wafer, thereby causing crystal defects. Such crystal defects lead to deterioration of electrical characteristics of the semiconductor device such as an increase in leakage current.

  A semiconductor device according to the present invention includes a silicon substrate, a strain imparting layer provided on the silicon substrate, a silicon layer provided on the strain imparting layer, a field effect transistor provided in the silicon layer, An element isolation region provided around the field effect transistor and reaching the strain imparting layer through the silicon layer, the strain imparting layer being separated from a source / drain region of the field effect transistor In addition, a strain is generated in the channel portion of the field effect transistor in the silicon layer.

  In this semiconductor device, the strain imparting layer causes lattice distortion in the channel portion of the FET in the silicon layer. Thereby, the carrier mobility in FET can be increased. This contributes to the improvement of the electrical characteristics of the FET and the semiconductor device. Furthermore, the element isolation region penetrates through the silicon layer and reaches the strain imparting layer. For this reason, during the manufacture of this semiconductor device, the curvature of the silicon wafer occurs in each region partitioned by the element isolation region. That is, it is possible to prevent the silicon wafer from being greatly curved as a whole. Thereby, generation | occurrence | production of the crystal defect in a silicon layer can be suppressed.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a field effect transistor, wherein an element isolation region is formed on a silicon substrate so as to surround the region where the field effect transistor is formed. A step of epitaxially growing a strain imparting layer on the silicon substrate on which the element isolation region is formed, a step of epitaxially growing a silicon layer on the strain imparting layer, and a source- Forming the field effect transistor such that a drain region is separated from the strain applying layer, and the strain applying layer causes lattice distortion in a channel portion of the field effect transistor in the silicon layer. It is characterized by being.

  In this manufacturing method, a silicon layer is formed on the strain imparting layer. For this reason, in the semiconductor device manufactured by this method, lattice strain occurs in the channel portion of the FET in the silicon layer due to the strain imparting layer. Thereby, the carrier mobility in FET can be increased. This contributes to the improvement of the electrical characteristics of the FET and the semiconductor device. Further, after the element isolation region is formed on the silicon substrate, the strain imparting layer and the silicon layer are formed. For this reason, the curvature of the silicon wafer occurs in each region partitioned by the element isolation region. That is, it is possible to prevent the silicon wafer from being greatly curved as a whole. Thereby, generation | occurrence | production of the crystal defect in a silicon layer can be suppressed.

  According to the present invention, a semiconductor device having excellent electrical characteristics and a manufacturing method thereof are realized.

1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows 2nd Embodiment of the semiconductor device by this invention. (A)-(c) is process drawing which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is sectional drawing which shows the semiconductor device which concerns on the modification of embodiment. It is sectional drawing which shows the conventional semiconductor device. 10 is a cross-sectional view showing a semiconductor device described in Patent Document 1. FIG. 10 is a cross-sectional view showing a semiconductor device described in Patent Document 2. FIG. (A)-(c) is process drawing which shows the manufacturing method of the semiconductor device of FIG.

  Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

(First embodiment)
FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a silicon substrate 10, a strain imparting layer 20, a silicon layer 30, an FET 40, and an element isolation region 50.

  A strain imparting layer 20 is provided on the silicon substrate 10. In the present embodiment, the strain imparting layer 20 is a SiGe layer. A silicon layer 30 is provided on the strain imparting layer 20. These strain imparting layer 20 and silicon layer 30 are epitaxial layers formed by an epitaxial growth method. The strain imparting layer 20 applies a biaxial stress to the silicon layer 30 to cause lattice strain in the channel portion of the FET 40 in the silicon layer 30. This biaxial stress is parallel to the interface between the strain imparting layer 20 and the silicon layer 30.

  An FET 40 is provided in the silicon layer 30. The FET 40 includes a source / drain region 42, an SD extension region (LDD (Light Doped Drain) region) 43, a gate electrode 44, and a sidewall 46. Here, the source / drain region 42 and the strain applying layer 20 are separated from each other.

  The FET 40 may be an N-channel FET or a P-channel FET. Although only one FET (FET 40) is shown in FIG. 1, the semiconductor device 1 may be provided with both an N-channel FET and a P-channel FET. In that case, these FETs are isolated from each other by an element isolation region 50 described later.

  An element isolation region 50 is provided around the FET 40. The element isolation region 50 penetrates through the silicon layer 30 and reaches the strain imparting layer 20. In particular, in the present embodiment, the element isolation region 50 penetrates through the silicon layer 30 and the strain imparting layer 20 and reaches the inside of the silicon substrate 10. This element isolation region 50 is, for example, an STI. As can be seen from FIG. 1, in the region surrounded by the element isolation region 50, the thickness of the strain imparting layer 20 is substantially uniform.

With reference to FIGS. 2 and 3, an example of a method for manufacturing the semiconductor device 1 will be described as a first embodiment of the method for manufacturing a semiconductor device according to the present invention. In general, this manufacturing method includes the following steps (a) to (d).
(A) Step of forming element isolation region 50 on silicon substrate 10 so as to surround the region where FET 40 is formed (b) Epitaxial growth of strain imparting layer 20 on silicon substrate 10 on which element isolation region 50 is formed (C) Step of epitaxially growing the silicon layer 30 on the strain imparting layer 20 (d) Step of forming the FET 40 in the silicon layer 30 so that the source / drain regions 42 are separated from the strain imparting layer 20

  More specifically, first, an element isolation region 50 having a shallow trench structure is formed in the silicon substrate 10a (FIG. 2A). Thereafter, the silicon substrate 10a is thinned by dry etching, and the silicon substrate 10a is retracted with respect to the element isolation region 50 (FIG. 2B). At this time, a part of the element isolation region 50 is left in the silicon substrate 10a. As a result, an element isolation region 50 surrounding the region where the FET 40 is formed is formed on the silicon substrate 10.

  That is, in the step of forming the element isolation region 50, after the element isolation region 50 is formed in the surface layer of the silicon substrate 10a, the silicon substrate 10a is thinned from the surface layer side.

  Subsequently, after the strain imparting layer 20 is epitaxially grown on the silicon substrate 10, the silicon layer 30 is epitaxially grown on the strain imparting layer 20 (FIG. 3A). Thereafter, the gate electrode 44 and the side wall 46 are formed on the silicon layer 30 (FIG. 3B). Furthermore, by forming the source / drain region 42 and the SD extension region 43 in the silicon layer 30, the semiconductor device 1 of FIG. 1 is obtained.

  The effect of this embodiment will be described. In the manufacturing method, the silicon layer 30 is formed on the strain imparting layer 20. For this reason, in the semiconductor device 1, the strain imparting layer 20 causes lattice distortion in the channel portion of the FET 40 in the silicon layer 30. Thereby, the carrier mobility in FET40 can be increased. This contributes to the improvement of the electrical characteristics of the FET 40 and thus the semiconductor device 1.

  Further, the element isolation region 50 penetrates through the silicon layer 30 and reaches the strain imparting layer 20. For this reason, when the semiconductor device 1 is manufactured, the curvature of the silicon wafer occurs for each region partitioned by the element isolation region 50. That is, it is possible to prevent the silicon wafer from being greatly curved as a whole. Thereby, generation | occurrence | production of the crystal defect in the silicon layer 30 can be suppressed. Therefore, the semiconductor device 1 excellent in electrical characteristics and the manufacturing method thereof are realized.

  A SiGe layer is used as the strain imparting layer 20. The SiGe layer can suitably function as a layer that causes lattice distortion in the channel portion of the FET 40.

  The element isolation region 50 passes through the silicon layer 30 and the strain imparting layer 20 and reaches the silicon substrate 10. For this reason, the strain imparting layer 20 is completely divided with the element isolation region 50 as a boundary. Thereby, the above-mentioned problem, that is, the problem that the silicon wafer is largely curved as a whole can be prevented more reliably. In particular, in the present embodiment, the element isolation region 50 reaches the inside of the silicon substrate 10. This further increases the certainty that the above problem is prevented.

  In the step of forming the element isolation region 50, after the element isolation region 50 is formed in the surface layer of the silicon substrate 10a, the silicon substrate 10a is thinned from the surface layer side. By doing so, a structure in which the element isolation region 50 reaches the inside of the silicon substrate 10 can be easily realized.

  In the region surrounded by the element isolation region 50, the thickness of the strain imparting layer 20 is substantially uniform. With this structure, the strain imparting layer 20 can suitably impart biaxial stress to the silicon layer 30.

  When both the N channel type FET and the P channel type FET are provided in the semiconductor device 1, the usefulness of the present embodiment is particularly high. This is because when biaxial stress is applied to the silicon layer 30, unlike the case where uniaxial stress is applied, the effect of increasing carrier mobility is obtained in both the N-channel FET and the P-channel FET. .

  Incidentally, conventional semiconductor devices include those shown in FIGS. 8 and 9 in addition to those shown in FIG. 7 described above.

  FIG. 8 is a cross-sectional view showing the semiconductor device described in Patent Document 1. In FIG. In the semiconductor device 200, a silicon epitaxial layer 202 doped with boron, a silicon epitaxial layer 203, a SiGe epitaxial layer 204, and a silicon epitaxial layer 205 are sequentially stacked on a silicon substrate 201. Further, source / drain regions 211 are formed over the four layers of the silicon epitaxial layer 202, the silicon epitaxial layer 203, the SiGe epitaxial layer 204, and the silicon epitaxial layer 205. The source / drain regions 211 together with the gate electrode 212 constitute an FET 210. An STI 206 is formed around the FET 210.

  Thus, in the semiconductor device 200, the source / drain regions 211 are formed in the SiGe epitaxial layer 204. This is to utilize the property that the mobility of hole carriers in the SiGe layer is higher than that in the silicon layer. In other words, the electrical characteristics are improved by using the SiGe layer as a hole carrier movement path.

  Here, if the source / drain region 42 is formed in the strain applying layer 20 in the semiconductor device 1, the stress of the strain applying layer 20 is relieved by ion implantation when forming the source / drain region 42. . Then, the function of the strain imparting layer 20 that applies biaxial stress to the silicon layer 30 is degraded. From this point of view, in the semiconductor device 1, the strain imparting layer 20 and the source / drain regions 42 are separated from each other.

  FIG. 9 is a cross-sectional view showing the semiconductor device described in Patent Document 2. As shown in FIG. In the semiconductor device 300, a P-channel FET 310 including a source / drain region 311 and a gate electrode 312 is provided on a silicon substrate 301. The source / drain region 311 is formed as a SiGe epitaxial layer. An STI 302 is formed around the P-channel FET 310.

  A method for manufacturing the semiconductor device 300 will be described with reference to FIG. First, the STI 302 is formed in the silicon substrate 301 (FIG. 10A). Next, a gate electrode 312 is formed on the silicon substrate 301 (FIG. 10B). Thereafter, a region to be the source / drain region 311 in the silicon substrate 301 is etched to form a recess 311a (FIG. 10C). Subsequently, a source / drain region 311 is formed by epitaxially growing a SiGe layer in the recess 311a. Thereby, the semiconductor device 300 of FIG. 9 is obtained.

  In this semiconductor device 300, uniaxial stress is applied to the silicon substrate 301 from the source / drain regions 311. As a result, the electrical characteristics of the P-channel FET 310 can be improved. On the other hand, however, the uniaxial stress cannot improve the electrical characteristics of the N-channel FET, but rather deteriorates it. Therefore, in manufacturing the semiconductor device 300, it is necessary to form the recess 311a in the region where the P-channel FET is formed in a state where the region where the N-channel FET is formed is covered with a mask. Therefore, the number of manufacturing steps increases and manufacturing becomes complicated.

  On the other hand, according to this embodiment, since the biaxial stress by the strain imparting layer 20 is used, as described above, the electrical characteristics of both the N-channel FET and the P-channel FET are improved. Can do. Therefore, an increase in the number of manufacturing steps can be suppressed.

(Second Embodiment)
FIG. 4 is a sectional view showing a second embodiment of the semiconductor device according to the present invention. The semiconductor device 2 includes a silicon substrate 10, a strain imparting layer 20, a silicon layer 30, an FET 40, and an element isolation region 50. The configurations of the silicon substrate 10, the strain imparting layer 20, the silicon layer 30, and the FET 40 are the same as those in the semiconductor device 1.

  In the semiconductor device 2, the configuration of the element isolation region 50 is different from that of the semiconductor device 1. That is, in the semiconductor device 1, the element isolation region 50 penetrates through the interface between the silicon substrate 10 and the strain imparting layer 20 and reaches the inside of the silicon substrate 10. On the other hand, in the semiconductor device 2, one end of the element isolation region 50 is stopped at the interface.

  With reference to FIG. 5, an example of a method for manufacturing the semiconductor device 2 will be described as a second embodiment of the method for manufacturing a semiconductor device according to the present invention. This manufacturing method also includes the steps (a) to (d) as in the first embodiment.

  More specifically, first, an insulating film 50a is formed on the silicon substrate 10 (FIG. 5A). Next, while leaving a part of this insulating film 50a (part to be the element isolation region 50), the other part is removed by photolithography or the like (FIG. 5B). As a result, an element isolation region 50 surrounding the region where the FET 40 is formed is formed on the silicon substrate 10.

  That is, in the step of forming the element isolation region 50, after forming the insulating film 50 a on the silicon substrate 10, the insulating film 50 a is patterned to form the element isolation region 50.

  Subsequently, after the strain imparting layer 20 is epitaxially grown on the silicon substrate 10, the silicon layer 30 is epitaxially grown on the strain imparting layer 20 (FIG. 5C). Thereafter, the FET 40 is formed to obtain the semiconductor device 2 of FIG.

  The effect of this embodiment will be described. Also in this embodiment, the strain imparting layer 20 causes lattice distortion in the channel portion of the FET 40 in the silicon layer 30. Thereby, the carrier mobility in FET40 can be increased. This contributes to the improvement of the electrical characteristics of the FET 40 and thus the semiconductor device 2.

  Further, the element isolation region 50 penetrates through the silicon layer 30 and reaches the strain imparting layer 20. For this reason, when the semiconductor device 2 is manufactured, the curvature of the silicon wafer occurs in each region partitioned by the element isolation region 50. That is, it is possible to prevent the silicon wafer from being greatly curved as a whole. Thereby, generation | occurrence | production of the crystal defect in the silicon layer 30 can be suppressed. Therefore, the semiconductor device 2 excellent in electrical characteristics and the manufacturing method thereof are realized.

  The element isolation region 50 passes through the silicon layer 30 and the strain imparting layer 20 and reaches the silicon substrate 10. For this reason, the strain imparting layer 20 is completely divided with the element isolation region 50 as a boundary. Thereby, the problem that the silicon wafer is largely curved as a whole can be prevented more reliably.

  In the step of forming the element isolation region 50, after forming the insulating film 50 a on the silicon substrate 10, the insulating film 50 a is patterned to form the element isolation region 50. By doing so, a structure in which the element isolation region 50 reaches the silicon substrate 10 can be easily realized. The remaining effects of this embodiment are the same as those of the first embodiment.

  The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment, and various modifications can be made. In the said embodiment, the example which the element isolation region 50 penetrated the distortion provision layer 20 was shown. However, the element isolation region 50 only needs to reach the strain imparting layer 20 and does not need to penetrate the strain imparting layer 20. For example, as shown in FIG. 6A, one end of the element isolation region 50 may stop inside the strain imparting layer 20. Alternatively, as illustrated in FIG. 6B, one end of the element isolation region 50 may stop at the interface between the strain imparting layer 20 and the silicon layer 30.

  The material of the strain imparting layer 20 is not limited to SiGe. Any material other than SiGe may be used as long as it causes lattice distortion in the channel portion of the FET 40.

  Moreover, in the said embodiment, the example using only biaxial stress was shown. However, biaxial stress and uniaxial stress may be used in combination. In that case, for example, in the semiconductor device 1 or the semiconductor device 2, the source / drain region 42 may be formed as a SiGe epitaxial layer.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 10 Silicon substrate 10a Silicon substrate 20 Strain imparting layer 30 Silicon layer 40 FET
42 Source / Drain Region 43 SD Extension Region 44 Gate Electrode 46 Side Wall 50 Element Isolation Region 50a Insulating Film

Claims (5)

A silicon substrate;
A strain-imparting layer provided on the silicon substrate;
A silicon layer provided on the strain imparting layer;
A field effect transistor provided in the silicon layer;
An element isolation region provided around the field effect transistor and reaching the strain imparting layer through the silicon layer,
The strain imparting layer is spaced apart from the source / drain regions of the field effect transistor, and causes lattice distortion in the channel portion of the field effect transistor in the silicon layer,
The element isolation region passes through the silicon layer and the strain imparting layer and reaches the inside of the silicon substrate,
The strain imparting layer is a semiconductor device formed on the silicon substrate after forming the element isolation region. The semiconductor device according to claim 1,
The strain imparting layer is a semiconductor device which is a SiGe layer. The semiconductor device according to claim 1 or 2,
In the region surrounded by the element isolation region, the thickness of the strain applying layer is uniform. The semiconductor device according to claim 1,
As the field effect transistor, both an N-channel field effect transistor and a P-channel field effect transistor are provided,
The N-channel field effect transistor and the P-channel field effect transistor are separated from each other by the element isolation region. The semiconductor device according to claim 1,
The strain applying layers located on both sides of the element isolation region are semiconductor devices having the same composition.

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