JP5674171B2 - Semiconductor integrated circuit and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit incorporating a regulator for stepping down an external power supply voltage, and further relates to a regulator layout method. For example, the present invention is applied to a data processing system such as a portable information terminal requiring miniaturization and low power consumption of a semiconductor chip. And effective technology.

  In a semiconductor integrated circuit having an internal circuit that operates at an internal power supply voltage (Vint: for example, 1.8 V, 1.5 V, etc.) lower than the external power supply voltage (for example, 3.3 V, 5 V, etc.), the external power supply voltage is stepped down. Some have a step-down power supply circuit that generates an internal power supply voltage. Conventionally, in order to suppress undesired voltage drop of the internal power supply voltage due to the parasitic resistance of the wiring from the step-down power supply circuit to the internal circuit, a plurality of step-down power supply circuits are made on-chip, and those step-down power supply circuits Is known in the art to reduce undesired voltage drop of the external power supply voltage caused by the parasitic resistance of the wiring from the power supply pad to the step-down power supply circuit. Examples of documents describing such techniques include JP-A-9-289288 and JP-A-2-224267.

Japanese Patent Laid-Open No. 9-289288 JP-A-2-224267

  The present inventor examined these techniques. According to this, in the prior art, the undesired voltage drop of the internal power supply voltage due to the parasitic resistance of the wiring from the step-down power supply circuit to the internal circuit and the undesired drop of the external power supply voltage from the power supply pad to the step-down power supply circuit. Although multiple step-down power supply circuits are arranged in the vicinity of the power supply pad in order to suppress this, the area occupied by the chip by increasing the number of step-down power supply circuits on-chip is not particularly considered. No clear solution has been shown for the means to reduce this.

  Furthermore, the present inventor has studied the promotion of the low power consumption intended by using the step-down voltage in the first place, and as a result, the level of the step-down voltage is controlled according to the internal state of the semiconductor integrated circuit. In order to reduce the subthreshold leakage current of the circuit to be operated, the usefulness of using the step-down voltage and the external power supply voltage properly when the threshold voltage is controlled by changing the substrate voltage has been found.

  An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing an increase in chip area due to a built-in regulator for stepping down an external power supply voltage and realizing stabilization of the stepped down voltage.

  Another object of the present invention is to provide a semiconductor integrated circuit that can further promote low power consumption by using a step-down voltage.

  Another object of the present invention is to provide a semiconductor integrated circuit capable of facilitating the design of a semiconductor integrated circuit capable of suppressing an increase in chip area due to the incorporation of a regulator for stepping down an external power supply voltage and realizing stabilization of the stepped down voltage. It is to provide a circuit design method.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] << Buffer and Protection Circuit Area >> A semiconductor integrated circuit according to the present invention is provided for disposing external terminals (20) such as a plurality of pad electrodes related to input / output of signals and power on a semiconductor chip. The first region (1) has a second region (2) for arranging a buffer and a protection element related to input / output of a signal and a power source next to the first region (1). The second region is used to step down the first power supply voltage (Vext) supplied from the outside of the semiconductor chip (10) to at least one internal power supply voltage (Vint) lower than the first power supply voltage (Vint). A plurality of regulators (150 to 157) are arranged. Specifically, the regulator uses an area having a width in which the buffer and the protection circuit are formed and roughly determined by the width of the layout of the external terminal receiving the first power supply voltage and the external terminal receiving the circuit ground voltage. Located in the vicinity. A first internal circuit that operates in response to the internal power supply voltage is disposed in the third region.

  In the second region, the external terminal that receives the first power supply voltage and the vicinity of the external terminal that receives the circuit ground voltage do not require a buffer unlike the signal external terminal, so that there is essentially no space. Yes, the layout of the regulator is relatively easy. It is sufficient that the buffer and the protection circuit are basically arranged for each external terminal, the number thereof is smaller than the number of mounting circuits in the entire semiconductor integrated circuit, and the region represented by the second region is substantially the same. It is considered an area with a high vacancy rate.

  As represented by the second region, by arranging a plurality of regulators in a region where a buffer and a protection circuit are formed and whose width is roughly determined by the width of the layout, the number of regulators can be increased relatively easily. Moreover, even if it is increased, there is almost no need to increase the chip area in proportion thereto. Therefore, it is easy to suppress the increase of the chip area due to the incorporation of the regulator for stepping down the external power supply voltage and to secure the maximum current required for the first internal circuit. Easy.

  [2] << Power Supply Main Line >> The semiconductor integrated circuit has a power supply line (L20) such as a power supply main line for connecting the outputs of the plurality of regulators to supply the internal power supply voltage to the first internal circuit. In a desirable mode, the power supply wiring may be formed in a closed loop shape. This makes it possible to easily equalize the internal power supply voltage on the power supply wiring, and to supply a constant and stable internal power supply voltage to many circuits widely distributed in the semiconductor chip.

  Parasitic resistance between the output coupling points of the regulator is made approximately equal to each other on the power supply wiring. As a result, the level of the internal power supply voltage is further uniformed. In other words, the distance between the output coupling points of the regulator on the power supply wiring may be approximately equal to each other.

  In terms of a regulator to be integrated into a semiconductor integrated circuit, even if it is a regulator, the chip occupying area is limited, so it is a good idea to employ a series regulator as the regulator. At this time, from the viewpoint of preventing an increase in the area occupied by the chip, the stabilizing capacitor is preferably an external component of the semiconductor integrated circuit. For this purpose, an external terminal (20A-2) connected to the power supply wiring is provided, and a stabilization capacitor (C10) may be externally connected to the external terminal.

  [3] << Level conversion circuit >> When a signal is transferred between a circuit operating at the first power supply voltage and a circuit operating at the internal power supply voltage, the signal input from the former to the latter may be performed as it is. In the opposite case, a signal having a smaller amplitude than that of the operating power supply is input, and for example, the logic level of the input signal may become an intermediate level in a CMOS input circuit, which may cause an undesired through current. In order to prevent such a risk, a signal output from the first internal circuit as a second internal circuit using the first power supply voltage is defined by the first power supply voltage. A level conversion circuit (G3) that converts the amplitude into an output may be used. For example, when the output of the first logic circuit is supplied to the buffer in the second area, the output signal is supplied to the buffer through the level conversion circuit.

  [4] << Reference voltage generation circuit >> When the reference voltage is required to define the target voltage when the step-down voltage is generated by the regulator, as a second internal circuit using the first power supply voltage A reference voltage generation circuit (60) for generating a reference voltage for the step-down voltage and supplying the reference voltage to the regulator may be provided.

  When the reference voltage is supplied to each regulator, in order to suppress the antenna effect due to the reference voltage wiring, the reference voltage wiring (L10) that is divided in the middle to form an open loop may be employed.

  The reference voltage wiring is arranged approximately along the arrangement of the regulator, and shield wiring to which the ground voltage of the circuit is supplied is arranged in parallel in the same wiring layer, and further another shield wiring or shield area is provided above and below the reference wiring. You may install in parallel. It is possible to suppress or reduce the fluctuation of the reference voltage due to the influence of crosstalk or the like.

  Considering the influence of process variations of the semiconductor integrated circuit, the reference voltage generation circuit generates a reference voltage based on the output voltage of the reference voltage generation circuit (100) whose circuit characteristics are determined by the trimming information, and the trimming information A configuration having an electrically writable nonvolatile memory that holds the memory may be employed. As a part of the wafer probe test, the characteristics of the reference voltage generation circuit are measured, trimming information for canceling the characteristic fluctuation due to the influence of process variation is acquired, and this is initially written in the nonvolatile memory (135). The trimming information may be read from the nonvolatile memory and latched in the reference voltage generation circuit as part of the reset process for the semiconductor integrated circuit, and the reference voltage may be generated according to the latched trimming information.

  The reference voltage generation circuit may be configured to output a reference voltage selected from a plurality of types of reference voltages. For example, when a semiconductor integrated circuit is operated in a clock synchronous manner, when the clock frequency is lowered to operate at a low speed, the reference voltage is lowered to operate the first circuit at a low speed, and the clock frequency is increased to operate at a high speed. Can increase the reference voltage and operate the first circuit at high speed.

  Such reference voltage selection control may be performed in response to an instruction given to the reference voltage generation circuit from the control means (120) such as a CPU according to the operation mode. For example, in a semiconductor integrated circuit such as a microprocessor or a data processor, a low-level reference voltage is selected in a standby mode or a sleep mode, and a high-level reference voltage is selected in an active mode.

  [5] << Activation control >> When the power consumption of the semiconductor integrated circuit is reduced, an activation control means for controlling activation / deactivation of the regulator as the second internal circuit using the first power supply voltage ( 70) may be employed.

  The activation control means can perform activation control separately for each of the single or plural regulators. For example, it is possible to control to operate all regulators in the active mode and operate only some regulators in the standby mode or the sleep mode. Alternatively, some of the regulators may be configured with a circuit having a small current driving capability or current consumption, and only such some of the regulators may be operated in the standby mode or the sleep mode.

  In addition, one or a small number of sub-regulators (80) having a small current driving capability or current consumption are formed in the fourth region as a second internal circuit using the first power supply voltage, and are provided as activation control means (70). Activates the regulator formed in the second region in response to the first operation mode such as the active mode of the semiconductor integrated circuit, and performs the second operation such as the standby mode or the sleep mode of the semiconductor integrated circuit. The sub regulator may be activated in response to the mode.

  [6] << Switching regulator control >> In some cases, a sufficient current supply capability cannot be obtained with only a regulator built in a semiconductor integrated circuit. Therefore, in order to easily cope with this in advance, a switching regulator driver control circuit (90) is used as the second circuit in the semiconductor chip having the plurality of regulators, assuming the use of an external switching regulator. Are assigned in advance, and several external terminals (20B-1, 20B-2) are assigned to the external output terminals of the drive control signals generated by the driver control circuit.

  When an external switching regulator is used, its voltage output terminal is coupled to a predetermined external terminal (20B-3). The predetermined external terminal is connected to a power supply wiring to which outputs of the plurality of regulators are coupled and supplies an internal power supply voltage to the first internal circuit. In this case, the operation of the regulator built in the semiconductor integrated circuit is not necessary. Deactivation control means (70, 135) for controlling one of the regulator and the driver control circuit in a fixed inactive state may be employed. For example, an electric fuse or a flash memory fuse using an electrically rewritable nonvolatile memory element may be used as the deactivation control means.

  If a driver control circuit for a switching regulator is built in, a switching regulator with a power transistor can be selected according to the required current drive capability. On the other hand, a driver control circuit as a logic circuit is built in a semiconductor integrated circuit. Therefore, the increase of the chip occupation area due to this can be suppressed relatively small.

  [7] << Substrate Bias Control Circuit >> The operating speed and subthreshold leakage current of a switching element such as a MOS (Metal Oxide Semiconductor) or MIS (Metal Insulated Semiconductor) transistor depend on the threshold voltage. In order to improve the operating frequency, the threshold voltage may be lowered. However, if the threshold voltage is set too low, the MOS transistor cannot be completely turned off due to the subthreshold characteristic of the transistor, and the subthreshold leakage current increases. The power consumption of the semiconductor integrated circuit becomes very large. If a forward substrate bias is applied to the switching transistor, the threshold voltage is reduced and the operation is further speeded up. If a reverse substrate bias is applied to the transistor, the threshold voltage increases and the subthreshold leakage current at the time of non-conduction decreases, which promotes low power operation.

  The substrate bias means that the substrate potential of the switching transistor is different from the source potential. If the substrate potential of the n-channel MOS transistor is lower than the source potential (reverse bias state), the threshold voltage increases as compared with the case where no bias is applied, and if the substrate potential is higher than the source potential (forward bias state), the threshold value is increased. The voltage is reduced compared to when no bias is applied. If the substrate potential of the p-channel MOS transistor is set higher than the source potential (reverse bias state), the threshold voltage increases compared to the case where no bias is applied, and if the substrate potential is lower than the source potential (forward bias state), the threshold value is increased. The voltage is reduced compared to when no bias is applied.

  A substrate bias control circuit (71) for controlling a substrate potential of a switching element constituting the first internal circuit is provided as a second internal circuit that operates at the first power supply voltage in the semiconductor integrated circuit having the regulator. The substrate bias control circuit uses the first power supply voltage and the internal power supply voltage to control the substrate potential according to the operation mode of the semiconductor integrated circuit. For example, the reverse substrate bias state is given to the switching element in the standby state or sleep state of the first internal circuit. As a result, when most of the internal circuits do not have to operate substantially as in the standby state or the sleep state, the threshold voltage of the switching transistor increases and the subthreshold leakage current decreases. In the active mode, it is not necessary to apply a substrate bias, and the source of the switching transistor and the substrate need only be at the same potential.

  As a specific aspect, the substrate bias control circuit defines the substrate potential of the first internal circuit by the internal power supply voltage and the ground voltage according to a first operation mode such as an active mode of a semiconductor integrated circuit, The substrate potential of the first internal circuit is defined by the first power supply voltage and the negative voltage of the circuit obtained by stepping down the ground voltage in accordance with a second operation mode such as a standby mode of the semiconductor integrated circuit.

  [8] << Design Method >> In designing a semiconductor integrated circuit having the regulator, the regulator has a width approximately equal to the width determined by the layout of the buffer, and the regulator has an external terminal for receiving the first power supply voltage and a ground voltage of the circuit. It is sufficient to include a step of arranging in the vicinity of the external terminal receiving the signal. In this step, if a regulator selected from the cell library according to the supply current required for the first internal circuit is arranged, the semiconductor integrated circuit can be designed relatively easily.

  [9] In a semiconductor integrated circuit according to still another aspect of the present invention, the regulator is composed of an amplifier section and a transistor circuit section, and the amplifier section is formed with a buffer connected to an external terminal and a protection circuit. The transistor portion is arranged in a region inside the region where the buffer and the protection circuit are formed. For example, a terminal area (1) in which a plurality of terminals used for connection to the outside are arranged on a semiconductor chip, and a buffer and a protection circuit connected to the terminals are arranged and supplied to predetermined terminals from the outside. A first circuit region (partial region outside region 2) used for arranging a plurality of regulators for stepping down the first power supply voltage to be at least one type of internal power supply voltage lower than the first power supply voltage, and the internal power supply voltage A second circuit region (3) in which a first internal circuit that operates in response to the second power supply voltage is disposed, and a third circuit region (4) in which a second internal circuit using the first power supply voltage is disposed. The amplifier unit is disposed in the first circuit region. The transistor circuit portion includes a region between the first circuit region and the second circuit region or a region between the first circuit control region and the third circuit region (a partial region inside the region 2). ). Thereby, the freedom degree with respect to arrangement | positioning of the said regulator can be increased.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, in a semiconductor integrated circuit having an internal circuit that operates with an internal power supply voltage lower than the external power supply voltage, a regulator that generates the internal power supply voltage can be arranged within the area for arranging the buffer and the protection element, or the width of the buffer layout. By arranging the buffer layout region with a roughly determined width, it is possible to reduce the area overhead due to the on-chip implementation of the step-down power supply circuit.

  In addition, a loop-shaped power supply trunk that transmits the step-down voltage is used, and an electrode pad is provided for connecting an external stabilization capacitor to the power supply trunk. Low power consumption can be further promoted by controlling deactivation or performing substrate bias control using an external power supply voltage and a step-down voltage.

  In designing a semiconductor integrated circuit having the regulator, the regulator has a width approximately equal to a width determined by the layout of the buffer, and includes a pad electrode that receives the first power supply voltage and a pad electrode that receives the ground voltage of the circuit. In this case, if a regulator selected from the cell library according to the supply current required for the first internal circuit is arranged, such a semiconductor integrated circuit can be designed relatively easily. Is possible.

It is explanatory drawing which shows an example of the semiconductor integrated circuit which concerns on this invention. It is a circuit diagram which shows an example of a series regulator. It is a circuit diagram which illustrates the differential amplifier which constitutes a regulator. It is a layout pattern which illustrates the basic arrangement configuration of a series regulator. This is a layout pattern in which a series regulator is arranged in a chip corner portion. It is another layout pattern in which the series regulator is arranged in the chip corner portion. It is a layout pattern which illustrates the planar structure of a reference voltage wiring. It is a longitudinal cross-sectional view illustrating a cross-sectional structure in the vicinity of the reference voltage wiring. It is a layout pattern which illustrates the detail of the connection state of the series regulator and wiring in the 2nd field. It is a circuit diagram which illustrates the connection state of a regulator and a power supply pad. It is a circuit diagram which illustrates a power supply pad and a protection element connected to this. It is a circuit diagram which illustrates a buffer for signal output and a protection element connected to this. It is a circuit diagram which illustrates the buffer for signal inputs, and the protection element connected to this. It is a circuit diagram which illustrates a level conversion circuit etc. It is explanatory drawing which shows an example of the semiconductor integrated circuit which employ | adopted the series regulator which does not require a reference voltage generation circuit. It is explanatory drawing which shows an example of the semiconductor integrated circuit which enabled it to carry out activation / deactivation control of several series regulator separately. It is explanatory drawing which shows an example of the semiconductor integrated circuit which also mounted the series regulator with small current drive capability compared with others. It is explanatory drawing which shows an example of the semiconductor integrated circuit which used multiple types of internal power supply voltages. It is explanatory drawing which shows an example of the semiconductor integrated circuit which enabled external attachment of one stabilization capacity | capacitance to the semiconductor chip via the pad electrode. It is explanatory drawing which shows an example of the semiconductor integrated circuit which enabled external attachment of several stabilization capacity | capacitance to the semiconductor chip via the pad electrode. It is explanatory drawing which shows an example of the semiconductor integrated circuit which enabled circulation of the power supply trunk line for internal power supply voltages also outside the semiconductor chip. It is explanatory drawing which shows an example of the semiconductor integrated circuit which added the subseries regulator and the substrate bias control circuit. It is explanatory drawing which illustrates the operation mode of a semiconductor integrated circuit, and the activation / deactivation control aspect of a circuit. It is explanatory drawing which illustrates the board | substrate bias control aspect according to the operation state of a semiconductor integrated circuit. It is a circuit diagram which shows an example of a charge pump circuit. It is explanatory drawing which shows an example of the semiconductor integrated circuit incorporating the driver control circuit of the switching regulator. FIG. 27 is an explanatory diagram showing an example of a semiconductor integrated circuit having both the configurations of FIG. 22 and FIG. FIG. 28 is a block diagram mainly showing circuit connection and power supply connection in the configuration of FIG. It is a circuit diagram showing an example of a reference voltage generating circuit and a circuit for setting its trimming information. It is a circuit diagram which illustrates the composition for changing an internal power supply voltage according to the operating frequency of the internal circuit arranged in the 3rd field using a buffer for reference voltages. It is explanatory drawing which shows roughly the layout design method of a semiconductor integrated circuit. It is a layout pattern which shows an example of the circuit pattern prescribed | regulated by the data of the mask pattern of a series regulator. FIG. 33 is a circuit diagram specified by circuit connection data linked to the layout pattern of FIG. 32. FIG. 33 is an explanatory diagram of symbols specified by circuit symbol data linked to the layout pattern of FIG. 32. It is explanatory drawing which shows an example of the effect by area overhead reduction by the circuit structure of FIG. It is explanatory drawing which represented the concentrated type and distributed type of a series regulator as a separate semiconductor integrated circuit, respectively. It is explanatory drawing for illustrating the quantitative effect about suppression of an undesired voltage drop. It is explanatory drawing which shows another example of the semiconductor integrated circuit which concerns on this invention. It is a layout pattern which illustrates arrangement | positioning of a series regulator. It is a layout pattern which shows an example which has arrange | positioned the series regulator in the chip | corner corner part.

  FIG. 1 shows a first example of a semiconductor integrated circuit according to the present invention. In the semiconductor chip 10, a first region 1 for arranging a plurality of external terminals, for example, pad electrodes 20, related to input / output to / from the outside, such as signals and power supplies, is circulated. The second region 2 is in contact with the first region 1 and is a region for arranging a buffer and a protection element related to input / output of a signal or a power supply to / from the outside of the semiconductor chip 10. . The second region 2 circulates on the chip with a constant width substantially defined by the size of the buffer and the protection element related to input / output. In the third region 3, an internal circuit that operates at an internal power supply voltage Vint lower than a first power supply voltage (also simply referred to as an external power supply voltage) Vext as an external power supply voltage used for an interface between the semiconductor chips 10 is arranged. It is an area for. The fourth area 4 is an area where an internal circuit using the external power supply voltage Vext is arranged.

  In order to reduce the overhead of the chip occupation area due to the on-chip step-down power supply circuit, a plurality of regulators 150 to 157 are arranged using the second region 2. Here, the second region 2 is a region where buffers and protection elements related to input / output are exclusively arranged, and is originally a region having a large gap (vacant space) compared to the third region and the fourth region. is there. In this example, the plurality of regulators 150 to 157 are series regulators, which are also referred to as series regulators 150 to 157. The series regulators 150 to 157 receive the reference potential generated by the reference voltage generation circuit 60 in the fourth region 4 through the reference voltage wiring L10, and supply the internal voltage defined by the reference potential to the power supply wiring, for example, the power supply trunk line Output to L20. The reference potential wiring L10 only needs to be arranged in the second region 2 or in the vicinity of the boundary thereof.

  The reference voltage wiring L10 is an open loop in which one part on the wiring is cut. Thereby, the antenna effect of a reference voltage wiring can be suppressed. The series regulators 150 to 157 step down the power supply voltage Vext supplied from the outside of the chip based on the voltage defined by the reference voltage generation circuit 60 and generate the internal power supply voltage Vint. The internal power supply voltage Vint is supplied to the internal circuit in the third region 3 by the power supply trunk line L20 that circulates in the second region 2 or in the vicinity of the boundary thereof. The series regulators 150 to 157 are activated or deactivated by a control signal S1 supplied from the control circuit 70 disposed in the fourth region 4. In FIG. 1, one supply path of the external power supply voltage Vext to the electrode pad and the circuit ground voltage Vss is representatively shown.

  In the example of FIG. 1, parasitic resistances between 150 to 157 output coupling points of the regulator on the power supply trunk line L20 are made approximately equal to each other. For example, the distance between the output coupling points of the regulators 150 to 157 on the power supply trunk line L20 is approximately equal to each other. As a result, the level of the internal power supply voltage is made more uniform on the power supply trunk line L20.

  FIG. 2 shows an example of the series regulator 150. Other series regulators 151 to 157 have the same circuit configuration. The series regulator 150 includes a differential amplifier 41 and a driver MOS transistor 40 as illustrated in FIGS. 2A and 2B. The driver MOS transistor 40 includes a p-channel MOS transistor having a source connected to the external power supply voltage Vext and a drain connected to the power supply trunk line L20 in (A), and a drain connected to the external power supply voltage Vext in (B). And an n-channel MOS transistor whose source is connected to the power supply trunk line L20. In (A) and (B), the differential amplifier 41 has a non-inverting input terminal A2, an inverting input terminal A1, and an output terminal G1, the non-inverting input terminal is on the power supply trunk line L20, and the inverting input terminal is on the reference voltage line L10. The output terminal is connected to the gate of the driver MOS transistor. The differential amplifier 41 is controlled to be activated / deactivated by a signal S1. When the differential amplifier 41 is deactivated, the output terminal G1 is reset to a high level (“1”) in the case of (A) and to a low level (“0”) in the case of (B). Then, the driver MOS transistor 40 is cut off.

  FIG. 3 illustrates the differential amplifier. The differential amplifier 41 illustrated in FIG. 2A corresponds to the circuit configuration of FIG. According to FIG. 3A, in the differential amplifier 41, a current mirror load composed of p-channel MOS transistors T3 and T4 is connected to n-channel differential input MOS transistors T6 and T5. An n-channel power switch MOS transistor T8 constituting a constant current source is connected to the common source of the MOS transistors T5 and T6, and is switch-controlled by a signal S1. The source of a p-channel pull-up MOS transistor T9 that is switch-controlled by the signal S1 is coupled to the common drain of the MOS transistors T3 and T6, and this source serves as the output terminal G1. The differential amplifier 41 is activated by the high level of the signal S1, is inactivated by the low level of the signal S1, and cuts off the driver MOS transistor 40 in the inactive state. Although not specifically shown, the differential amplifier 41 corresponding to FIG. 2B is different from the pull-up MOS transistor in FIG. 3A in that it is a pull-down MOS switch-controlled by an inverted signal to the signal S1. The difference is that a transistor is included.

  In FIG. 3A, the differential input MOS transistors T6 and T5 are of the enhancement type. In (B) showing another example of the differential amplifier 41, a depletion type is adopted for the MOS transistor T7 constituting the inverting input terminal A1. When using the enhancement type MOS transistor T6, it is necessary to apply the voltage defined by the reference voltage generation circuit 60 to the input terminal A1, but when using the depletion type MOS transistor T7, the input is simplified. By simply connecting the terminal A1 to the ground potential Vss, a desired level can be obtained at the output terminal G1, and the reference voltage generation circuit 60 need not be provided. However, in that case, the output voltage of the terminal G1 is accurately controlled, in other words, the conductance control of the driver MOS transistor 40, that is, the ability to accurately control the internal power supply voltage Vint is inferior.

  FIG. 4 shows a detailed arrangement example of the series regulator 150. Although not specifically shown, the other series regulators 152 to 157 are the same. In the vicinity of the power supply pad 20A in the second region 2, it is not necessary to arrange the buffers 30 and 31 related to input / output, and only the protection element 32 having a small layout area is arranged, so that it can be an empty region. It is. Focusing on this point, a plurality of power supply pads 20A are collectively arranged at several locations on the four sides of the semiconductor chip 10, and the series regulator 150 is arranged by utilizing empty areas that can be ensured thereby. Here, the power supply pad 20A includes an input pad electrode for the external power supply voltage Vext and a pad electrode for the circuit ground voltage Vss. The pad electrode indicated by 20B represents another pad electrode such as a signal.

  With this layout, even if the series regulator 150 is provided, it is not necessary to increase the chip area. In short, it is possible to reduce the area overhead for adding a series regulator. Since series regulator 150 uses power supply pad 20A in the vicinity thereof, external power supply voltage Vext is also prevented from undesirably dropping due to wiring resistance and parasitic capacitance between series regulator 150 and power supply pad 20A.

  FIG. 5 shows another arrangement example of the series regulator 150. For example, when pad electrodes are not arranged in the vicinity of the four corners of the semiconductor chip 10, there are empty areas on the second region 2 located at the four corners of the semiconductor chip 10. The series regulator 150 is disposed here. The power supply pad 20A used by the series regulator 150 assigns the pad electrode near the series regulator 150 as the power supply pad 20A on both sides of two sides intersecting at the four corners of the semiconductor chip 10. By adopting this arrangement method, not only the vacant area in the vicinity of the power supply pad 20A but also the vacant areas generated by not arranging the pad electrodes in the vicinity of the four corners of the semiconductor chip 10 can be used for the arrangement of the series regulator 150. it can. Regarding the other series regulators 152 to 157, the layout similar to that of FIG. 5 can be adopted for some series regulators, and the rest can be laid out in the form of FIG.

  FIG. 6 shows still another arrangement example of the series regulator 150. When pad electrodes are not arranged in the vicinity of the four corners of the semiconductor chip 10, the series regulator 150 is arranged in an empty area that can be secured in the second area 2 at the four corners of the semiconductor chip 10, and the power source used by the series regulator 150 The pad 20 </ b> A is assigned to one of the two pad electrodes intersecting at the four corners of the semiconductor chip 10.

  FIG. 7 illustrates a layout of the reference voltage wiring L10. The reference voltage line L10 is placed near the second region 2 or its boundary. The shield wiring L30 connected to the ground potential Vss is provided on both sides in parallel with the reference voltage wiring L10, in other words, in the same wiring layer. Since the reference voltage wiring L10 transmits a voltage serving as a reference for the internal power supply voltage Vint, it is necessary to reduce the influence of crosstalk noise and the like, and the shield wiring L30 is effective in reducing this noise.

  FIG. 8 illustrates a cross-sectional structure near the reference voltage wiring L10. In the example of FIG. 7, the shield lines L30 are arranged on both sides along the reference voltage line L10. However, in order to further improve the noise reduction effect, the shield line L31 is formed using the upper layer wiring layer above the reference voltage line L10. A well WELL as a shield region is formed in the lower substrate SUB. The shield wiring L31 and the well WELL are made conductive to the ground potential Vss similarly to the shield wiring L30. Although not particularly illustrated, when the reference voltage wiring L10 is formed in the second or higher metal wiring layer, a shield wiring formed in the lower wiring layer may be used instead of the well WELL. Note that INS means an interlayer insulating layer.

  FIG. 9 illustrates details of the connection state between the series regulator and the wiring in the second region 2. 10 to 13 illustrate the circuit configurations of the respective units in FIG.

  As is clear from FIG. 10, the power supply pad 20A connected to the regulator 150 has an input terminal 20A-1 for the external power supply voltage Vext, an input terminal 20A-3 for the circuit ground voltage Vss, and a connection terminal 20A- for the power supply trunk line L20. The function as 2 is assigned. The connection terminal 20A-2 can be used, for example, to connect a stabilizing capacitor externally. Such a connection terminal 20A-2 does not have to be provided for each series regulator, and only one connection terminal 20A-2 may be provided in the semiconductor integrated circuit.

  A protection element 32a is coupled to each power supply pad 20A. The protection element 32a is not particularly limited, but as illustrated in FIG. 11, a high breakdown voltage n-channel MOS transistor whose gate is connected to the ground potential Vss and a high voltage whose gate is connected to the external power supply potential Vext. These p-channel MOS transistors have a withstand voltage. These MOS transistors are in a reverse connection state during normal operation, and when an excessive negative voltage surge is applied to the pad electrode 20A, the n-channel high withstand voltage MOS transistor When the forward connection state is reached and the surge is released to the ground potential Vss and an excessive positive voltage surge is applied to the pad electrode 20A, the p-channel type high voltage MOS transistor is in the forward connection state and the surge is externally supplied. Release to voltage Vext.

  The signal output pad electrode 20Bb and the signal input pad electrode 20Ba are also composed of a diode-connected p-channel high-voltage MOS transistor and n-channel high-voltage MOS transistor as illustrated in FIGS. A protection element 32b is provided.

  Although not particularly shown, the second region 2 is provided with a power supply trunk line of the external power supply voltage Vext and a power supply trunk line of the ground potential, and operates in the input buffer 31 and the output buffer 30 etc. arranged in the second region. Power is supplied.

  As illustrated in FIG. 13, when signals are transferred between a circuit that operates at the external power supply voltage Vext and a circuit that operates at the internal power supply voltage Vint, signal input from the former to the latter may be performed as it is. According to the example of FIG. 13, the gate circuit G1 using the internal power supply voltage Vint as the operation power supply in the third region 3 can operate by receiving the output of the input buffer 31 as it is.

  On the other hand, when a signal is supplied from a circuit operating at the internal power supply voltage Vint to a circuit operating at the external power supply voltage Vext, the latter circuit inputs a signal having a smaller amplitude than that of the operating power supply. There is a possibility that the logic level of the signal becomes an intermediate level and an undesirable through current is generated. In order to prevent such a risk, as illustrated in FIG. 12, the signal output from the gate G2 having the internal power supply voltage Vint as the operation power supply in the third region 3 is used as the external power supply voltage Vext. A level conversion circuit G3 that converts and outputs the signal amplitude defined in (4) is formed in the fourth region 4. In the example of FIG. 12, the output of the level conversion circuit G3 is given to the output buffer 30 in the second area 2.

  FIG. 14 shows an example of the level conversion circuit G3. The level conversion circuit G3 shown in the figure has n-channel differential input MOS transistors T10 and T11 that receive complementary signals from the gate G2 of the third region 3, and the drains of the transistors T10 and T11 are connected to each other. Are connected to the drains of p-channel load MOS transistors T12 and T13 whose one gate is cross-coupled to the other drain, and the common drains of the MOS transistors T11 and T13 are amplified by an inverter INV and output. The The output of the gate G4 in the fourth region 4 may be directly received by the gate G5 in the third region 3.

  FIG. 15 shows another example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure employs a configuration including the differential amplifier described in FIG. 3B as the series regulators 150 to 157. Thereby, it is not necessary to provide the reference voltage generation circuit 60 in the fourth region 4.

  FIG. 16 shows still another example of the semiconductor integrated circuit according to the present invention. In the figure, the control circuit 70 outputs individual activation / deactivation control signals S10 to S17 so that the series regulators 150 to 157 can be individually activated / deactivated. The control circuit 70 activates a required number of series regulators in accordance with a supply current required for the internal circuit. By activating only the necessary number of series regulators according to the supply current, it is possible to cut off the wasteful power supply. Such control can be performed by the control circuit 70 in accordance with, for example, mode setting from an external terminal of the semiconductor integrated circuit. Since other configurations are the same as those in FIG. 1, a detailed description thereof will be omitted.

  FIG. 17 shows still another example of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure has a plurality of series regulators 150 to 156 having the same current driving capability and a series regulator 158 having a current driving capability smaller than those current driving capabilities on the semiconductor chip 10. . The control signal S2 controls activation / deactivation of a plurality of series regulators 150 to 156 having the same driving ability. On the other hand, the series regulator 158 having a small driving capability is controlled to be activated / deactivated by the control signal S3. When a large current driving capability is required, the control circuit 70 includes only a plurality of series regulators 150 to 156 having a large current driving capability, or a series regulator 158 having a small current driving capability in addition to the series regulators 150 to 156. Activate. When a small current driving capability is sufficient, only the series regulator 158 having a small current driving capability is activated. Thus, for example, during standby set in response to the state of the external terminal of the semiconductor integrated circuit, the series regulator 158 is activated and the other series regulators 150 to 156 are deactivated to reduce wasteful power consumption. Can do.

  FIG. 18 shows still another example of the semiconductor integrated circuit according to the present invention. In the example of FIG. 18, the semiconductor chip 10 has several different internal power supply voltages supplied to the internal circuits arranged in the third region 3. If the internal power supply voltages are VintA and VintB, the series regulators that generate these voltages can be divided into groups A and B. For example, the group A series regulators 150A, 152A, 154A, and 156A that generate the internal power supply voltage VintA have the same current drive capability. On the other hand, the group B series regulators 151B, 153B, 155B, and 157B that generate the internal power supply voltage VintB have the same or different current drive capability as the group A series regulator. Group A series regulators 150A, 152A, 154A, 156A use reference voltage wiring L10A and power supply trunk L20A, and group B series regulators 151B, 153B, 155B, 157B use reference voltage wiring L10B and power supply trunk L20B. To do. The activation / deactivation control of the series regulator is performed in a batch for each group. For example, the series regulators 150A, 152A, 154A, and 156A of the group A are controlled by the control signal S18, and the activation / inactivation of the series regulators 151B, 153B, 155B, and 157B of the group B are controlled by the control signal S19. As a result, it is possible to use a mixture of internal circuits operating at several different internal power supply voltages in the semiconductor chip 10. Since other configurations are the same as those in FIG. 1, detailed description thereof is omitted.

  FIG. 19 shows still another example of the semiconductor integrated circuit according to the present invention. In the semiconductor integrated circuit shown in the figure, the power supply trunk line L20 is one stable externally attached to the semiconductor chip 10 via any one of the pad electrodes 20A-2 in the first region 1. Connected to the capacitor C10. Thereby, the fluctuation | variation and fall of the internal power supply voltage Vint on the power supply trunk line L20 are suppressed. Since other configurations are the same as those in FIG. 1, detailed description thereof is omitted.

  FIG. 20 shows still another example of the semiconductor integrated circuit according to the present invention. In the semiconductor integrated circuit shown in the figure, the power supply trunk line L20 is connected to the outside of the semiconductor chip via a plurality of, for example, two pad electrodes 20A-2a and 20A-2b in the pad electrode 20 in the first region 1. Are connected to the stabilization capacitors C10a and C10b. As a result, the internal power supply voltage Vint can be further stabilized.

  FIG. 21 shows still another example of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure can circulate the power supply trunk line L21 for the internal power supply voltage Vint not only inside the semiconductor chip 10 but also outside. That is, the power supply trunk line L20 is connected to the power supply trunk line L21 via a plurality of, for example, four 20A-2a, 20A-2b, 20A-2c, and 20A-2d of the pad electrodes 20 arranged in the first region 1. It is connected. At least one stabilizing capacitor C10 is connected to the power supply trunk line L21. The power supply trunk line L21 is formed inside a package of a semiconductor integrated circuit or formed on a mounting substrate on which the semiconductor integrated circuit is mounted. As a result, the internal power supply voltage Vint can be further stabilized.

  FIG. 22 shows still another example of the semiconductor integrated circuit according to the present invention. In the semiconductor integrated circuit shown in the figure, a sub-series regulator 80 with low self-consumption current and a substrate bias control circuit 71 for the third region 3 are added to the fourth region 4 in the configuration of FIG. The point is different. The voltage output terminal of the subseries regulator 80 is coupled to the power supply trunk line L20. The substrate bias control circuit 71 outputs the substrate voltage Vbp of the p-channel MOS transistor and the substrate voltage Vbn of the n-channel MOS transistor. The substrate voltage in the region other than the third region is not particularly limited, but the p-channel MOS transistor is set to the power supply voltage and the n-channel MOS transistor is set to the circuit ground voltage, and is not particularly substrate biased.

  The operation mode of the semiconductor integrated circuit of FIG. 22 is not particularly limited, but considering the operation of the internal circuit arranged in the third region 3, as illustrated in FIG. 23, the active mode, standby mode, data Consider four states: holding mode (sleep mode) and shutdown.

  The active mode is an operation mode that enables the semiconductor integrated circuit to operate with the maximum capability. In the active mode, the reference voltage generation circuit 60 and the plurality of series regulators 150 to 157 are activated, and the substrate bias control by the small series regulator 80 and the substrate bias control circuit 71 is deactivated. For example, in this state, the substrate potential of the p-channel MOS transistor in the third region is set to the internal power supply voltage Vint, and the substrate potential of the n-channel MOS transistor is set to the circuit ground voltage Vss.

  The standby mode is a low power consumption mode, and is an operation mode that can respond to a minimum required request such as acceptance of an interrupt. In the standby mode, the reference voltage generation circuit 60 and the subseries regulator 80 are activated, and the plurality of series regulators 150 to 157 are deactivated. By switching the series regulator, the self-current consumption of the series regulator is reduced. Further, the substrate bias control by the substrate bias control circuit 71 is activated, and substrate bias voltages are applied as the substrate potentials Vbp and Vbn of the internal circuit in the third region 3. Here, the substrate bias control for the purpose of low power consumption is performed, and a reverse substrate bias is applied so that the threshold voltage of the MOS transistor is increased. For example, the external power supply voltage Vext is applied as the substrate voltage Vbp of the p-channel MOS transistor, and the negative potential with respect to the circuit ground potential Vss is applied as the substrate voltage Vbn of the n-channel MOS transistor. The negative potential is generated by a charge pump circuit in the substrate bias control circuit 71, for example. Thereby, in the standby mode, the subthreshold leakage current in the internal circuit of the third region 3 can be reduced.

  The data holding mode is an operation for statically holding the internal state of the semiconductor integrated circuit. In this data retention mode, the subthreshold leakage current can be further reduced by lowering the level of the internal power supply voltage Vint in addition to the switching of the series regulator and the substrate bias control performed during standby.

  FIG. 24 shows the states of the substrate voltages Vbp and Vbn and the internal power supply voltage Vint that are used when the active mode, the standby mode, and the data holding mode are reached. As a circuit included in the third region 3, in a circuit such as a CMOS inverter, for example, the substrate voltage Vbp of the p-channel MOS transistor, the substrate voltage Vbn of the n-channel MOS transistor, and the internal power supply voltage Vint are changed as shown in FIG. Let When active, the substrate voltage Vbp is set to the internal voltage Vint, and the substrate voltage Vbn is set to the ground voltage Vss of the circuit so that no substrate bias is applied to the MOS transistor. During standby, the substrate voltage Vbp is set to the external voltage Vext, and the substrate voltage Vbn is set to a negative voltage such as −1.5V. At the time of data retention, the internal power supply voltage Vint is lowered, and in response to this, the substrate voltage of the n-channel MOS transistor is also changed to a negative voltage such as -2.3V. In the substrate voltage control according to the operation mode or operation state of the semiconductor integrated circuit, the external power supply voltage Vext is used as it is for the positive-side reverse bias substrate voltage, and only the negative-side reverse bias substrate voltage is used by the charge pump circuit. It only has to be generated. In short, it is not necessary to input a dedicated voltage from the outside of the semiconductor integrated circuit for substrate bias control.

  The negative substrate voltage can be generated by the charge pump circuit of FIG. In this charge pump circuit, by operating the ring oscillator 72, a clock signal having an opposite phase is supplied to the gates of the MOS capacitors T20 and T21, and the transistor is driven by the charge pump action of the p-channel MOS transistors T22 to T25 synchronized therewith. A negative voltage can be obtained at the junction of T22 and T23. The negative voltage at this time can be lowered to −Vint + Vth1 + Vth2 (Vth1: threshold voltage of T22, Vth2: threshold voltage of T23). When multiple types of negative voltages are required, negative feedback control may be performed on the oscillation operation or the oscillation frequency of the ring oscillator so that the negative voltage becomes the target voltage. As a result, the substrate bias voltage Vbn of −1.5 V during standby and the substrate bias voltage Vbn of −2.3 V during data retention illustrated in FIG. 24 can be obtained.

  At the time of shutdown, the reference voltage generation circuit 60, the series regulators 150 to 157, the subseries regulator 80, and the substrate bias control circuit 71 are deactivated. Activation / deactivation of the series regulators 150 to 157 is selected by the control signal S1, activation / deactivation of the small series regulator 80 is selected by using the control signal S4, and activation / deactivation control of the substrate bias control circuit 71 is performed. This is performed by the control signal S8.

  FIG. 26 shows still another example of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure is different from FIG. 1 in that a switching regulator driver control circuit 90 is arranged in the fourth region 4 of the semiconductor chip 10. The driver control circuit 90 generates a square wave from the external power supply voltage Vext by driving the external parts outside the semiconductor chip 10, for example, the gates of the driver MOS transistors PM1 and PM2 made of power MOS transistors. Is supplied to an internal circuit arranged in the third region 3 through a low-pass filter composed of external components such as an inductance L1, a capacitor C1, and a Schottky diode D1. Only the driver control circuit 90 of the switching regulator is on-chip, and if it is on-chip, a driver MOS transistor or the like that occupies a large layout area is used as an external component, so that switching can be performed while incorporating the series regulators 150 to 157. Despite the fact that regulators can be easily selected, there is no significant area overhead. Further, when the driver MOS transistor is made on-chip, the pad electrodes of the three power supplies Vext, Vint, and Vss must be increased as a set in accordance with the current supplied to the internal circuit. Although a pad is required, the problem can be avoided by configuring the driver MOS transistor with an external component. The electrode pads 20B-1 and 20B-2 are output pad electrodes for switching control signals GS1 and GS2 of the driver MOS transistor, and the electrode pad 20B-3 is a power supply pad for inputting an internal voltage Vint generated by an external switching regulator. .

  The activation control of the series regulators 150 to 157 and the driver control circuit 90 is performed by the control circuit 70 using the control signals S1 and S5. However, when using this semiconductor integrated circuit, generally only one of the regulators is used. Therefore, either one of the control signals S1 and S5 may be fixed to the inactivation level. As such deactivation control means, an electric fuse program circuit, a laser fuse program circuit, or a flash memory fuse using a nonvolatile memory cell in the control circuit 70 may be used.

  FIG. 27 shows still another example of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure is an example in which the configurations of FIGS. 22 and 26 are combined. The semiconductor chip 10 includes a sub-series regulator 80 used during standby, a substrate bias control circuit 71, and a driver control circuit 90 for a switching regulator. Here, as a specific example of the third area 3, a CPU 120, a register 130, a nonvolatile memory 135, and other peripheral circuits 140 are illustrated. For the nonvolatile memory 135, an electric fuse, a flash memory, or the like is used. S50 exemplifies signals input / output by the peripheral circuit 140 and the CPU 120, S51 means a signal output from the register 130, S52 means a signal output from the non-volatile memory 135, and S20 indicates a signal to the control circuit 70. Indicates the output signal. L50 is a generic name for the supply lines for the substrate voltages Vbn and Vbp output from the substrate bias control circuit 71.

  In the example of FIG. 27, the use of the switching regulator is selected, and the use of the built-in series regulators 150 to 157, 80 is not selected. When using the series regulators 150 to 157, 80, the connection of the power MOS transistors PM1, PM2 to the electrode pads 20B-1, 20B-2 is stopped, and instead, the stabilization capacitor C10 is connected to the electrode pad 20A-2a. do it.

  FIG. 28 shows the configuration of FIG. 27 mainly for circuit connection and power supply connection. The reference voltage generation circuit 60 is divided into a reference voltage generation circuit 100 and a reference voltage buffer 110. A circuit that operates with the external power supply voltage Vext for the voltage includes a control circuit 70, a substrate bias control circuit 71, a reference voltage generation circuit 100, a reference voltage generation circuit 110, a standby subseries regulator 80, series regulators 150 to 157, input The output buffers 30 and 31, the protection element 32, and the driver control circuit 90 for the switching regulator. On the other hand, circuits that operate with the internal power supply voltage Vint are the CPU 120, the register 130, the nonvolatile memory 135, and other peripheral circuits 140.

  The control signal S1 is a signal for controlling activation / deactivation of the series regulators 150 to 157. The control signal S4 is a signal for controlling the activation / deactivation of the subseries regulator 80 for standby. The control signal S5 is a signal for selecting activation / deactivation of the driver control circuit 90 of the switching regulator. The control signal S6 is a signal for controlling the activation / deactivation of the reference voltage generation circuit 100. The control signal S7 is a signal for controlling the activation / deactivation of the reference voltage buffer 110. The control signal S8 is a signal for controlling the activation / deactivation of the substrate bias control circuit 71. The control signal S20 is a signal for the CPU 120 to control the control circuit 70. The control signal S22 is a signal for switching the level of the output voltage of the reference voltage buffer 110. The control signal S21 is a signal for switching the level of the output voltage of the reference voltage generation circuit 100. S53 means an input / output signal between the CPU 120 and the buffers 30 and 31.

  FIG. 29 shows an example of the reference voltage generation circuit 100 and a circuit for setting the trimming information thereof. The reference voltage generation circuit 100 of FIG. 29 is an example using a band gap reference circuit. In this circuit, bipolar transistors B2 and B3 having different Vbe are used, and the difference between them is compensated by the current and the resistor R14, so that the current paths of the MOS transistors T38 and T39, the resistors R10, R11 and R12, and the bipolar transistor B1 A predetermined current is passed to form a reference voltage. Each pair of MOS transistors T36 and T37, MOS transistors T40 and T41, and MOS transistors T42 and T43 constitute a current mirror load. In the reference voltage generation circuit 100, the reference voltage can be selected by the CMOS transfer gates SW0 to SW2 in order to cancel the influence of process variations, that is, to enable trimming. The selection control can be performed by the control circuit 70 using the selection signals S21a, S21b, S21c. The trimming information for selection is held in the nonvolatile memory 135. For example, as part of the reset process, the trimming information is loaded from the nonvolatile memory 135 into the register 130 by the signal S52, and the output of the register 130 is controlled by the signal S51. Trimming is performed according to the above.

  The trimming operation will be described in further detail. For example, before setting the output voltage, only the switch SW1 is turned on by the control signal S21b, and the output voltage is made equal to the voltage V1. The output voltage V1 is transmitted to the reference voltage buffer 110 via the wiring L40. When the reference voltage generating circuit 100 performs a normal operation, the voltage having the lowest temperature dependency is theoretically defined. Therefore, if this voltage is used as a reference, the level of the voltage V1 is due to manufacturing variation or the like. Is higher than this reference voltage, when a control signal is supplied to the control circuit 70 from the outside of the chip, only the switch SW2 is turned on by the control signal S21c, and the output voltage level is set to the voltage V2 lower than the voltage V1. Switch to. Further, when the level of the voltage V1 is lower than this reference voltage due to manufacturing variation or the like, similarly, a control signal is given from the outside of the chip to the control circuit 70, and only the switch SW0 is turned on by the control signal S21a. The output voltage level is switched to a voltage V0 higher than the voltage V1. Next, the non-volatile memory 135 holds the set value in which the deviation due to the manufacturing variation of the output voltage is corrected, and the next time the power is turned on, the data is read from the non-volatile memory 135 to the register 130 and the value is set. Accordingly, one of the switches SW0 to SW2 can be selected.

  FIG. 30 illustrates a configuration for switching the internal power supply voltage Vint according to the operating frequency of the internal circuit arranged in the third region 3 using the reference voltage buffer 110.

  The reference voltage buffer 110 includes a voltage dividing circuit composed of a series circuit of a p-channel MOS transistor T44 and resistors R20 to R24 and a differential amplifier AMP. The differential amplifier AMP is a component for the output voltage of the reference voltage generating circuit 100. An amplifying operation corresponding to the voltage difference at the node V12 of the voltage circuit is performed to control the conductance of the MOS transistor T44. One of the voltages of the nodes V10, V11, and V12 of the voltage dividing circuit is selected by the switches SW10, SW11, and SW12 and is output to the signal line L10-a. The voltages of the nodes V12, V13, and V14 are switched by the switches SW20, SW21, and SW22. One is selected and output to the signal line L10-b. The selection control signals for the switches SW10 to SW12 and SW20 to SW22 are S22a to S22f and are output from the control circuit 70 in accordance with instructions from the CPU 120. In this example, the reference potential wiring L10 is divided into two systems L10-a and L10-b.

  The output voltage of the reference voltage generation circuit 60 is used not only as a reference voltage for series regulators such as the series regulators 150 to 157 and the subseries regulator 80 with low self-current consumption, but also as a reference for the driver control circuit 90 of the switching regulator. Also used as a voltage. Although not particularly limited, the former is the voltage of the signal line L10-a, and the latter is the voltage of the signal line L10-b. When the voltages of the signal lines L10-a and L10-b are changed, the output voltage by the series regulator or the switching regulator is also changed according to the voltage level.

  For example, before the voltage variable control by the reference voltage buffer 110, the switch SW11 is turned on by the control signal S22b, and the output voltage level on the wiring L10-a is equal to the voltage V11. On the other hand, the output voltage level on the wiring L10-b is turned on by the control signal S22e and becomes equal to the voltage V13. If the CPU 120 operates at a low speed, the switches SW12 and SW22 are turned on by the control signals S22c and S22f, the output voltage level on the wiring L11 is switched to the voltage V12 lower than the voltage V11, and the output voltage level on the wiring L12. Is switched to a voltage V14 lower than the voltage V13. When the CPU 120 operates at high speed, the switches SW10 and SW20 are turned on by the control signals S22a and S22d, the output voltage level on the wiring L11 is switched to the voltage V10 higher than the voltage V11, and the output voltage level on the wiring L12. Is switched to a voltage V12 higher than the voltage V13. With this method, it is possible to reduce power consumption according to the operating state of the CPU 120. Note that the level of the output voltage can be switched in more stages.

  FIG. 31 shows an outline of the layout design method of the semiconductor integrated circuit. In the layout design of a semiconductor integrated circuit, an approximate arrangement of circuit blocks is determined by a floor plan (S1), and then a layout of a circuit pattern for realizing a logically designed function is referred to with reference to the floor plan. The layout design to be determined is performed (S2). Layout verification is performed on the layout design result (S3).

  In layout design, efficiency can be improved by using verified circuit pattern or mask pattern data registered in the macro cell library LBR. The macro cell library LBR includes a digital circuit library DGT, an analog circuit library ALG, and the like. The analog circuit library ALG includes a plurality of types of circuit layout data CKT for step-down power supply circuits such as the series regulators 150 to 157. Yes.

  In designing a semiconductor integrated circuit having the regulators 150 to 157, the regulators 150 to 157 have a width approximately equal to the width determined by the layout of the buffer 30, and the pad electrodes that receive the first power supply voltage Vext and the ground of the circuit. A step of arranging in the vicinity of the pad electrode that receives the voltage Vss may be included in the layout design (S2). In this step, if the regulator selected from the cell library LBR according to the supply current required for the first internal circuit in the third region 3 is arranged, the layout design of the step-down power supply circuit can be performed relatively easily. Is possible.

  FIG. 32 illustrates a circuit pattern PTN of a series regulator as an example of a circuit pattern defined by the layout data (that is, mask pattern data) of the step-down power supply circuit. The layout data of the circuit pattern PTN is linked with the circuit connection data CNTD shown in FIG. 33 and the circuit symbol data SBLD shown in FIG. 34 in one-to-one correspondence. That is, information such as connection and MOS size is shared among these three types of electronic data PTN, CNTD, and SBLD. In the drawing, the patterns shown in FIG. 32 correspond to the circuit shown in FIG. 33 according to symbols T50 to T56 attached to the MOS transistors, signals A1 and E1, and voltages Vext, Vint and Vss. The circuit shown in FIG. 33 and the symbol shown in FIG. It is supported. By utilizing such electronic data, circuit design and layout design of the step-down power supply circuit can be easily performed, and information management is also facilitated.

  FIG. 38 shows still another example of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in the figure includes a plurality of series regulators 300 to 306 having an equivalent current driving capability and a series regulator 150 having an equivalent current driving capability. As a modification of this aspect, a configuration may be adopted in which a plurality of series regulators 150 are arranged or not arranged at all.

  FIG. 39 shows a detailed example of the series regulator 300. Although not specifically shown, the other series regulators 301 to 306 may be configured in the same manner. The series regulator 300 includes a driver transistor 40 and an amplifier 41. In the arrangement of the series regulator 150 described with reference to FIG. 4, the driver transistor 40 and the amplifier 41 are arranged in an area (outer area of the second area 2) in which the buffers 30 and 31 related to input / output are arranged. Therefore, it is necessary to arrange the power supply pads 20A in the vicinity thereof. In the example of FIG. 39, the area where the buffers 30 and 31 are arranged (the first circuit area located outside the second area 2) includes an area where only the amplifier 41 can be arranged in the series regulator 300. It's enough. The driver transistor 40 is arranged in a region inside that region (an inner region in the second region 2). Thereby, the freedom degree with respect to arrangement | positioning of the series regulators 300-306 increases. Note that the driver transistor may be electrically connected to a plurality of smaller transistors so as to have a constant driving capability as a whole.

  FIG. 40 shows another arrangement example of the series regulator 300. For example, when pad electrodes are not arranged near the four corners of the semiconductor chip 10, there are empty areas on the second region 2 located at the four corners of the semiconductor chip 10. The amplifier 41 of the series regulator 300 is arranged here. In the arrangement example of FIG. 40, the amplifiers 41 are arranged at the four corners of the area where the buffers 30 and 31 related to input / output are arranged. In this case, the driver transistor 40 can be bent instead of the linear arrangement described with reference to FIG. For other series regulators, the same layout as in FIG. 40 can be adopted, and the rest can be laid out in the same form as in FIG.

  As is clear from the above description, in an LSI having an internal circuit that operates at an internal power supply voltage Vint lower than the power supply voltage Vext used for the interface between chips, a regulator that generates the internal power supply voltage Vint is provided with a buffer and protection. By arranging using the region for arranging the elements, the area overhead due to the on-chip implementation of the step-down power supply circuit can be reduced.

Illustrates the quantitative effect of reducing area overhead. FIG. 35 shows the effect of area overhead reduction by the circuit configuration of FIG. In FIG. 35, the area overhead of the series regulators 150 to 157 is eliminated in the semiconductor integrated circuit of FIG. 1 compared to before the area overhead is reduced without forming the series regulator in the second region 2. For example, the increase in chip area Can be reduced from 0.63 mm ² to 0.34 mm ² .

  Illustrate the quantitative effect of suppressing unwanted voltage drop. FIG. 36A illustrates a concentrated type semiconductor integrated circuit in which one series regulator 200 having sufficient current supply capability for driving the semiconductor chip 10 is arranged, and FIG. 1 illustrates a distributed type semiconductor integrated circuit in which a plurality of series regulators are distributed as shown in FIG. Further, the sum of the driving capabilities of the plurality of series regulators is comparable to, or at least equivalent to, the driving capability of the series regulator 200. FIG. 37 shows the maximum drop of the internal power supply voltage Vint that appears on the power supply trunk line L20 when the sums of the currents I1 to I7 to be supplied to the internal circuits arranged in the third region 3 of the semiconductor integrated circuit of FIG. showed that. In this example, the target voltage of the internal power supply voltage Vint is 1.8V. In FIG. 37, for example, when the current supplied to the internal circuit is 200 mA, the drop of the internal power supply voltage Vint is about 0.1 V in the distributed type in FIG. 36B, but the concentrated type in FIG. In this case, the internal power supply voltage Vint drops about 0.7V. Therefore, by adopting a configuration in which a plurality of series regulators are arranged at almost equal intervals on the circulating power line L20 as illustrated in FIG. 1, the internal power supply voltage Vint can be obtained even when the required amount of current is large. Can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the number of series regulators, the circuit configuration, the functions of specific circuits formed in the third region, and the like are not limited to the above example, and can be changed as appropriate. The present invention is not limited to a microcomputer or a microprocessor having a CPU, but can be applied to various semiconductor integrated circuits such as a communication protocol controller and an accelerator specialized for error correction. The electrode pad is not limited to the bonding pad, and may be a pad electrode for a bump electrode used for a chip size package or the like. Furthermore, the region where the pad electrode, the buffer, and the like are disposed is not limited to the peripheral portion of the semiconductor chip, but may be the central portion or the like.

  In terms of low power consumption, the semiconductor integrated circuit of the present invention is optimal for a portable information terminal such as a cellular phone, but is not limited thereto and can be widely applied to various types of logic LSIs.

DESCRIPTION OF SYMBOLS 1 1st area | region 2 2nd area | region 3 3rd area | region 4 4th area | region 10 Semiconductor chip 20 Pad electrode 20A Series regulator utilization power supply pad 20A-1 Vext input terminal 20A-2, 20A-2a, 20A- 2b Power supply main line connection terminal C10, C10a, C10b Stabilization capacitor 20A-3 Vss input terminal 20B-1, 20B-2 Switching regulator control signal output terminal 20B-3 Vint input terminal from switching regulator Vint, VintA, VintB Inside Power supply voltage Vext External power supply voltage Vss Circuit ground voltage 30, 31 Buffer 32, 32a, 32b Protection element 40 Driver MOS transistor 41 Differential amplifier 60 Reference voltage generation circuit L10, L10a, L10b Reference potential wiring L20, L20A, L 0B Power supply trunk line L21 Off-chip power supply trunk line L30, L31 Shield wiring WELL Shield well region G1, G2, G5 Third region gate circuit G3 Level conversion circuit G4 Fourth region gate circuit 70 Control circuit 71 Substrate bias control circuit 80 Subseries regulator 150 to 157 Series regulator 158 Series regulator with low quiescent current 150A, 152A, 154A, 156A Series regulator 151B, 153B, 155B, 157B Series regulator 90 Switching regulator driver control circuit 100 Reference voltage generation circuit 110 For reference voltage Buffer 120 CPU
130 Register 135 Nonvolatile memory

Claims (9)

To semiconductor chip,
A plurality of regulators arranged on the semiconductor chip, supplied with an external power supply voltage, and generating an internal power supply lower than the external power supply voltage ;
A control circuit that is supplied with the external power supply voltage and controls operations of the plurality of regulators;
An internal circuit to which the internal power is supplied,
The plurality of regulators are arranged in an I / O portion of the semiconductor chip,
The control circuit, the plurality of regulators is operable to generate a supply current necessary for the internal circuit,
The control circuit outputs a plurality of control signals to the plurality of regulators,
The semiconductor integrated circuit, wherein operations of the plurality of regulators are controlled in accordance with the plurality of control signals. 2. The semiconductor integrated circuit according to claim 1 , wherein the control circuit controls operations of the plurality of regulators in accordance with mode setting from an external terminal . The plurality of regulators include a differential amplifier and a driver MOS transistor whose outputs are connected to a common power supply line to the internal circuit,
One of the plurality of control signals is input to the differential amplifier, and on or off of the driver MOS transistor is controlled according to one of the plurality of control signals. Item 14. A semiconductor integrated circuit according to Item 1. 2. The semiconductor integrated circuit according to claim 1, wherein outputs of the plurality of regulators are connected to a common power supply line that supplies the internal power to the internal circuit. A first region in which a plurality of terminals used for connection to the outside are arranged on a semiconductor chip;
The buffer and the protection circuit is connected to the terminal disposed, and a plurality of regulator to step down the first lower than this power supply voltage of at least one of the internal power supply voltage to be externally et subjected sheet is placed Two regions,
A third region in which a first internal circuit that operates in response to the internal power supply voltage is disposed; and a fourth region in which a second internal circuit that uses the first power supply voltage is disposed;
The regulator is disposed in the vicinity of a first power supply terminal that receives the first power supply voltage and a ground power supply terminal that receives a ground voltage , among the terminals.
A power line for connecting the outputs of the plurality of regulators to supply the internal power supply voltage to the first internal circuit;
The power line is disposed and included in the second region, and is connected to an internal power terminal included in the terminal ,
The semiconductor device, wherein the internal power supply terminal is disposed between the first power supply terminal and the ground power supply terminal .   6. The semiconductor device according to claim 5, wherein the power supply line is formed in a closed loop shape. 6. The semiconductor device according to claim 5, wherein a stabilizing capacitor is connected to the internal power supply terminal. 6. The semiconductor device according to claim 5, wherein the internal power supply terminal is disposed in the vicinity of the regulator.   6. The semiconductor device according to claim 5, wherein the regulator is a series regulator.

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