JP5667926B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a trench gate structure.

  For example, as a substrate material used for a power semiconductor element that controls a high breakdown voltage and a large current, a silicon wafer has been conventionally used in many cases. An example of a power semiconductor element using a silicon wafer as a substrate is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Such a MOSFET can be used as a high-speed switching element up to several MHz although it has a high breakdown voltage and a large loss.

  However, in recent years, MOSFETs having both a large current and a high-speed switching property have been demanded. In order to realize a MOSFET having such a large current and high-speed switching property, silicon carbide (SiC) is used as a substrate material for the MOSFET. SiC is a chemically very stable material, has a wide band gap, and has excellent characteristics that it is extremely stable as a semiconductor even in a high temperature environment. SiC also has an excellent feature that the maximum electric field strength that causes avalanche breakdown in the semiconductor substrate is 10 times or more larger than Si.

  As an example of a semiconductor element using SiC, there is a MOSFET having a trench structure (see, for example, Patent Document 1). In such a MOSFET having a trench structure, it is necessary to make the gate trench sufficiently protected by the protection trench so that an excessive electric field is not applied to the gate trench and destroyed.

  FIG. 6 shows an example of a formation pattern of a protection trench and a gate trench in a MOSFET having a trench structure using a conventional SiC substrate. In the trench formation pattern shown in FIG. 6, a plurality of gate trenches 101 are arranged in parallel with each other on one main surface side 100a of the semiconductor substrate 100 made of SiC. A protection trench 102 having a rectangular ring shape is formed so as to surround every other gate trench 101.

JP 2007-194283 A

  However, in the MOSFET having the conventional trench structure as described above, the distance between the protection trench and the gate trench is not constant. That is, in the example shown in FIG. 6, the distance between the protection trench 102 and the gate trench 101 is different between n1 and n2. For this reason, there is a concern that an excessive electric field is applied to a portion where the distance between the gate trench and the protection trench is wide and the gate trench 101 is locally destroyed.

  The present invention has been made in view of the above problems, and provides a semiconductor element having a trench structure capable of preventing electric field concentration on a specific portion of a gate trench and improving breakdown voltage. Objective.

In order to solve the above problems, some embodiments of the present invention provide the following semiconductor device.
That is, a semiconductor element of the present invention includes a first conductivity type semiconductor substrate made of silicon carbide, a first conductivity type drift layer formed on one main surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, A second conductivity type base layer having an impurity concentration higher than that of the drift layer; a first conductivity type source region selectively disposed on a surface layer of the base layer; and a gate trench in which a gate is embedded. A first trench having a depth reaching the drift layer from a main surface of the source region , and a Schottky barrier trench having an anode electrode formed therein, the depth reaching the drift layer and the first trench comprising at least, a deep second trenches than said at one main surface side of the semiconductor substrate, the first trench and the second trench, at a predetermined distance from each other Characterized by being formed so that the annular pattern surrounding each other.

  The first trench and the second trench are formed on one main surface of the semiconductor substrate so as to have an annular pattern approximating a crystal structure of silicon carbide constituting the semiconductor substrate.

  The first trench and the second trench are formed so that all the widths along one main surface of the semiconductor substrate are the same.

  The silicon carbide constituting the semiconductor substrate has a crystal structure that forms a hexagonal crystal, and the first trench and the second trench are formed to have a hexagonal shape when the one main surface side is viewed in plan view. Features.

  The outer shape of the semiconductor substrate is a rhombus composed of four sides parallel to four of the six sides forming the hexagon.

  The silicon carbide constituting the semiconductor substrate has a cubic crystal structure, and the first trench and the second trench are formed to have a quadrangle when the one main surface side is viewed in plan view. And

  On the one main surface side of the semiconductor substrate, the first trench or the second trench arranged at the center is also the first trench or the second trench in the entire central region surrounded by the annular pattern. A trench is formed.

According to the semiconductor element of the present invention, in any portion of the first trench, a predetermined interval is maintained with respect to the adjacent second trench, and there is no portion where the width is narrower or wider than this. .
As a result, the electric field is uniformly distributed in any part between the first trench and the second trench, the electric field is not concentrated on the specific part, and an excessive electric field is applied to the specific part. It is possible to reliably prevent one trench from being locally destroyed.

  Further, by forming the first trench and the second trench so as to all have the same width w, the trench depth can be made uniform, and the withstand voltage capacity can be increased.

It is sectional drawing which shows the semiconductor element of this invention. It is a top view when the one main surface side of the semiconductor element of 1st embodiment is planarly viewed. It is a top view which shows the modification of 1st embodiment. It is a top view which shows another modification of 1st embodiment. It is a top view which shows 2nd embodiment of the semiconductor element of this invention. It is a top view which shows the example of formation of the trench of the conventional semiconductor element.

  Hereinafter, a semiconductor device according to the present invention will be described with reference to the drawings. In the following embodiments, a vertical trench gate MOS power semiconductor device will be described as an example of a semiconductor element. Further, the present embodiment is specifically described in order to make the gist of the invention better understood, and does not limit the present invention unless otherwise specified. In addition, in the drawings used in the following description, in order to make the features of the present invention easier to understand, there is a case where a main part is shown in an enlarged manner for convenience, and the dimensional ratio of each component is the same as the actual one. Not necessarily.

(First embodiment)
FIG. 1 is a sectional view showing a vertical trench gate MOS power semiconductor device (trench MOSFET) which is an embodiment of the semiconductor device of the present invention. A vertical trench gate MOS power semiconductor device (hereinafter simply referred to as a semiconductor device) 10 includes a trench MOSFET having an active region in which a main current flows and a peripheral breakdown voltage structure region disposed so as to surround the active region. It is. The semiconductor element 10 includes a semiconductor substrate 11.

The semiconductor substrate 11 may be made of, for example, SiC (silicon carbide) that is an n-type semiconductor doped with about 2 × 10 ¹⁸ cm ⁻³ of nitrogen as an impurity. As is well known, SiC (silicon carbide) has different types of crystal structures such as 2H, 3C, 4H, 6H, 8H, 10H, and 15R depending on the arrangement of C atoms and Si atoms. In this embodiment, A semiconductor substrate 11 made of 4H—SiC having a hexagonal crystal structure is used.

A drift layer 12 is formed on one main surface 11 a of the semiconductor substrate 11. The drift layer 12 may be, for example, a layer in which n ^- type SiC doped with about 1.0 × 10 ¹⁶ cm ^{−3 of} n-type impurities is stacked about 10 μm thick. Such a drift layer 12 may be formed on one main surface 11a of the semiconductor substrate 11 by epitaxial growth.

A base layer 13 is further formed on the drift layer 12. The base layer 13 may be, for example, a layer in which p-type SiC doped with about 2.1 × 10 ¹⁷ cm ^{−3 of} Al is laminated to a thickness of about 2.5 μm. Such a base layer 13 may be formed by epitaxial growth over the drift layer 12.

A p ⁺ -type contact region 14 and an n ⁺ -type source region 15 are formed on the base layer 13, respectively. The contact region 14 may use Al as an impurity to be doped, and the source region 15 may use P as an impurity to be doped. The contact region 14 and the source region 15 can be formed by ion implantation and activation heat treatment at about 1700 ° C., respectively.

Further, a gate trench (first trench) 21 and a Schottky barrier trench (protection) that penetrate through the p ⁺ -type contact region 14, the n ⁺ -type source region 15, and the base layer 13 and reach the drift layer 12. Trench: second trench) 22 is formed.

  The gate trench (first trench) 21 is, for example, a groove having a width of about 1.0 μm and a depth reaching the drift layer 12 of about 3 μm. For example, a gate oxide film 23 having a thickness of about 100 nm and a gate electrode 24 made of polysilicon or the like formed in the gate oxide film 23 are buried in the gate trench 21. Further, in order to insulate the gate electrode 21a from the source region 15, an interlayer insulating layer 25 covering the upper surface of the gate electrode 24 is formed.

  The Schottky barrier trench (second trench) 22 is, for example, a groove formed with a width of about 1.0 μm and a depth of about 5 μm deeper than the gate trench 21. In such a Schottky barrier trench 22, an extended portion of the anode electrode 26 covering the one main surface 11 a side of the semiconductor substrate 11 is formed. An extension portion of the anode electrode 26 formed inside the Schottky barrier trench 22 is formed as an electrode film common to the anode electrode 26.

  The source region 15 formed inside the Schottky barrier trench 22 functions as an anode electrode of the built-in Schottky barrier diode by being Schottky joined to the base layer 13 at the bottom of the Schottky trench 22.

A p ⁺ -type region 27 is formed at the bottom of the Schottky barrier trench 22 to improve the avalanche breakdown resistance. Such a p ⁺ type region 27 is formed by implanting Al ions into the bottom of the Schottky barrier trench 22 and performing a heat treatment at about 1700 ° C.

  On the other hand, a drain electrode 28 is formed on the other main surface 11 b side of the semiconductor substrate 11. The drain electrode 28 may be made of, for example, Ti, Ni, Au or the like.

FIG. 2 is a plan view showing a formation pattern of the first trench and the second trench on one main surface side of the semiconductor substrate.
When the semiconductor substrate 11 composed of 4H—SiC having a hexagonal crystal structure as in the present embodiment is used, one main surface 11a of the semiconductor substrate 11 has a [0001] axial direction or [000-1]. Any crystal plane that is perpendicular to an axis inclined from 30 degrees to 39 degrees in the <01-10> axial direction from the axial direction may be used. The crystal axis extending in the normal direction of one main surface 11a of the semiconductor substrate 11 made of 4H—SiC is the [0001] axis or the [000-1] axis, and the main axis corresponding to each crystal axis. The plane may be a (0001) plane or a (000-1) plane.

  As shown in FIG. 2, when the one main surface 11 a side of the semiconductor substrate 11 is viewed in plan, the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 each have a predetermined groove width. Are formed so as to draw an annular pattern alternately surrounding each other at a predetermined interval. When the semiconductor substrate 11 is formed of hexagonal 4H—SiC as in the present embodiment, the annular pattern of the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 is regular. It is formed to have a square shape.

  That is, in the embodiment shown in FIG. 2, a regular hexagonal Schottky barrier trench (second trench) 22 is arranged at the center most on the main surface 11a side, and the center Schottky barrier is spaced a predetermined distance d outside thereof. A gate trench (first trench) 21 having a regular hexagonal shape that is slightly larger than the trench (second trench) 22 is formed. Further, the semiconductor substrate 11 is formed so as to alternately surround the Schottky barrier trench (second trench) 22 and the gate trench (first trench) 21 toward the outer side (outer edge portion). The gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 are formed in a nested structure so that the outermost periphery is a Schottky barrier trench (second trench) 22. For example, in the embodiment shown in FIG. 2, three regular hexagonal gate trenches (first trenches) 21 and four Schottky barrier trenches (second trenches) 22 are formed.

  When the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 are formed on the one main surface 11a side of the semiconductor substrate 11 in such a pattern, all regular hexagonal gate trenches are formed. The (first trench) 21 is surrounded by the Schottky barrier trench (second trench) 22 from both sides with a predetermined interval d.

  Each gate trench (first trench) 21 and Schottky barrier trench (second trench) 22 are all formed to have the same width w.

  Further, the semiconductor substrate 11 has four sides whose outer shapes are parallel to four of the six sides of the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 each having a regular hexagonal shape. It is formed to be a rhombus (parallelogram) surrounded by. The semiconductor substrate 11 having such a shape is set so that, for example, a substantially circular (disk-shaped) SiC wafer is inclined with respect to the dicing line in the X-axis direction by tilting the dicing line in the Y direction from 90 degrees, for example, 60 degrees. And obtained by cutting.

  According to the semiconductor element 10 of the present embodiment as described above, a predetermined hexagonal gate trench (first trench) 21 is predetermined with respect to the adjacent Schottky barrier trench (second trench) 22 in any part. The distance d is maintained, and there is no portion where the width becomes narrower or wider than this.

  The distance d between the gate trench (first trench) 21 and the adjacent Schottky barrier trench (second trench) 22 may be, for example, about 0.5 μm to 8.0 μm. In FIG. 2, such a distance d indicates the distance between the peripheral edge (edge) of the gate trench 21 and the peripheral edge (edge) of the adjacent Schottky barrier trench 22. May be a so-called formation pitch from the center to the center of the width of the adjacent Schottky barrier trench 22.

  Between the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22, the electric field is uniformly distributed in any part, and the electric field is not concentrated in a specific part. As a result, it is possible to reliably prevent the gate trench (first trench) 21 from being locally destroyed by applying an excessive electric field to a specific portion.

  That is, in the conventional trench gate MOS power semiconductor device shown in FIG. 6, since the distance between the protection trench 102 and the gate trench 101 is not uniform, for example, the distances n1 and n2 are different. There is a concern that an excessive electric field is applied to the portion where the gate trench 101 is present, and the gate trench 101 is locally destroyed.

  However, as in the present embodiment, the distance d between the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 is formed to be equal in any part of the regular hexagonal formation pattern. Therefore, such partial electric field concentration can be prevented and local breakdown of the gate trench 21 can be surely prevented.

  Further, by forming each gate trench (first trench) 21 and Schottky barrier trench (second trench) 22 to have the same width w, the trench depth can be made uniform. It becomes possible to increase the withstand voltage capacity.

  Further, as in the present embodiment, the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 are formed on one main surface 11 a of the semiconductor substrate 11 with silicon carbide constituting the semiconductor substrate 11. In the case of using a semiconductor substrate 11 composed of an annular pattern approximated to a crystal structure, for example, 4H-SiC having a hexagonal crystal structure, a gate trench (first trench) 21 and a Schottky barrier trench (first By forming the (2 trench) 22 so as to be hexagonal when the one main surface 11a side is viewed in plan, a trench gate MOS power semiconductor device (semiconductor element) having high channel mobility can be obtained.

  In addition, the outer shape of the semiconductor substrate 11 is four sides parallel to four of the six sides of the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 that form a regular hexagon. By forming so as to form an enclosed rhombus (parallelogram), when dicing a large number of semiconductor substrates 11 from one SiC wafer, the gate trench (first trench) 21 and the Schottky barrier trench (first) (2 trenches) 22 can be made the least wasteful on the space layout. As a result, the maximum amount of semiconductor substrate (chip) 11 can be obtained from one SiC wafer, and the manufacturing cost can be reduced.

FIG. 3 is a modification of the first embodiment. In the first embodiment described above, the Schottky barrier trench (second trench) 22 arranged at the center of the semiconductor substrate 11 is formed in a regular hexagon with the center removed.
On the other hand, in the embodiment shown in FIG. 3, the Schottky barrier trench (second trench) 32 arranged at the center of the semiconductor substrate 11 is also formed in the entire central region surrounded by a regular hexagonal annular pattern. The so-called filled hexagonal hexagon is formed. Even in such a form of Schottky barrier trench (second trench) 32, the distance d between the gate trench (first trench) 31 formed on the outer side thereof is uniformly formed in any part. It is possible to prevent concentration of the electric field at the portion.

FIG. 4 is another modification of the first embodiment.
In the first embodiment described above, the corners of the gate trench (first trench) 21 and the Schottky barrier trench (second trench) 22 formed in a regular hexagon are formed at acute angles.
On the other hand, in the embodiment shown in FIG. 4, the corners of the gate trench (first trench) 41 and the Schottky barrier trench (second trench) 42 are rounded. This makes it possible to more surely prevent the concern that the electric field is biased particularly at the corners of the regular hexagon.

(Second embodiment)
Hereinafter, a second embodiment of the semiconductor element of the present invention will be described. The cross-sectional structure of the semiconductor element is the same as that of FIG. 1 of the first embodiment, and the description of the same configuration as that of the first embodiment is omitted.
FIG. 5 is a plan view showing a formation pattern of the first trench and the second trench when one main surface side of the semiconductor substrate in the second embodiment is viewed in plan.
The semiconductor substrate 51 constituting the semiconductor element 50 of the present embodiment is made of 3C—SiC that forms a cubic crystal structure.

  As shown in FIG. 5, when one main surface 51 a side of the semiconductor substrate 51 is viewed in plan, the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 each have a predetermined groove width. Are formed so as to draw an annular pattern alternately surrounding each other at a predetermined interval. When the semiconductor substrate 51 is composed of cubic 3C-SiC as in this embodiment, the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 have a quadrangular annular pattern. It is formed to become.

  The gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 have, on one main surface 51a, two parallel sides extending in the <100> axis direction and the other two parallel sides being <010. > It extends in the axial direction, and the side wall surface in the depth direction of each trench (the depth direction in FIG. 5) is formed so as to extend along the (001) plane.

  When the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 are formed on the one main surface 51a side of the semiconductor substrate 51 in such a pattern, all square gate trenches ( The first trench 61 is surrounded by the Schottky barrier trench (second trench) 62 from both sides with a predetermined interval d.

  According to the semiconductor element 50 of the present embodiment as described above, a predetermined gate-trench (second trench) 62 is predetermined with respect to an adjacent Schottky barrier trench (second trench) 62 in any part of the square-shaped gate trench (first trench) 61. The interval d is maintained, and there is no portion where the width becomes narrower or wider than this.

  Each gate trench (first trench) 61 and Schottky barrier trench (second trench) 62 are all formed to have the same width w.

  The distance d between the gate trench (first trench) 61 formed in such a square pattern and the adjacent Schottky barrier trench (second trench) 62 is, for example, about 0.5 μm to 8.0 μm. It ’s fine. In FIG. 5, such a distance d indicates the distance between the periphery (edge) of the gate trench 61 and the periphery (edge) of the adjacent Schottky barrier trench 62. May be a so-called formation pitch from the center to the center of the width of the adjacent Schottky barrier trench 62.

  Between the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62, the electric field is uniformly distributed in any part, and the electric field is not concentrated in a specific part. Accordingly, by forming the distance d between the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 so as to be equal in any part of the square formation pattern, such a partial region is formed. Electric field concentration can be prevented, and local destruction of the gate trench 61 can be surely prevented.

  Further, the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 are all formed to have the same width w, so that the trench depth can be made uniform. It becomes possible to increase the withstand voltage capacity.

  Furthermore, since the side wall surfaces in the depth direction of the gate trench (first trench) 61 and the Schottky barrier trench (second trench) 62 are formed so as to extend along the (001) surface with high channel mobility, Variations in channel mobility can be suppressed.

  In the embodiment of the present invention, 4H—SiC (hexagonal crystal) and 3C—SiC (cubic crystal) are exemplified as SiC (silicon carbide) constituting the semiconductor substrate, but other than this, 2H—SiC (hexagonal) Dozens of types such as 4H-SiC (hexagonal), 6H-SiC (hexagonal), 8H-SiC (hexagonal), 10H-SiC (hexagonal), and 15R-SiC (rombohedral) The present invention can be applied to any SiC crystal polymorph.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor element (vertical trench gate MOS power semiconductor device), 11 ... Semiconductor substrate, 11a ... One main surface, 21 ... Gate trench (1st trench), 22 ... Schottky barrier trench (2nd trench).

Claims (7)

A first conductivity type semiconductor substrate made of silicon carbide;
A drift layer of a first conductivity type formed on one main surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
A second conductivity type base layer having a higher impurity concentration than the drift layer;
A source region of a first conductivity type selectively disposed on a surface layer of the base layer;
A gate trench having a gate electrode embedded therein, and a first trench having a depth reaching the drift layer from a main surface of the source region;
A Schottky barrier trench having an anode electrode formed therein, a second trench having a depth reaching the drift layer and deeper than the first trench;
At least one main surface side of the semiconductor substrate, wherein the first trench and the second trench are formed in an annular pattern alternately surrounding each other at a predetermined interval. .   The first trench and the second trench are formed on one main surface of the semiconductor substrate so as to have an annular pattern approximating a crystal structure of silicon carbide constituting the semiconductor substrate. Item 14. A semiconductor device according to Item 1.   3. The semiconductor device according to claim 1, wherein the first trench and the second trench are formed to have the same width along one main surface of the semiconductor substrate.   The silicon carbide constituting the semiconductor substrate has a crystal structure that forms a hexagonal crystal, and the first trench and the second trench are formed to have a hexagonal shape when the one main surface side is viewed in plan view. The semiconductor element according to claim 2 or 3, characterized in that 5. The semiconductor element according to claim 4 , wherein an outer shape of the semiconductor substrate is a rhombus composed of four sides parallel to four of the six sides forming the hexagon.   The silicon carbide constituting the semiconductor substrate has a cubic crystal structure, and the first trench and the second trench are formed to have a quadrangle when the one main surface side is viewed in plan view. The semiconductor element according to claim 2 or 3.   On the one main surface side of the semiconductor substrate, the first trench or the second trench arranged at the center is also the first trench or the second trench in the entire central region surrounded by the annular pattern. The semiconductor device according to claim 1, wherein a trench is formed.

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