JP5650652B2 - 有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 - Google Patents
有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 Download PDFInfo
- Publication number
- JP5650652B2 JP5650652B2 JP2011534746A JP2011534746A JP5650652B2 JP 5650652 B2 JP5650652 B2 JP 5650652B2 JP 2011534746 A JP2011534746 A JP 2011534746A JP 2011534746 A JP2011534746 A JP 2011534746A JP 5650652 B2 JP5650652 B2 JP 5650652B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- depth
- donor semiconductor
- weakened slice
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 119
- 238000000034 method Methods 0.000 title claims description 89
- 239000012212 insulator Substances 0.000 title claims description 9
- 238000000926 separation method Methods 0.000 claims description 60
- 238000005468 ion implantation Methods 0.000 claims description 55
- 238000002513 implantation Methods 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 46
- 230000007423 decrease Effects 0.000 claims description 4
- 230000003313 weakening effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 120
- 150000002500 ions Chemical class 0.000 description 62
- 230000006911 nucleation Effects 0.000 description 44
- 238000010899 nucleation Methods 0.000 description 44
- 230000008859 change Effects 0.000 description 26
- 239000001257 hydrogen Substances 0.000 description 26
- 229910052739 hydrogen Inorganic materials 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 238000009826 distribution Methods 0.000 description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 17
- 239000000758 substrate Substances 0.000 description 17
- 238000010884 ion-beam technique Methods 0.000 description 15
- 230000007547 defect Effects 0.000 description 11
- -1 hydrogen ions Chemical class 0.000 description 11
- 238000013459 approach Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000003776 cleavage reaction Methods 0.000 description 9
- 239000011521 glass Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 230000007017 scission Effects 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- 238000006664 bond formation reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005465 channeling Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 239000002241 glass-ceramic Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004581 coalescence Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000003902 lesion Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 239000006096 absorbing agent Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
- H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Physical Vapour Deposition (AREA)
- Recrystallisation Techniques (AREA)
Description
120 ドナー半導体ウエハ
121 注入表面
122 表面剥離層
125 弱化スライス
Claims (4)
- 絶縁体上半導体(SOI)構造を形成する方法において、
幅、深さ及び高さを有し、前記幅及び前記深さがX軸方向及びY軸方向を定め、前記高さが軸線を定める、ドナー半導体ウエハを提供する工程、
前記ドナー半導体ウエハの注入表面をイオン注入工程にかけて、前記ドナー半導体ウエハの表面剥離層を定める断面において弱化スライスを形成する工程、及び
前記弱化スライスの最小深さの点、辺及び/または領域が、前記ドナー半導体ウエハの辺の全体にわたり、前記弱化スライスの前記注入表面からの深さが前記軸線に直交する前記X軸方向及び前記Y軸方向に拡がる基準面に対して前記ドナー半導体ウエハの面内で空間的に変化するように、前記イオン注入工程前、工程中または工程後に前記ドナー半導体ウエハを空間的変化工程にかける工程を含み、
前記弱化スライスの最大深さが400〜425nmの第1の領域にあり、最小深さが200〜380nmの前記弱化スライスの第2の領域にあって、前記第2の領域が、前記X軸方向及び前記Y軸方向の少なくとも一方において前記第1の領域から隔てられ、前記弱化スライスの深さが前記第1の領域から前記第2の領域に向けて小さくなることを特徴とする方法。 - 前記第1の領域における前記弱化スライスの最大深さが、前記第2の領域における前記弱化スライスの最小深さの1.05〜2.00倍であることを特徴とする請求項1に記載の方法。
- 前記ドナー半導体ウエハの温度を、前記基準面に対する前記弱化スライスの最小深さの点、辺及び/または領域から前記弱化スライスにおける分離を開始するに十分な温度まで高める工程をさらに含むことを特徴とする請求項1または2に記載の方法。
- 前記ドナー半導体ウエハの温度を、前記最小深さから前記最大深さに向けて、前記弱化スライスの前記変化する深さの関数として有向で前記弱化スライスに実質的に沿って分離を続けるに十分な温度までさらに高める工程をさらに含むことを特徴とする請求項3に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/290,384 | 2008-10-30 | ||
US12/290,384 US8003491B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
US12/290,362 | 2008-10-30 | ||
US12/290,362 US7816225B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
PCT/US2009/062504 WO2010059361A2 (en) | 2008-10-30 | 2009-10-29 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012507868A JP2012507868A (ja) | 2012-03-29 |
JP5650652B2 true JP5650652B2 (ja) | 2015-01-07 |
Family
ID=41559616
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011534755A Expired - Fee Related JP5650653B2 (ja) | 2008-10-30 | 2009-10-29 | 有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置 |
JP2011534746A Expired - Fee Related JP5650652B2 (ja) | 2008-10-30 | 2009-10-29 | 有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011534755A Expired - Fee Related JP5650653B2 (ja) | 2008-10-30 | 2009-10-29 | 有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置 |
Country Status (6)
Country | Link |
---|---|
EP (2) | EP2356676A2 (ja) |
JP (2) | JP5650653B2 (ja) |
KR (2) | KR101568898B1 (ja) |
CN (2) | CN102203933B (ja) |
TW (2) | TWI451534B (ja) |
WO (2) | WO2010059361A2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5703853B2 (ja) * | 2011-03-04 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
FR3055063B1 (fr) * | 2016-08-11 | 2018-08-31 | Soitec | Procede de transfert d'une couche utile |
CN111834205B (zh) * | 2020-07-07 | 2021-12-28 | 中国科学院上海微系统与信息技术研究所 | 一种异质半导体薄膜及其制备方法 |
CN114975765A (zh) * | 2022-07-19 | 2022-08-30 | 济南晶正电子科技有限公司 | 复合单晶压电薄膜及其制备方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
US6155909A (en) * | 1997-05-12 | 2000-12-05 | Silicon Genesis Corporation | Controlled cleavage system using pressurized fluid |
JP3031904B2 (ja) * | 1998-02-18 | 2000-04-10 | キヤノン株式会社 | 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法 |
TW437078B (en) | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
US20010007790A1 (en) * | 1998-06-23 | 2001-07-12 | Henley Francois J. | Pre-semiconductor process implant and post-process film separation |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
JP2002124652A (ja) * | 2000-10-16 | 2002-04-26 | Seiko Epson Corp | 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器 |
FR2830983B1 (fr) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
FR2847077B1 (fr) * | 2002-11-12 | 2006-02-17 | Soitec Silicon On Insulator | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
EP1429381B1 (en) * | 2002-12-10 | 2011-07-06 | S.O.I.Tec Silicon on Insulator Technologies | A method for manufacturing a material compound |
US7176528B2 (en) | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
DE10318283A1 (de) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
JP2006324051A (ja) * | 2005-05-17 | 2006-11-30 | Nissin Ion Equipment Co Ltd | 荷電粒子ビーム照射方法および装置 |
JP4977999B2 (ja) * | 2005-11-21 | 2012-07-18 | 株式会社Sumco | 貼合せ基板の製造方法及びその方法で製造された貼合せ基板 |
US7691730B2 (en) * | 2005-11-22 | 2010-04-06 | Corning Incorporated | Large area semiconductor on glass insulator |
-
2009
- 2009-10-28 TW TW098136607A patent/TWI451534B/zh not_active IP Right Cessation
- 2009-10-28 TW TW098136605A patent/TWI430338B/zh not_active IP Right Cessation
- 2009-10-29 EP EP09744303A patent/EP2356676A2/en not_active Withdrawn
- 2009-10-29 JP JP2011534755A patent/JP5650653B2/ja not_active Expired - Fee Related
- 2009-10-29 KR KR1020117012221A patent/KR101568898B1/ko not_active IP Right Cessation
- 2009-10-29 CN CN200980143709.4A patent/CN102203933B/zh not_active Expired - Fee Related
- 2009-10-29 WO PCT/US2009/062504 patent/WO2010059361A2/en active Application Filing
- 2009-10-29 EP EP09744304A patent/EP2359400A2/en not_active Withdrawn
- 2009-10-29 CN CN200980143710.7A patent/CN102203934B/zh not_active Expired - Fee Related
- 2009-10-29 WO PCT/US2009/062531 patent/WO2010059367A2/en active Application Filing
- 2009-10-29 JP JP2011534746A patent/JP5650652B2/ja not_active Expired - Fee Related
- 2009-10-29 KR KR1020117012220A patent/KR20110081318A/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP2356676A2 (en) | 2011-08-17 |
JP2012507868A (ja) | 2012-03-29 |
KR20110081881A (ko) | 2011-07-14 |
KR20110081318A (ko) | 2011-07-13 |
KR101568898B1 (ko) | 2015-11-12 |
WO2010059367A2 (en) | 2010-05-27 |
TW201030815A (en) | 2010-08-16 |
WO2010059361A3 (en) | 2010-08-12 |
WO2010059361A2 (en) | 2010-05-27 |
EP2359400A2 (en) | 2011-08-24 |
TWI451534B (zh) | 2014-09-01 |
CN102203934A (zh) | 2011-09-28 |
TW201036112A (en) | 2010-10-01 |
TWI430338B (zh) | 2014-03-11 |
CN102203934B (zh) | 2014-02-12 |
JP2012507870A (ja) | 2012-03-29 |
CN102203933B (zh) | 2015-12-02 |
JP5650653B2 (ja) | 2015-01-07 |
WO2010059367A3 (en) | 2010-08-05 |
CN102203933A (zh) | 2011-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8338269B2 (en) | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation | |
KR101134485B1 (ko) | 공동 주입 및 후속 주입에 의해 박막을 획득하는 방법 | |
US6429104B1 (en) | Method for forming cavities in a semiconductor substrate by implanting atoms | |
JP5042837B2 (ja) | 気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 | |
JP5133908B2 (ja) | エピタキシによって支持基板上に得られる、非晶質材料の少なくとも1層の薄層を備える構造を製作する方法、およびその方法により得られた構造 | |
US8420500B2 (en) | Method of producing a structure by layer transfer | |
JP5650652B2 (ja) | 有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 | |
US8003491B2 (en) | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation | |
JP2007500435A (ja) | 共注入と熱アニールによって特性の改善された薄層を得るための方法 | |
JP2012507870A5 (ja) | ||
US7799651B2 (en) | Method of treating interface defects in a substrate | |
US8258043B2 (en) | Manufacturing method of thin film semiconductor substrate | |
TW202036784A (zh) | 用於將有用層移轉至支撐底材上之方法 | |
Direction | c12) United States Patent | |
Raineri et al. | Radiation damage–He interaction in He implanted Si during bubble formation and their evolution in voids | |
Huang et al. | A nano-thick SOI fabrication method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20121022 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140304 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140603 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141111 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141113 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5650652 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |