JP5645143B2 - High frequency components and communication devices - Google Patents

Description

  The present invention relates to a wireless communication apparatus that performs wireless transmission between electronic and electrical devices, and relates to a high-frequency component used in the wireless communication apparatus and a communication apparatus using the same.

  At present, data communication using a wireless LAN represented by the IEEE 802.11 standard is widely used. For example, personal computers (PCs), PC peripherals such as printers, hard disks, broadband routers, fax machines, refrigerators, standard televisions (SDTVs), high-definition televisions (HDTVs), electronic devices such as cameras, videos, mobile phones, etc. It is adopted as a signal transmission means that replaces wired communication in an airplane, and wireless data transmission is performed between the respective electronic devices. In addition to single-band communication using one communication frequency band, multi-band communication that handles two communication systems with different communication frequency bands has become widespread.

  A high-frequency circuit used in such a multiband communication apparatus using a wireless LAN is one that can be transmitted and received by two communication systems (IEEE802.11a and IEEE802.11b and / or IEEE802.11g) having different communication frequency bands. A high-frequency switch for switching the connection between the antenna and the transmission-side circuit and the reception-side circuit. With such a high frequency switch, the transmission side circuit and the reception side circuit of the two communication systems are switched. With the downsizing and high functionality of wireless devices, there is a strong demand for miniaturization while integrating many functional parts into the high frequency parts that implement the high frequency circuit, and the integration of functions is further advanced. Yes.

  For example, Patent Document 1 discloses a high-frequency component that includes a switch circuit, a power amplifier circuit, and the like, and is configured by integrating a high-frequency circuit that can be shared by two communication systems into a laminated substrate. The high-frequency component has an equivalent circuit shown in FIG. 26 of Patent Document 1 and is miniaturized by using a pattern configuration as shown in FIG.

  As in the example shown in Patent Document 1, it is possible to reduce the size by integrating a circuit that processes a high-frequency signal, such as a switch circuit or a power amplifier circuit, into a laminated substrate. However, when trying to achieve high integration of functions and elements, there is a problem that electrode patterns constituting a circuit are close to each other, and circuits formed on a high-frequency component are likely to interfere with each other. For example, in Patent Document 1, each electrode pattern connected to the transmission, reception port, power supply port, etc. on the back surface is formed over each layer, so that the transmission line, reception line, and power supply line interfere with downsizing. It becomes easy. In particular, when the integration of functions progresses and the number of high-frequency signal processing circuits such as switch circuits increases, many power supply lines used for the control and the like become a structure in which signal lines such as transmission lines and reception lines are complicatedly arranged. For this reason, the interference becomes significant, which hinders miniaturization of the high-frequency component.

  On the other hand, in Patent Document 2, in order to prevent deterioration of filter characteristics due to electromagnetic coupling between the control signal line and the filter, the stacking direction of the dielectric layer and the conductor layer is sandwiched between the control signal lines. There has been proposed a high-frequency module having two grounding conductor layers arranged at different positions in which no other conductor layer is interposed between the grounding conductor layer and the control signal line.

WO 2006/003959 (FIG. 29) JP 2007-81769 A

  However, when the number of control signal lines increases due to the increase in functionality and integration as described above, a large amount of space is required to extend the power supply lines such as the control signal lines, and the high-frequency module becomes larger. There is a problem. On the other hand, the high-frequency module disclosed in Patent Document 2 in which the control signal line is extended in the stacking direction from the portion sandwiched between the two grounding conductor layers is a means for solving the above problem. The high-frequency component has not been sufficiently reduced in size.

  Therefore, the present invention provides a configuration suitable for miniaturization in a high-frequency component having a high-frequency signal processing circuit on a multilayer substrate formed by laminating a plurality of dielectric layers on which conductor patterns are formed. The purpose is to reduce the size of the communication device used.

A first high-frequency component according to the present invention is a high-frequency component including a high-frequency signal processing circuit that processes a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers on which a conductor pattern is formed. A terminal group including an input terminal, an output terminal, and a plurality of power supply terminals of the high-frequency signal processing circuit is formed on one main surface of the multilayer substrate, and an inductance element is provided on the dielectric layer constituting the multilayer substrate. A plurality of power supply lines, one end of which is connected to the power supply terminal, via the via electrode formed in the dielectric layer. high-frequency signal processing circuit is connected to at least one semiconductor element has at least two power supply lines among the plurality of power supply lines, respectively, before when viewed from the laminating direction In a position spaced apart from the power supply terminal, and having a via electrode row formed so as to overlap when viewed from the stacking direction over adjacent two or more dielectric layers, a via electrode row of said at least two power supply lines, the adjacent The dielectric layers are adjacent to each other without interposing other conductor patterns. Since the influence of interference is small even if the power supply lines are close to each other, the high-frequency components can be miniaturized by bringing them close to each other without passing through other conductor patterns such as signal lines. Note that the proximity without passing through other conductor patterns means that other conductor patterns other than the conductor pattern related to the via electrode on the line segment connecting the centers of the via electrodes in the plane direction along the dielectric layer. Means there is no. In the dielectric layer in which the via electrodes of the plurality of power supply lines are close to each other, it is preferable that the via electrodes of the plurality of power supply lines are surrounded by a group of via electrodes connected to the ground. Furthermore, the via electrodes of the via electrode group are preferably connected to each other by a strip-like conductor pattern on the surface of the dielectric layer on which the via electrode group is formed.

A second high-frequency component according to the present invention is a high-frequency component including a high-frequency signal processing circuit that processes a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers on which a conductor pattern is formed. A terminal group including an input terminal, an output terminal, and a plurality of power supply terminals of the high-frequency signal processing circuit is formed on one main surface of the multilayer substrate, and an inductance element is provided on the dielectric layer constituting the multilayer substrate. A plurality of power supply lines, one end of which is connected to the power supply terminal, via the via electrode formed in the dielectric layer. Connected to at least one semiconductor element of a high-frequency signal processing circuit, and the via electrodes of the plurality of power supply lines are at least one dielectric layer of the plurality of dielectric layers Oite, at a position spaced apart from the power supply terminal when viewed from the laminating direction, and close without passing through the other conductor patterns, the dielectric layer via electrode of the plurality of power supply lines are close, the plurality of power supply lines The via electrode is surrounded by a via electrode group connected to the ground. Since the influence of interference is small even if the power supply lines are close to each other, the high-frequency components can be miniaturized by bringing them close to each other without passing through other conductor patterns such as signal lines. Further, by surrounding the via electrodes of adjacent power supply lines with a group of via electrodes connected to the ground, it is possible to prevent interference between the power supply line and the signal line due to miniaturization.

  In the second high-frequency component, it is preferable that the via electrodes of the via electrode group are connected to each other by a strip-like conductor pattern on the surface of the dielectric layer on which the via electrode group is formed. According to such a configuration, it is possible to more effectively prevent interference between the power supply line and the signal line accompanying downsizing. In order to enhance the shielding effect, it is more preferable to form an annular conductor pattern by connecting via electrodes of the via electrode group with the strip-shaped conductor pattern.

A third high-frequency component of the present invention is a high-frequency component including a high-frequency signal processing circuit that processes a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers on which conductor patterns are formed. A terminal group including an input terminal, an output terminal, and a plurality of power supply terminals of the high-frequency signal processing circuit is formed on one main surface of the multilayer substrate, and an inductance element is provided on the dielectric layer constituting the multilayer substrate. A plurality of power supply lines, one end of which is connected to the power supply terminal, via the via electrode formed in the dielectric layer. Via electrodes of at least two power supply lines connected to a plurality of semiconductor elements included in the high-frequency signal processing circuit and connected to different semiconductor elements among the plurality of power supply lines, In at least one dielectric layer of a serial plurality of dielectric layers, at a position spaced apart from the power supply terminal when viewed from the laminating direction, and is characterized in that in proximity to without going through another conductor pattern. Even if the power lines are close to each other, the influence of interference is small. For this reason, if high-frequency components having a plurality of semiconductor elements can be miniaturized by making them close to each other without interposing other conductor patterns such as signal lines. In the dielectric layer in which the via electrodes of the plurality of power supply lines are close to each other, it is preferable that the via electrodes of the plurality of power supply lines are surrounded by a group of via electrodes connected to the ground. Furthermore, the via electrodes of the via electrode group are preferably connected to each other by a strip-like conductor pattern on the surface of the dielectric layer on which the via electrode group is formed.

  Further, in the high frequency component, the high frequency signal processing circuit includes a switch circuit and a low noise amplifier circuit, and at least one of the plurality of power supply lines includes a control power supply line of the semiconductor element of the switch circuit and the low power amplifier circuit. It is preferable to have a common line portion that also serves as a power supply line of the semiconductor element of the noise amplifier circuit. According to such a configuration, the required power supply line is reduced, and the high-frequency component can be further downsized.

  The high-frequency signal processing circuit includes an SPnT-type or DPnT-type (n is a natural number of 3 or more) switch circuit, and a low-noise amplifier circuit connected to at least two switching terminals of the switch circuit, A power supply for each of the low noise amplifier circuits and a control power supply for switching to the switching terminal to which the low noise amplifier circuit is connected are shared, and at least one of the plurality of power supply lines is the low power amplifier circuit. It is preferable to have a common line portion that also serves as a power supply line for the semiconductor element of the noise amplifier circuit and a control power supply line for switching to the switching terminal to which the low noise amplifier circuit is connected. In this configuration, a branch to a plurality of paths to which a low-noise amplifier circuit is connected is performed by an SPnT type (Single Pole n throw) or DPnT (Dual Pole n throw) type switch circuit. Even in such a configuration, at least one of the plurality of power supply lines has a common line portion that serves as both the power supply line of the switch circuit and the control power supply line of the low-noise amplifier circuit, thereby reducing the required power supply line and increasing the Further downsizing of parts can be achieved.

  Further, in the high-frequency component, the high-frequency signal processing circuit includes at least one of a plurality of switch circuits, a plurality of high-frequency amplifier circuits, and a plurality of low-noise amplifier circuits, and at least one of the plurality of power supply lines is It is preferable that the semiconductor elements of the plurality of switch circuits, the semiconductor elements of the plurality of high-frequency amplifier circuits, or the common line portion that also serves as a power line for the semiconductor elements of the plurality of low-noise amplifier circuits. According to such a configuration, the required power supply line is reduced, and the high-frequency component can be further downsized.

Furthermore, in the high-frequency component, it is preferable that the terminal group is formed on the one main surface and arranged along an outer edge of the main surface.
Furthermore, in the high-frequency component, it is preferable that power supply lines having one end connected to the power supply terminal are brought close to each other and connected to the adjacent via electrode or via electrode row.
Furthermore, in the high-frequency component, the plurality of power supply lines, one end of which is connected to the power supply terminal, are formed in one dielectric layer to form a first power supply line layer, and the first power supply line layer is sandwiched therebetween. A first ground electrode that overlaps at least a part of the plurality of power supply lines in plan view is disposed on the main surface side in the stacking direction, and at least one of the power supply lines in plan view on the side opposite to the main surface in the stacking direction. It is preferable that a second ground electrode that partially overlaps is disposed, and the high-frequency signal processing circuit is disposed on a side opposite to the first power supply line layer with the second ground electrode interposed therebetween. According to this configuration, the power supply line can be routed in the first power supply line layer sandwiched between the ground electrodes and further away from the high frequency signal processing circuit via the ground electrode. The interference with the signal line of the signal processing circuit can be avoided, and the high-frequency component can be downsized.

  Furthermore, in the high-frequency component, the semiconductor element is mounted on the other main surface of the multilayer substrate, a third ground electrode is disposed on the other main surface side in the multilayer substrate, and the common line portion Is connected to one of the plurality of power supply terminals, and the other end of the common line portion is a second power supply line layer formed between the semiconductor element and the third ground electrode. It is preferable to branch to a line connected to each semiconductor element. According to such a configuration, since the common line portion of the power supply line can be made long, the high-frequency component can be further downsized.

  Further, in the high-frequency component, a capacitor having one end grounded is connected to the common line portion, and an electrode constituting the capacitor is the first ground electrode sandwiched between the first ground electrode and the second ground electrode. Preferably, it is formed in the power line layer. The capacitor functions as a power supply noise cut capacitor. According to such a configuration, the power source noise cut capacitor can be shared, and the capacitor can be configured spatially and efficiently, so that the high-frequency component can be reduced in size.

  Further, in the high-frequency component, the high-frequency signal processing circuit is input to an input terminal of the high-frequency signal and a switch circuit that switches connection between an antenna terminal connected to an antenna and the input terminal or output terminal of the high-frequency signal. It is preferable to have a high-frequency amplifier circuit that amplifies the transmission signal and a low-noise amplifier circuit that amplifies the reception signal input from the antenna terminal and outputs the amplified signal to the output terminal. Since the high-frequency component having the switch circuit, the high-frequency amplifier, and the low-noise amplifier circuit includes many semiconductor elements, the above-described configuration relating to the power supply line of the semiconductor element is particularly effective for downsizing the high-frequency component.

  In the first to third high-frequency components, the plurality of power lines, one end of which is connected to the power terminal, are formed on one dielectric layer to form a first power line layer. A first ground electrode that overlaps at least a part of the plurality of power supply lines in plan view is disposed on the main surface side in the stacking direction across the power supply line layer, and in plan view on the side opposite to the main surface in the stacking direction. A second ground electrode that overlaps at least part of the plurality of power supply lines is disposed, and the high-frequency signal processing circuit is disposed on the opposite side of the first power supply line layer with the second ground electrode interposed therebetween. It is preferable. According to this configuration, the power supply line can be routed in the first power supply line layer sandwiched between the ground electrodes and further away from the high frequency signal processing circuit via the ground electrode. The interference with the signal line of the signal processing circuit can be avoided, and the high-frequency component can be downsized.

  Further, in the high-frequency component, the terminal group is formed on the one main surface and arranged along an outer edge of the main surface, and the first ground electrode is formed on the one main surface, It is preferably formed inside the terminal group. According to such a configuration, since the surface on which the terminal group is provided and the surface on which the first ground electrode is provided can be shared, a separate dielectric layer is not required to provide the first ground electrode, so that the height is reduced. The size can be reduced.

  In the high-frequency component, it is preferable that at least a part of the power supply terminal overlaps the second ground electrode in plan view. According to such a configuration, even if a portion where the ground electrode is not formed is formed in the portion facing the power supply terminal in the first power supply line layer, the second ground electrode interferes with the high frequency signal processing circuit side and the power supply terminal. Demonstrate the effect of preventing.

  Furthermore, in the high-frequency component, at least some other ends of the plurality of power supply lines are connected to the high-frequency signal processing circuit via via electrodes formed in a region overlapping the first ground electrode in plan view. It is preferable. By positioning the other end of the power supply line, one end of which is connected to the power supply terminal, in the region, it is possible to prevent interference with the input terminal and the output terminal of the high frequency signal. Further, the via connection position of the power supply line to the high-frequency signal processing circuit can be freely arranged in the plane direction of the first power supply line layer regardless of the position of the power supply terminal. Thereby, the degree of freedom in the layout design of the power supply line is remarkably improved, and the miniaturization design is enabled. Further, in the high-frequency component, a signal line connected to at least one of the input terminal and the output terminal of the high-frequency signal is formed in the first power supply line layer, and the signal line is seen in plan view, Preferably, it is formed in a region that does not overlap with one ground electrode.

  Further, in the high-frequency component, a signal line connected to at least one of the input terminal and the output terminal of the high-frequency signal is formed in the first power supply line layer, and the signal line is seen in plan view, Preferably, it is formed in a region that does not overlap with one ground electrode. Even when a signal line is formed in the power supply line layer, a region outside the region overlapping the first ground electrode where the other end of the power supply line is concentrated in plan view, that is, in plan view, the first ground electrode and By forming a signal line in a region that does not overlap, interference between the power supply line and the signal line can be prevented. Further, in the terminal group, it is preferable that the input terminal and output terminal of the high-frequency signal and the power supply terminal are arranged via terminals other than the input terminal, output terminal and power supply terminal of the high-frequency signal. . According to this configuration, interference between the power supply terminal and the input terminal and output terminal of the high frequency signal can be suppressed.

  Furthermore, in the high-frequency component, the high-frequency signal processing circuit can be suitably used when at least one of a switch circuit, a high-frequency amplifier circuit, and a low-noise amplifier circuit is used.

  Further, in the high-frequency component, the high-frequency signal processing circuit is input to an input terminal of the high-frequency signal and a switch circuit that switches connection between an antenna terminal connected to an antenna and the input terminal or output terminal of the high-frequency signal. It is preferable to have a high-frequency amplifier circuit that amplifies the transmission signal and a low-noise amplifier circuit that amplifies the reception signal input from the antenna terminal and outputs the amplified signal to the output terminal. The above configuration is suitable for applications that require high functionality and downsizing, such as when the switch circuit, the high frequency amplifier circuit, and the low noise amplifier circuit are provided as the high frequency signal processing circuit.

  A communication apparatus according to the present invention is characterized by using any of the above high-frequency components. By using the high-frequency component, the communication device can be reduced in size, and a configuration suitable for a portable communication device can be provided.

  In addition, the said structure can be combined suitably.

  ADVANTAGE OF THE INVENTION According to this invention, the structure suitable for the size reduction can be provided in the high frequency component which provided the high frequency signal processing circuit on the laminated substrate formed by laminating | stacking the several dielectric layer in which the conductor pattern was formed. Further, the communication device can be downsized by using the high-frequency component.

It is a schematic diagram which shows a part of high frequency components which concern on one Embodiment of this invention. It is a schematic diagram which shows a part of high frequency components which concern on other embodiment of this invention. It is a schematic diagram which shows a part of high frequency components which concern on other embodiment of this invention. It is a schematic diagram which shows a part of high frequency components which concern on other embodiment of this invention. It is a schematic diagram which shows a part of high frequency components which concern on other embodiment of this invention. It is a schematic diagram which shows a part of high frequency components which concern on other embodiment of this invention. It is a circuit block diagram of the high frequency component which concerns on one Embodiment of this invention. It is a sheet | seat expanded view of the high frequency component which concerns on one Embodiment of this invention. It is a circuit block diagram of the high frequency component which concerns on other embodiment of this invention.

  Embodiments of the present invention will be described below in detail with reference to the drawings, but the present invention is not limited thereto. As a high-frequency component provided with a high-frequency signal processing circuit for processing a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers on which a conductor pattern is formed, the 2.4 GHz band and the 5 GHz band having the circuit block shown in FIG. A front-end module for a dual-band wireless LAN using the above will be described as an example. The front end module shown in FIG. 7 includes, as a high-frequency signal processing circuit, a first switch circuit SPDT1 that switches connection between a first antenna terminal Ant1 or a second antenna terminal Ant2 connected to two antennas, and an antenna. A second switch circuit SPDT2 for switching the connection between the terminal and the input terminals Tx1 and Tx2 of the high-frequency signal or the output terminals Rx1 and Rx2, and a first high-frequency amplifier circuit for amplifying the transmission signal input to the input terminal Tx1 of the high-frequency signal PA1, a second high-frequency amplifier circuit PA2 that amplifies the transmission signal input to the input terminal Tx2, and low noise that amplifies the reception signal input from the antenna terminal Ant1 or Ant2 and outputs the amplified signal to the output terminals Rx1 and Rx2 One transmission, one reception type dual band with amplifier circuit LNA It is a line LAN front-end module.

  The common terminal of the first switch circuit SPDT1 is connected to the common terminal of the second switch circuit SPDT2, so that the antenna to be connected is switched and diversity reception is possible. The first branching circuit Dip1 is connected to the second switch circuit SPDT2. The first branching circuit is composed of a low frequency side filter and a high frequency side filter, the first low pass filter LPF1 is connected to the low frequency side filter of the first branching circuit Dip1, and the first detection circuit is further provided. A first high-frequency amplifier circuit PA1 is connected via DET1. The first high-frequency amplifier circuit PA1 is connected to the 2.4 GHz band input terminal Tx1 via the first band-pass filter BPF1. In addition, a second low-pass filter LPF2 is connected to the high-frequency filter of the first demultiplexing circuit, and a second high-frequency amplifier circuit PA2 is further connected via the second detection circuit DET2. The second high-frequency amplifier circuit PA2 is connected to the input terminal Tx2 in the 5 GHz band via the second bandpass filter BPF2. Further, the second branch circuit Dip2 is connected to the second switch circuit SPDT2 via the low noise amplifier circuit LNA. As the low noise amplifier circuit LNA, a wide band low noise amplifier is used, and signals in two bands (2.4 GHz band and 5 GHz band) are amplified by one low noise amplifier circuit. The second demultiplexing circuit is composed of a low frequency side filter and a high frequency side filter, and the third band pass filter BPF3 is connected to the low frequency side filter of the second demultiplexing circuit Dip2, and the third band pass The filter BPF3 is connected to the output terminal Rx1 in the 2.4 GHz band. The fourth band pass filter BPF4 is connected to the high frequency side filter of the second branching circuit Dip2, and the fourth band pass filter BPF4 is connected to the output terminal Rx2 in the 5 GHz band.

  FIG. 8 shows the conductor pattern of each dielectric layer of the high-frequency module including the circuit block shown in FIG. 7 and the conductor pattern of one main surface (back surface) of the multilayer substrate. The multilayer substrate is composed of 15 dielectric layers with conductor patterns formed, and the back surface, which is one main surface of the multilayer substrate, is connected to the radio LAN high-frequency signal input and output terminals and antennas. A terminal group including a plurality of power supply terminals connected to the semiconductor elements of the antenna terminal, the switch circuit, the high-frequency amplifier circuit, and the low-noise amplifier circuit is formed. The terminal arrangement on the main surface is shown in a perspective view from the upper surface side of the laminated substrate for convenience. This terminal arrangement will be further described later.

  Each of the first switch circuit SPDT1 and the first switch circuit SPDT1 is a single pole double throw type switch circuit configured by using a field effect transistor or the like, and a combination of these switches is a DPDT (Dual). (Pole Dual Throw) type switch circuit is configured. A terminal group including power supply terminals Vant1, Vant2, Vtx1, Vlna, Vcc, Vab, and Vgb of the high-frequency signal processing circuit is arranged along the edge of one main surface of the multilayer substrate. The power supply terminals Vant1 and Vant2 are power supply terminals that control path switching of the first switch circuit SPDT1. The power terminals Vtx1 and Vlna are power terminals that control path switching of the second switch circuit SPDT2. For example, when 3.0V is applied to Vant1 and 0V is applied to Vant2, the first switch circuit SPDT1 is controlled to connect between the first antenna terminal Ant1 and the second switch circuit SPDT2, and 0V is applied to Vant1. When 3.0 V is applied to Vant2, the first switch circuit SPDT1 is controlled so as to connect the second antenna terminal Ant2 and the second switch circuit SPDT2. When 3.0 V is applied to Vtx1 and 0 V is applied to Vlna, the second switch circuit SPDT2 is controlled so as to connect the first switch circuit SPDT1 and the high-frequency signal input terminals Tx1 and Tx2 to Vtx1. When 3.0 V is applied to 0 V and Vlna, the second switch circuit SPDT2 is controlled so as to connect between the first switch circuit SPDT1 and the high-frequency signal output terminals Rx1 and Rx2.

  The control voltage of the switch circuit and the control voltage of the low noise amplifier circuit are both equal to 3.0 V, and the power supply terminal Vlna also serves as the control power supply for the low noise amplifier circuit LNA. By sharing a power supply terminal connected to different semiconductor elements and a power supply line connected thereto, the high-frequency component can be reduced in size. As described above, when 3.0 V is applied to Vtx1 and 0 V is applied to Vlna, the second switch circuit SPDT2 is controlled to connect between the first switch circuit SPDT1 and the high-frequency signal input terminals Tx1 and Tx2. Is done. In this case, the voltage applied to the low noise amplifier circuit LNA is 0 V, and the low noise amplifier circuit LNA is turned off. On the other hand, when 0 V is applied to Vtx1 and 3.0 V is applied to Vlna, the second switch circuit SPDT2 is controlled to connect between the first switch circuit SPDT1 and the high-frequency signal output terminals Rx1 and Rx2. . In this case, the voltage applied to the low noise amplifier circuit LNA is 3.0 V, and the low noise amplifier circuit LNA is turned on. That is, by sharing the power supply of the low-noise amplifier circuit LNA and the second switch circuit SPDT2, these operations can be synchronized and the control can be simplified.

  The power supply terminal Vcc is a power supply terminal that shares the power supply of the first high-frequency amplifier circuit PA1 and the second high-frequency amplifier circuit PA2. The power supply terminal Vgb is a power supply terminal that controls ON / OFF of the first high-frequency amplifier circuit PA1. For example, when a voltage of 3.3V is applied to the power supply terminal Vcc and a voltage of 2.8V is applied to Vgb, the first high-frequency amplifier circuit PA1 is turned on, and the first high-frequency amplifier circuit PA1. The high frequency signal input to is amplified. The power supply terminal Vab is a power supply terminal that controls ON / OFF of the second high-frequency amplifier circuit PA2. For example, when a voltage of 3.3 V is applied to the power supply terminal Vcc and a voltage of 2.8 V is applied to Vab, the second high-frequency amplifier circuit PA2 is turned on, and the second high-frequency amplifier circuit PA2 is turned on. The high frequency signal input to is amplified.

  Among the power supply terminals of the terminal group, the power supply lines lvtx, lvlna, lvab, lvgb, lvcc, lvant2 having one end connected to the power supply terminals Vtx, Vlna, Vab, Vgb, Vcc, Vant2 are one dielectric layer (15 layers). In addition, the first power line layer is formed by extending in the plane direction of the dielectric layer. The first detection circuit DET1 and the second detection circuit DET2 share one detection output terminal Vpd, and the line lvpd connected to the detection output terminal Vpd is also the one dielectric layer (15 layers). Is formed. A first ground electrode GND1 that overlaps at least a part of the power supply line in plan view is disposed on the main surface side in the stacking direction across the first power supply line layer, and in plan view on the opposite side to the main surface in the stacking direction. A second ground electrode GND2 that overlaps at least a part of the power supply line is disposed. If the first ground electrode GND1 is formed on one main surface (back surface) on which the terminal group is formed as in the configuration of FIG. 8, a separate dielectric layer is disposed to form the first ground electrode GND1. Therefore, the high-frequency module can be reduced in size. The second ground electrode is arranged so as to sandwich the power supply line layer in the stacking direction without interposing a layer on which another conductor pattern is formed. The configuration of the portion from the first power supply line layer to the power supply terminal will be described later. The conductive patterns relating to the signal lines of the high-frequency signals of the switch circuits SPDT1, SPDT2, the high-frequency amplifier circuits PA1, PA2, and the low-noise amplifier circuit LNA are different from the first power supply line layer across the second ground electrode GND2. Arranged from the 13th layer on the opposite side to the upper layer. That is, the high-frequency signal processing circuit is disposed on the opposite side of the power supply line layer with the second ground electrode GND2 interposed therebetween, except for the portion related to the power supply line and the wiring portion for connecting to the terminal.

  A plurality of power supply lines of the first and second switch circuits, the first and second high frequency amplifier circuits, and the low noise amplifier circuit, each having one end connected to a power supply terminal, have via electrodes formed in the dielectric layer. The high frequency signal processing circuit is connected to a semiconductor element. In the configuration shown in FIG. 8, the IC chip of the switch including the transistor as a semiconductor element, the high frequency amplifier, and the low noise amplifier is mounted on the surface layer (first layer). Alternatively, it may be arranged in the laminate. The power supply lines connected to the power supply terminals Vtx, Vlna, and Vant2 have via electrode rows formed so as to overlap each other from the 14th layer to the 4th layer as viewed from the stacking direction. The power line pattern formed on the power line layer of the 15th layer is connected to the semiconductor element on the surface layer through the via electrode row. The power supply line connected to the power supply terminal Vant1 has a via electrode array formed so as to overlap from the 12th layer to the 4th layer when viewed from the stacking direction. The three via electrode rows of the power supply line connected to the power supply terminals Vtx, Vlna, Vant2 are four layers including the via electrode row of the power supply line connected to the power supply terminal Vant1 in the 14th to 4th layers. The via electrode rows are close to each other in the 12th to 4th layers without interposing other conductor patterns. The number of power supply lines related to adjacent via electrode rows is not limited to three or four, and may be at least two. In the configuration shown in FIG. 8, via electrode arrays are formed so as to overlap 11 or 9 continuous dielectric layers as viewed from the stacking direction, but the two or more adjacent dielectric layers are viewed from the stacking direction. As long as the via electrode rows are formed so as to overlap each other.

  The manner in which the via electrode rows of the power supply line are close will be further described with reference to FIG. 1A and 1B are schematic views in which a portion of a stacked body including two via electrode rows of a power supply line is extracted. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view of a plane including via electrode rows. In FIG. 1B, via electrodes are formed so as to overlap each other as viewed from the stacking direction over four adjacent dielectric layers. The two via electrode arrays 2 are close to each other without interposing other conductor patterns. The other conductor pattern is an electrode other than the conductor pattern related to the via electrode, for example, a ground electrode, an electrode of a high-frequency signal line, or the like. The other conductor pattern does not include a conductor pattern related to the via electrode like a pad pattern formed around the via electrode for forming the via electrode. On the line segment connecting the centers of the via electrodes shown by the dotted line in FIG. 1A, no other conductor pattern is arranged in the plane direction along the layer of the dielectric layer 1. The other conductor pattern and the via electrode array need to be spaced apart from each other to avoid mutual interference. By removing other conductor patterns from the line connecting the centers of the via electrodes and bringing the via electrode rows close to each other, the space necessary for forming the via electrode rows can be reduced. In addition, it contributes to miniaturization of a portion related to a via electrode group connected to the ground and a strip-like conductor pattern, which is provided around the via electrode row for shielding, which will be described later. The distance between the via electrodes is preferably 0.08 mm or more from the viewpoint of a problem caused by a short circuit between the electrodes. However, if the interval is too large, the high-frequency component becomes large, and therefore the interval between the via electrodes is preferably 0.15 mm or less. The via electrodes constituting the via electrode array may overlap with each other when viewed from the stacking direction as long as electrical conduction is ensured in the via electrode portion, but manufacturing errors are allowed. However, as shown in FIG. 1, it is more preferable that it overlaps substantially seeing from the lamination direction.

  Since the power supply lines are less affected by interference, the via electrodes can be brought close to not only the power supply lines connected to the same semiconductor element but also the power supply lines connected to different semiconductor elements. The configuration in which vias of power supply lines connected to different semiconductor elements are close to each other is particularly suited to miniaturization of high-frequency components including a plurality of types and multiple types of semiconductor elements as high-frequency signal processing circuits become more functional and highly integrated. It is valid. Therefore, not only when the via electrode rows are brought close to each other, but also when the via electrodes are brought close to each other in at least one dielectric layer, there is an effect of sufficient miniaturization. In the high-frequency module of FIG. 8, the via electrode row Rant1 of the power supply line from the power supply terminal Vant1 and the via electrode row Rant2 of the power supply line from the power supply terminal Vant2 connected to the semiconductor element of SPDT1 do not pass through other conductor patterns. Is close to. Similarly, the via electrode row Rtx of the power supply line from the power supply terminal Vtx and the via electrode row Rlna of the power supply line from the power supply terminal Vlna that are connected to the semiconductor element of the SPDT 2 are adjacent to each other without passing through other conductor patterns. ing. The via electrode of the power supply line connected to the semiconductor element of SPDT1 and the via electrode of the power supply line connected to the semiconductor element of SPDT2 are close to each other without any other conductor pattern. In the configuration of FIG. 8, via electrodes of these power supply lines connected to different semiconductor elements are arranged as via electrode arrays in the 12th to 4th layers without interposing other conductor patterns.

  A state in which the four via electrode arrays are close to each other will be described with reference to FIG. 2A and 2B are schematic views in which a portion including four via electrode rows of a power supply line is extracted from the stacked body, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view of a plane including via electrode rows. In FIG. 2B, via electrodes are formed so as to overlap with each other as viewed from the stacking direction over four adjacent dielectric layers. The four via electrode rows 2 are arranged at the vertices of a square when viewed from the stacking direction. No other conductor pattern is arranged on the line connecting the adjacent vertices and the diagonal line shown by the dotted line in FIG. 2, and the four via electrode rows are close to each other without passing through the other conductor pattern. That is, no other conductor pattern is formed on the polygon formed by the via electrode array when viewed from the stacking direction. The number of adjacent via electrodes or via electrode arrays is not limited in this way, but if the number of via electrodes or via electrode arrays in the power supply line is constant, the smaller the number of adjacent via electrodes or the like, the smaller the number. Therefore, it is preferable to have a configuration in which four or more via electrodes or via electrode arrays are close to each other as in the high-frequency module of FIG.

  In the configuration shown in FIG. 8, in the sixth to eleventh dielectric layers in which via electrodes are arranged close to each other without any other conductor pattern, vias in which the plurality of adjacent via electrodes are connected to the ground. Surrounded by electrode groups. 3A and 3B are schematic views in which a portion including four via electrode rows of a power supply line is extracted from the laminated body, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view of a surface including the via electrode rows. A via electrode group 3 connected to the ground electrode 4 is formed in a quadrangular shape so as to surround the periphery of the four via electrode rows 2 arranged at each vertex of the square as viewed from the stacking direction. The via electrode group 3 functions as a shield via and prevents interference between the power supply line and the high-frequency signal line. In the configuration of FIG. 8, the via electrode group is connected to planar ground electrodes formed in the fifth and twelfth layers.

  In addition, among the sixth to eleventh dielectric layers in which the via electrode group is formed, vias connected to the ground electrode are provided on the surfaces of the sixth layer, the seventh layer, the ninth layer, and the eleventh layer. The via electrodes of the electrode group are connected to each other by a strip-like conductor pattern to form an annular shield electrode as shown in FIG. 4A and 4B are schematic views in which a portion including four via electrode rows of the power supply line is extracted from the laminated body, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view of a surface including the via electrode rows. In the configuration shown in FIG. 4, each via electrode of the via electrode group 3 connected to the ground electrode 4 shown in FIG. 3 is connected by a strip-shaped conductor pattern to form an annular shield electrode having a rectangular outer shape. . The outer shape of the annular shield electrode is not limited to a quadrangle, but may be a polygon, a circle, or an ellipse. From the viewpoint of space efficiency, the outer shape formed by the via electrode group 3 or the outer shape of the shield electrode is preferably substantially similar to the outer shape formed by the via electrode row of the power supply line. In addition, even if a part of via electrodes in the via electrode group 3 are connected by a strip-shaped conductor pattern to form a shield electrode, a predetermined shielding effect can be obtained, but the entire via electrode group is connected and continuous. More preferably, it is formed in an annular shape. The configuration in which the annular shield electrode is formed may be applied to a configuration having adjacent via electrodes, or may be applied to a configuration having adjacent via electrode rows.

  A plurality of power supply lines may be provided independently, but the high frequency module can be reduced in size by sharing the power supply. As described above, in the high-frequency circuit shown in FIG. 7, the power supply terminal Vlna related to the control of the switch circuit also serves as the control power supply terminal of the low noise amplifier circuit LNA. As shown in FIG. 8, the power supply line connected to the power supply terminal Vlna is connected to the 15th power supply line layer, via the via electrode array Rlna extending from the 14th layer to the 4th layer, and to the second layer. It branches into two lines and is connected to the IC chip of the switch circuit and the IC chip of the low noise amplifier mounted on the surface layer. In the fourth layer, the position of the via electrode is shifted in the plane direction of the layer through the conductor pattern. Therefore, from the power supply terminal Vlna to the branch point of the power supply line of the second layer, a common line portion that serves as both the control power supply line of the semiconductor element of the switch circuit and the power supply line of the semiconductor element of the low noise amplifier circuit is configured. . The configuration of the common line portion of the power supply line will be further described with reference to FIGS. The common line portion of the power supply line is constituted by the power supply terminal Vlna or a line to the power supply line layer close to the power supply terminal Vlna, and the power supply line layer branches the power supply line of the switch circuit and the power supply line of the low noise amplifier circuit. Also good. In this case, as shown in FIG. 5, in the vicinity of the IC chip 8 having semiconductor elements, a plurality of via electrode arrays 2 of power supply lines are arranged corresponding to the plurality of semiconductor elements, and the conductor pattern 6 is used in the vicinity of the surface layer. Then, it is connected to the electrode pad 7 on the surface layer via the via electrode shifted to a desired position. The connection of the power supply line not provided with the common line portion to the semiconductor element may be performed as shown in FIG. In the configuration of FIG. 5, the electrode pad 7 and the terminal electrode of the IC chip 8 are connected by wire bonding. The IC chip 8 may be flip-chip mounted. In addition, the conductor pattern 6 in FIG. 5 may be omitted and the via electrode array may be directly connected to the surface electrode pad.

  In the configuration shown in FIG. 6A with respect to the configuration in FIG. 5, the common line portion of the power supply line extends from the power supply terminal Vlna to the end of the via electrode array on the semiconductor element side. When the switch circuit and the low-noise amplifier circuit are provided as the high-frequency signal processing circuit, at least one of the plurality of power supply lines doubles as the control power supply line of the semiconductor element of the switch circuit and the power supply line of the semiconductor element of the low-noise amplifier circuit By adopting the configuration having the common line portion, it is possible to reduce the conductor pattern and via electrode required for the power supply line, and to make the high-frequency module smaller and lower in cost. As shown in FIG. 6A, the end portion of the common line portion opposite to the power supply terminal (end portion of the via electrode array 9) is arranged closer to the semiconductor element in the stacked body, and the end portion is arranged. By branching using the conductor pattern 10, the conductor pattern and via electrode required for the power supply line can be further reduced. 6A and 8 is provided on the dielectric layer (second layer) adjacent to the surface layer on which the IC chip 8 having the semiconductor element is mounted, and the common line portion of FIG. Maximizes the effect of the installation. As described above, in the high-frequency module shown in FIGS. 7 and 8, the low-noise amplifier circuit LNA uses a wideband low-noise amplifier capable of amplifying signals in two frequency bands, and has the configuration including the common line section. Together, the power supply line portion related to the switch circuit and the low noise amplifier circuit is greatly simplified and miniaturized.

  When the common line section includes at least one of a plurality of switch circuits, a plurality of high frequency amplifier circuits, and a plurality of low noise amplifier circuits, the semiconductor elements of the plurality of switch circuits, the semiconductor elements of the plurality of high frequency amplifier circuits, or You may form with respect to the power supply line of the semiconductor elements of a some low noise amplifier circuit. For example, in the high-frequency circuit shown in FIG. 7, the first and second high-frequency amplifier circuits share the power supply. The power supply terminal Vcc formed on the back surface of FIG. 8 is shared, and the power supply line connected to the power supply terminal Vcc is a 15th power supply line layer, a via electrode array extending from the 14th layer to the 4th layer. Via Rcc, it branches at the second layer and is connected to the IC chip of the high-frequency amplifier circuit mounted on the surface layer. The semiconductor elements of the first and second high frequency amplifier circuits are accommodated in one IC chip. A common line portion of the power supply line extends from the power supply terminal Vcc to the end of the via electrode array Rcc on the semiconductor element side (second layer). As shown in FIG. 8, in the high-frequency amplifier circuit, the via electrode row of the power supply line connected to the power supply terminal Vcc related to the power supply is not adjacent to the via electrode row of other power supply lines, and is formed independently. However, in order to prevent interference with the high-frequency signal line, a via electrode group connected to the ground, and further, a band-shaped shield electrode in which the via electrodes of the via electrode group are connected to each other are formed.

  Another embodiment according to the common line portion will be described with reference to FIG. 6B and FIG. As shown in FIG. 6B, an IC chip 8 having a semiconductor element is mounted on the other principal surface (surface layer) of the multilayer substrate, and the third ground electrode 11 is disposed on the other principal surface side in the multilayer substrate. Is arranged. One end of the common line portion is connected to the power supply terminal as described above, and the end portion of the via electrode row 9 which is the other end of the common line portion is an IC chip 8 having a semiconductor element and a third ground electrode 11. The second power supply line layer formed between the two branches to a line connected to each semiconductor element. A second dielectric layer is assigned to the second power supply line layer, and a conductor pattern for wiring the power supply line is formed. The via electrode row 9 penetrates through one electrode non-forming portion formed so as to cut out the third ground electrode 11. The portion where the conductor pattern of the power supply line is increased and arranged on the upper layer side of the ground electrode, thereby suppressing interference with the high-frequency signal line of the high-frequency signal processing circuit formed on the lower layer side of the ground electrode. be able to. In the configuration shown in FIG. 8, a planar third ground electrode is formed over the entire third layer, and a power line is wired in the in-plane direction of the layer between the surface layer and the third layer. A second power supply line layer is formed. Further, no other dielectric layer is disposed between the second power line layer, the surface layer on which the semiconductor element is mounted, and the third layer on which the third ground electrode is formed, so that the size is reduced. . The via electrode row Rlna connected to the shared power supply terminal Vlna changes the position of the via electrode in the fourth layer and penetrates through the third electrode layer formed so as to cut out the third layer ground electrode. The common line portion branches at the second layer.

  Similarly, the other end of the common line portion of the power supply line connected at one end to the power supply terminal Vcc shared by the first and second high frequency amplifier circuits is also branched to a line connected to each semiconductor element in the second layer. doing.

  Another embodiment according to the common line portion will be described with reference to FIG. 6C and FIG. The configuration on the surface layer side where the IC chip having the semiconductor element is mounted is the same as the configuration shown in FIG. In the configuration of FIG. 6C, the conductor pattern 14 of the plurality of power supply lines, one end of which is connected to the power supply terminal 15, is formed on one dielectric layer to form a power supply line layer, and the stacking direction with the power supply line layer interposed therebetween. A first ground electrode 13 that overlaps at least a part of the plurality of power supply lines in plan view is disposed on the main surface side, and at least one of the plurality of power supply lines in plan view is disposed on the side opposite to the main surface in the stacking direction. A second ground electrode 12 that overlaps the portion is disposed. The high-frequency signal processing circuit is disposed on the opposite side of the power supply line layer with the second ground electrode 12 interposed therebetween. In FIG. 6C, the conductor pattern 14 of the power supply line connected to the power supply terminal 15 is a common line portion that serves as both the control power supply line of the semiconductor element of the switch circuit and the power supply line of the semiconductor element of the low noise amplifier circuit. Although the case is illustrated, other power supply lines can be formed in the power supply line layer.

  As shown in FIG. 8, a terminal group including an input terminal for an RF signal, an output terminal, and a power supply terminal for the RF signal processing circuit is arranged in a rectangular frame shape on one main surface along the outer edge of the main surface. It is formed and arranged side by side with high density while facilitating connection with external terminals. The power supply terminal formed on the surface of the multilayer substrate may be formed on the side surface, but is preferably formed on one main surface from the viewpoint of isolation between the signal line and the power supply line. In the figure, the input terminal, output terminal and antenna terminal of the high-frequency signal are collectively denoted as RF. Further, a solid rectangular first ground electrode is formed inside the terminal group so as to fill the inside of the terminal group formed in the rectangular frame shape on the one main surface. . In the configuration of FIG. 8, the first ground electrode GND1 is separated from the terminal group at substantially the same interval as the terminal interval of the terminal group. The first ground electrode may be formed in the laminated substrate, but is preferably formed on one main surface (back surface) from the viewpoint of miniaturization. Further, a part of the power supply terminals excluding the power supply terminal Vant1 overlap the second ground electrode GND2 in plan view. By overlapping the second ground electrode GND2 in a plan view as viewed from the stacking direction, interference between these power supply terminals and the high-frequency signal processing circuit formed above the second ground electrode GND2 is suppressed. be able to.

  In the configuration shown in FIG. 8, the power supply line of the high frequency signal processing circuit and the power supply line of the control power supply are formed in the fifteenth layer which is the power supply line layer. In the embodiment of FIG. Power supply lines lvtx, lvlna, lvab, lvgb, lvcc, and lvant2 having one ends connected to Vlna, Vab, Vgb, Vcc, and Vant2 are formed. The power line connected to the electrode terminal formed on the back surface by the via electrode provided in the sixteenth layer is formed so as to be away from the power terminal while forming a bent portion or a plane electrode portion in the power line layer. Has been. The other end of the power supply line is connected to the high-frequency signal processing circuit through a through hole formed at a position separated from the power supply terminal. By using the power supply line layer partitioned from the signal line of the high-frequency signal processing circuit by the ground electrode, the freedom of wiring of the power supply line is remarkably improved while suppressing interference with the signal line. For example, since the power supply terminals are arranged along the outer edge of the back surface, the larger the number of power supply terminals, the larger the interval. In order to realize the configuration in which the via electrode rows shown in FIGS. 1 to 4 are brought close to each other, it is necessary to make the power supply line connected to the power supply terminal significantly close, but the configuration in which the power supply line layer is provided is suitable in such a case. is there. Such a configuration related to the first power supply line layer is not limited to the case where the via electrodes of a plurality of power supply lines are brought close to each other, and can be widely applied. For example, when configuring a common line portion that serves as both a control power supply line of a semiconductor element of a switch circuit and a power supply line of a semiconductor element of a low noise amplifier circuit, or a semiconductor element of a plurality of switch circuits, a semiconductor of a plurality of high frequency amplifier circuits The present invention can also be applied to the case where a common line portion that also serves as a power supply line between elements or between semiconductor elements of a plurality of low-noise amplifier circuits is configured. As shown in FIG. 8, in the layer where the high-frequency signal processing circuit above the second ground electrode GND2 is formed, the power supply line may be further routed as necessary.

  Since the power supply line can be freely wired in the first power supply line layer, the first power supply line layer is used to form a choke coil in front of the high frequency signal processing circuit to remove high frequency noise in the power supply line. be able to. Further, in the embodiment of FIG. 8, in the fifteenth layer that is the first power supply line layer sandwiched between the first ground electrode and the second ground electrode, the power supply terminals Vlna, Vant2, Vtx, and Vcc are respectively connected. A planar capacitor electrode is formed in the middle of the power supply lines lvlna, lvant2, lvtx, and lvcc, and a noise-cutting capacitor is formed between the capacitor electrode and the ground electrode. By using the power supply line layer sandwiched between the ground electrodes, a large capacitor can be formed without being restricted by interference with the signal line. In addition, since a common capacitor, which serves as both the control power supply line for the semiconductor element of the switch circuit SPDT2 and the power supply line for the semiconductor element of the low noise amplifier circuit LNA, is connected to one capacitor, one end of which is grounded. Can be shared, contributing to the miniaturization of high-frequency modules.

  The via electrode may be formed through a notch portion or a circular electrode non-forming portion of the second ground electrode and connected to the high-frequency signal processing circuit. Further, the via electrode adjacent to the power supply line is also arranged in one electrode non-formation portion formed so as to cut out the ground electrode in the dielectric layer provided with the planar ground electrode. Since the second ground electrode is not formed in the portion where the via electrode is formed, it is preferable that the position where the portion is projected has a ground electrode from the viewpoint of preventing interference with the outside. That is, the via electrode is preferably formed in a region overlapping the first ground electrode GND1 in plan view. Further, in the embodiment shown in FIG. 8, a ground electrode is arranged at a portion facing the via electrode of the power supply line or the end portion in the stacking direction of the via electrode row. The end portion in the stacking direction of the via electrode or via electrode row of the power supply line is, in other words, a portion connected to the power supply line wired in the in-plane direction of the layer. By providing a ground electrode without disposing a conductor pattern other than the ground electrode in a portion of the adjacent dielectric layer facing the portion, interference with a signal line or the like can be suppressed. It is more preferable to apply such a configuration to all the via electrodes and via electrode rows of the power supply line, except for the case where they are formed on the dielectric layers on both main surfaces of the power supply line. Such a configuration can be widely applied when the power supply line is wired in the stacked body. Also, some of the power supply terminals are not connected by the line electrodes on the power supply line layer, but are directly connected to the high frequency signal processing circuit without changing the position in the horizontal direction. ing. In this way, since the position where the power supply line is connected to the high-frequency signal processing circuit can be designed freely, the degree of design freedom regarding the arrangement of the power supply line is dramatically improved.

  By connecting the via electrode group shown in FIG. 3 or FIG. 4 to the second ground electrode adjacent to the first power supply line layer and / or the third ground electrode adjacent to the second power supply line layer, Isolation between the signal line of the high-frequency signal processing circuit and the power supply line becomes more reliable. In the embodiment shown in FIG. 8, a part of the via electrode group surrounding the four via electrode rows is a second ground electrode adjacent to the first power supply line layer or a third ground electrode adjacent to the second power supply line layer. Connected to the ground electrode. The ground electrodes are also provided on the fifth layer and the twelfth layer.

  Next, as another example of the high-frequency signal processing circuit applicable to the high-frequency component according to the present invention, a switch circuit of SPnT (Single Pole n throw) type or DPnT type (Dual Pole n throw) (n is a natural number of 3 or more) FIG. 9 shows a high-frequency signal processing circuit having a low-noise amplifier circuit connected to at least two switching terminals of the switch circuit. FIG. 9 is a circuit block diagram of a front-end module for a dual-band wireless LAN using the 2.4 GHz band and the 5 GHz band. The front-end module shown in FIG. 9 is a high-frequency signal processing circuit, which is a single-pole, three-throw switch that switches the connection between an antenna terminal Ant3 connected to an antenna and high-frequency signal input terminals Tx3 and Tx4 or output terminal Rx3 and output terminal Rx4. Type switch circuit SP3T, a third high-frequency amplifier circuit PA3 that amplifies the transmission signal input to the high-frequency signal input terminal Tx3, and a fourth high-frequency amplifier circuit PA4 that amplifies the transmission signal input to the input terminal Tx4 The first low noise amplifier circuit LNA1, which amplifies the 2.4 GHz band received signal input from the antenna terminal Ant and outputs it to the output terminal Rx3, and amplifies the 5 GHz band received signal and outputs the amplified signal to Rx4. 1 low-noise amplifier circuit LNA2 and a single-band single-reception dual-band wireless LAN front end Module. However, the configuration of the transmission path and the arrangement of the filters are not limited to the configuration shown in FIG.

  The common terminal of the switch circuit SP3T is connected to the antenna terminal Ant, and the third branching circuit Dip3 on the transmission side is connected to one of the switching terminals. The third branching circuit is composed of a low frequency side filter and a high frequency side filter, and a third high frequency amplifier circuit PA3 is connected to the low frequency side filter of the third branching circuit Dip1. The third high-frequency amplifier circuit PA3 is connected to the 2.4 GHz band input terminal (transmission terminal) Tx3 via the fifth bandpass filter BPF5. The fourth high-frequency amplifier circuit PA4 is connected to the high-frequency filter of the third branching circuit Dip3. The fourth high-frequency amplifier circuit PA4 is connected to an input terminal (transmission terminal) Tx4 in the 5 GHz band via a sixth bandpass filter BPF6. In addition, the first low-noise amplifier circuit LNA1 is connected to the other switching terminal of the switch circuit SP3T via the seventh band-pass filter BPF7. An output terminal (reception terminal) Rx3 is further connected to the first low noise amplifier circuit LNA1. Furthermore, the second low-noise amplifier circuit LNA2 is connected to the other switching terminal of the switch circuit SP3T via the eighth band-pass filter BPF8. An output terminal (receiving terminal) Rx4 is further connected to the second low noise amplifier circuit LNA2.

  The switch circuit SP3T is configured using a field effect transistor or the like. The power supply terminals Vswtx, Vlna2, and Vlna5 are power supply terminals that control path switching of the switch circuit SP3T. For example, when 3.0 V is applied to Vswtx and 0 V is applied to Vlna2 and Vlna5, the switch circuit SP3T is controlled to connect between the antenna terminal Ant and the input terminals Tx3 and 4, and 3.0 V, Vswtx and Vlna5 are connected to Vlna2. When 0V is applied to the switch circuit SP3T, the switch circuit SP3T is controlled to connect between the antenna terminal Ant and the output terminal Rx2, and when 3.0V is applied to Vlna5 and 0V is applied to Vswtx and Vlna2, the switch circuit SP3T is connected to the antenna terminal Ant. And the output terminal Rx5.

  Further, the power supply terminal Vlna2 also serves as a control power supply for the low noise amplifier circuit LNA2, and the power supply terminal Vlna5 also serves as a control power supply for the low noise amplifier circuit LNA5. By sharing a power supply terminal connected to different semiconductor elements and a power supply line connected thereto, the high-frequency component can be reduced in size. As described above, when 3.0 V is applied to Vlna2 and 0 V is applied to Vswtx and Vlna5, the switch circuit SP3T is controlled to connect between the antenna terminal Ant and the output terminal Rx2. In this case, the applied voltage to the low noise amplifier circuit LNA2 is 0V, the applied voltage to the low noise amplifier circuit LNA5 is 3.0V, the low noise amplifier circuit LNA2 is turned off, and the low noise amplifier circuit LNA5 is turned on. . On the other hand, when 3.0 V is applied to Vlna5 and 0 V is applied to Vswtx and Vlna2, the switch circuit SP3T is controlled to connect the antenna terminal Ant and the output terminal Rx5. In this case, the applied voltage to the low noise amplifier circuit LNA2 is 3.0V, the applied voltage to the low noise amplifier circuit LNA5 is 0V, the low noise amplifier circuit LNA2 is in the on state, and the low noise amplifier circuit LNA5 is in the off state. . By sharing the power supply of each low noise amplifier circuit LNA1,2 and the control power supply for switching to the switching terminal to which the low noise amplifier circuit LNA1,2 is connected, these operations are synchronized, Simplification can be achieved. By such sharing, a common line portion is formed which also serves as a power supply line of the semiconductor element of each low noise amplifier circuit and a control power supply line for switching to the switching terminal to which the low noise amplifier circuit is connected. The common line portion only needs to have the configuration of the power supply lines shown in FIGS. 1 to 6 described above as at least a part of the plurality of power supply lines.

  Note that the high-frequency processing circuit shown in FIG. 9 is not limited to the configuration of the power supply line and can be widely applied as a high-frequency circuit for switching between transmission and reception. For example, a high-frequency circuit used in a multiband radio apparatus that performs radio communication selectively using a first frequency band and a second frequency band that is higher than the first frequency band, the antenna and An antenna terminal to be connected; a first input terminal to which a transmission signal of the first frequency band is input; a second input terminal to which a transmission signal of the second frequency band is input; and the first A first output terminal from which a reception signal in the frequency band is output, a second output terminal from which the reception signal in the second frequency band is output, a path of the transmission signal and the reception signal connected to the antenna terminal An SPnT type or DPnT type (n is a natural number greater than or equal to 3) switch circuit, a first power amplifier circuit provided between the switch circuit and the first input terminal, and the switch A second power amplifier circuit provided between a circuit and the second input terminal; a first low noise amplifier circuit provided between the switch circuit and the first output terminal; A second low noise amplifier circuit circuit provided between the switch circuit and the second output terminal, and a control power source for the switch circuit and a control power source for the first low noise amplifier circuit; Is preferably used, and a high frequency circuit in which another control power supply of the switch circuit and a control power supply of the second low-noise amplifier circuit are shared is suitable. Such a high-frequency circuit shares the control power supply, thereby reducing the control terminals and the control power supply line, thereby simplifying the control and reducing the size of the components constituting the circuit, and also has the following effects. Conventionally, a branching circuit is used to branch the reception path of the first frequency band and the reception path of the second frequency band, and the low-noise amplifier circuit for the first frequency band and the second frequency are used for the branching circuit. It is common to connect a low-noise amplifier circuit for the band. However, in this configuration, when a signal in the second frequency band is received, the interference signal in the first frequency band generates a harmonic in the low-noise amplifier circuit for the first frequency band, and then passes through the branching circuit. In some cases, the signal is amplified by the low-noise amplifier for the second frequency band, which affects the reception of the second frequency band. This problem is particularly noticeable when the n-fold frequency of the first frequency band matches the second frequency band. On the other hand, in the configuration in which the switch circuit branches the reception path of the first frequency band and the reception path of the second frequency band, the isolation between the paths can be secured about 25 dB in a wide band. The influence of harmonics can be suppressed. In addition, since the number of demultiplexing circuits on the input side of the low noise amplifier circuit can be reduced, it contributes to improvement in reception sensitivity.

  The switch circuit may adopt SPnT or DPnT depending on the required function. If DPnT is employed, diversity reception can be supported. Also, n corresponding to the number of switching terminals may be selected according to the required function. In the case of dual band communication, an SP3T type switch circuit may be used if branching of the frequency band on the reception side is performed by a switch circuit and branching of the frequency band on the transmission side is performed by a demultiplexing circuit. Further, when branching of the frequency band on the transmission side is performed by a switch circuit, an SPnT type switch circuit having n of 4 or more may be used when there are more frequency bands such as a triple band. Further, a configuration including a plurality of SPnT-type or DPnT-type switch circuits may be used as the high-frequency processing circuit. Furthermore, it is possible to set Pole to 3 or more.

Next, an example in which the high-frequency component according to the present invention is configured as a component using a ceramic multilayer substrate will be described. The ceramic laminated substrate which comprises high frequency components having patterns and circuits as shown in FIG. 8 in each dielectric layer is made of, for example, ceramic dielectric material LTCC (Low Temperature Co-fired Ceramics) capable of low temperature sintering at 1000 ° C. or lower. A predetermined electrode pattern is formed on a green sheet having a thickness of 10 μm to 200 μm by printing a conductive paste such as Ag or Cu having a low resistivity, and a plurality of green sheets are laminated appropriately and sintered. Can be manufactured. As the dielectric material, for example, Al, Si, Sr as a main component, Ti, Bi, Cu, Mn, Na, K as a subcomponent, Al, Si, Sr as a main component, Ca, Pb, A material containing Na and K as a multicomponent, a material containing Al, Mg, Si, and Gd, and a material containing Al, Si, Zr, and Mg are used, and a material having a dielectric constant of about 5 to 15 is used. In addition to the ceramic dielectric material, it is also possible to use a resin multilayer substrate or a multilayer substrate made of a composite material obtained by mixing a resin and ceramic dielectric powder. Further, the ceramic substrate is made of HTCC (high temperature co-fired ceramic) technology, the dielectric material is mainly Al ₂ O ₃ , and the transmission line is a metal conductor that can be sintered at a high temperature such as tungsten or molybdenum. You may comprise as.

  When high-frequency components such as a front-end module are configured with this ceramic multilayer substrate, pattern electrodes for an inductance element, a capacitor element, a wiring line, and a ground electrode are appropriately configured in each layer. Via electrodes are formed to form a desired circuit. Mainly, a circuit portion that can be configured by an LC circuit is configured. A demultiplexing circuit, a band-pass filter circuit, a low-pass filter circuit, and a balance-unbalance conversion circuit are mainly configured inside the ceramic multilayer substrate. Moreover, a chip element mounted on the upper surface of the ceramic multilayer substrate may be used as a part of the elements of each circuit.

  In addition, a single-pole double-throw SPDT switch or diode switch, a semiconductor element for a transmission-side amplifier circuit PA, a reception-side low-noise amplifier circuit LNA, or the like is mounted on the ceramic multilayer substrate. And it connects to a ceramic laminated substrate with a wire bonder, LGA, BGA, etc., and the high frequency circuit of this invention can be comprised as a small high frequency component. Of course, the component mounted on the ceramic multilayer substrate and the built-in element of the ceramic multilayer substrate are connected to form a predetermined circuit, and a high frequency circuit is configured. In addition to the semiconductor elements described above, elements such as a chip capacitor, a chip resistor, and a chip inductor are appropriately mounted on the ceramic multilayer substrate. These mounting elements can be appropriately selected from the relationship with the elements incorporated in the ceramic laminated substrate.

  Next, a high-frequency component having the pattern / circuit configuration shown in FIG. 8 was produced. An Ag electrode is formed on a ceramic sheet, laminated and integrated, and fired at about 900 ° C. to produce a laminated substrate. A semiconductor element for a switch circuit, a semiconductor element for a high frequency amplifier circuit, and a semiconductor for a low noise amplifier are formed on the laminated substrate. A device, chip capacitor, chip resistor and chip inductor were mounted and integrated to obtain a high-frequency component. The dimension of the obtained high frequency component is 5.4 * 4.0 * 1.2 mm. The diameter of the via electrode was 0.12 mm, and the distance between adjacent via electrodes was 0.15 mm. The via electrode of the power line needs to be separated from other conductor patterns by 0.08 mm or more. The high-frequency circuit shown in FIG. 7 requires nine power supply lines, but forms a common line portion that serves as both the control power supply line of the semiconductor element of the switch circuit and the power supply line of the semiconductor element of the low-noise amplifier circuit. 1. A common line portion that also serves as a power supply line for the power supply of the second high-frequency amplifier circuit is formed, and via electrodes are placed close to each other, so that the area occupied in the plane of the dielectric layer compared to the case where they are separately arranged Was reduced by up to 65%. In addition, the interference between the power line and the RF circuit is reduced, and the characteristics of the front end module are improved.

  Further, by using the above-described high-frequency component, it is possible to configure a small communication device, which contributes to cost reduction and size reduction of the communication device. Further, the high-frequency component can be widely applied to portable devices, personal computers, and the like having a wireless communication function.

RF: signal terminal G: ground terminal GND1: first ground electrode GND2: second ground electrode GND3: third ground electrode GND: ground electrode Vab, Vgb, Vcc: power supply terminals Vtx1, Vlna, Vant1, Vant2: power supply Terminals Vswtx, Vlna2, Vlna5: Power supply terminals lvab, lvgb, lvcc, lvtx1, lvlna1: Power supply line lvant1, lvant2: Power supply line Ant1, Ant2, Ant: Antenna terminals Tx1, Tx2, Rx3, Tx3, Rx4 , Rx4: output terminals DET1, DET2: detection circuits Dip1, Dip2, Dip3: demultiplexing circuits BPF1-8: band pass filter circuits LPF1, LPF2: low pass filter circuits PA1-4: high frequency amplifier circuit LNA, LNA1, LNA2: Low noise amplifier circuit SPDT1, SPDT2, SP3T: Switch circuit 1: Dielectric layer 2: Via electrode array 3: Via electrode group 4, 11, 12, 13: Ground electrode 5: Conductor pattern (shield electrode) )
6, 10, 14: Conductor pattern 7: Electrode pad 8: IC chip 9: Via electrode array 15: Power supply terminal

Claims (11)

A high-frequency component comprising a high-frequency signal processing circuit for processing a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers formed with a conductor pattern, the input terminal for the high-frequency signal, the output terminal, and the high-frequency signal processing A terminal group including a plurality of power supply terminals of the circuit is formed on one main surface of the multilayer substrate, and the dielectric layer constituting the multilayer substrate includes an inductance element, a capacitor element, a wiring line, And a plurality of power supply lines, each having one end connected to the power supply terminal, and at least one semiconductor included in the high-frequency signal processing circuit via via electrodes formed in a dielectric layer. At least two power lines among the plurality of power lines are connected to the element, respectively, at positions separated from the power terminals when viewed from the stacking direction. And via electrode rows formed so as to overlap two or more adjacent dielectric layers when viewed from the stacking direction, and the via electrode rows of the at least two power supply lines are connected to each other between the adjacent dielectric layers. In the dielectric layer adjacent to each other without passing through the conductor pattern, the via electrodes of the plurality of power supply lines are surrounded by a via electrode group connected to the ground . High frequency parts characterized by A high-frequency component comprising a high-frequency signal processing circuit for processing a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers formed with a conductor pattern, the input terminal for the high-frequency signal, the output terminal, and the high-frequency signal processing A terminal group including a plurality of power supply terminals of the circuit is formed on one main surface of the multilayer substrate, and the dielectric layer constituting the multilayer substrate includes an inductance element, a capacitor element, a wiring line, And a plurality of power supply lines, each having one end connected to the power supply terminal, and at least one semiconductor included in the high-frequency signal processing circuit via via electrodes formed in a dielectric layer. The via electrodes of the plurality of power supply lines are connected to the element, and at least one dielectric layer of the plurality of dielectric layers is viewed from the stacking direction. In the dielectric layer where the via electrodes of the plurality of power supply lines are close to each other at a position separated from the power supply terminal and not through another conductor pattern, the via electrodes of the plurality of power supply lines are connected to the ground. A high frequency component characterized by being surrounded by a group of via electrodes. A high-frequency component comprising a high-frequency signal processing circuit for processing a high-frequency signal on a laminated substrate formed by laminating a plurality of dielectric layers formed with a conductor pattern, the input terminal for the high-frequency signal, the output terminal, and the high-frequency signal processing A terminal group including a plurality of power supply terminals of the circuit is formed on one main surface of the multilayer substrate, and the dielectric layer constituting the multilayer substrate includes an inductance element, a capacitor element, a wiring line, And a plurality of power supply lines each having one end connected to the power supply terminal and a plurality of semiconductor elements included in the high-frequency signal processing circuit via via electrodes formed in a dielectric layer. And via electrodes of at least two power supply lines connected to different semiconductor elements among the plurality of power supply lines are connected to each other in the plurality of dielectric layers. In one dielectric layer even without high-frequency components that characterized the in close proximity at a position spaced from the power supply terminal when viewed from the lamination direction, and not through the other conductor patterns. The dielectric layer in which the via electrodes of the plurality of power supply lines are close to each other, the via electrodes of the plurality of power supply lines are surrounded by a group of via electrodes connected to the ground. High frequency components. The via electrode of the via electrode group is connected to each other on the surface of the dielectric layer on which the via electrode group is formed by a strip-shaped conductor pattern. High-frequency components as described. The high-frequency component according to claim 1, wherein the terminal group is formed on the one main surface along an outer edge of the main surface. 7. The high-frequency component according to claim 1, wherein power supply lines having one end connected to the power supply terminal are brought close to each other and connected to the adjacent via electrode or via electrode array. . The plurality of power supply lines, one end of which is connected to the power supply terminal, are formed in one dielectric layer to form a first power supply line layer, and on the main surface side in the stacking direction across the first power supply line layer. Has a first ground electrode that overlaps at least part of the plurality of power supply lines in plan view, and a second direction that overlaps at least part of the plurality of power supply lines in plan view on the side opposite to the main surface in the stacking direction. The ground electrode is disposed, and the high-frequency signal processing circuit is disposed on the opposite side of the first power supply line layer with the second ground electrode interposed therebetween. The high frequency component as described in any one. The terminal group is formed on the one main surface and arranged along an outer edge of the main surface, and the first ground electrode is formed on the one main surface and inside the terminal group. The high frequency component according to claim 8, wherein the high frequency component is provided. As the high-frequency signal processing circuit, a switch circuit that switches connection between an antenna terminal connected to an antenna and an input terminal or an output terminal of the high-frequency signal, and a high-frequency amplifier that amplifies a transmission signal input to the input terminal of the high-frequency signal The high-frequency component according to claim 1, further comprising: a circuit; and a low-noise amplifier circuit that amplifies a reception signal input from the antenna terminal and outputs the amplified signal to an output terminal. A communication device using the high-frequency component according to claim 1.

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