JP5644536B2 - Power semiconductor device - Google Patents

Description

The present invention relates to a power semiconductor device, and in particular, an object thereof is to improve a resistance to surge current of the power semiconductor device.

  When a surge current flows in the forward direction of the SiC Schottky diode, especially when a metal having a low Schottky barrier height such as Ti, Ni, Mo or an alloy thereof is used as an electrode, due to the self-heating effect due to Joule heating, The temperature of the diode sometimes increased. As the diode temperature increases, the mobility of the semiconductor portion of the SiC material decreases, resulting in an increase in the forward resistance of the diode. As a result, Joule heat generation due to surge current further increases, leading to a temperature rise. Due to the positive feedback effect described above, the element temperature suddenly rises and the Schottky diode may be destroyed.

A diode structure called JBS (Junction Barrier Controlled Schottky) or MPS (Merged PiN Schottky Diode) is used in order to prevent the element destruction of the Schottky diode due to the positive feedback effect due to the temperature rise caused by such surge current flow. Proposed. For example, it has been known that a JBS diode has a smaller forward voltage when driven at a large current than a Schottky diode, and is less likely to be destroyed by a forward surge current (for example, Patent Document 1). Such).

In addition, a p-type semiconductor region having an impurity concentration of 10 ¹⁷ to 10 ²⁰ cm ⁻³ and an n-type semiconductor region having an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ or less are in contact with a mixed electrode of nickel and aluminum, and the p-type semiconductor region A JBS diode in which an electrode and an electrode are in ohmic contact is known (for example, Patent Document 2).

  Further, in order to suppress the occurrence of local overheating phenomenon of the JBS diode, the p region of the JBS diode is densely arranged at a place where the overheating such as the central portion of the element is easily overheated. It has been known to form a p region of a diode (for example, Patent Document 3).

JP 2003-258271 A Special table 2003-510817 JP 2010-3841

  However, in a SiC JBS diode that is used with a semiconductor device that operates at a high voltage and a large current and is capable of high-speed switching, such as a MOSFET semiconductor device using SiC, the surge current increases and the degree of overheating increases. There was a case. Therefore, the resistance from the p region of the JBS diode to the electrode (Schottky electrode) is lower than conventionally known, and needs to be as low as possible.

  In order to lower the resistance of the p region of the JBS diode, it is better to increase the impurity concentration of ions implanted into the p region. On the other hand, if too much impurity ions are implanted into the p region, crystal defects are caused by ion implantation. In some cases, there is a problem that leakage current increases.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a power semiconductor device which is a JBS diode having a small resistance from the p region to the electrode of the JBS diode and a small leakage current. And

A power semiconductor device according to the present invention includes a first conductivity type SiC substrate, a first conductivity type SiC substrate formed on a first main surface of the SiC substrate and having a lower impurity concentration than the SiC substrate, The second conductivity type SiC first semiconductor region formed in the drift layer and the surface layer side of the first semiconductor region, and the impurity concentration is higher than that of the first semiconductor region. A second semiconductor region of SiC of the second conductivity type, a Schottky electrode formed on the surface of the drift layer and Schottky connected to the region of the first conductivity type, and ohmic connected to the second semiconductor region; An anode electrode formed on the surface of the Schottky electrode, and the surface of the anode electrode is formed immediately above the first semiconductor region and includes the region of the first semiconductor region as viewed from above. Formed wider area than one semiconductor region, those having a first bond of wire bonds, and a cathode electrode formed on the second main surface opposed to said first main surface of the SiC substrate.

  According to the present invention, it is possible to obtain a power semiconductor device in which element destruction due to surge current is suppressed and leakage current is small when a reverse bias is applied to a diode.

1 is a configuration diagram for explaining a power semiconductor device according to a first embodiment; FIG. 3 is a top view for illustrating the power semiconductor device of the first embodiment. FIG. 3 is a configuration diagram for explaining the manufacture of the power semiconductor device of the first embodiment. FIG. 3 is a configuration diagram for explaining the manufacture of the power semiconductor device of the first embodiment. FIG. 3 is a configuration diagram for explaining the manufacture of the power semiconductor device of the first embodiment. FIG. 6 is a configuration diagram for explaining a modification of the first embodiment. FIG. 3 is a configuration diagram for explaining the first embodiment; FIG. 3 is a configuration diagram for explaining the first embodiment; FIG. 6 is a configuration diagram for explaining a second embodiment;

Embodiment 1 FIG.
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a Schottky diode which is a power semiconductor device according to Embodiment 1 of the present invention. In the Schottky diode 100 according to the first embodiment, an N ⁺ type SiC substrate 2 (under the N ⁻ type epitaxial layer 1 (first conductivity type semiconductor region, drift layer) of silicon carbide (SiC) ( A cathode region). SiC substrate 2 is a low-resistance silicon carbide substrate having a 4H polytype in which the plane orientation of first main surface 2a is off by 4 ° or 8 ° from the <0001> silicon surface. The impurity concentration of epitaxial layer 1 is lower than the impurity concentration of SiC substrate 2. A cathode electrode 3 (drain electrode) made of silicide is formed on the second main surface 2b of the SiC substrate 2 so that it can be electrically connected. Here, the impurity concentration of the epitaxial layer 1 may be 2 × 10 ¹⁴ pieces / cm ³ or more and 2 × 10 ¹⁶ pieces / cm ³ or less.

A Ti Schottky electrode 4 is formed on the N ⁻ type epitaxial layer 1, and an anode electrode 5 is further formed on the upper portion. The anode electrode 5 (Al electrode) is connected to another electrode (not shown) by a wire bond 6. The first bond 7 (1st bond) of the wire bond 6 is generated in the process of forming the wire bond 6. A second conductivity type p region 8 (first semiconductor region) is formed in the epitaxial layer 1 below the Schottky electrode 4 immediately below the first bond 7. A p ⁺ region 9 (second semiconductor region) having a higher conductivity and a two-conductivity type is formed. The p ⁺ region 9 and the Schottky electrode 4 are in ohmic contact, and the epitaxial layer 1 and the Schottky electrode 4 are in Schottky connection. A termination structure 10 of the second conductivity type is formed on the surface layer portion of the epitaxial layer 1 around the Schottky electrode 4. The impurity concentration of the termination structure 10 may be 1 × 10 ¹⁶ pieces / cm ³ or more and 1 × 10 ¹⁸ pieces / cm ³ or less.

The p region 8 and the p ⁺ region 9 are formed by implanting Al ions. Similar effects can be realized by implanting impurities such as B in addition to Al ions. A desirable impurity concentration of the p region 8 is 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less. A desirable impurity concentration of the p ⁺ region 9 is 1 × 10 ²⁰ pieces / cm ³ or more and 5 × 10 ²⁰ pieces / cm ³ or less.

FIG. 2 is a top view showing the Schottky diode 100 according to the first embodiment of the present invention. In FIG. 2, the p region 8 and the p ⁺ region 9 are located below the first bond 7, the anode electrode 5, and the Schottky electrode 4, but are seen through in order to clarify the positional relationship. Here, the first bond 7 is formed in a larger area than the p region 8 so as to include a region where the p region 8 is formed as viewed from above. The p region 8 is indicated by a broken line. The termination structure 10 is formed around the anode electrode 5 and the Schottky electrode 4.

Here, the depth of the p region 8 may be about 0.3 to 2 μm, and the depth of the p ⁺ region 9 may be about 0.05 to 0.1 μm. The depth of the p region 8 is assumed to be smaller than the thickness of the epitaxial layer 1.

  Next, a JBS diode 100 that is a power semiconductor device of the present embodiment will be described with reference to FIGS. 3-5 is a cross-sectional schematic diagram for demonstrating the manufacturing process of the power semiconductor device of this Embodiment.

First, the first conductivity type epitaxial layer 1 is epitaxially grown on the first main surface 2a of the first conductivity type low-resistance SiC substrate 2 having a 4H polytype. Next, as shown in FIG. 3, an impurity such as Al of the second conductivity type is ion-implanted into the epitaxial layer 1 and then activation annealing is performed, whereby a p region 8, a p ⁺ region 9, and a termination structure 10 are formed. Form. Subsequently, as shown in FIG. 4, the cathode electrode 3 is formed by sputtering or the like in contact with the second main surface 2b of the SiC substrate 2. Next, as shown in FIG. 5, a Schottky electrode 4 and an Al electrode are sequentially formed on the first main surface 2a of the SiC substrate 2 from the first main surface 2a side by a sputtering method or the like. Finally, the wire bond 6 is formed so that the first bond 7 is directly above the p region 8 and the p ⁺ region 9, and the JBS diode which is a power semiconductor shown in FIG. 1 is formed.

Here, when Al ions are implanted, the acceleration energy at the time of ion implantation in the p region 8 may be 200 to 900 KeV, and the acceleration energy at the time of ion implantation in the p ⁺ region 9 may be 40 to 300 KeV. That's fine. When B ions are implanted, the acceleration energy at the time of ion implantation of the p region 8 may be 40 to 200 KeV.

  Next, the operation of the JBS diode 100 having the structure according to the present embodiment will be described.

  First, the normal operation will be described. The current that flows during normal operation is orders of magnitude smaller than the surge current. For this reason, the voltage across the diode is smaller than the voltage at which the bipolar operation starts. The current at this time becomes a current through the Schottky interface (interface between the Schottky electrode 4 and the epitaxial layer 1), and functions as a normal Schottky diode.

  When the diode of the first embodiment operates as a Schottky diode and a forward bias voltage is applied, the forward current flows through a region where there is no p region 8 (Schottky interface) and flows into the Schottky electrode 4. To do. In addition, since no current flows in the central portion of the plan view where the p region 8 is provided, heat generation due to the on-current does not occur in the central portion, and the temperature distribution has a low donut shape in the central portion. Become. Furthermore, heat is dissipated through the first bond 7, and the temperature rise at the center becomes an extremely small value.

Next, a case where a surge current flows will be described. When surge current flows, current flows initially at the Schottky interface. As the current increases, the voltage across the diode (the voltage between the anode electrode 5 and the cathode electrode 3) increases, eventually exceeding the voltage at which the pn diode operates, and the current also flows through the pn diode portion via the p region 8. Become. The Schottky diode performs a bipolar operation by the p region 8 (and the p ⁺ region 9) formed in the central portion and the epitaxial layer 1.

The temperature of the p region 8 (and the p ⁺ region 9) rises with time due to the current value at this time, but the first bond 7 formed on the upper part acts as a heat sink having a large heat capacity, so the p region 8 (and p The temperature rise in the ⁺ region 9) is suppressed.

According to the structure of the present invention, the first bond 7 of the wire bond 6 is formed in the vicinity of the surge current flowing, and the size of the first bond 7 is the contact area (0.5 mm) between the anode electrode 5 and the p ⁺ region 9. × 1 mm). That is, a heat sink having a large heat capacity is present immediately above the p ⁺ region 9. The p ⁺ region 9 and the Schottky electrode 4 are ohmically connected. For this reason, generation of Joule heat is small even when a surge current flows, and the generated Joule heat is released by the heat dissipation effect of the heat sink directly above, so that the elements (p region 8, p + region 9) due to heat generation Temperature rise is suppressed, and the element can be prevented from being destroyed. In addition, since the temperature rise due to the surge current is suppressed in this way, the surge resistance is improved. Further, as an incidental effect, it is possible to suppress an increase in element temperature during normal operation, and it is possible to operate the element in a larger current region.

Furthermore, since the impurity concentration of the p ⁺ region 9 is increased and the impurity concentration of the p region 8 is lower than a predetermined value, the p region 8 and the p ⁺ region 9 are formed by ion implantation. ^An increase in defects near the ⁺ region 9 can be suppressed, and an increase in leakage current can be suppressed when a reverse bias is applied.

  In the present embodiment, one p region is used. However, even if a plurality of divided p regions 8 are formed immediately below the first bond 7 of the wire bond as shown in FIG. Play. In the present embodiment, the case where the horizontal size of the p region 8 is smaller than the wire bond first bond 7 has been described. However, the horizontal size of the p region is approximately the same size as the first bond 7. The same effect can be obtained even with a slightly larger size.

  In the present embodiment, the Al wire bond 6 has been described as an example of the material of the wire bond 6, but the material of the wire bond 6 is not limited to this, and may be Cu or other means ( Even if electrical connection is realized using solder connection, ribbon bond, etc., the effect of the present invention is not affected.

  Furthermore, in the present invention, the p region 8 has been described as having a uniform concentration distribution. However, the distribution in the depth direction or the horizontal direction of the concentration of the p region 8 does not have to be uniform. For example, the same effect can be realized even when the concentration gradually increases from the surface of the p region 8 in the depth direction and takes a maximum value in the vicinity of the deepest portion. Further, even if the distribution is such that the impurity concentration increases or decreases in the horizontal direction from the central portion of the p region 8, the distribution is the same as described below regardless of whether the distribution is an extreme value. The effect can be realized.

  Further, the termination structure 10 is usually formed in the peripheral portion of the element in order to improve the breakdown voltage, but does not affect the effect of the present application.

The p ⁺ region 9 and the Schottky electrode 4 are ohmically connected. In order to realize an ohmic contact therebetween, the impurity concentration of the p ⁺ region 9 is 1 × 10 ²⁰ / cm 2. A concentration of about ³ or more and 5 × 10 ²⁰ pieces / cm ³ or less is required. Further, as shown in the sectional view thereof in FIG. 6, on the p ⁺ region 9, the ohmic electrode 11 in order to lower the contact resistance between the p ⁺ region 9 may be provided separately.

  Further, the SiC JBS diode of the present embodiment is more effective in facilitating high-speed driving when used in combination with SiC switching elements such as SiC MOSFETs.

Embodiment 2. FIG.
The second embodiment is a modification of the Schottky diode structure shown in the first embodiment. According to the second embodiment, a p-type semiconductor layer is formed in two regions as shown in FIG. The positions where the p region 8 and the p + region 9 are formed are designed to be directly below the front surface of the anode electrode 5 connected by wire bonding or the like when the Schottky diode is used in an actual power converter.

Since the operation in this embodiment is the same as that in Embodiment 1, it will not be described repeatedly. Further, according to the present embodiment, the p region 8 and the p ⁺ region 9 are formed in two places, but as shown in FIG. 8, a larger number of p regions are formed and immediately above them. If the wire bond first bond 7 is formed, the same effect is obtained. As described above, in the first embodiment, one p region 8 is formed immediately below the first bond 7. However, as shown as a modification of the first embodiment, the p region 8 is composed of a plurality of p regions. Even if it is, the same effect can be realized. Further, since the p region 8 and the p ⁺ region 9 are formed in each of the plurality of first bonds 7, the temperature rise can be further suppressed. Further, like the power semiconductor device of the first embodiment, it is possible to suppress an increase in leakage current when a reverse bias is applied.

Embodiment 3 FIG.
The third embodiment will be described with reference to FIG. The third embodiment shows a modification of the Schottky diode structure shown in the first embodiment. This invention realizes both improvement of basic surge current withstand capability and reduction of resistance during normal operation. According to the present embodiment, the p region 8 is formed over the entire front surface of the diode.

The p region 8 and the p ⁺ region 9 according to the third embodiment are not uniformly distributed, as shown in the cross-sectional view of FIG. 9, but where the dot density is locally high and low. Is the point that forms. The first bond 7 of the wire bond 6 is formed at a high density portion of the p region 8 and the p ⁺ region 9. The diameters of the dots in the p region 8 and the p ⁺ region 9 may be about 1 to 20 μm, preferably about 3 to 10 μm.

Also in the power semiconductor device of the present embodiment, a large number of p regions 8 and p ⁺ regions 9 are formed in a dot shape, and the first bond 7 is formed corresponding to the high density of dots. Can be suppressed. Further, like the power semiconductor device of the first embodiment, it is possible to suppress an increase in leakage current when a reverse bias is applied. Although the p region 8 is formed in a dot shape in the present embodiment, the same effect can be realized even if it is formed in a short stripe shape.

1 epitaxial layer, 2 drain region, 3 drain electrode, 4 Schottky electrode, 5 Al electrode, 6 wire bond, 7 first bond, 8 p region, 9 p ⁺ region, 10 termination structure, 11 ohmic electrode, 100 Schottky diode.

Claims (7)

A first conductivity type SiC substrate;
A drift layer of SiC formed on the first main surface of the SiC substrate and having a first conductivity type having a lower impurity concentration than the SiC substrate;
A first semiconductor region of SiC of the second conductivity type formed in the drift layer;
A second semiconductor region of SiC of the second conductivity type formed on the surface layer side of the first semiconductor region and having a higher impurity concentration than the first semiconductor region; and
A Schottky electrode formed on the surface of the drift layer and Schottky connected to the first conductivity type region, and ohmic connected to the second semiconductor region;
An anode electrode formed on the surface of the Schottky electrode;
Formed on the surface of the anode electrode, directly above the first semiconductor region, and formed in a wider area than the first semiconductor region so as to include the region of the first semiconductor region when viewed from above; First bond of wire bond,
A power semiconductor device comprising: a cathode electrode formed on a second main surface opposite to the first main surface of the SiC substrate. The impurity concentration of the first semiconductor region is 1 × 10 ¹⁷ pieces / cm ³ or more and 1 × 10 ¹⁸ pieces / cm ³ or less, and the impurity concentration of the second semiconductor region is 1 × 10 ²⁰ pieces / cm ³ or more. The power semiconductor device according to claim 1, wherein the number is 5 × 10 ²⁰ pieces / cm ³ or less. 3. The power semiconductor device according to claim 1, wherein a thickness of the second semiconductor region is 0.05 to 0.1 μm. 3. The power semiconductor device according to claim 1, further comprising a plurality of first semiconductor regions under one Schottky electrode. 5. The power semiconductor device according to claim 4, wherein the plurality of first semiconductor regions are arranged densely toward the central portion from the outside of the Schottky electrode. The power semiconductor device according to claim 1, further comprising a SiC switching element. A first conductivity type SiC substrate;
A drift layer of SiC formed on the first main surface of the SiC substrate and having a first conductivity type having a lower impurity concentration than the SiC substrate;
A first semiconductor region formed in a plurality of SiC dots in the second conductivity type formed in the drift layer;
A plurality of second semiconductor regions of SiC of the second conductivity type formed on the surface layer side of the plurality of first semiconductor regions and having a higher impurity concentration than the plurality of first semiconductor regions;
A Schottky electrode formed on the surface of the drift layer and Schottky connected to the first conductivity type region, and in ohmic contact with the plurality of second semiconductor regions;
An anode electrode formed on the surface of the Schottky electrode;
First wire bond formed on the surface of the anode electrode corresponding to the high dot density portion of the first semiconductor region as viewed from above,
A power semiconductor device comprising: a cathode electrode formed on a second main surface opposite to the first main surface of the SiC substrate.

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