JP5643278B2 - RADIO COMMUNICATION SYSTEM, RECEPTION DEVICE, AND RADIO COMMUNICATION METHOD - Google Patents

Description

The present invention relates to a wireless communication system, receiving apparatus, and a radio communication method.

  2. Description of the Related Art Conventionally, in wireless communication and wired communication, improvement in frequency band utilization efficiency has been demanded as demand increases. In order to improve the utilization efficiency of the frequency band, for example, the signal spectrum of the modulated modulation signal is divided into a plurality of sub-spectrums and transmitted, and the plurality of transmitted sub-spectrums are received and converted into the original modulation signal. A technique for demodulating is disclosed (see Non-Patent Document 1).

  In this technique, unused bands are scattered on the frequency axis to reduce unused bands. Further, the total occupied bandwidth of the signal is reduced by removing a part of the sub-spectrum. The technique disclosed in Non-Patent Document 1 achieves improvement in the frequency band utilization efficiency as described above.

  FIG. 11 is a functional block diagram illustrating a functional configuration of a wireless communication system 500 realized using related technologies. The wireless communication system 500 includes a transmission device 510 and a reception device 520. Transmitting apparatus 510 divides the modulated signal into a plurality of bands for transmission. Receiving device 520 receives the signal transmitted from transmitting device 510 and restores the modulated signal before division.

  As illustrated in FIG. 11, the transmission device 510 includes a modulation circuit 601, a transmission filter bank 602, and a D / A (Digital / Analog) converter 603. The reception device 520 includes an A / D (Analog / Digital) converter 611, a reception filter bank 612, and a demodulation circuit 613. The transmission filter bank 602 includes a series-parallel conversion circuit 604, an FFT (Fast Fourier Transform) circuit 605, a division circuit 606, and N switches (N is an integer equal to or greater than 1) SW-1 to SW-N, N Frequency shifters 607-1 to 607 -N, an adder circuit 608, an IFFT (Inverse Fast Fourier Transform) circuit 609, and a parallel-serial converter circuit 610. The reception filter bank 612 includes a serial-parallel conversion circuit 614, an FFT circuit 615, an extraction circuit 616, N frequency shifters 617-1 to 617-N, a distortion compensation circuit 618, an addition circuit 619, an IFFT circuit 620, a parallel-serial conversion circuit. 621 is provided.

  Next, a signal flow in the wireless communication system 500 will be described. FIG. 12 is a conceptual diagram illustrating an example of signal processing in the wireless communication system 500. FIG. 12A to FIG. 12C are diagrams illustrating an example of processing when the transmission apparatus 510 divides a band into N (N = 2) and distributes the band. FIG. 12D to FIG. 12F are diagrams illustrating an example of processing when the reception device 520 combines the bands divided by the transmission device 510.

First, processing in the transmission apparatus 510 in the wireless communication system 500 will be described.
The modulation circuit 601 of the transmission apparatus 510 modulates the data signal to be transmitted by a modulation method such as QPSK (Quadrature Phase Shift Keying), and transmits the waveform-shaped modulated signal shown in FIG. Input to the filter bank 602. The output signal from the transmission filter bank 602 is converted into an analog signal by the D / A converter 603 and transmitted.

  The transmission filter bank 602 performs processing as follows. First, the serial-parallel conversion circuit 604 performs serial-parallel conversion on the input signal, and the FFT circuit 605 performs fast Fourier transform to convert the signal in the time domain to the signal in the frequency domain. Next, the dividing circuit 606 multiplies the modulated signal converted into the frequency domain by a coefficient for dividing the signal band indicated by the broken lines 701-1 and 701-2 in FIG. Are generated (FIG. 12B). Next, the frequency shifters 607-1 to 607 -N distribute N sub-spectrums in a predetermined band on the frequency axis, and the adder circuit 608 adds the outputs of the frequency shifters 607-1 to 607 -N ( FIG. 12 (C)).

  Next, the IFFT circuit 609 performs fast inverse Fourier transform, and converts the signal added by the adder circuit 608 from a frequency domain signal to a time domain signal. Then, the parallel-serial conversion circuit 610 performs parallel-serial conversion. At this time, with respect to the band to be partially deleted, before inputting to the frequency shifters 607-1 to 607 -N, the switches SW-1 to SW-N corresponding to the band to be deleted are opened (OFF). Block signal transmission. As a result, no signal component is arranged in the band, and transmission can be performed with a part of the spectrum removed.

Next, processing in receiving apparatus 520 will be described.
The A / D converter 611 of the reception device 520 converts the received signal into a digital signal and inputs the converted digital signal to the reception filter bank 612. The demodulation circuit 613 demodulates the modulation signal output from the reception filter bank 612 and restores the data signal.

  The reception filter bank 612 performs processing as follows. First, the serial-parallel conversion circuit 614 performs serial-parallel conversion on the input signal, and the FFT circuit 615 performs fast Fourier transform to convert the signal in the time domain to the signal in the frequency domain. Next, the extraction circuit 616 multiplies the reception signal converted into the frequency domain by coefficients indicated by broken lines 701-3 and 701-4 in FIG. 12D to extract N subspectrums. Next, the frequency shifters 617-1 to 617-N return the extracted sub-spectrums to the bands before being shifted by the frequency shifters 607-1 to 607-N of the transmission apparatus 510 (FIG. 12E). ). Next, the adder circuit 619 adds all the sub-spectrums and obtains a combined modulated signal (FIG. 12F).

  Next, the IFFT circuit 620 performs fast inverse Fourier transform, and converts the synthesized demodulated signal obtained by the adder circuit 619 from a frequency domain signal to a time domain signal. Then, the parallel-serial conversion circuit 621 performs parallel-serial conversion. At this time, the transmission signal is not received by the reception device 520 for the band of the part from which the spectrum is removed by the transmission device 510. Therefore, some compensation processing is required. For example, there may be a noise component that causes not only a transmission signal component but also a deterioration in reception characteristics in this band. Therefore, the distortion compensation circuit 618 inputs a value based on the sub-spectrum received by the receiving device 520 to the band where the signal is transmitted by the transmitting device 510, and “ Compensation with 0 ”as input. As a result, the noise component in the band from which the signal is removed in the transmission apparatus 510 is removed, and the reception characteristics can be improved.

  As described above, the wireless communication system 500 divides the occupied band of the transmission signal and disperses the generated sub-spectrums at arbitrary locations on the frequency axis. Therefore, it is possible to effectively use a discontinuous free band or the like. Further, the frequency utilization efficiency can be improved by not transmitting a part of the occupied band of the transmission signal.

  In the wireless communication system 500 described above, the receiving apparatus 520 performs distortion compensation with “0” input to the band from which the signal is removed by the transmission apparatus 510, whereby noise components in this band are removed. Then, it becomes a spectrum in which signals in this band are missing. Therefore, the error rate when demodulating the signal received by the receiving device 520 increases. Therefore, a technique as described in Non-Patent Document 2 is considered as a technique for improving this.

  In the technique proposed in Non-Patent Document 2, a transmission replica signal obtained by re-encoding and re-modulating a received bit string obtained by temporarily demodulating a spectrum in which a part of the band is lost is transmitted to a transmission device. Is divided into sub-spectrum replicas by the same band dividing filter. By adding a sub-spectrum replica corresponding to the sub-spectrum deleted in the transmission device to the received signal, waveform equalization is realized and the error rate is improved. Further, the error rate can be further improved by repeatedly applying the method of Non-Patent Document 2.

Junichi Abe et al., “A Study on Occupied Bandwidth Reduction Method in Spectrum-Edited Band-Distributed Transmission”, 2010 IEICE Society Conference, B-3-26, September 2010 Satoshi Masuno et al., “Proposal of waveform equalization using sub-spectrum replica in spectrum-suppressed transmission”, Proceedings of the IEICE Conference, Vol. 2011, B-3-9, 290, March 2011

  However, when the method of Non-Patent Document 2 is applied to a modulation scheme having a large modulation multi-level number such as 16QAM (Quadrature Amplitude Modulation) or 64QAM, a large number of errors are included in the initial provisional demodulation decoding result. There is. In this case, there is a problem that the error rate characteristic does not improve even if a sub-spectrum replica is generated from the replica signal obtained based on the provisional demodulation decoding result and combined with the received signal.

The present invention has been made to solve the above problems, its object is to provide a wireless communication system capable of improving the error rate in radio communication, reception apparatus, and a wireless communication method.

  In order to solve the above problem, the present invention divides an occupied band occupied by transmission data and distributes and distributes the band on the frequency axis, and distributes the signal transmitted by the transmission apparatus on the frequency axis. In a wireless communication system including a receiving device that synthesizes and demodulates arranged signals, the transmitting device includes a serial-parallel conversion unit that performs serial-parallel conversion of the transmission data into a plurality of data strings, and desired data transfer A modulation unit that modulates each of the plurality of data sequences with a modulation scheme with a low modulation multilevel number that is less than the modulation multilevel number of the modulation scheme corresponding to the rate, and synthesizes signals obtained by the modulation to generate a signal; The receiving apparatus receives a signal generated by the modulation unit from a received signal based on the low-modulation multi-level modulation scheme and corresponds to any one of the data strings. A first demodulator that demodulates the signal, a first replica signal generator that generates a first replica signal from the first demodulated signal demodulated by the first demodulator, and the first replica signal generated from the received signal. A first subtraction unit that subtracts the replica signal of the first subtraction signal to calculate the first suppression signal, and the first subtraction signal calculated by the first subtraction unit based on the low modulation multi-level modulation scheme A second demodulator that demodulates a second demodulated signal corresponding to the data sequence of the second demodulator, and a second replica signal generator that generates a second replica signal from the second demodulated signal demodulated by the second demodulator And a second subtraction unit that calculates a second suppression signal by subtracting the second replica signal from the received signal, wherein the first demodulation unit further includes the second suppression Demodulating the signal based on the low-modulation multi-level modulation scheme, A wireless communication system, characterized by updating the demodulation signal.

  Further, the present invention is the above-described invention, wherein the receiving device corresponds to the first non-distributed band among the occupied bands occupied by the transmission data in the transmitting device. A first dividing unit that divides and outputs a missing signal and a compressed signal corresponding to a dispersedly arranged band; and a second suppression signal that is calculated by the second subtracting unit. And a first adding unit that corrects the second suppression signal by adding and synthesizing the missing signals output from the first subtracting unit, wherein the first subtracting unit outputs the compressed signal output from the first dividing unit. The first suppression signal is subtracted from the received signal to calculate the first suppression signal, and the first demodulation unit demodulates the corrected second suppression signal based on the low modulation multi-level modulation scheme And updating the first demodulated signal. .

  In the present invention described above, the receiving apparatus may correspond to the second replica signal in a band that is not distributed in the occupied band occupied by the transmission data in the transmitting apparatus. A second dividing unit that divides and outputs a missing signal and a compressed signal corresponding to a distributed band; and the second dividing unit that outputs the first suppression signal output from the first subtracting unit. And a second adder that corrects the first suppression signal by adding and synthesizing the missing signals output from the second subtractor, wherein the second subtractor outputs the compressed signal output from the second divider. The second suppression unit calculates the second suppression signal by subtracting from the received signal, and the second demodulation unit demodulates the corrected first suppression signal based on the modulation scheme of the low modulation multilevel number And updating the second demodulated signal. .

  Further, the present invention provides the above-described invention, wherein the modulation unit modulates each of the plurality of data strings by using a modulation scheme in which a distance from an origin to each symbol is different on a complex plane. The first demodulating unit demodulates the first demodulated signal based on a modulation method used for modulating each of the plurality of data strings, which has a long distance from the origin to each symbol on the complex plane. It is characterized by doing.

  In order to solve the above problem, the present invention provides a transmission device that divides an occupied band occupied by transmission data and distributes the transmission band on the frequency axis and transmits the signal on the frequency axis. A transmission device in a wireless communication system comprising a receiving device that synthesizes and demodulates signals dispersedly arranged, and a serial-parallel conversion unit that serial-parallel converts the transmission data into a plurality of data strings, and a desired A modulation unit that modulates each of the plurality of data strings in a modulation scheme with a low modulation multi-level number that is less than the modulation multi-level number of the modulation method corresponding to the data transfer rate, and generates a signal by combining signals obtained by the modulation; And a transmitter that transmits the signal generated by the modulator to the receiver.

  In order to solve the above problem, the present invention provides a transmission device that divides an occupied band occupied by transmission data and distributes the transmission band on the frequency axis and transmits the signal on the frequency axis. Receiving apparatus for synthesizing and demodulating signals dispersedly arranged in a wireless communication system, and having a low modulation multilevel less than the modulation multilevel number of a modulation scheme corresponding to a desired data transfer rate The low modulation multi-level modulation scheme is applied to a received signal that is obtained by modulating each of a plurality of data strings obtained by serial-parallel conversion of the transmission data and receiving a signal obtained by synthesizing a signal obtained by modulation. A first demodulator that demodulates a first demodulated signal corresponding to any one of the data strings, and a first replica from the first demodulated signal demodulated by the first demodulator A first replica signal generation unit that generates a signal, a first subtraction unit that calculates a first suppression signal by subtracting the first replica signal from the received signal, and a calculation performed by the first subtraction unit A second demodulating unit that demodulates a second demodulated signal corresponding to another data sequence based on the low modulation multi-level modulation scheme for the first suppression signal, and the second demodulating unit A second replica signal generation unit that generates a second replica signal from the second demodulated signal demodulated by the second demodulator, and a second suppression signal that calculates a second suppression signal by subtracting the second replica signal from the received signal The first demodulator further demodulates the second suppression signal based on the low-modulation multi-level modulation scheme, and converts the first demodulated signal into the first demodulated signal. The receiving apparatus is characterized by updating.

  In order to solve the above problem, the present invention provides a transmission device that divides an occupied band occupied by transmission data and distributes the transmission band on the frequency axis and transmits the signal on the frequency axis. A wireless communication method in a wireless communication system comprising a receiving device that synthesizes and demodulates signals distributed and distributed, and a serial-parallel conversion step for serial-parallel conversion of the transmission data into a plurality of data strings; A modulation step of modulating each of the plurality of data strings with a modulation scheme with a low modulation multilevel number smaller than the modulation multilevel number of the modulation scheme corresponding to the data transfer rate, and generating a signal by synthesizing signals obtained by the modulation A transmission step of transmitting the signal generated in the modulation step to the reception device, and a modulation method of the low modulation multi-level number from the reception signal received from the transmission device A first demodulating step for demodulating a first demodulated signal corresponding to any one data sequence based on the first demodulated signal, and a first replica signal from the first demodulated signal demodulated in the first demodulating step Calculated in the first replica signal generating step, the first subtracting step of subtracting the first replica signal from the received signal to calculate the first suppression signal, and the first subtracting step. A second demodulation step for demodulating a second demodulated signal corresponding to another data sequence from the first suppression signal based on the low modulation multi-level modulation scheme; and a second demodulation step demodulated in the second demodulation step. A second replica signal generation step of generating a second replica signal from the second demodulated signal, and a second suppression signal is calculated by subtracting the second replica signal from the received signal. And a renewal step of performing demodulation based on the low-modulation multi-level modulation scheme on the second suppression signal and updating the first demodulated signal. It is a communication method.

  According to the present invention, for a signal modulated by combining a low modulation multi-level modulation scheme, each data string is decoded by each of the low modulation multi-level modulation schemes used in the modulation, and each data By suppressing the component of the data string in the received signal using the replica signal of the string, it is possible to improve the accuracy of the demodulation result of another data string and improve the error rate in wireless communication.

It is the schematic which shows an example of the modulation system in embodiment which concerns on this invention. It is the schematic which shows an example of the demodulation in the same embodiment. It is a schematic block diagram which shows the structure of the transmitter 100 in the embodiment. 3 is a schematic diagram illustrating an example of a transmission signal transmitted by the transmission device 100 in the embodiment. FIG. It is a schematic block diagram which shows the structure of the receiver 200 in the embodiment. It is a schematic block diagram which shows the structure of the reception filter bank 202 in the embodiment. 3 is a schematic block diagram showing a configuration of an outer frame first demodulation / decoding circuit 204 in the same embodiment. FIG. 2 is a schematic block diagram showing a configuration of an outer frame first replica signal generation circuit 205 in the same embodiment. FIG. 3 is a schematic block diagram showing a configuration of an outer frame first division circuit 206 in the same embodiment. FIG. It is the schematic which showed the flow of the process in the case of repeating the demodulation decoding of outer frame QPSK and the demodulation decoding of inner frame QPSK several times. It is a functional block diagram showing the function structure of the radio | wireless communications system 500 implement | achieved using the related technique. 1 is a conceptual diagram illustrating an example of signal processing in a wireless communication system 500. FIG.

(Outline of the embodiment according to the present invention)
In the embodiment of the present invention, a transmission signal is divided into a plurality of signals, and each signal is modulated by a low-order modulation multi-level modulation method and then combined (for example, addition combining), thereby performing high-order modulation. Wireless communication is performed at the same data transfer rate as when a multi-level modulation scheme is applied.

  FIG. 1 is a schematic diagram showing an example of a modulation scheme in an embodiment according to the present invention. Here, a case will be described in which wireless communication is performed at a data transfer rate equivalent to 16QAM. In the present embodiment, as shown in the figure, a signal space diagram equivalent to 16QAM is obtained by modulating a signal to be transmitted using two QPSK and combining the modulated signals. Here, two QPSKs include an inner frame QPSK (hereinafter referred to as an inner frame QPSK) having a short distance between each data signal point and the origin on the complex plane, and each data signal point and the origin on the complex plane. An outer frame QPSK having a long distance (hereinafter referred to as an outer frame QPSK) is used. In the modulation system in the present embodiment, as shown in FIG. 1, 16 combinations of 4 points of QPSK of the inner frame and 4 points of QPSK of the outer frame correspond to 16QAM points.

  In transmission in the present embodiment, a transmission data string to be transmitted is divided into two data strings. Modulation using the inner frame QPSK is performed on one data string. Modulation using the outer frame QPSK is performed on the other data string. By combining the signals obtained by the two modulations, a transmission signal to be transmitted to the communication partner is generated.

  Next, an outline of reception in the present embodiment will be described. FIG. 2 is a schematic diagram illustrating an example of demodulation in the present embodiment. In the reception signal that has received the transmission signal subjected to the modulation shown in FIG. 1, the symbols are scattered in the hatched area in FIG. 2A due to the influence on the transmission path, noise, and the like. In this embodiment, the outer frame QPSK is demodulated based on whether the symbol of the received signal is located in the first quadrant to the fourth quadrant (demodulation by quadrant determination). A replica signal for the signal of the outer frame QPSK is generated from the data string obtained by demodulating the outer frame QPSK, and the replica signal is subtracted from the received signal. By this subtraction, a signal in which the signal of the outer frame QPSK in the received signal is suppressed, that is, a signal of the inner frame QPSK is obtained. Each symbol in the signal of the inner frame QPSK is scattered in the hatched area in FIG.

  The signal of the inner frame QPSK is demodulated, and a replica signal for the signal of the inner frame QPSK is generated from the data string obtained as the demodulation result. By subtracting this replica signal from the received signal, a signal in which the signal of the inner frame QPSK in the received signal is suppressed, that is, the signal of the outer frame QPSK is obtained. Since the influence of the signal of the inner frame QPSK is reduced in the signal of the outer frame QPSK, the region where the symbols are scattered becomes narrower than that of FIG. 2A as shown in FIG. The demodulation result obtained by demodulating the signal of the outer frame QPSK improves the accuracy of demodulation because the influence of the signal of the inner frame QPSK is reduced compared to the demodulation result obtained by directly demodulating the received signal.

  A replica signal for the signal of the outer frame QPSK is generated from the data string obtained by demodulating the signal of the outer frame QPSK corresponding to FIG. By subtracting this replica signal from the received signal, a signal in which the signal of the outer frame QPSK in the received signal is suppressed, that is, a signal of the inner frame QPSK is obtained. Since the signal of the inner frame QPSK is a signal obtained by using the replica signal of the outer frame QPSK with improved demodulation accuracy, the region where each symbol is scattered is shown in FIG. Narrower than B). The demodulation result obtained by demodulating the signal of the inner frame QPSK has improved demodulation accuracy compared with the demodulation result obtained by demodulating the signal corresponding to FIG.

In the reception of this embodiment, the signal of the outer frame QPSK is demodulated, and a replica signal of the outer frame QPSK is generated based on the demodulation result. The replica signal of the outer frame QPSK is subtracted from the received signal to demodulate the signal of the inner frame QPSK. Further, a replica signal of the inner frame QPSK is generated based on the demodulation result of the signal of the inner frame QPSK. The replica signal of the inner frame QPSK is subtracted from the received signal, and the signal of the outer frame QPSK is demodulated again. A highly accurate replica signal of the outer frame QPSK is generated based on the demodulation result of the demodulated signal of the outer frame QPSK. The replica signal of the outer frame QPSK with high accuracy is subtracted from the received signal, and the signal of the inner frame QPSK is demodulated again.
As described above, by demodulating the outer frame QPSK and the inner frame QPSK in order using the replica signal, high-accuracy demodulation is performed while realizing a data transfer rate equivalent to a higher-order modulation method such as 16QAM. . Note that, here, an example in which demodulation is performed twice for the outer frame QPSK and the inner frame QPSK has been described, but demodulation may be performed repeatedly three or more times.

Hereinafter, specific configuration examples of the transmission device and the reception device included in the wireless communication system according to the present embodiment will be described. Here, a case will be described in which a modulation method in the transmission apparatus is a combination of the two QPSK modulation methods described above.
FIG. 3 is a schematic block diagram illustrating a configuration of the transmission device 100 according to the present embodiment. The transmitting apparatus 100 performs the above-described modulation on the transmission data string to be transmitted to the receiving apparatus, divides the obtained signal into a plurality of parts, and distributes the divided signals to arbitrary locations on the frequency axis. Place and send. Further, the transmission apparatus 100 may transmit a part of the signals without being distributed and arranged when the divided signals are distributed and arranged on the frequency axis.

  A transmission apparatus 100 includes a serial-parallel conversion circuit 101, an outer frame error correction encoder 102, an outer frame modulator 103, an amplifier 104, an inner frame error correction encoder 105, an inner frame modulator 106, an adder circuit 107, a transmission filter A bank 108 and a D / A conversion circuit 109 are provided.

The serial / parallel conversion circuit 101 performs serial / parallel conversion on the input transmission data string to form two data strings, a data string for the outer frame QPSK and a data string corresponding to the inner frame QPSK.
Outer frame error correction encoder 102 performs error correction encoding on the data string for outer frame QPSK input from serial-to-parallel conversion circuit 101.
Outer frame modulator 103 performs modulation processing (symbol mapping) on the data sequence that has been subjected to error correction coding in outer frame error correction encoder 102, using a low-order modulation method (QPSK modulation method), and performs modulation. Generate a signal.
The amplifier 104 amplifies the modulation signal generated by the outer frame modulator 103. More specifically, by multiplying the distance between the symbol mapped by the outer frame modulator 103 and the origin of the complex plane by a constant, the symbol is located farther from the origin than the symbol mapped by the inner frame modulator 106. To do.

The inner frame error correction encoder 105 performs error correction encoding on the data string for the inner frame QPSK input from the serial-parallel conversion circuit 101.
The inner frame modulator 106 performs modulation processing (symbol mapping) on the data string error-encoded by the inner frame error correction encoder 105 using a low-order modulation method (QPSK modulation method), and performs modulation. Generate a signal.
The adder circuit 107 adds and combines the modulation signal amplified by the amplifier 104 and the modulation signal generated by the inner frame modulator 106 to generate a combined modulation signal.

  The transmission filter bank 108 converts the combined modulation signal generated by the adder circuit 107 from a time domain signal to a frequency domain signal by fast Fourier transform, and converts the frequency domain signal obtained by the conversion into a plurality of frequency domain signals. To divide. The transmission filter bank 108 disperses and arranges each of a plurality of frequency domain signals in a predetermined frequency band, and converts the frequency domain signal into a time domain signal by fast inverse Fourier transform.

That is, the transmission filter bank 108 generates a transmission signal obtained by dividing the spectrum of the combined modulation signal into a plurality of bands. Further, the transmission filter bank 108 may improve the frequency utilization efficiency by not transmitting some of the signals in the plurality of frequency regions. Note that the transmission filter bank 108 can be configured in the same manner as the transmission filter bank 602 shown in FIG. 11, for example.
The D / A conversion circuit 109 converts the transmission signal generated by the transmission filter bank 108 into an analog signal. The transmission signal converted into the analog signal is up-converted to a carrier frequency band by an unillustrated RF (Radio Frequency: radio frequency) circuit, and transmitted to the receiving apparatus.

  FIG. 4 is a schematic diagram illustrating an example of a transmission signal transmitted by the transmission apparatus 100 in the present embodiment. In the figure, the horizontal axis represents frequency and the vertical axis represents power. In the example shown in FIG. 4A, in the transmission filter bank 108, the combined modulated signal is divided into n (# 1 to #n) frequency domain signals and (n-1) in a predetermined continuous frequency band. (# 1 to # (n-1)) signals are arranged. The # n-th signal is not included in the transmission signal and is missing. In the following description, as shown in FIG. 4B, a spectrum corresponding to a frequency domain signal included in a transmission signal transmitted from the transmission apparatus 100 is referred to as a compressed subspectrum. A spectrum corresponding to a frequency domain signal not included in the transmission signal is referred to as a missing subspectrum. A spectrum corresponding to all frequency domain signals, that is, a spectrum corresponding to a transmission data string is called a full spectrum.

  FIG. 5 is a schematic block diagram illustrating a configuration of the receiving device 200 in the present embodiment. The receiving device 200 receives the transmission signal transmitted by the transmitting device 100, extracts signals distributed and arranged at predetermined frequency axis locations in the received signal, and synthesizes the extracted signals. The receiving apparatus 200 demodulates the signal of the outer frame QPSK and the signal of the inner frame QPSK included in the synthesized signal by using the reception process described above.

  The receiving apparatus 200 includes an A / D conversion circuit 201, a reception filter bank 202, a reception buffer 203, an outer frame first demodulation / decoding circuit 204, an outer frame first replica signal generation circuit 205, an outer frame first division circuit 206, and a subtraction circuit. 207, first inner frame demodulating and decoding circuit 208, first inner frame replica signal generating circuit 209, first inner frame dividing circuit 210, subtracting circuit 211, adding circuit 212, second outer frame demodulating and decoding circuit 213, second outer frame A replica signal generation circuit 214, an outer frame second division circuit 215, a subtraction circuit 216, an addition circuit 217, an inner frame second demodulation / decoding circuit 218, and a parallel-serial conversion circuit 219 are provided.

The A / D conversion circuit 201 receives a reception signal received by the antenna of the reception apparatus 200 and down-converted to a baseband frequency band by an RF circuit (not shown). The A / D conversion circuit 201 converts the input reception signal into a digital signal.
The reception filter bank 202 performs a process corresponding to the transmission filter bank 108 of the transmission apparatus 100 on the reception signal digitized by the A / D conversion circuit 201, and synthesizes signals distributed and arranged in a predetermined frequency band. The time domain signal (hereinafter referred to as a combined received signal) is output. That is, the reception filter bank 202 performs the same signal processing as the reception filter bank 612 shown in FIG.
The reception buffer 203 stores the combined reception signal output from the reception filter bank 202. The reception buffer 203 functions as a delay device that stores the combined reception signal and absorbs a processing delay time until the subtraction circuits 207, 211, and 217 are processed.

The outer frame first demodulation / decoding circuit 204 demodulates the outer frame QSPK signal by quadrant determination with respect to the combined reception signal output from the reception filter bank 202. The outer frame first demodulation / decoding circuit 204 performs error correction on the demodulated signal of the outer frame QPSK, and calculates a data string for the outer frame QPSK (hereinafter referred to as an outer frame data string).
The outer frame first replica signal generation circuit 205 generates a replica signal corresponding to the signal of the outer frame QPSK based on the outer frame data calculated by the outer frame first demodulation / decoding circuit 204.
The outer frame first division circuit 206 divides the replica signal generated by the outer frame first replica signal generation circuit 205 into a time domain signal corresponding to the compressed sub-spectrum and a time domain signal corresponding to the missing sub-spectrum. To do. Outer frame first division circuit 206 outputs a signal in the time domain corresponding to the compressed sub-spectrum to subtraction circuit 207. Outer frame first division circuit 206 outputs a signal in the time domain corresponding to the missing sub-spectrum to addition circuit 212.

When the time-domain signal corresponding to the compressed sub-spectrum is input from the outer frame first division circuit 206, the subtraction circuit 207 reads the combined reception signal stored in the reception buffer 203. The subtracting circuit 207 subtracts the input signal from the combined reception signal to generate a signal in which the signal of the outer frame QPSK is suppressed, and outputs the signal to the inner frame first demodulation / decoding circuit 208.
The inner frame first demodulation / decoding circuit 208 performs demodulation of the inner frame QPSK by quadrant determination using the signal output from the subtraction circuit 207 as a signal of the inner frame QPSK. The inner frame first demodulation / decoding circuit 208 performs error correction on the demodulated signal of the inner frame QPSK, and calculates a data string for the inner frame QPSK (hereinafter referred to as an inner frame data string).

The inner frame first replica signal generation circuit 209 generates a replica signal corresponding to the signal of the inner frame QPSK based on the inner frame data calculated by the inner frame first demodulation / decoding circuit 208.
The inner frame first division circuit 210 divides the replica signal generated by the inner frame first replica signal generation circuit 209 into a time domain signal corresponding to the compressed sub-spectrum and a time domain signal corresponding to the missing sub-spectrum. To do. The inner frame first division circuit 210 outputs a time-domain signal corresponding to the compressed sub-spectrum to the subtraction circuit 211. The inner frame first division circuit 210 outputs a time domain signal corresponding to the missing sub-spectrum to the adder circuit 217.

  When the time-domain signal corresponding to the compressed sub-spectrum is input from the inner frame first division circuit 210, the subtraction circuit 211 reads the combined reception signal stored in the reception buffer 203. The subtracting circuit 211 generates and subtracts the input signal from the received signal, generates a signal in which the signal of the inner frame QPSK is suppressed, and outputs the signal to the adding circuit 212. The signal output from the subtracting circuit 211 to the adding circuit 212 is a signal corresponding to a signal in the time domain of the compressed sub-spectrum of the signal of the outer frame QPSK.

  The adding circuit 212 adds the signal in the time domain corresponding to the missing sub-spectrum input from the outer frame first division circuit 206 and the signal input from the subtracting circuit 211 to the outer frame second demodulation decoding circuit 213. Output. Here, the signal output from the addition circuit 212 to the outer frame second demodulation / decoding circuit 213 includes a signal corresponding to a time-domain signal corresponding to the compressed sub-spectrum of the outer frame QPSK signal and a missing signal of the outer frame QPSK. This is a signal obtained by adding and synthesizing a signal in the time domain corresponding to the sub-spectrum. In other words, the added and synthesized signal corresponds to a signal in the time domain corresponding to the full spectrum of the signal of the outer frame QPSK.

The outer frame second demodulation / decoding circuit 213 demodulates the signal of the outer frame QPSK by quadrant determination on the signal output from the adder circuit 212. The outer frame second demodulation / decoding circuit 213 performs error correction on the demodulated signal of the outer frame QPSK, and calculates a data string for the outer frame QPSK.
The outer frame second replica signal generation circuit 214 generates a replica signal corresponding to the signal of the outer frame QPSK based on the outer frame data string calculated by the outer frame second demodulation / decoding circuit 213.
The outer frame second division circuit 215 divides the replica signal generated by the outer frame second replica signal generation circuit 214 into a time domain signal corresponding to the compressed sub-spectrum and a time domain signal corresponding to the missing sub-spectrum. To do. Outer frame second division circuit 215 outputs a signal in the time domain corresponding to the compressed subspectrum of outer frame QPSK to subtraction circuit 216.

  When a signal in the time domain corresponding to the compressed sub-spectrum of the outer frame QPSK is input from the outer frame second division circuit 215, the subtraction circuit 216 reads the combined received signal stored in the reception buffer 203. The subtraction circuit 216 subtracts the input signal from the combined reception signal, generates a signal in which the signal of the outer frame QPSK is suppressed, and outputs the signal to the addition circuit 217. The signal output from the subtracting circuit 216 to the adding circuit 217 is a time domain signal corresponding to the compressed sub-spectrum of the signal of the inner frame QSPK.

  The adder circuit 217 adds and combines the signal in which the signal of the outer frame QPSK input from the subtractor circuit 216 is suppressed and the signal in the time domain corresponding to the missing sub-spectrum input from the inner frame first division circuit 210. The added and synthesized signal is output to the inner frame second demodulation / decoding circuit 218. Here, the signal output from the adder circuit 217 to the inner frame second demodulation / decoding circuit 218 corresponds to the time domain signal corresponding to the compressed subspectrum of the inner frame QPSK signal and the missing subspectrum of the inner frame QPSK signal. This is a signal obtained by adding and synthesizing the time domain signal. In other words, the added and synthesized signal corresponds to a signal in the time domain corresponding to the full spectrum of the signal of the inner frame QPSK.

The inner frame second demodulation / decoding circuit 218 demodulates the signal of the inner frame QPSK by quadrant determination with respect to the signal output from the adder circuit 217. The inner frame second demodulation / decoding circuit 218 performs error correction on the demodulated signal of the inner frame QPSK, and calculates a data string for the inner frame QPSK.
The parallel / serial conversion circuit 219 receives the data string calculated by the outer frame second demodulation / decoding circuit 213 and the data string calculated by the inner frame second demodulation / decoding circuit 218. The parallel-serial conversion circuit 219 generates one data string by performing parallel-serial conversion on the two input data strings, and outputs the generated data string as a received data string.

  FIG. 6 is a schematic block diagram showing the configuration of the reception filter bank 202 in the present embodiment. The reception filter bank 202 includes a serial-parallel conversion circuit 301, an FFT circuit 302, an extraction circuit 303, a frequency shift circuit 304, a transmission path estimator 305, an amplitude / phase control circuit 306, a synthesis circuit 307, an IFFT circuit 308, and a parallel-serial conversion. A circuit 309 is included.

The serial / parallel conversion circuit 301 performs serial / parallel conversion on the received signal.
The FFT circuit 302 performs fast Fourier transform on the reception signal that has been serial-parallel converted by the serial-parallel conversion circuit 301, and converts the reception signal from a time-domain signal to a frequency-domain signal.
The extraction circuit 303 multiplies the reception signal converted into the frequency domain signal by the FFT circuit 302 by a predetermined coefficient to extract (N−1) sub-spectrums.
The frequency shift circuit 304 returns each sub-spectrum extracted by the extraction circuit 303 to the frequency band before being shifted in the transmission filter bank 108 of the transmission device 100.

The transmission path estimator 305 estimates a transmission path coefficient based on a known signal (for example, a training signal, a reference signal, a sounding signal, etc.) included in the received signal or a known signal received in advance.
Based on the transmission path coefficient estimated by the transmission path estimator 305, the amplitude phase control circuit 306 corrects the amplitude phase distortion of each subspectrum returned to the original frequency band by the frequency shift circuit 304 by frequency domain equalization processing. . As the frequency domain equalization processing, for example, the Zero Forcing method is known.
The synthesizing circuit 307 adds and synthesizes the sub-spectrums whose amplitude and phase distortion are corrected, and outputs the synthesized signal to the IFFT circuit 308.

The IFFT circuit 308 performs fast inverse Fourier transform on the signal output from the synthesis circuit 307, converts the signal in the frequency domain into a signal in the time domain, and outputs the signal to the parallel-serial conversion circuit 309.
The parallel-serial conversion circuit 309 outputs a signal obtained by parallel-serial conversion of the signal output from the IFFT circuit 308 to the reception buffer 203 and the outer frame first demodulation / decoding circuit 204 as a combined reception signal.

  FIG. 7 is a schematic block diagram showing the configuration of the outer frame first demodulation / decoding circuit 204 in the present embodiment. The outer frame first demodulation / decoding circuit 204 includes a demodulation circuit 341 and a decoding circuit 342. The demodulation circuit 341 demodulates the time domain signal output from the reception filter bank 202. The decoding circuit 342 performs error correction on the signal demodulated by the demodulation circuit 341, and outputs data obtained by the error correction to the outer-frame first replica signal generation circuit 205. The inner frame first demodulation and decoding circuit 208, the outer frame second demodulation and decoding circuit 213, and the inner frame second demodulation and decoding circuit 218 have the same configuration as the outer frame first demodulation and decoding circuit 204. The inner frame first demodulation / decoding circuit 208 and the inner frame second demodulation / decoding circuit 218 are different from the outer frame first demodulation / decoding circuit 204 in that demodulation corresponding to the inner frame QPSK is performed at the time of demodulation.

FIG. 8 is a schematic block diagram showing a configuration of the outer frame first replica signal generation circuit 205 in the present embodiment. The outer frame first replica signal generation circuit 205 includes a re-encoding circuit 351 and a re-modulation circuit 352. The re-encoding circuit 351 performs the same error correction encoding on the signal input from the outer frame first demodulation / decoding circuit 204 as the outer frame error correction encoder 102 included in the transmission apparatus 100. The remodulation circuit 352 performs the same modulation processing as the outer frame modulator 103 included in the transmission apparatus 100 on the signal error-correction-encoded by the re-encoding circuit 351. The remodulation circuit 352 outputs the modulation signal obtained by the modulation process to the outer frame first division circuit 206. The outer frame second replica signal generation circuit 214 has the same configuration as the outer frame first replica signal generation circuit 205.
The inner frame first replica signal generation circuit 209 has the same configuration as the outer frame first replica signal generation circuit 205. However, the re-encoding circuit 351 performs the same error correction encoding as the inner frame error correction encoder 105. Further, the remodulation circuit 352 performs the same modulation processing as the inner frame modulator 106.

  FIG. 9 is a schematic block diagram showing a configuration of the outer frame first division circuit 206 in the present embodiment. The outer frame first division circuit 206 includes a series-parallel conversion circuit 361, an FFT circuit 362, a division circuit 363, an IFFT circuit 364, a parallel-serial conversion circuit 365, an IFFT circuit 366, and a parallel-serial conversion circuit 367.

The serial / parallel conversion circuit 361 performs serial / parallel conversion on the replica signal input from the outer frame first replica signal generation circuit 205.
The FFT circuit 362 performs fast Fourier transform on the replica signal that has been subjected to serial-parallel conversion, and converts the time-domain signal into a frequency-domain signal.

  The dividing circuit 363 divides the spectrum (full spectrum) obtained by the FFT circuit 362 into N sub-spectrums using the same coefficients as those used to generate N sub-spectrums in the transmitting apparatus 100. . The dividing circuit 363 outputs the sub-spectrum included in the transmission signal among the N sub-spectrums to the IFFT circuit 364. Further, the dividing circuit 363 outputs a sub-spectrum that is not included in the transmission signal among the N sub-spectrums to the IFFT circuit 366. For example, in the description of the present embodiment, the # 1 to # (n−1) th subspectrums are output to the IFFT circuit 364, and the #nth subspectrum is output to the IFFT circuit 366.

The IFFT circuit 364 performs fast inverse Fourier transform on the sub-spectrum input from the dividing circuit 363, and converts the frequency domain signal into a time domain signal.
The parallel-serial conversion circuit 365 performs parallel-serial conversion on the time domain signal converted by the IFFT circuit 364 and outputs the result to the subtraction circuit 207.
With the above processing, the IFFT circuit 364 and the parallel-serial conversion circuit 365 generate a time domain signal corresponding to the compressed sub-spectrum.

The IFFT circuit 366 performs a fast inverse Fourier transform on the sub-spectrum input from the dividing circuit 363, and converts the frequency domain signal into a time domain signal.
The parallel-serial conversion circuit 367 performs parallel-serial conversion on the time domain signal converted by the IFFT circuit 366 and outputs the signal to the adder circuit 212.
With the above processing, the IFFT circuit 366 and the parallel-serial conversion circuit 367 generate a time-domain signal corresponding to the missing sub-spectrum.
The inner frame first division circuit 210 has the same configuration as the outer frame first division circuit 206.

In the above-described embodiment, a transmission signal is generated by combining low-order modulation multilevel modulation schemes without using high-order modulation multilevel modulation schemes. When this transmission signal is received and demodulated, a replica signal is generated by sequentially repeating demodulation corresponding to the modulation scheme of the low-order modulation multi-level for the received signal, and the replica signal corresponding to one modulation scheme is generated. The demodulation accuracy can be improved by performing demodulation corresponding to the other modulation method on the signal obtained by subtracting the signal from the received signal.
In addition, when performing band division transmission, a replica signal is obtained by demodulating and decoding a signal in the time domain corresponding to a sub-spectrum that is not included in the transmission signal by demodulating and decoding the signal in the sub-spectrum included in the transmission signal. The accuracy of demodulation can be improved for each of the low-order modulation multilevel modulation schemes.

In this embodiment, in the demodulation of the signal of the outer frame QPSK, not only the demodulation is performed directly from the received signal, but also the demodulation is performed again from the signal in which the influence of the signal of the inner frame QPSK is suppressed using the replica signal of the inner frame QPSK. Like. As a result, data with higher accuracy than data obtained by directly demodulating the received signal can be obtained.
In this way, errors when demodulating and decoding the signal of the outer frame QPSK can be reduced, so that the accuracy of the replica signal corresponding to the compressed sub-spectrum and the replica signal corresponding to the missing sub-spectrum can also be improved. The error rate of the QPSK signal can be reduced.
Further, data with higher accuracy can be obtained by demodulating the signal of the outer frame QPSK from the signal in which the influence of the signal of the outer frame QPSK is suppressed by the replica signal generated using the data of the inner frame QPSK with high accuracy. Can do.

  In addition, the program for realizing the functions of the transmission device or the reception device in the present invention, or both devices is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system, A process for generating a transmission signal and a process for demodulating and decoding a received data string may be performed by executing them. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system having a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

In addition, said embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
For example, in the above embodiment, a configuration has been described in which demodulation and decoding of the outer frame QPSK and demodulation and decoding of the inner frame QPSK are performed twice. However, the present invention is not limited to this, and demodulation and decoding of the outer frame QPSK and demodulation and decoding of the inner frame QPSK may be performed repeatedly three or more times. Further, as a condition for stopping the repetition, the repetition may be stopped when an error rate in error correction for each signal is equal to or lower than a predetermined error rate.

FIG. 10 is a schematic diagram showing a flow of processing when the outer frame QPSK demodulation and decoding and the inner frame QPSK demodulation and decoding are repeated a plurality of times. In the figure, the flow of processing when four iterations are performed is shown. In the correspondence relationship between the processing in FIG. 5 and the receiving apparatus 200 in FIG. 5, the processing from the inner frame first demodulation / decoding circuit 208 to the inner frame second demodulation / decoding circuit 218 repeatedly corresponds to the first time.
When the second and subsequent iterations are performed, for example, for demodulation and decoding of the outer frame QPSK, the signal of the outer frame missing sub-spectrum (outer frame QPSK sub-spectrum replica) calculated by the outer frame second division circuit 215 and the inner frame first The full spectrum replica signal of the inner frame generated by the data obtained by the dual demodulation decoding circuit 218 is used. With respect to the demodulation and decoding of the inner frame QPSK, the inner frame generated by the compressed data of the outer frame PQSK obtained in the second iteration (compressed spectrum replica) and the data obtained by the inner frame second demodulation and decoding circuit 218 is missing. A sub-spectrum replica signal (inner frame QPSK sub-spectrum replica) is used.

In the above-described embodiment, the configuration using the QPSK modulation method as the modulation method of the outer frame and the inner frame (the modulation method of the low-order modulation multi-level number) has been described. However, the present invention is not limited to this, and other modulation schemes such as a BPSK modulation scheme and a π / 4 shift QPSK modulation scheme may be used.
In the above embodiment, a configuration has been described in which a data transfer rate equivalent to that of the 16QAM modulation method is realized by combining the modulation methods of the outer frame and the inner frame. However, the present invention is not limited to this, and other modulation schemes, for example, a data transfer rate equivalent to 64QAM may be realized. In order to make it equivalent to 64QAM, for example, the QPSK modulation schemes of the outer frame, the middle frame, and the inner frame may be combined. At this time, in the demodulation on the receiving side, the same processing is repeated in the order of the outer frame QPSK, the middle frame QPSK, and the inner frame QPSK.

  In the above embodiment, the configuration in which the modulation schemes used for the outer frame and the inner frame are both QPSK modulation schemes has been described. However, the present invention is not limited to this, and different modulation schemes may be combined. In this case, a combination in which the modulation level of the inner frame is smaller than the modulation level of the outer frame is preferable. Also, the encoding method and encoding rate for the outer frame signal and the encoding method and encoding rate for the inner frame signal may be the same or different.

  Further, in the above-described embodiment, the configuration has been described in which the output of the outer frame modulator 103 is amplified by the amplifier 104 and the symbols outside the symbols output from the inner frame modulator 106 are generated in the transmission device 100. However, the present invention is not limited to this, and an attenuator or the like may be used so that the symbol output from the inner frame modulator 106 is located inside the symbol output from the outer frame modulator 103.

  In the above embodiment, the outer frame first demodulation / decoding circuit 204, the outer frame first replica signal generation circuit 205, and the outer frame first division circuit 206, the outer frame second demodulation / decoding circuit 213, and the outer frame second The replica signal generation circuit 214 and the outer frame second division circuit 215 have the same configuration. Therefore, a switching circuit is provided for inputting either the synthesized reception signal output from the reception filter bank 202 or the signal output from the addition circuit 212 to the outer frame first demodulation / decoding circuit 204, and according to the signal to be demodulated. Thus, the switching circuit may be controlled. Similarly, since the inner frame first demodulation / decoding circuit 208 and the inner frame second demodulation / decoding circuit 218 have the same configuration, the signal in the time domain corresponding to the compressed sub-spectrum of the signal of the outer frame QPSK in the combined reception signal. Or a signal obtained by suppressing a signal in the time domain corresponding to the compressed subspectrum of the signal of the outer frame QPSK and adding a signal corresponding to the missing subspectrum of the signal of the inner frame QPSK in the combined reception signal A switching circuit for switching between and inputting may be provided.

  Note that the first demodulator described in the present invention corresponds to the outer frame first demodulation / decoding circuit 204 or the outer frame second demodulation / decoding circuit 213 in the embodiment. The first replica signal generation unit described in the present invention corresponds to the outer frame first replica signal generation circuit 205 or the outer frame second replica signal generation circuit 214 in the embodiment. The first subtraction unit described in the present invention corresponds to the subtraction circuit 207 or the subtraction circuit 216 in the embodiment. The second demodulator described in the present invention corresponds to the inner frame first demodulation / decoding circuit 208 or the inner frame second demodulation / decoding circuit 218 in the embodiment. The second replica signal generation unit described in the present invention corresponds to the inner frame first replica signal generation circuit 209 in the embodiment. The second subtraction unit described in the present invention corresponds to the subtraction circuit 211 in the embodiment.

100, 510 Transmitting apparatus 101, 301, 361, 604, 614 Series-parallel conversion circuit 102 Outer frame error correction encoder 103 Outer frame modulator 104 Amplifier 105 Inner frame error correction encoder 106 Inner frame modulator 107, 212, 217, 608, 619 Adder circuit 108, 602 Transmission filter bank 109 D / A conversion circuit 200, 520 Reception device 201 A / D conversion circuit 202, 612 Reception filter bank 203 Reception buffer 204 Outer frame first demodulation / decoding circuit 205 Outer frame First replica signal generation circuit 206 Outer frame first division circuit 207, 211, 216 Subtraction circuit 208 Inner frame first demodulation / decoding circuit 209 Inner frame first replica signal generation circuit 210 Inner frame first division circuit 213 Outer frame second demodulation Decoding circuit 214 Outer frame second replica signal generation circuit 215 Outer frame second division times 218 Inner frame second demodulation / decoding circuit 219, 309, 365, 367, 610 Parallel / serial conversion circuit 302, 362, 605, 615 FFT circuit 303, 616 Extraction circuit 304 Frequency shift circuit 305 Transmission path estimator 306 Amplitude phase control circuit 307 Synthesis circuit 308, 364, 366, 609, 620, IFFT circuit 341, 613 demodulation circuit 342 decoding circuit 351 re-encoding circuit 352 re-modulation circuit 363, 606 division circuit 500 wireless communication system 601 modulation circuit SW-1, SW-2 , SW-N switch 603 D / A converter 607-1, 607-2, 607-N, 617-1, 617-2, 617-N Frequency shifter 611 A / D converter 618 Distortion compensation circuit

Claims (6)

A transmission device that divides an occupied band occupied by transmission data and distributes and distributes the signal on the frequency axis, and a reception that synthesizes and demodulates a signal transmitted by the transmission device that is distributed on the frequency axis A wireless communication system comprising:
The transmitter is
A serial-parallel converter that serial-parallel converts the transmission data into a plurality of data strings;
Modulation that generates a signal by modulating each of the plurality of data sequences with a modulation method with a low modulation multi-level number that is less than the modulation multi-level number of the modulation method corresponding to the desired data transfer rate, and combining the signals obtained by the modulation And
With
The receiving device is:
First demodulation for demodulating a first demodulated signal corresponding to any one of the data sequences based on the low-modulation multi-level modulation scheme from a received signal that has received the signal generated by the modulation unit And
A first replica signal generator for generating a first replica signal from the first demodulated signal demodulated by the first demodulator;
A first subtraction unit that subtracts the first replica signal from the received signal to calculate a first suppression signal;
A second demodulator that demodulates a second demodulated signal corresponding to another data sequence based on the low modulation multi-level modulation scheme from the first suppression signal calculated by the first subtractor;
A second replica signal generator for generating a second replica signal from the second demodulated signal demodulated by the second demodulator;
A second subtracting unit that calculates a second suppression signal by subtracting the second replica signal from the received signal;
With
The first demodulator further demodulates the second suppression signal based on the low-modulation multi-level modulation scheme, and updates the first demodulated signal. Communications system. The wireless communication system according to claim 1, wherein
The receiving device is:
Dividing the first replica signal into a missing signal corresponding to a band that is not distributed and a compressed signal corresponding to a band that is distributed in the occupied band occupied by the transmission data in the transmission device And a first dividing unit that outputs
A first addition unit that corrects the second suppression signal by adding and synthesizing the missing signal output from the first division unit to the second suppression signal calculated by the second subtraction unit;
Further comprising
The first subtracting unit calculates the first suppression signal by subtracting the compressed signal output from the first dividing unit from the received signal,
The first demodulation unit demodulates the corrected second suppression signal based on the low modulation multi-level modulation scheme and updates the first demodulation signal. Wireless communication system. The wireless communication system according to claim 2,
The receiving device is:
Dividing the second replica signal into a missing signal corresponding to a band that is not distributed and a compressed signal corresponding to a band that is distributed in the occupied band occupied by the transmission data in the transmission device A second dividing unit that outputs the output,
A second addition unit that corrects the first suppression signal by adding and combining the missing signal output from the second division unit to the first suppression signal output from the first subtraction unit;
Further comprising
The second subtracting unit subtracts the compressed signal output from the second dividing unit from the received signal to calculate the second suppression signal,
The second demodulation unit demodulates the corrected first suppression signal based on the low-modulation multi-level modulation scheme and updates the second demodulation signal. Wireless communication system. In the radio | wireless communications system as described in any one of Claims 1-3,
The modulator is
When modulating each of the plurality of data strings, using a modulation method in which the distance from the origin to each symbol is different on the complex plane,
The first demodulator includes:
The first demodulated signal is demodulated based on a modulation method that is used to modulate each of the plurality of data strings and has a long distance from the origin to each symbol on the complex plane. Wireless communication system. A transmission device that divides an occupied band occupied by transmission data and distributes and distributes the signal on the frequency axis, and a reception that synthesizes and demodulates a signal transmitted by the transmission device that is distributed on the frequency axis A receiving device in a wireless communication system comprising:
Modulation of each of a plurality of data strings obtained by serial-parallel conversion of the transmission data in a modulation scheme of a low modulation multilevel number smaller than the modulation multilevel number of the modulation scheme corresponding to a desired data transfer rate, and a signal obtained by the modulation A first demodulator that demodulates a first demodulated signal corresponding to any one of the data sequences based on the low-modulation multi-level modulation scheme for a received signal that has received the synthesized signal When,
A first replica signal generator for generating a first replica signal from the first demodulated signal demodulated by the first demodulator;
A first subtraction unit that subtracts the first replica signal from the received signal to calculate a first suppression signal;
A second demodulator that demodulates a second demodulated signal corresponding to another data sequence based on the low modulation multi-level modulation scheme for the first suppression signal calculated by the first subtractor When,
A second replica signal generator for generating a second replica signal from the second demodulated signal demodulated by the second demodulator;
A second subtracting unit that calculates a second suppression signal by subtracting the second replica signal from the received signal;
With
The first demodulator further demodulates the second suppression signal based on the low-modulation multi-level modulation scheme and updates the first demodulated signal. apparatus. A transmission device that divides an occupied band occupied by transmission data and distributes and distributes the signal on the frequency axis, and a reception that synthesizes and demodulates a signal transmitted by the transmission device that is distributed on the frequency axis A wireless communication method in a wireless communication system comprising the apparatus,
A serial-parallel conversion step for serial-parallel conversion of the transmission data into a plurality of data strings;
Modulation that generates a signal by modulating each of the plurality of data sequences with a modulation method with a low modulation multi-level number that is less than the modulation multi-level number of the modulation method corresponding to the desired data transfer rate, and combining the signals obtained by the modulation Steps,
A transmission step of transmitting the signal generated in the modulation step to the receiving device;
A first demodulation step of demodulating a first demodulated signal corresponding to any one of the data sequences from the received signal received from the transmission device based on the modulation scheme of the low-modulation multilevel number;
A first replica signal generation step of generating a first replica signal from the first demodulated signal demodulated in the first demodulation step;
A first subtraction step of subtracting the first replica signal from the received signal to calculate a first suppression signal;
A second demodulation step of demodulating a second demodulated signal corresponding to another data sequence from the first suppression signal calculated in the first subtraction step based on the low modulation multi-level modulation scheme;
A second replica signal generation step of generating a second replica signal from the second demodulated signal demodulated in the second demodulation step;
A second subtraction step of subtracting the second replica signal from the received signal to calculate a second suppression signal;
A wireless communication method comprising: an updating step of performing demodulation on the second suppression signal based on the low modulation multi-level modulation scheme and updating the first demodulated signal.

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