JP5585649B2 - 金属ベース基板およびその製造方法 - Google Patents
金属ベース基板およびその製造方法 Download PDFInfo
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- JP5585649B2 JP5585649B2 JP2012508230A JP2012508230A JP5585649B2 JP 5585649 B2 JP5585649 B2 JP 5585649B2 JP 2012508230 A JP2012508230 A JP 2012508230A JP 2012508230 A JP2012508230 A JP 2012508230A JP 5585649 B2 JP5585649 B2 JP 5585649B2
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- C04B2237/70—Forming laminates or joined articles comprising layers of a specific, unusual thickness
- C04B2237/708—Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the interlayers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Inorganic Chemistry (AREA)
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- Compositions Of Oxide Ceramics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
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- Insulated Metal Substrates For Printed Circuits (AREA)
Description
1.複合グリーンシートの作製
BaCO3、Al2O3、およびSiO2(クオーツ)の各粉末を用意し、これらを混合した混合粉末を840℃の温度で120分間仮焼することによって、原料粉末を作製し、この原料粉末およびMnCO3粉末を、分散剤が添加された有機溶剤中で混合し、後に樹脂および可塑剤を添加してさらに混合して、低温焼結セラミック材料を含む低温焼結セラミックスラリーを得た。
(1)第1の評価用試料
平面寸法30mm□、厚み0.8mmの純銅からなる銅板の両面に、上記複合グリーンシートを10枚ずつ積層し、温度80℃、圧力80kgf/cm2の条件で300秒間プレスし、未焼成の第1の評価用試料を作製した。ここで、銅板には、複合グリーンシートの低温焼結セラミックグリーン層側が接し、この評価用試料の両主面には、難焼結性セラミックグリーン層が露出するように積層した。
上記第1の評価用試料の作製途中の複合グリーンシートの積層段階において、銅板側から7層目および8層目の複合グリーンシートとして、コンデンサを構成するように銅ペーストを用いて平面寸法4mm□の導体パターンを互いに同じ位置に形成した複合グリーンシートを用いたことを除いて、第1の評価用試料の場合と同様の操作を経て、第2の評価用試料を得た。
表2に示すように、「平面気孔率」、「界面接合性」および「絶縁信頼性」を評価した。
平面気孔率は、焼結性を評価するために求めたもので、第1の評価用試料を断面研磨し、走査型電子顕微鏡(SEM)を用いて、倍率1000倍でセラミック部分を観察し、画像解析により平面気孔率を測定した。各試料につき10視野画像解析し、その平均値を表2に示した。
第1の評価用試料を断面研磨し、SEMを用いて、倍率5000倍で銅板とセラミック部分との界面部でのクラック発生状況を観察した。各試料で30視野観察し、クラックの全く発生していない場合は界面接合性が良好であると判定し、表2において「○」で示し、他方、1箇所でもクラックが発生している場合は界面接合性が不良であると判定し、表2において「×」で示した。
第2の評価用試料を用い、温度:121℃、湿度:100%、導体パターン間への印加電圧:100DCV、および試験時間:300時間の条件で試験した。試験後の抵抗値を測定電圧:100DCVで測定した。この測定結果が表2に示されている。
1.複合グリーンシートの作製
BaCO3、Al2O3、SiO2(クオーツ)、およびH3BO3の各粉末を用意し、これらを混合した混合粉末を840℃の温度で120分間仮焼することによって、原料粉末を作製し、この原料粉末を、分散剤が添加された有機溶剤中で混合し、後に樹脂および可塑剤を添加してさらに混合して、低温焼結セラミック材料を含む低温焼結セラミックスラリーを得た。
実験例1の場合と同様の操作を経て、第1の評価用試料および第2の評価用試料を得た。
実験例1の場合と同様の方法で、表4に示すように、「平面気孔率」、「界面接合性」および「絶縁信頼性」を評価した。
12 金属ベース基板
14 金属板
15 低温焼結セラミック層
16 拘束層
22 ガラス層
Claims (3)
- 少なくとも表面にCu成分を含む金属板と、
前記金属板の上に形成されたCu−Ba−Si系のガラスからなる厚み1〜5μmのガラス層と、
前記ガラス層の上に形成された低温焼結セラミック層と
を備え、
前記低温焼結セラミック層は、バリウムをBaO換算で10〜40モル%およびケイ素をSiO 2 換算で40〜80モル%含む、金属ベース基板。 - 前記ガラス層は、前記金属板の少なくとも表面の成分と前記低温焼結セラミック層の成分との少なくとも一部からなる、請求項1に記載の金属ベース基板。
- 少なくとも表面にCu成分を含む金属板を準備する工程と、
前記金属板の表面上に、バリウムをBaO換算で10〜40モル%およびケイ素をSiO2換算で40〜80モル%含む低温焼結セラミック材料を含む、低温焼結セラミックグリーン層を積層することによって、生の積層体を作製する工程と、
前記生の積層体を、前記低温焼結セラミックグリーン層が焼結する温度で焼成する工程と
を備え、
前記焼成工程の結果、前記低温焼結セラミックグリーン層が焼結して得られた低温焼結セラミック層と前記金属板との間に、厚み1〜5μmのガラス層が形成される、金属ベース基板の製造方法。
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JPH10167851A (ja) * | 1996-12-05 | 1998-06-23 | Ngk Insulators Ltd | 金属とセラミックスの接合方法 |
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JPS63277549A (ja) * | 1987-05-08 | 1988-11-15 | Fujitsu Ltd | 超伝導セラミックスペ−スト組成物 |
US5256469A (en) | 1991-12-18 | 1993-10-26 | General Electric Company | Multi-layered, co-fired, ceramic-on-metal circuit board for microelectronic packaging |
KR970008145B1 (ko) * | 1991-12-18 | 1997-05-21 | 제너럴 일렉트릭 컴페니 | 세라믹-온 금속-회로 기판 및 그 제조방법 |
JPH05286776A (ja) * | 1992-04-06 | 1993-11-02 | Noritake Co Ltd | 金属−セラミックス複合構造体及びその製造方法 |
US5581876A (en) | 1995-01-27 | 1996-12-10 | David Sarnoff Research Center, Inc. | Method of adhering green tape to a metal support substrate with a bonding glass |
DE69623930T2 (de) | 1995-01-27 | 2003-05-15 | Sarnoff Corp., Princeton | Gläser mit niedrigem dielektrischem verlust |
JPH11514627A (ja) | 1995-11-03 | 1999-12-14 | サーノフ コーポレイション | 多層共焼成セラミック組成物およびセラミックオンメタル回路基板 |
US5725808A (en) * | 1996-05-23 | 1998-03-10 | David Sarnoff Research Center, Inc. | Multilayer co-fired ceramic compositions and ceramic-on-metal circuit board |
JP3601208B2 (ja) * | 1996-09-26 | 2004-12-15 | 富士電機デバイステクノロジー株式会社 | 半導体装置用基板およびその製造方法 |
US5866240A (en) * | 1997-03-06 | 1999-02-02 | Sarnoff Corporation | Thick ceramic on metal multilayer circuit board |
US6753277B2 (en) * | 2000-02-29 | 2004-06-22 | Kyocera Corporation | Ceramics having excellent high-frequency characteristics and method of producing the same |
JP2001267443A (ja) * | 2000-03-14 | 2001-09-28 | Kyocera Corp | 半導体素子収納用パッケージ |
CN1142615C (zh) * | 2000-05-29 | 2004-03-17 | 北京科大天宇微电子材料技术开发有限公司 | 一种薄膜集成天线及其制作方法 |
JP2006095677A (ja) * | 2004-08-30 | 2006-04-13 | Showa Denko Kk | 研磨方法 |
US20080289866A1 (en) | 2004-12-28 | 2008-11-27 | Ngk Spark Plug Co., Ltd. | Wiring Board and Wiring Board Manufacturing Method |
JP4825012B2 (ja) | 2005-01-21 | 2011-11-30 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
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CN102822112A (zh) | 2012-12-12 |
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