JP5577796B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same.

  In general, a thin film transistor using amorphous silicon, polycrystalline silicon, or the like has been used as a transistor for driving an electronic device. However, since a high-temperature amorphous silicon or polycrystalline silicon requires a film forming temperature of 200 ° C. or higher, in order to realize a flexible device, it is extremely It was necessary to use an expensive film with a high water absorption rate that was difficult to handle.

  In recent years, thin film transistors using organic semiconductor materials have been actively studied. Since the organic semiconductor material can be produced by a printing process without using a vacuum process, there is an advantage that the cost can be significantly reduced and the organic semiconductor material is provided on a flexible plastic substrate. However, the mobility of the organic semiconductor material is extremely low, and it is difficult to deteriorate with time.

In view of the above situation, oxide semiconductor materials that can be formed at a low temperature have attracted much attention in recent years. For example, it has been reported that a thin film transistor formed on a PET (polyethylene terephthalate) substrate using an amorphous In—Ga—Zn—O-based material as a semiconductor active layer has excellent characteristics with a mobility of about 10 cm ² / Vs. (See Non-Patent Document 1). By demonstrating that high mobility can be achieved at room temperature, it is possible to form transistors on inexpensive general-purpose plastic substrates such as PET, and there is a great expectation for widespread use of flexible displays that are lightweight and difficult to break. It has increased. However, the surface roughness of the plastic substrate is larger than that of the glass substrate. This is a big problem in realizing a flexible device.
In addition, as the gate insulating layer of the flexible thin film transistor using the above-described oxide semiconductor as a semiconductor active layer, for example, a single film of silicon oxide, silicon nitride, aluminum oxide, or the like formed at room temperature by sputtering is stacked A film is used (see Patent Document 1).

Japanese Patent Laid-Open No. 2007-73697

K. Nomura et al Nature, 432, 488 (2004)

However, when all gate insulating layers are formed by sputtering, the surface of the film formed by sputtering inherits the surface state of the substrate as it is, so when using a plastic substrate for the substrate, gate insulation The surface roughness of the layer is increased. In this case, there is a problem that the interface roughness between the gate insulating layer and the semiconductor active layer increases, which adversely affects the element characteristics.
Furthermore, when all the gate insulating layers are formed by sputtering, the sputtering method has a problem that the manufacturing cost increases because the film formation rate is low.

The above problem also applies when the gate insulating layer is formed using an atomic layer deposition method or a plasma CVD method.
Accordingly, the present invention has been made paying attention to the above-mentioned problems, and a thin film transistor in which the surface of the gate insulating layer is flat regardless of the surface roughness of the insulating substrate, the reliability is high, and the manufacturing cost is reduced. And it aims at providing the manufacturing method.

According to a first aspect of the present invention, a gate electrode is formed on an insulating substrate, a gate insulating layer is formed on the gate electrode and the insulating substrate, and a semiconductor active layer is formed on the gate insulating layer. And forming a source electrode and a drain electrode connected to the semiconductor active layer on the gate insulating layer, comprising:
The gate insulating layer includes a lower layer formed on the insulating substrate and at least one upper layer laminated on the lower layer in this order, and the lower layer is formed by a vacuum ultraviolet light CVD method. ,
Wherein at least one layer of the upper layer, the sputtering method is characterized atomic layer deposition, or that you have been formed by a plasma CVD method.
According to the first aspect of the present invention, the lower layer formed on the insulating substrate among the lower layer and the upper layer constituting the gate insulating layer is formed using the vacuum ultraviolet light CVD method. Regardless of the surface state, the surface of the gate insulating layer is flat, and as a result, a highly reliable thin film transistor can be provided.
Here, when silicon oxide is formed by a vacuum ultraviolet light CVD method, siloxane or the like of an organic silicon compound is formed as a material. At that time, the material gas is not completely decomposed, but a part of the reaction active species generated by decomposition is migrated to form a film while flowing. Therefore, Si—CH ₃ or the like contained in the material gas is also present. It is contained a lot in the film. For this reason, when the gate insulating layer formed by the vacuum ultraviolet light CVD method is not subjected to high-temperature annealing at 400 ° C. or higher, it may be difficult to provide sufficient voltage resistance with only one layer.
Therefore, as the upper layer, by using any one of a sputtering method, a plasma CVD method, and an atomic layer deposition method, by forming any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, A thin film transistor in which a gate insulating layer having a sufficient withstand voltage is formed can be obtained.

According to a second aspect of the present invention, in the method of manufacturing a thin film transistor according to the first aspect, the lower layer is made of a material containing silicon oxide.
According to the second aspect of the present invention, a thin film transistor having excellent insulating characteristics can be obtained by forming the lower layer with a material containing silicon oxide .

The invention according to claim 3 is the method of manufacturing a thin film transistor according to claim 1 or 2 , wherein at least one of the upper layers is at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. It is characterized by containing one kind of compound .

Also, it invention according to claim 4 is the method of manufacturing the thin film transistor according to any one of claims 1 to 3, the resistivity of the lower layer is 1.0 × 10 ¹¹ Ω · cm or more It is characterized by.
According to the invention of claim 4, when the resistivity of the lower layer is 1.0 × 10 ¹¹ Ω · cm or more, the gate insulating layer as a whole exhibits sufficient insulation, and gate leakage current is suppressed. A thin film transistor can be obtained.

The invention according to claim 5 is the method of manufacturing a thin film transistor according to any one of claims 1 to 4 , wherein after the formation of the lower layer, heat treatment is performed at 150 ° C. or more and 200 ° C. or less. Yes.
According to the invention of claim 5 , after forming the lower layer, a heat treatment is performed at 150 ° C. or higher and 200 ° C. or lower to obtain a gate insulating layer with better insulation, and gate leakage current is suppressed. A thin film transistor can be obtained.

According to a sixth aspect of the present invention, in the thin film transistor manufacturing method according to any one of the first to fifth aspects, the thickness of the lower layer is not less than 1/4 of the thickness of the gate insulating layer. / 2 or less.
According to the invention of claim 6 , since the thickness of the lower layer is ¼ or more and ½ or less of the thickness of the gate insulating layer, the gate insulating layer as a whole has a particularly excellent insulating property. Thus, a thin film transistor in which the gate leakage current is suppressed can be obtained.

The invention according to claim 7 is the method of manufacturing a thin film transistor according to any one of claims 1 to 6 , wherein the thickness of the lower layer is larger than the thickness of the gate electrode. .
According to the seventh aspect of the invention, by making the film thickness of the lower layer larger than the film thickness of the gate electrode, the step between the insulating substrate and the gate electrode is flattened, and a highly reliable transistor that hardly causes dielectric breakdown Can be obtained.

The invention according to claim 8 is the method of manufacturing a thin film transistor according to any one of claims 1 to 7 , wherein the semiconductor active layer is made of a metal oxide semiconductor.
According to the invention of claim 8 , since the semiconductor active layer is made of a metal oxide semiconductor, a thin film transistor having excellent transistor characteristics can be obtained.

The invention according to claim 9 is the method of manufacturing a thin film transistor according to claim 8 , wherein the metal oxide contains at least one of In, Ga, and Zn.
According to the ninth aspect of the invention, when the metal oxide contains at least one of In, Ga, and Zn, a thin film transistor having particularly excellent transistor characteristics can be obtained.

According to a tenth aspect of the present invention, in the method for manufacturing a thin film transistor according to any one of the first to ninth aspects, the insulating substrate is a flexible plastic substrate.
The invention according to claim 11 is manufactured by the method of manufacturing a thin film transistor according to any one of claims 1 to 9 .

  According to the present invention, it is possible to provide a thin film transistor and a manufacturing method thereof in which the surface of the gate insulating layer is flat regardless of the surface roughness of the insulating substrate, the reliability is high, and the manufacturing cost is reduced.

It is sectional drawing which shows the structure of the thin-film transistor obtained by one Embodiment of the manufacturing method of the thin-film transistor which concerns on this invention. It is sectional drawing which shows one Embodiment of the manufacturing method of the thin-film transistor which concerns on this invention. It is sectional drawing which shows the structure of the thin-film transistor obtained by other embodiment of the manufacturing method of the thin-film transistor which concerns on this invention. It is sectional drawing which shows the structure of the thin-film transistor obtained by the Example of the manufacturing method of the thin-film transistor which concerns on this invention. It is sectional drawing which shows the structure of the comparative example of a thin-film transistor.

Hereinafter, embodiments of a thin film transistor and a method for manufacturing the same according to the present invention will be described with reference to the drawings. Note that, in the description of the present embodiment, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.
FIG. 1 is a cross-sectional view showing a configuration of a thin film transistor obtained by an embodiment of a method of manufacturing a thin film transistor according to the present invention. FIG. 2 is a cross-sectional view showing an embodiment of a method for manufacturing a thin film transistor according to the present invention.

  As shown in FIG. 1, a thin film transistor 1 obtained by an embodiment of a method of manufacturing a thin film transistor according to the present invention includes an insulating substrate 10, a gate electrode 11 formed on the insulating substrate 10, and a gate electrode 11. A lower layer 12a formed to cover the gate electrode 11, an upper layer 12b formed on the lower layer 12a, a semiconductor active layer 13 formed on the upper layer 12b, and the semiconductor active layer 13 is a bottom gate-top contact type thin film transistor including a source electrode 14 and a drain electrode 15 formed on a gate insulating layer 12 so as to cover a part of the gate electrode 13 and connected to the semiconductor active layer 13. . The lower layer 12a and the upper layer 12b constitute the gate insulating layer 12, and the lower layer 12a in contact with the insulating substrate 10 is formed by a vacuum ultraviolet light CVD method.

<Insulating substrate>
As the insulating substrate 10, for example, a glass substrate or a plastic substrate can be used.
Examples of the plastic substrate include polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone (PES), polyolefin, polyethylene terephthalate, polyethylene naphthalate (PEN), cycloolefin polymer, polyethersulfene, triphenyl. Acetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluorine resin, cyclic polyolefin resin Etc. can be used.
These substrates can be used alone or a composite substrate in which two or more kinds are laminated. A substrate in which a resin layer such as a color filter is formed on a glass substrate or a plastic substrate can also be used.

<Electrode>
As materials for the gate electrode 11, the source electrode 14, and the drain electrode 15, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), indium oxide Oxide materials such as cadmium (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO ₄ ), zinc tin oxide (Zn ₂ SnO ₄ ), and indium zinc oxide (In—Zn—O) are preferably used.

  In addition, it is preferable that the gate electrode 11, the source electrode 14, and the drain electrode 15 be made of a material obtained by doping impurities into the oxide material in order to increase conductivity. For example, indium oxide doped with tin, molybdenum, titanium, tin oxide doped with antimony or fluorine, zinc oxide doped with indium, aluminum, gallium, and the like.

  Among these, indium tin oxide obtained by doping tin into indium oxide (commonly referred to as ITO) is particularly preferably used because of its low resistivity. In addition, low resistance metal materials such as Au, Ag, Cu, Cr, Al, Mg, and Li are also preferably used. Further, a laminate in which a plurality of conductive oxide materials and low resistance metal materials are stacked can be used. In this case, a three-layer structure in which a conductive oxide thin film / metal thin film / conductive oxide thin film is laminated in order in order to prevent oxidation or deterioration with time of the metal material is particularly preferably used. An organic conductive material such as PEDOT (polyethylenedioxythiophene) can also be suitably used. The gate electrode, the source electrode, and the drain electrode may all be the same material, or may be all different materials. However, in order to reduce the number of steps, it is more desirable that the source electrode and the drain electrode are made of the same material.

  These electrodes are formed by vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (chemical vapor deposition), photo CVD, hot wire CVD, or the like. In addition, the conductive material described above in an ink form or a paste form can be applied by screen printing, letterpress printing, an ink jet method or the like, and baked, but is not limited thereto.

<Gate insulation layer>
The gate insulating layer 12 includes a lower layer 12a and an upper layer 12b. The thickness of the gate insulating layer 12 is preferably 50 nm or more and 2 μm or less. The lower layer 12a is formed by a vacuum ultraviolet light CVD method.
Here, a film formed using the vacuum ultraviolet light CVD method has high self-flattening characteristics unlike a film formed using the magnetron sputtering method or the like.
In the vacuum ultraviolet light CVD method, a flat film is formed regardless of the material and surface shape of the insulating substrate 10. The film is not formed by a surface reaction, but is generated by photolysis in the gas phase. This is because a reactive active species such as the above deposits while migrating and flowing on the surface to form a thin film.

Therefore, by forming the lower layer 12a of the bottom gate type thin film transistor 1 using the vacuum ultraviolet light CVD method, the surface irregularities of the insulating substrate 10 and the insulating layer 10 are formed on the insulating substrate 10 before the gate insulating layer 12 is formed. Unevenness (steps) due to the formed pattern can be embedded and flattened, and a flat surface can be obtained.
Thus, by forming the gate insulating layer (lower layer) so as to reduce the unevenness on the surface of the insulating substrate 10, a flat gate insulating layer-semiconductor active layer interface is obtained, and the thin film transistor with improved transistor characteristics 1 can be obtained.

In addition, since vacuum ultraviolet light CVD can form a film at room temperature, it can be easily formed even when a plastic substrate is employed as the insulating substrate.
In addition, the vacuum ultraviolet light CVD method is different from the magnetron sputtering method, for example, in the case of forming a silicon oxide film, it is a method capable of forming a very fast film of 100 nm / min or more. Therefore, the manufacturing cost can be reduced by forming a part of the gate insulating layer using a photo-CVD method with a high film formation rate.

As a material of the lower layer 12a, for example, a material containing silicon oxide is preferable. Examples of the starting material include octamethylcyclotetrasiloxane and tetraethoxysilane / O ₂ .
The resistance value of the lower layer 12a is preferably 1.0 × 10 ¹¹ Ω · cm or more, more preferably 1.0 × 10 ¹² Ω · cm or more. When the resistance value is smaller than 1.0 × 10 ¹¹ Ω · cm, the gate insulating layer 12 as a whole cannot exhibit sufficient insulation, and the gate leakage current increases, so that good device characteristics cannot be obtained. .

The film thickness of the lower layer 12a is preferably 4/5 or less of the film thickness of the entire gate insulating layer 12 to provide sufficient insulation as the entire gate insulating layer 12 and to suppress gate leakage current. The film thickness of 12a is more preferably ¼ or more and ½ or less of the film thickness of the entire gate insulating layer 12.
Furthermore, by making the film thickness of the lower layer 12a larger than the film thickness of the gate electrode 11, the undulation of the shape of the gate electrode 11 and the level difference between the insulating substrate 10 and the gate electrode 11 are flattened, and the breakdown is less likely to occur. It is possible to obtain a high transistor.

  Here, the upper layer 12b may be a single layer, or a plurality of layers may be stacked. That is, the configuration of the gate insulating layer 12 is not limited to the configuration including the lower layer 12a and one or more upper layers 12b, and a plurality of gate insulating layers (lower layer 12a and upper layer 12b) are provided on at least the insulating substrate 10. The gate insulating layer 12 formed to constitute the gate insulating layer 12 and formed on the insulating substrate 10 may be formed by vacuum ultraviolet light CVD.

Further, the material of the upper layer 12b is not particularly limited as long as it has sufficient insulation for suppressing the gate leakage current, but a material having a resistivity of 1.0 × 10 ¹² Ω · cm or more is preferable, Furthermore, it is preferably 1.0 × 10 ¹⁴ Ω · cm or more.
As the material constituting the upper layer 12b, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide are particularly preferable. In addition, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, titanium oxide, and the like can also be used. By using these materials, sufficient insulation can be obtained to suppress gate leakage current. it can.

<Semiconductor active layer>
Examples of the material of the semiconductor active layer 13 include oxides containing one or more elements of zinc, indium, tin, tungsten, magnesium, and gallium. Well-known materials such as zinc oxide, indium oxide, indium zinc oxide, tin oxide, tungsten oxide, and zinc gallium indium oxide (In—Ga—Zn—O) may be used, but the material is not limited to these. The structure of these materials may be single crystal, polycrystal, microcrystal, crystal / amorphous mixed crystal, nanocrystal scattered amorphous, or amorphous. The thickness of the semiconductor active layer is preferably at least 10 nm. If it is smaller than 10 nm, there may occur a problem that a portion where no semiconductor is formed in the film is generated due to island-like growth.

<Method for Manufacturing Thin Film Transistor>
Next, a method for manufacturing the thin film transistor 1 will be described with reference to FIG.
First, as shown in FIG. 2A, the gate electrode 11 is formed (film formation) on the insulating substrate 10 using a sputtering apparatus or the like.
Next, as shown in FIG. 2B, a lower layer 12a made of a material containing silicon oxide is formed (film formation) so as to cover the insulating substrate 10 and the gate electrode 11 using a vacuum ultraviolet light CVD apparatus. To do.

  Then, after forming (depositing) the lower layer 12a, heat treatment is performed on the insulating substrate 10 on which the lower layer 12a is formed. This heat treatment is preferably performed at 150 ° C. or higher and 200 ° C. or lower. If the heat treatment temperature is lower than 150 ° C., the insulation properties may deteriorate. Further, when the heat treatment temperature exceeds 200 ° C., the resistance of the insulating substrate and the lower layer as a base material is lowered. By performing the heat treatment in the above range, a gate insulating layer with better insulation can be obtained.

Next, as shown in FIG. 2C, an upper layer 12b is formed (deposited) on the lower layer 12a using a sputtering apparatus or the like.
The upper layer 12b is preferably formed by sputtering, plasma CVD, or atomic layer deposition, but methods such as vacuum deposition, ion plating, laser ablation, and hot wire CVD may also be used. Absent. As these upper layers 12b, those whose composition is inclined toward the growth direction of the film can also be suitably used.
The lower layer 12a and the upper layer 12b thus formed constitute the gate insulating layer 12.

Next, as shown in FIG. 2D, the semiconductor active layer 13 is formed (deposited) on the upper layer 12b.
The semiconductor active layer 13 is formed using a method such as a sputtering method, a pulse laser deposition method, a vacuum evaporation method, a CVD method, or a sol-gel method. Of these methods, the sputtering method, the pulse laser deposition method, the vacuum evaporation method, and the CVD method are preferable. Examples of sputtering include RF magnetron sputtering, DC sputtering, and ion beam sputtering. Vacuum deposition includes heating deposition, electron beam deposition, and ion plating. CVD includes hot wire CVD and plasma. Examples include, but are not limited to, CVD.

The semiconductor active layer 13 is mainly composed of a metal oxide, and examples of the metal oxide include an oxide containing one or more elements of zinc, indium, tin, tungsten, magnesium, and gallium. Note that the temperature in forming the gate insulating layer 12 and the semiconductor active layer 13 is both room temperature.
Further, when a plurality of upper layers 12b are formed, it is more preferable that the method of forming the semiconductor active layer 13 and the layer in contact with the semiconductor active layer 13 among the plurality of upper layers 12b are the same. By performing continuous film formation in the same chamber, a thin film transistor having excellent device characteristics and high reliability can be obtained.

Thereafter, the semiconductor active layer 13 is patterned by etching using a photolithography method.
Thereafter, as shown in FIG. 2E, the source electrode 14 and the drain electrode 15 are formed (deposited) on the semiconductor active layer 14 by vapor deposition, whereby the thin film transistor 1 is obtained.

(Other embodiments)
FIG. 3 is a cross-sectional view showing the configuration of another embodiment of the thin film transistor according to the present invention.
As shown in FIG. 3, as another embodiment, the thin film transistor 1 is formed so as to cover the gate electrode 11 on the insulating substrate 10, the gate electrode 11 formed on the insulating substrate 10, and the gate electrode 11. Lower layer 12a, upper layer 12b formed on lower layer 12a, source electrode 14 and drain electrode 15 formed on upper layer 12b, and part of source electrode 14 and drain electrode 15 A bottom gate-top contact thin film transistor including a semiconductor active layer 13 formed on the upper layer 12b and connected to each of the source electrode 14 and the drain electrode 15 may be used. Also in this embodiment, the lower layer 12a and the upper layer 12b constitute the gate insulating layer 12, and the lower layer 12a in contact with the insulating substrate 10 is formed by vacuum ultraviolet light CVD.

Examples 1 to 6 and Comparative Examples 1 and 2 of the thin film transistor of the present invention and the manufacturing method thereof will be described below.
Example 1
In Example 1, a thin film transistor 1 as shown in FIG. 4 was produced as follows.
On the PEN base material (Q65 manufactured by Teijin DuPont Co., Ltd., thickness: 125 μm) as the insulating substrate 10, ITO was formed to a thickness of 80 nm using a DC magnetron sputtering apparatus, and the gate electrode 11 was formed by etching using a photolithography method. The input power during the ITO film formation was 100 W, the gas flow rate was Ar = 50 SCCM, O ₂ = 0.1 SCCM, and the film formation pressure was 1.0 Pa.

Next, a lower layer 12a made of SiO _{2 was formed} to a thickness of 100 nm using a vacuum ultraviolet light CVD apparatus. The lower layer 12a was formed with a flow of 5 SCCM of octamethylcyclotetrasiloxane as a raw material, with an input power of 100 W and a film formation pressure of 10 Pa. After the film formation, the substrate was heat-treated in the air at 150 ° C. for 3 hours. The resistivity obtained using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 1.3 × 10 ¹² Ω · cm.

Thereafter, the upper layer 12b made of SiON is formed on the lower layer 12a with an RF magnetron sputtering apparatus to 300 nm (input power is 500 W, Ar = 50 SCCM, O ₂ = 20 SCCM, film forming pressure 1.0 Pa), In—Ga—Zn A semiconductor active layer 13 made of an O-based oxide was continuously formed at 40 nm (input power 100 W, Ar = 100 SCCM, O ₂ = ₂ SCCM, film forming pressure 1.0 Pa). The substrate temperature in each film formation is room temperature.

  Then, after patterning the semiconductor active layer 13 by etching using a photolithography method, the source electrode 14 and the drain electrode 15 made of Al are formed with a film thickness of 100 nm by EB (Electron Beam) deposition using a metal mask. A thin film transistor 1 was obtained. The length between the source / drain electrodes is 0.2 mm, and the width between the source / drain electrodes is 2 mm. The film thickness was measured with a stylus type film thickness meter (manufactured by ULVAC, Dektak 6M). The deposition rate of the lower layer 12a is 100 nm / min, and the deposition rate of the upper layer 12b is 10 nm / min. Therefore, the time required for forming the gate insulating layer 12 was 31 min. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 1 manufactured as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 1 measured by using a semiconductor parameter analyzer (SCS4200 manufactured by Keithley) was 10 cm ² / Vs, and when a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio was 6 digits and the subthreshold swing value (s value) was 0.8 V / decade. The gate leakage current at a gate voltage of 20 V was 2.3 × 10 ⁻¹¹ A, showing good transistor characteristics and sufficiently suppressing the gate leakage current.

(Example 2)
A thin film transistor 1 was fabricated in the same manner as in Example 1 except that the thickness of the lower layer was 200 nm and the thickness of the upper layer 12b was 200 nm. The resistivity of the lower layer 12a was 1.3 × 10 ¹² Ω · cm, as in Example 1. The time required for forming the gate insulating layer 12 was 22 minutes. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 2 manufactured as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 2 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 10 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio is 6 digits, the s value is 0.8 V / decade, and the gate leakage current is 9.5 × 10 ⁻¹¹ A when the gate voltage is 20 V. The current was suppressed.

Example 3
A thin film transistor 1 was fabricated in the same manner as in Example 1 except that the thickness of the lower layer 12a was 320 nm and the thickness of the upper layer 12b was 80 nm. The resistivity of the lower layer 12a was 1.3 × 10 ¹² Ω · cm, as in Example 1. The time required for forming the gate insulating layer 12 was 11.2 min. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 3 manufactured as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 3 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 8 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio is 5 digits, the s value is 1.0 V / decade, and the gate leakage current at a gate voltage of 20 V is 1.1 × 10 ⁻¹⁰ A. Compared with Example 1, the value of the gate leakage current is Large but good device characteristics.

Example 4
A thin film transistor 1 was produced in the same manner as in Example 3 except that the heat treatment conditions after the formation of the lower layer 12a were changed. The heat treatment was performed in the air at 80 ° C. for 3 hours. The resistivity of the lower layer 12a was 1.3 × 10 ¹¹ Ω · cm. The time required for forming the gate insulating layer 12 was 11.2 min. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 4 fabricated as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 4 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 7 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio is 4 digits, the s value is 1.5 V / decade, and the gate leakage current when the gate voltage is 20 V is 1.5 × 10 ⁻⁹ A. Compared with Example 1, the value of the gate leakage current is Large but good device characteristics.

(Example 5)
A thin film transistor 1 was produced in the same manner as in Example 3 except that an Al ₂ O ₃ film was formed using an atomic layer deposition apparatus as the upper layer 12b. Al ₂ O ₃ was deposited at a substrate temperature of 150 ° C. using trimethylaluminum and H ₂ O as raw materials. The resistivity of the lower layer 12a was 1.3 × 10 ¹² Ω · cm, as in Example 3. The film formation time for Al ₂ O ₃ was 3 nm / min, and the time required for film formation of the gate insulating layer 12 was 30 minutes. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 5 manufactured as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 5 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 12 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio was 7 digits, the s value was 0.4 V / decade, and the gate leakage current at a gate voltage of 20 V was 1.5 × 10 ⁻¹⁰ A, showing good device characteristics.

(Example 6)
A thin film transistor 1 was manufactured in the same manner as in Example 3 except that SiO ₂ was formed as the upper layer 12b using a parallel plate plasma CVD apparatus. SiO ₂ was deposited at a substrate temperature of 120 ° C., hexamethyldisiloxane (50 ° C.) at a gas flow rate of 5 SCCM, O ₂ at a gas flow rate of 50 SCCM, an input power of 100 W, and a deposition pressure of 20 Pa. The resistivity of the lower layer 12a was 1.3 × 10 ¹² Ω · cm, as in Example 3. The deposition time for SiO ₂ was 20 nm / min, and the time required for deposition of the gate insulating layer 12 was 7.2 min. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 6 fabricated as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 6 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 8 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio was 6 digits, the s value was 0.8 V / decade, and the gate leakage current at a gate voltage of 20 V was 1.8 × 10 ⁻¹⁰ A, showing good device characteristics.

(Example 7)
In FIG. 3, the thin film transistor 1 was produced in the same manner as in Example 3 except that SiN was formed as the upper layer 12 b using a parallel plate plasma CVD apparatus. SiN was deposited at a substrate temperature of 120 ° C., silane at a gas flow rate of 100 SCCM, ammonia at a gas flow rate of 50 SCCM, N ₂ at a gas flow rate of 1 SLM, and H ₂ at a gas flow rate of 1 SLM, with an input power of 100 W and a deposition pressure of 200 Pa. The resistivity of the lower layer 12a was 1.3 × 10 ¹² Ω · cm, as in Example 3. The deposition time for SiN was 20 nm / min, and the time required for deposition of the gate insulating layer 12 was 7.2 min. Table 1 shows the transistor characteristics of the thin film transistor 1 of Example 7 fabricated as described above.

As shown in Table 1, the mobility of the thin film transistor 1 of Example 7 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 9 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio was 6 digits, the s value was 0.7 V / decade, and the gate leakage current at a gate voltage of 20 V was 2.2 × 10 ⁻¹⁰ A, showing good device characteristics.

(Example 8)
In FIG. 3, the thin film transistor 1 was manufactured in the same manner as in Example 3 except that the heat treatment after forming the lower layer 12 a was not performed. The resistivity of the formed lower layer 12a was 1.0 × 10 ¹¹ Ω · cm, and the carbon content was 30 atm%.
The thin film transistor 1 in which the thin film transistor element is formed on the insulating substrate was subjected to a test repeatedly wound 10 times around a cylinder having a diameter of 2 cm, and then the element of the thin film transistor 1 of Example 8 using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200). As a result of measuring the characteristics, the mobility was 7 cm ² / Vs, the ON / OFF ratio when a voltage of 10 V was applied between the source / drain electrodes was 3 digits, and the gate leakage current at a gate voltage of 20 V was 3.6 ×. It was 10 ⁻⁹ A. Compared with Example 1, the gate leakage current was large, but good device characteristics were shown.

(Comparative Example 1)
In Comparative Example 1, as shown in FIG. 5, a thin film transistor 100 in which the gate insulating layer 12 was a single layer was manufactured. Specifically, SiON is 400 nm (input power 500 W, Ar = 50 SCCM, O ₂ = 20 SCCM, film forming pressure 1.0 Pa) using an RF magnetron sputtering apparatus as the gate insulating layer 12 (upper layer 12 b). A thin film transistor 100 was fabricated in the same manner as in Example 1 except that the film was formed.

The resistivity of the formed gate insulating layer 12 was 7.3 × 10 ¹⁴ Ω · cm. Since the gate insulating layer 12 was formed at a rate of 10 nm / min, the time required for the film formation was 40 min. Table 1 shows the transistor characteristics of the thin film transistor 100 of Comparative Example 1 manufactured as described above.
As shown in Table 1, the mobility of the thin film transistor 100 of Comparative Example 1 measured using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200) was 1 cm ² / Vs, and a voltage of 10 V was applied between the source / drain electrodes. The ON / OFF ratio is 2 digits, the s value is 5.0 V / decade, and the gate leakage current at a gate voltage of 20 V is 3.5 × 10 ⁻¹¹ A. Compared with Example 1, the mobility and s The value was inferior, and good device characteristics could not be obtained.

(Comparative Example 2)
The gate insulating layer 12 is a single layer, and a SiO ₂ film having a thickness of 400 nm (input power 100 W, film forming pressure 10 Pa) is formed as a gate insulating layer 12 (lower layer 12 a) using a vacuum ultraviolet light CVD apparatus. A thin film transistor 100 was manufactured in the same manner as in Example 1.
The resistivity of the formed gate insulating layer 12 was 1.3 × 10 ¹² Ω · cm. Since the gate insulating layer 12 was formed at a rate of 100 nm / min, the time required for the film formation was 4 min. Table 1 shows the transistor characteristics of the thin film transistor 100 of Comparative Example 2 manufactured as described above.
As shown in Table 1, device breakdown occurred during evaluation of device characteristics using a semiconductor parameter analyzer (manufactured by Keithley, SCS4200), and the device characteristics of the thin film transistor 100 of Comparative Example 2 could not be evaluated.

In the thin film transistor manufacturing method of the present invention, the gate insulating layer has a multilayer structure of two or more layers, and the layer in contact with the substrate is formed by a vacuum ultraviolet light CVD method so that the film surface is flat regardless of the surface state of the substrate. The gate insulating layer can be provided in a short time. Thus, a thin film transistor with high reliability and reduced manufacturing cost can be provided.
The thin film transistor thus obtained can be used as a switching element for electronic paper, LCD, organic EL display and the like by taking advantage of the characteristics of high reliability and reduced manufacturing cost. In particular, the present invention can be widely applied to flexible displays, IC cards, IC tags, etc. using a flexible substrate as a substrate.
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Thin-film transistor 10 Insulating substrate 11 Gate electrode 12 Gate insulating layer 12a Lower layer 12b Upper layer 13 Semiconductor active layer 14 Source electrode 15 Drain electrode

Claims (11)

Forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode and the insulating substrate; forming a semiconductor active layer on the gate insulating layer; and a source electrode connected to the semiconductor active layer; A method for producing a bottom-gate thin film transistor in which a drain electrode is formed on the gate insulating layer,
The gate insulating layer includes a lower layer formed on the insulating substrate and at least one upper layer laminated on the lower layer in this order, and the lower layer is formed by a vacuum ultraviolet light CVD method. ,
At least one layer, sputtering, atomic layer deposition, or a method of manufacturing the thin film transistor is characterized that you have been formed by plasma CVD of the upper layer.   2. The method of manufacturing a thin film transistor according to claim 1, wherein the lower layer is made of a material containing silicon oxide. 3. The method of manufacturing a thin film transistor according to claim 1, wherein at least one of the upper layers contains any one compound of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide . 4. The method of manufacturing a thin film transistor according to claim 1, wherein the resistivity of the lower layer is 1.0 × 10 ¹¹ Ω · cm or more . 5. 5. The method for manufacturing a thin film transistor according to claim 1 , wherein after the lower layer is formed, heat treatment is performed at 150 ° C. to 200 ° C. 5 . 6. The method of manufacturing a thin film transistor according to claim 1, wherein the thickness of the lower layer is not less than 1/4 and not more than 1/2 of the thickness of the gate insulating layer . 7. The method of manufacturing a thin film transistor according to claim 1 , wherein a thickness of the lower layer is larger than a thickness of the gate electrode . The method for manufacturing a thin film transistor according to claim 1 , wherein the semiconductor active layer is made of a metal oxide semiconductor . 9. The method of manufacturing a thin film transistor according to claim 8, wherein the metal oxide is a metal oxide containing at least one of In, Ga, and Zn . The method for manufacturing a thin film transistor according to claim 1, wherein the insulating substrate is a flexible plastic substrate . A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1.

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