JP5568891B2 - Heterojunction field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a heterojunction field effect transistor which is a nitride semiconductor field effect transistor in which the traveling direction of electrons under a gate electrode which is a carrier is substantially parallel to a substrate surface, and a method for manufacturing the same.

  In the nitride semiconductor FET structure, conventionally, a method of increasing the gate-drain distance (Lgd) has been taken in order to increase the operating voltage and breakdown voltage. For example, Kaneko et al. Have an AlGaN / GaN heterojunction capable of high-voltage operation in the Japanese Journal of Applied Physics (Vol.43, No.7A, pp.L831-L833). It reports on FET.

  They stacked an AlN layer, a GaN / AlN superlattice layer, a 1 μm thick GaN layer, and an AlGaN layer on a Si (111) substrate, and then laminated Ti / Al as a source electrode and a drain electrode at 650 ° C. for 10 minutes. Heat treatment was performed.

  Furthermore, after laminating the SiOx film, the gate forming part was opened to form a gate electrode made of Ni / Au, the SiNx protective film was laminated, the plated part was opened, and finally the gold plated part was formed on the electrode part. .

  With this structure, the distance between the source electrode and the drain electrode is 16 μm. As described above, by increasing the distance between the source electrode and the drain electrode, the breakdown voltage can be set to 350 V or more, and a high voltage FET can be obtained.

  However, as in the above technique, even if the distance between the source electrode and the drain electrode (Lsd) is increased, the electric field distribution becomes non-uniform due to the influence of the surface (interface with the SiN film). There was a problem that the electric field was concentrated and the breakdown voltage could not be increased as expected from the physical properties of GaN.

  On the other hand, in order to obtain a desired withstand voltage, there is a problem that, for example, Lsd needs to be set to a large value of 15 μm or more as in the prior art, resulting in an increase in chip size. Therefore, a vertical transistor structure has been proposed in the nitride semiconductor FET structure in order to solve the above problems while maintaining a high operating voltage and withstand voltage.

  For example, Kanetica et al. In Japanese Journal of Applied Physics, Vol.46, No.21,2007, pp.L503-L505 A vertical AlGaN / GaN heterojunction FET with an aperture is reported.

FIG. 14 is a cross-sectional structure diagram of a field effect transistor reported by Kanetika et al. As shown in the figure, an n ⁻ -GaN layer 1002 to which Si is added, a p-GaN layer 1003 to which Mg is added, an AlN layer 1004 and an i-GaN layer 1005 are stacked on an n-GaN substrate 1001, and then SiO ₂ is masked. A portion of the p-GaN layer 1003, AlN layer 1004, i-GaN layer 1005 and n ⁻ -GaN layer 1002 to which Mg in the aperture portion is added is removed by dry etching, and after removing the SiO ₂ mask, Si is removed. The added n-GaN layer 1006 and i-AlGaN layer 1007 are regrown.

Next, Si ions are implanted into the ohmic contact region and activation annealing is performed, and then an ohmic electrode 1008 is formed. Next, after the SiO ₂ film 1009 was formed, the gate electrode 1010 made of n ⁺ -poly Si was formed and activated annealing was performed.

  Thus, by adopting a structure in which current flows vertically toward the back surface of the substrate through the aperture portion, the electric field distribution becomes uniform because it is not affected by the surface, and the physical property value of the breakdown voltage of GaN (3 MV / cm ) Can be expected to have a higher breakdown voltage.

  Currently, there are various proposals for the heterojunction field effect transistor as described above (see, for example, Patent Documents 1 to 4).

JP 2000-174285 A JP 2006-269939 A JP 2008-235613 A JP 2008-270310 A

  However, the above-described technique has a problem. When a part of the semiconductor is removed as in the above vertical structure and an upper layer in which electrons actually travel by regrowth is formed, impurities at the regrowth interface cannot be removed, and the crystallinity of the regrowth semiconductor is reduced. There are problems that it is worse than the original semiconductor crystal, the current collapse increases, and the mobility of electrons decreases.

  Further, it is necessary to add Si to the regrown GaN layer to make it n-type, and there is a problem that mobility is lowered even if the crystal is ideally regrown. Due to the low mobility, there is also a problem that it is difficult to reduce the on-resistance.

  In order to solve the above-mentioned problems of the nitride semiconductor field effect transistor, electrons are used as carriers, but it is necessary to improve the device structure so that the traveling direction of electrons under the gate electrode is substantially parallel to the substrate surface. There is.

  The present invention has been made in view of the above-described problems. A heterojunction electric field in which various adverse effects are solved while the device structure is improved so that the traveling direction of electrons under the gate electrode is substantially parallel to the substrate surface. An effect transistor and a manufacturing method thereof are provided.

The first heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode serving as a carrier is substantially parallel to the substrate surface. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. In the n-type conductive layer, ions are implanted with an acceleration energy of 200 keV or more, deeper than the p-type nitride semiconductor layer, and the second n-type impurity is activated by annealing. It is formed by selective ion implantation in which implanted ions reach the semiconductor layer, and the n-type impurity concentration implanted into the connection portion between the n-type conductive layer and the channel region into which no n-type impurity is implanted is 1 × 10. ^{It is 18} cm ⁻³ or less.

The second heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode serving as a carrier is substantially parallel to the substrate surface. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. In the n-type conductive layer, ions are implanted with an acceleration energy of 200 keV or more, deeper than the p-type nitride semiconductor layer, and the second n-type impurity is activated by annealing. The n-type impurity concentration is 1 × at the connection between the n-type conductive layer and the channel region into which the n-type impurity is not implanted. It is 10 ²⁰ cm ⁻³ or more, or the ionized n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more.

The third heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is substantially parallel to the substrate surface, and is gated through a gate insulating film or the like. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. N-type impurities are activated by annealing, and the n-type conductive layer is implanted by accelerating ions with a first acceleration energy of 10 keV or more and less than 200 keV. In addition to the first ion implantation in which the implanted ions reach deeper, the ions are implanted at a second acceleration energy of 200 keV or higher, and the implanted ions are deeper than the p-type nitride semiconductor layer and reach the second semiconductor layer. The second ion implantation is applied to the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted. And yet not, but the first ion implantation has been performed, however, the connection portion, or n-type impurity concentration that is injected is 1 × 10 ²⁰ cm ^-3 or more, or is ionized The n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more.

The fourth heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is substantially parallel to the substrate surface, and is gated through a gate insulating film or the like. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. The n-type impurity is formed by activating the n-type impurity by annealing, and the n-type conductive layer has a trench structure in which the ion implantation region is in contact with the side surface and the bottom surface. The ion projection range Di (μm) is formed by ion implantation at an acceleration energy such that the projected range Di (μm) is longer than the trench depth Dt (μm) (Di> Dt), and is deeper than the p-type nitride semiconductor layer. Implanted ions have reached the semiconductor layer, and the concentration of the n-type impurity implanted into the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted is 1 × 10 ¹⁸ cm ⁻³ or less. It is characterized by .

The fifth heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is substantially parallel to the substrate surface, and is gated through a gate insulating film or the like. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. The n-type impurity is formed by activating the n-type impurity by annealing, and the n-type conductive layer has a trench structure in which the ion implantation region is in contact with the side surface and the bottom surface. The ion projection range Di (μm) is formed by ion implantation at an acceleration energy such that the projected range Di (μm) is longer than the trench depth Dt (μm) (Di> Dt), and is deeper than the p-type nitride semiconductor layer. Implanted ions reach the semiconductor layer, and the concentration of the implanted n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more at the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted. Is there again It is n-type impurity concentration that is ionized is 1 × ¹⁰ 19 ^{cm -3} or more, and the.

The sixth heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is substantially parallel to the substrate surface, and is gated through a gate insulating film or the like. The first semiconductor layer in contact with the electrode and the second semiconductor layer or drain electrode electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or gate electrode Between, and at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer, and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer, This is a heterojunction field effect transistor using this as a channel, with a gate insulating film interposed on the opposite side of the source electrode from the gate electrode, etc. A first semiconductor layer in contact with the gate electrode and an n-type conductive layer that forms a conduction path between the semiconductor layer and the drain electrode. The n-type conductive layer is selectively ion-implanted. The n-type impurity layer is formed by activating the n-type impurity by annealing, and the n-type conductive layer has a trench structure in which the side surface and the bottom surface are in contact with the ion implantation region. In addition to the first ion implantation in which ions are implanted deeper than the semiconductor heterointerface, ions are implanted with the second acceleration energy, and the p-type is implanted. It is selectively formed by the second ion implantation deeper than the nitride semiconductor layer and reaches the second semiconductor layer, and the first and second ion implantation regions overlap each other. Has a region, in the connection portion between the channel region n-type conductive layer and the n-type impurity is not implanted, or n-type impurity concentration that is injected is 1 × 10 ²⁰ cm ^-3 or more, or An ionized n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more, and an n ⁺ conduction path is formed between the connection portion and the semiconductor layer conducted with the drain electrode through the ion implantation region. It is characterized by that.

The first method for producing a heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under a gate electrode serving as a carrier is substantially parallel to the substrate surface, via a gate insulating film, etc. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity is ion-implanted with an activation energy of 200 keV or more, and the n-type impurity is deeper than the p-type nitride semiconductor layer. The n-type impurity concentration formed by selective ion implantation that reaches the semiconductor layer and reaching the semiconductor layer and implanted into the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted is 1 × 10 ¹⁸ cm ⁻³ or less. It is characterized by.

The second heterojunction field effect transistor manufacturing method of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode serving as a carrier is substantially parallel to the substrate surface, and the like through the gate insulating film. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity is ion-implanted with an activation energy of 200 keV or more, and the n-type impurity is deeper than the p-type nitride semiconductor layer. The n-type impurity concentration is 1 × 10 ²⁰ cm ⁻³ or higher at the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted. Or the ionized n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more.

The third method for manufacturing a heterojunction field effect transistor according to the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under a gate electrode serving as a carrier is substantially parallel to the substrate surface, via a gate insulating film, etc. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity is ion-implanted by activating the n-type impurity by annealing, and the n-type conductive layer is implanted by accelerating ions with a first acceleration energy of 10 keV or more and less than 200 keV. In combination with the first ion implantation in which the implanted ions reach deeper, the ions are implanted with the second acceleration energy of 200 keV or more, and the implanted ions reach the second semiconductor layer deeper than the p-type nitride semiconductor layer. The connection between the n-type conductive layer and the channel region where the n-type impurity is not implanted is selectively formed by the second ion implantation, and the second ion implantation is not performed, and only the first ion implantation is performed. Performing, but, at the connecting portion, the n-type impurity concentration to be injected either 1 × ¹⁰ 20 ^{cm -3} or more, or to the n-type impurity concentration of ionized and 1 × ¹⁰ 19 ^{cm -3} or higher, the Features.

The fourth method for manufacturing a heterojunction field effect transistor according to the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode serving as a carrier is substantially parallel to the substrate surface, and the like through a gate insulating film. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity layer is formed by activating the ion-implanted n-type impurity by annealing, and the n-type conductive layer forms a trench structure in which the ion-implanted region is in contact with the side surface and the bottom surface. The second semiconductor layer is formed by ion implantation with acceleration energy such that the projected range Di (μm) of ions is longer than the trench depth Dt (μm) (Di> Dt) and deeper than the p-type nitride semiconductor layer The concentration of the n-type impurity implanted into the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted is 1 × 10 ¹⁸ cm ⁻³ or less.

The fifth method for producing a heterojunction field effect transistor of the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under a gate electrode serving as a carrier is substantially parallel to the substrate surface, via a gate insulating film, etc. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity layer is formed by activating the ion-implanted n-type impurity by annealing, and the n-type conductive layer forms a trench structure in which the ion-implanted region is in contact with the side surface and the bottom surface. The second semiconductor layer is formed by ion implantation with acceleration energy such that the projected range Di (μm) of ions is longer than the trench depth Dt (μm) (Di> Dt) and deeper than the p-type nitride semiconductor layer In the connection portion between the n-type conductive layer and the channel region into which no n-type impurity is implanted, the concentration of the implanted n-type impurity is set to 1 × 10 ²⁰ cm ⁻³ or higher, or ionization is performed. n-type Pure things concentration be 1 × ¹⁰ 19 ^{cm -3} or more, and the.

The sixth method for producing a heterojunction field effect transistor according to the present invention is a nitride semiconductor field effect transistor in which the traveling direction of electrons under a gate electrode serving as a carrier is substantially parallel to the substrate surface, and the like through a gate insulating film. The first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer or drain electrode that is electrically connected to the drain electrode are opposed to each other with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode Alternatively, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located between the gate electrode and a two-dimensional electron gas is formed at least at one of the heterojunction interfaces of the semiconductor layer. A method of manufacturing a heterojunction field effect transistor using this as a channel, wherein a gate electrode is connected to the opposite side of the source electrode to the gate electrode. Forming a first semiconductor layer in contact with the gate electrode through an insulating film and the like, and an n-type conductive layer forming a conduction path between the semiconductor layer and the drain electrode, and the n-type conductive layer is selected The n-type impurity is ion-implanted and activated by annealing, and the n-type conductive layer forms a trench structure in which the ion-implanted region is in contact with the side and bottom surfaces. In addition to the first ion implantation in which ions are implanted deeper than the semiconductor heterointerface, ions are implanted with the second acceleration energy, and the p-type nitride semiconductor layer is implanted. The n-type conductive layer and the n-type impurity are selectively formed by a second ion implantation that is deeper and the implanted ions reach the second semiconductor layer, and the first and second ion implantation regions overlap each other. In connection portion of the implanted without the channel region, the n-type impurity concentration to be injected either 1 × ¹⁰ 20 ^{cm -3} or more, or, the n-type impurity concentration of ionized and 1 × ¹⁰ 19 ^{cm -3} or more, the connecting portion And an n ⁺ conduction path is formed between the drain electrode and the semiconductor layer conducted through the ion implantation region.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the manufacturing method of this invention has described several manufacturing process in order, the order of the description does not limit the order which performs several manufacturing process. For this reason, when implementing the manufacturing method of this invention, the order of the some manufacturing process can be changed in the range which does not interfere in content.

  Furthermore, the manufacturing method of the present invention is not limited to being executed at a timing when a plurality of manufacturing steps are individually different. For this reason, another manufacturing process may occur during the execution of a certain manufacturing process, or a part or all of the execution timing of a certain manufacturing process and the execution timing of another manufacturing process may overlap.

  The heterojunction field effect transistor of the present invention can maintain good high frequency characteristics and low on-resistance by using a two-dimensional electron gas. In general, the breakdown voltage is determined by the breakdown voltage of the current path through the p-type electron barrier layer directly under the source electrode and the breakdown voltage of the current path through the electron conduction layer.

  First, the withstand voltage of the current path via the p-type electron barrier layer directly under the source electrode depends on the electric field relaxation layer and the p-type electron barrier layer that suppress punch-through. In addition, if the electric field relaxation layer is provided, the Al composition ratio changes so as to gradually decrease from the substrate side to the surface side, so that the conduction band (load) is caused by the piezo effect and the spontaneous polarization effect. Since the electron band also bends so as to be convex toward the vacuum level as if it was p-type doped, punch-through can be made more difficult and a higher breakdown voltage can be achieved.

  In addition, the breakdown voltage via the electron conduction layer is basically determined by the drift layer (if the electric field relaxation layer is provided, the drift layer and the electric field relaxation layer). The distribution is uniform and high breakdown voltage can be expected up to the bulk breakdown voltage (3MV / cm), and high breakdown voltage can be achieved even with a small chip size. Further, since the length of the rib on the opposite side of the source electrode is increased through the gate electrode, the electric field concentration in the vicinity of the gate electrode can be reduced.

  In the structure of the present invention, an electron conduction connection region (channel / drain connection region) is formed by activating an n-type impurity such as ion-implanted silicon (Si) by annealing.

  The activation annealing treatment is performed at a temperature within a range of 1100 ° C. or more and less than 1300 ° C. after an annealing protective film (through film) that covers the entire epitaxial multilayer film sample to be annealed is formed.

  The connection resistance at the connection portion between the n-type conductive layer thus formed and the channel region into which no n-type impurity is implanted has been a problem until now, as described above. Utilize selected ion implantation conditions that can be reduced to a low level without hindrance. The condition has been clarified through experimental investigations up to the present invention, as will be described later in the section of the embodiment. The condition is one of the following two conditions.

First, the concentration of the n-type impurity implanted into the connection portion between the n-type conductive layer and the channel region into which no n-type impurity is implanted is 1 × 10 ¹⁸ cm ⁻³ or less. In the first place, under this implantation condition, the absolute amount of the implanted n-type impurity concentration is small and the connection resistance hardly increases at the connection portion between the n-type conductive layer and the channel region where the n-type impurity is not implanted.

Second, the concentration of the implanted n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more at the connection portion between the n-type conductive layer and the channel region into which no n-type impurity is implanted, or the device operating temperature ( In general, the ionized n-type impurity concentration at room temperature: 5 ° C. or more and 35 ° C. or less is 1 × 10 ¹⁹ cm ⁻³ or more.

When the ionized impurity concentration reaches at least 10 ¹⁹ cm ⁻³ or more (preferably 3 × 10 ¹⁹ cm ⁻³ or more) in the n-type conductive layer of the connection portion of the 2DEG-n type conductive layer, the atomic spacing of the impurity atoms is reduced. By shrinking, the electronic state of the conduction band is degenerated in the semiconductor, and the lower energy level of the conduction band is lower than the Fermi level.

  By using a stiffening mechanism, the inventor has experimentally found that the conduction band potential of the connection including the potential barrier is reduced, and that the connection resistance is almost zero or a low level that does not hinder device operation. .

It is a typical longitudinal cross-sectional view which shows the internal structure of the heterojunction field effect transistor of embodiment of this invention. It is a device structure figure showing a technical background. It is a typical longitudinal cross-sectional view which shows the internal structure of the heterojunction field effect transistor of other embodiment. It is a typical longitudinal section showing the internal structure of the heterojunction field effect transistor of other embodiments. It is a typical longitudinal section showing the internal structure of the heterojunction field effect transistor of other embodiments. It is a typical longitudinal cross-sectional view which shows the epitaxial multilayer film structure for ion implantation condition examination. It is a band diagram of the epitaxial multilayer structure for ion implantation condition examination. FIG. 2 is a schematic longitudinal sectional view showing a structure of a TEG for TLM evaluation, where (a) is for 2DEG region, (b) is for n ⁺ region, and (c) is for 2DEG-n ⁺ connection resistance evaluation. It is a characteristic view which shows the dose amount dependence of implantation ion distribution. It is a characteristic view which shows 2DEG-n ^+/- connection resistance increase rate. It is a characteristic view which shows the dose dependence of the conduction band lower end energy in a HEMT structure. It is a characteristic view which shows the consideration from a horizontal direction band figure. It is a band figure which shows the effect of two-stage injection | pouring. It is a typical longitudinal cross-sectional view which shows the internal structure of the field effect transistor of one prior art example.

  An embodiment of the present invention will be described below with reference to the drawings. However, the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description thereof is omitted.

  As shown in FIG. 1, the heterojunction field effect transistor according to the present embodiment is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode 112 serving as a carrier is substantially parallel to the surface of the substrate 101.

  A semiconductor layer that is in contact with the gate electrode 112 through the gate insulating film 111 and the like, or a semiconductor layer or the drain electrode 114 that is electrically connected to the drain electrode 114 sandwiches the p-type electron barrier layer 105 that is a p-type nitride semiconductor layer. Relative.

  Between the p-type electron barrier layer 105 and the source electrode 109 or the gate electrode 112, at least a carrier traveling layer and a third semiconductor layer having a lower electron affinity than the carrier traveling layer are located.

  In the heterojunction field effect transistor of this embodiment, a two-dimensional electron gas is formed at least at one of the heterojunction interfaces (106/107 interface) of the semiconductor layer, and this is used as a channel.

  However, the heterojunction field effect transistor of this embodiment includes a semiconductor layer in contact with the gate electrode 112 on the opposite side of the source electrode 109 with respect to the gate electrode 112, the drain electrode 114, and the like. An n-type conductive layer that forms a conduction path between the conductive semiconductor layers. The n-type conductive layer is formed by activating n-type impurities such as silicon (Si), which are selectively ion-implanted, by annealing.

Further, in the n-type conductive layer, ions are implanted with an acceleration energy of 200 keV or more, and by selective ion implantation in which the implanted ions reach a semiconductor layer deeper than the p-type nitride semiconductor layer and conductive with the drain electrode 114. Is formed. The n-type impurity concentration injected into the connection portion 115 between the n-type conductive layer and the channel region into which no n-type impurity is implanted is 1 × 10 ¹⁸ cm ⁻³ or less.

  More specifically, as shown in FIG. 2, in the heterojunction field effect transistor of the present embodiment, when the gate electrode 112 is a Schottky junction, it contacts the gate electrode 112, or when the gate has a MIS structure, The electron supply layer 107 which is a semiconductor layer in contact with the gate electrode 112 through the insulating film 111 and the high-concentration n-type collector layer 102 or the drain electrode 114 which are semiconductor layers in contact with the drain electrode 114 are connected to the p-type electron barrier layer 105. Place them at opposite positions across

  Then, the electron supply layer 107 in contact with the gate electrode 112 on the opposite side of the source electrode 109 with respect to the gate electrode 112, or the electron supply in contact with the gate electrode 112 through the gate insulating film 111 when the gate has a MIS structure. It is necessary to provide an electron conduction region (channel / drain connection region) 108 for allowing electrons to flow between the layer 107 and the n-type collector layer 102 in contact with the drain electrode 114.

  As a method of forming the electron conduction region (channel / drain connection region) 108, the semiconductor layer in the corresponding region is temporarily removed to form a trench structure, and then the electron conduction region (channel / drain connection region) 108 is amorphous or After stacking polycrystalline silicon, a region in which silicon is diffused in the semiconductor by heat treatment is provided, or a metal is disposed directly or adjacent to the electron conduction region (channel / drain connection region) 108, or the electron conduction region (Channel / drain connection region) There is a method of providing a region where a metal and a semiconductor interact with each other by heat treatment after a metal is stacked on the channel / drain connection region 108. In these methods, the bottom surface of the trench structure forms at least a channel. It is necessary to form it deeper than the semiconductor heterojunction surface (106/107 interface).

  When the trench structure is actually formed by a method such as dry etching, the heterojunction interface (106/107 interface) is disordered in the vicinity of the trench structure due to the etching damage, and the heterojunction interface near the trench structure. It has been found that the channel characteristics of the (106/107 interface) deteriorate, and the on-resistance and access resistance of the element increase or their values may vary greatly.

  In order to solve the above-mentioned damage problem, as a method of forming the electron conduction region (channel / drain connection region) 108, it is not necessary to form a deep trench structure extending to the semiconductor heterojunction interface (106/107 interface). This is one of the effective solutions.

  It is effective to form the electron conduction region (channel / drain connection region) 108 by implanting impurities by means of ion implantation using an accelerator and activating the impurities by heat treatment. A basic structure is formed (FIG. 2).

  The method of forming the electron conduction region (channel / drain connection region) 108 by the ion implantation means not only contributes to the improvement or stabilization of the characteristics of the vertical transistor, but also simplifies the manufacturing process and increases the number of steps. This also leads to a reduction, and further draws out the merit of the vertical structure such as the reduction of the element area (that is, the improvement of the element density), and future utilization is desired.

  However, according to the present inventor, in the ion implantation under the normal implantation conditions, the electron conduction region 108 made of the n-type conductive layer formed by ion implantation of 28Si or the like is connected to the semiconductor heterojunction interface 2DEG region (106/107 interface) It has been experimentally clarified that the connection portion 115 has an unnecessary connection resistance component that cannot be ignored in device operation, and that this connection resistance increases the on-resistance and access resistance of the element.

  Furthermore, in a planar device structure in which no trench for implantation is formed, the depth of the electron conduction region (channel / drain connection region) 108 made of an n-type conductive layer formed by means of ion implantation is generally the conventional lateral type. It needs to be much deeper than in the case of devices.

  Therefore, the acceleration energy of the implanted ions is larger than the conventional (usually around 100 keV) and typically needs to be 200 keV or more, which is also the difference between the n-type conductive layer and the semiconductor heterojunction interface (106/107 interface) 2DEG region. There is a risk that the atomic arrangement in the connection portion 115 is more disturbed and the connection resistance in the connection portion 115 is increased or the value thereof varies.

  Therefore, as shown in FIG. 1, the field effect transistor of the present embodiment has a high concentration of the first GaN-based semiconductor on the substrate 101 for epitaxially growing the GaN-based semiconductor by gallium surface or aluminum surface growth. An n-type collector layer 102, a drift layer 103 made of a second GaN-based semiconductor, an optional electric field relaxation layer 104 made of a third GaN-based semiconductor to generate a negative polarization charge, and a fourth GaN-based semiconductor A p-type electron barrier layer 105, an electron transit layer 106 made of a fifth GaN-based semiconductor layer, and an electron supply layer 107 made of a sixth GaN-based semiconductor layer are formed.

  A cap layer 116 may be formed on the electron supply layer 107 for the purpose of stabilizing the contact with the electrode. Thereafter, electron conductive regions 108A and 108B made of n-type conductive layers are formed by the first and second ion implantations in the portion corresponding to the opposite side of the source electrode 109 via the gate electrode 112 (FIG. 3).

  After the first ion implantation, the ion implantation trench 117 (FIG. 4) may be formed, and then the second ion implantation may be performed. After the source electrode 109 is formed, a part of the electron supply layer 107 is removed using the first insulating film 110 as a mask to form a recess structure.

  Next, after forming the gate insulating film 111, filling the recess region, and forming the gate electrode 112 so that the length of the opposite side of the source electrode 109 is longer than the length of the source side via the gate electrode 112 Then, the protective film 113 is formed.

  After the substrate 101 has a desired thickness, a drain electrode 114 is formed to form a field effect transistor. When the substrate 101 is highly insulating and typified by sapphire or SiC, it is generally difficult to form the drain electrode 114 through the substrate 101.

  In such a case, it is easy in the device process to dig a trench groove (common name: drain mesa) from the front surface of the device until it reaches the drift layer 103 and form the drain electrode 114 on the bottom surface. .

  Alternatively, when the original substrate 101 is thick and it is difficult to form the electron conduction region 108 that reaches the drain electrode 114, the “smart cut” (Japanese Patent Application No. 2008-519736 “Group III nitride enhancement type device”), A method called International Rectifier Corporation, USA) cuts and removes the substrate portion from the wafer at the substrate or buffer layer portion, and further “SopSiC” (V. Hoel et al. , First microwave power performance of AlGaN / GaN HEMTs on SopSiC composite substrate, Electronics Letters, Vol. 44, Issue 3, pp. 238-239, January 2008.) If the method of bonding the substrates is used, the drain electrode 114 and the electron conduction region 108 reaching the drain electrode 114 can be formed more easily.

In the structure of the present embodiment, electrons entering from the source flow in the i-GaN channel layer in the horizontal direction, and then in the _n- GaN drift layer 103 through the n-type conduction region formed by ion implantation in the vertical direction. And reaches the drain electrode 114. The channel current is controlled by the potential of the gate electrode 112 provided on the device surface side.

_{The p-} GaN layer functions as a barrier layer for blocking leakage current between the channel and the drain. The drain breakdown voltage of such an element is mainly determined by the thickness of the _n- GaN drift layer 103.

  For this reason, there is an advantage that the breakdown voltage can be improved without increasing the chip area. When the drain electrode 114 is formed on the back surface, there is no increase in the chip area due to the drain electrode 114. Even when the drain mesa is formed and the electrode is provided on the front side, it is not necessary to form the drain electrode 114 in the device intrinsic region as in the case of the lateral FET, so that an increase in the chip area is suppressed.

In addition, since electric field concentration hardly occurs in the _n- GaN drift layer 103, the breakdown voltage (BV) can be easily improved. Furthermore, since 2DEG generated at the semiconductor heterojunction interface (106/107 interface) is used as the two-dimensional electron gas (2DEG), the high electron mobility of the channel also contributes to the improvement of the on-resistance (Ron). Based on the above principle, the vertical heterojunction FET can be expected to improve the on-resistance vs. breakdown voltage (Ron-BV) trade-off.

  Examples of the substrate 101 of the present embodiment include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. For example, Si, S, Se, O, or the like is preferably added to the substrate 101 as an n-type impurity.

  Examples of the n-type collector layer 102 that is the first GaN-based semiconductor include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, it can be omitted if the substrate 101 has a sufficiently low resistance. Further, it is preferable to add, for example, Si, S, Se, O, or the like as an n-type impurity in the first GaN-based semiconductor at a high concentration.

  Examples of the drift layer 103 made of the second GaN-based semiconductor include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Further, it is preferable to add, for example, Si, S, Se, O or the like as an n-type impurity in the second GaN-based semiconductor.

  The electric field relaxation layer 104 made of the third GaN-based semiconductor includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, the third GaN-based semiconductor has a composition that generates a negative polarization charge.

  Therefore, when the Ga surface is on the source electrode 109 side and the N surface is on the substrate 101 side, the Al composition ratio is decreased, the In composition ratio is increased, or the Al composition ratio is increased from the substrate 101 side to the source electrode 109 side. And the In composition ratio must be increased. Further, it is preferable to add, for example, Si, S, Se, O or the like as an n-type impurity in the third GaN-based semiconductor.

  The p-type electron barrier layer 105 made of the fourth GaN-based semiconductor includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Further, it is preferable to add, for example, Be, C, Mg, or the like as a p-type impurity in the fourth GaN-based semiconductor at a high concentration.

Examples of the electron transit layer 106 made of the fifth GaN-based semiconductor include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Also, it is possible to add, for example, Si, S, Se, O, etc. as the n-type impurity, and, for example, Be, C, Mg, etc. as the p-type impurity in the fifth GaN-based semiconductor. However, when the impurity concentration in the fifth GaN-based semiconductor increases, the mobility of electrons decreases due to the influence of Coulomb scattering, and thus the impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

  Examples of the electron supply layer 107 made of the sixth GaN-based semiconductor include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, in the embodiment of the present embodiment, the material or composition has a smaller electron affinity than the fifth GaN-based semiconductor. Also, it is possible to add, for example, Si, S, Se, O, etc. as the n-type impurity, and, for example, Be, C, Mg, etc. as the p-type impurity in the sixth GaN-based semiconductor.

  The cap layer 116, which is the seventh GaN-based semiconductor, is effective as a cap layer if it is a GaN-based material having a higher electron affinity (smaller band gap) than the material of the electron supply layer 107.

  The first insulating film 110 includes a substance composed of one or more of Si, Mg, Hf, Al, Ti, and Ta and one or more of O and N.

  The gate insulating film 111 includes a substance composed of one or more of Si, Mg, Hf, Al, Ti, and Ta and one or more of O and N.

  Further, as the protective film 113, there is a substance made of one or more of Si, Mg, Hf, Al, Ti and Ta and one or more of O and N, or an organic material.

  Since it is the film thickness of the epitaxial layer that forms the vertical structure that determines the ion implantation conditions of the vertical transistor of this embodiment, the film thickness of the epitaxial layer will be considered next. First, with respect to the GaN electron transit layer 106, a depletion layer enters from the p-type electron barrier layer 105 on the back depending on the bias condition. As a result, the carrier of the channel may be depleted. In order to avoid this, the thickness of the GaN electron transit layer 106 needs to be 0.1 μm or more.

In the structure of the present embodiment, the drain breakdown voltage of the element is mainly determined by the thickness of the _n- GaN drift layer 103. In order to achieve an avalanche breakdown voltage of 1000 V or higher in the collector (which becomes the collector breakdown voltage), the impurity concentration of the _n- GaN drift layer 103 is approximately 1 × 10 ¹⁶ cm ⁻³ or less and the film thickness is approximately 4 μm or more. Must be set to

Further, in order for the punch-through breakdown voltage in the p-type electron barrier layer 105 made of p _- GaN and the n-drift layer 103 to exceed the avalanche breakdown voltage in the drift layer 103, the ( The (impurity concentration × film thickness) product needs to be 1.8 × 10 ¹³ cm ⁻² or more.

Since the current technology makes it difficult to increase the p-type ionized impurity concentration to 1E18 / cm ³ or more, the thickness of the p-type electron barrier layer 105 made of p _- GaN should be at least 0.018 μm or more when estimated from this. become.

As discussed above, even if only the GaN electron traveling layer 106, the p-type electron barrier layer 105 made of p _- GaN, and the n-type drift layer 103 are considered, It can be seen that in the vertical structure transistor, the epitaxial layer thickness is considerably larger than that in the horizontal structure transistor.

Therefore, in the case of adopting a structure in which no trench for implantation is formed, as ion implantation for forming the n-type electron conduction region 108, p-type electrons composed of at least the GaN electron transit layer 106 and _p- GaN. The implanted ions need to reach a depth equal to or greater than the sum of the thicknesses of the barrier layers 105, and the electron conduction region 108B by deep ion implantation with a relatively high acceleration energy of 200 keV or more is necessary.

  Further, in order to secure a low resistance in the connection portion 115 between the channel and the n-type electron conduction region 108, it is desirable to use the electron conduction region 108A by surface ion implantation with relatively low acceleration energy of 10 keV or more and less than 200 keV. It is understood.

  Next, optimization of ion implantation conditions will be described. The multilayer epitaxial film used for the examination for selecting suitable conditions for ion implantation is a typical structure, and has an AlGaN / GaN heterojunction structure. FIG. 6 is a diagram schematically showing the epi structure of this element, and FIG. 7 is a graph showing the calculation result of the band structure of the epi structure shown in FIG.

  Regarding carrier statistics, 2D quantum statistics were adopted for 2DEG, and Fermi-Dirac statistics were adopted for bulk electrons and holes. Impurities (donors and acceptors) were assumed to be completely ionized. For the polarization effect, Ambacher's model was adopted, and the polarization charge was introduced as a fixed charge.

  Table 1 shows the physical property constants used in the analysis. The horizontal axis of the graph of FIG. 7 indicates the depth (Depth) of the epi structure, the vertical axis on the left side of the graph indicates the conduction band bottom energy (Energy), and the vertical axis on the right side of the graph indicates the carrier concentration. (Carrier Concentration). The solid line in the graph represents the distribution of the conduction band bottom energy in the depth direction, and the broken line in the graph represents the carrier concentration distribution in the depth direction.

A polarization effect, which is a characteristic of nitride semiconductor materials, occurs at the gallium (Ga) -plane or aluminum (Al) -plane grown AlGaN / GaN heterojunction interface (106/107 interface). Electrons constituting carriers having a high sheet charge concentration Ns of about 10 ¹³ cm ⁻² order, which is about five times that of the heterojunction interface (106/107 interface), can be accumulated.

  The HEMT device having such an AlGaN / GaN heterojunction structure can realize excellent characteristics such as a high current value, a high output power, a low on-resistance and an access resistance.

Various dopant species for selectively forming an n ⁺ -type conductive layer by ion implantation into the HEMT structure have been reported. Of these, the most effective is Si (atomic weight: 28). The layer thickness of the AlGaN layer (electron supply layer 107) is usually 0.015 to 0.045 μm, and 0.15 to 0.20 is usually used as the Al composition in the AlGaN layer.

  When Si (atomic weight: 28) is ion-implanted into an AlGaN / GaN heterojunction type HEMT structure having this profile, ion implantation is usually performed by through-implantation through a through film.

Here, the acceleration energy in the range of 20 to 130 keV and the dose amount in the range of 1 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² are normal values applied to the device. After ion implantation, activation annealing is preferably performed at a temperature near 1200 ° C. in order to activate the doped ions.

A 0.08 μm-thick nitride film (SiN film) is deposited as a through film on an Al0.15Ga0.85N (0.045 μm thickness) / GaN heterojunction type epitaxial structure (epitaxial structure). Then, Si was ion-implanted with an acceleration energy of 100 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

  Thereafter, activation annealing was performed at 1200 ° C. for 3 minutes. A Ti / Al / Nb / Au multilayer metallized ohmic electrode was formed on the resulting structure. The electrical characteristics of the resulting device were measured using a Hall measurement method or a TLM (Transmission Line Model) method.

  Three types of structures shown in FIGS. 8A, 8B, and 8C were prepared as objects to be measured by the TLM method. 8A includes an electron transit layer (GaN layer) formed on a substrate via a buffer film (not shown), an electron supply layer (AlGaN layer) heterojunction with the electron transit layer, This structure has a source electrode and a drain electrode that are in ohmic contact with the upper surface of the electron supply layer.

The structure of FIG. 8B includes an electron transit layer (GaN layer) formed on a substrate via a buffer film (not shown), and an electron supply layer (AlGaN layer) heterojunction with the upper surface of the electron transit layer. And a source electrode and a drain electrode that are in ohmic contact with the upper surface of the electron supply layer. By ion implantation, a high concentration n ⁺ -type impurity implantation region is formed from the upper surface of the electron supply layer to a depth exceeding the heterojunction interface (106/107 interface).

  8C includes an electron transit layer (GaN layer) formed on a substrate via a buffer film (not shown), an AlGaN layer heterojunction with the upper surface of the electron transit layer, and the AlGaN layer. This has a source electrode and a drain electrode that are in ohmic contact with the upper surface.

On both sides of the gate electrode (not shown), high concentration n ⁺ -type impurity implantation regions are formed by ion implantation from the upper surface of the electron supply layer to a depth exceeding the heterojunction interface.

  The structure of FIG. 8A is a structure for obtaining the ohmic contact resistance Rc (2DEG) and the sheet resistance Rsh (2DEG) of the two-dimensional electron gas layer in a region where ion implantation is not performed.

The structure of FIG. 8B is a structure for obtaining the ohmic contact resistance Rc (n) and the sheet resistance Rsh (n) in the ion-implanted region. The structure of FIG. 8C is a structure for evaluating the connection resistance Rb at the connection portion between the n ⁺ -type impurity implantation region and the channel of the two-dimensional electron gas layer in these impurity implantation regions.

  The sheet resistance of the structure of FIG. 8C is equal to the sheet resistance Rsh (2DEG) of the structure of FIG. On the other hand, the apparent contact resistance Rc † evaluated in the structure of FIG. 8C is expressed by the following equation (1) in consideration of the margin ΔL of the connection portion in the structure of FIG. .

        Rc † = Rb + Rc (n) + Rsh (n) · ΔL (1)

Here, since Rc (n) and Rsh (n) are obtained from FIG. 8B and ΔL is also known, the connection resistance Rb at the connection portion between the n ⁺ -type impurity implantation region and the channel is obtained from this equation. Can be requested.

As a result of the evaluation, it was found that the contact resistance in the n ⁺ -type impurity implantation region was Rc = 0.47Ωmm, and the sheet resistance was 408Ω / □ (ohm / square). The problem here is the connection resistance between the n ⁺ -type impurity implantation region and the channel.

When the 28Si dose is 1E11 cm ^−2, that is, the 28Si impurity concentration at the semiconductor heterojunction interface (106/107 interface) is 1E16 cm ⁻³ , the connection resistance is almost negligible, but compared with the connection resistance value. The measurement result of the connection resistance at a dose of 1 × 10 15 cm ⁻² was a large value of 116 times. Since this connection resistance increases the access resistance and on-resistance of the device as contact resistance, it is an urgent need to reduce this connection resistance.

Therefore, the dose dependency of the connection resistance between the channel and the n ⁺ -type impurity implantation region was examined. This is because the conduction band potential of the n ⁺ -type impurity implantation region changes greatly according to the dose, and as a result, the connection resistance may be reduced.

The sample of FIG. 6 was ion-implanted with an acceleration energy of 100 keV and a dose varied within the range of 1 × 10 ¹¹ (1E + 11) to 3 × 10 ¹⁶ (3E + 16) cm ⁻² . Here, the thickness of the through SiN film was constant (0.08 μm).

FIG. 9 is a graph showing the dose dependency of the ion distribution in the depth direction of the sample. FIG. 10 is based on the connection resistance when the dose amount is 1E11 cm ⁻² , that is, the impurity concentration at the heterojunction interface (106/107 interface) is approximately 1E16 cm ⁻³ with respect to the impurity concentration at the semiconductor heterointerface. 5 is a graph plotting the value (increase rate) of the connection resistance Rb in the case of

In the region where the Si impurity concentration at the semiconductor heterojunction interface is 1 × 10 ¹⁸ (1E18) cm ⁻³ or less, the connection resistance Rb is very low and close to zero. In the first place, with the amount of implantation in this region, since there are few implanted ions reaching the heterojunction interface (106/107 interface), the heterojunction interface (106/107 interface) is held in a state close to the state before ion implantation. Conceivable.

Therefore, in this implantation amount region, the effect of ion implantation on contact resistance and sheet resistance is small in the first place. At the point where the ionized impurity concentration is about 1 × 10 ¹⁸ cm ⁻³ , the connection resistance (increase rate) was the highest.

  The reason for this is considered to be that the atomic arrangement of the semiconductor heterojunction interface channel portion is damaged by ion implantation, and the potential of the portion is increased to become a barrier against electrical conduction.

On the other hand, in the region where the ionized impurity concentration exceeds 1 × 10 ¹⁹ cm ⁻³ and reaches 1 × 10 ²⁰ cm ⁻³ , the resistance value decreases as the ionized impurity concentration increases, and the ionized impurity concentration becomes 6 × 10 ¹⁹ (6E19). ) It was found that the increase rate of the connection resistance Rb takes a minimum value 17 at a point of cm ⁻³ .

This value may be considered as a value that does not cause a problem in device application. Also, a dose amount of 1 × 10 ¹⁶ (1E16) cm ⁻² giving this value (a value introduced through the through film, and an effective dose amount of 9.2 × 10 ¹⁵ (9.2E15) cm ⁻² ) Is an optimum or almost optimum dose for reducing the connection resistance between the channel and the n ⁺ -type impurity implantation region.

Note that, when the Si impurity concentration is 3 × 10 ²¹ (3E21) cm ⁻³ or more, the connection resistance tends to increase. However, when this dose is exceeded, the solid solution limit of Si in the GaN-based material appears. It is considered a thing.

It has been experimentally clarified that the resistance value decreases as the ionized impurity concentration increases in the region where the ionized impurity concentration exceeds 1 × 10 ¹⁹ cm ⁻³ and reaches 1 × 10 ²⁰ cm ^−3. The mechanism by which the connection resistance Rb is reduced under this ion implantation condition will be considered.

  The Schrödinger equation and Poisson equation were combined to obtain a self-consistent solution by numerical calculation, and a quantitative one-dimensional band structure incorporating the quantum mechanical effect was obtained.

  Regarding carrier statistics, two-dimensional quantum statistics are adopted for 2DEG, and Fermi-Dirac statistics are adopted for bulk electrons and holes. Impurities (donors and acceptors) were assumed to be completely ionized.

  For the polarization effect, an Ambacher model was adopted, and the polarization charge was introduced as a fixed charge. Table 1 shows the physical property constants used in the analysis. FIG. 11 is a plot of the conduction band bottom energy of the sample corresponding to the effective dose amount N in the depth direction.

As shown in FIG. 9, 9.2 × 10 ¹³ (9.2E13) cm ⁻² , 9.2 × 10 ¹⁴ (9.2E14) cm ⁻² , 9.2 × 10 ¹⁵ (9.2E15). ) The values in the case of increasing the cm ⁻² and the effective dose stepwise are plotted.

  At that time, the distribution P (z) of the implanted ions in the depth direction z was obtained statistically using Monte Carlo calculation, and the ion activation rate η was obtained by actually measuring the hole at room temperature. Experimental values were used. The distribution D (z) in the depth direction of the ionized donor concentration obtained as a result is represented by the following formula (2).

        D (z) = η · N · P (z) (2)

As shown in the graph of FIG. 11, when the effective dose is 9.2 × 10 ¹³ (9.2E13) cm ⁻² , the ohmic contact portion, the AlGaN electron supply layer 107, the AlGaN / GaN heterojunction portion But the potential of the electron conduction band has not dropped sufficiently.

Correspondingly, experimental values of contact resistance Rc (n), sheet resistance Rsh (n), and connection resistance Rb were high. In the case where the effective dose amount is 9.2 × 10 ¹⁵ (9.2E15) cm ⁻² that gives an optimum Si ion concentration of 1E21 cm ⁻³ at the semiconductor heterointerface, the AlGaN electron supply layer 107 is formed even in the ohmic contact portion. However, even at the AlGaN / GaN heterojunction, the potential is sufficiently reduced from the Fermi level.

Correspondingly, sufficiently low values were obtained in experiments for the contact resistance Rc (n), the sheet resistance Rsh (n), and the connection resistance Rb. In the region where the Si impurity concentration at the semiconductor heterojunction interface is 1 × 10 ¹⁸ (1E18) cm ⁻³ or less, the connection resistance Rb is very low and close to zero.

In the first place, since there are few implanted ions reaching the heterojunction interface (106/107 interface), the heterojunction interface (106/107 interface) is held in a state close to the state before ion implantation. On the other hand, when the ionized impurity concentration exceeds 1 × 10 ¹⁹ cm ⁻³ , the connection resistance is reduced because the conduction band potential of the AlGaN / GaN heterojunction is sufficiently reduced from the Fermi level. Conceivable.

FIG. 12 is a diagram for explaining this in the “lateral” band structure. FIG. 12 shows two types of potentials Pi and Pd. Referring to FIG. 11, if there is a sufficient amount of ionized donor in the n ⁺ -type impurity implantation region in the vicinity of the two-dimensional electron gas layer (2DEG by heterojunction) generated by the semiconductor heterojunction, the potential Pi otherwise As compared with, the potential Pd at that point decreases.

In connection with this, it is guessed that the barrier height of a connection part reduces and a connection resistance falls. In order to sufficiently reduce the conduction band potential of the n ⁺ -type impurity implantation region in the vicinity of the two-dimensional electron gas layer at room temperature, the “ionization donor impurity concentration at room temperature is 1 × 10 ¹⁹ (1E19) cm ⁻³ or more”. It is considered necessary.

  Therefore, to reduce the connection resistance, it is effective to increase the dose amount itself as described above, and it is also effective to increase the activation rate of the implanted ions by increasing the activation annealing temperature.

  Furthermore, from the viewpoint of improving the activation rate, “temperature rising ion implantation” in which ions are implanted in a state where the temperature of the substrate 101 is raised at the time of ion implantation is also effective. The above describes the case where the operating temperature of the device is normal room temperature (5 ° C. or more and 35 ° C. or less).

When the operating temperature of the device is far from room temperature (for example, when the device operates in an automobile engine room), the connection resistance is reduced when the ionized impurity concentration exceeds 1 × 10 ¹⁹ cm ^−3. Requires that the ionized donor impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more at the device operating temperature, and further “the ionized donor impurity concentration is 3 × at the device operating temperature. 10 ¹⁹ cm ⁻³ or more ”is desirable.

  In the structure of the present invention, since the trench groove is not formed, there is an advantage that the two-dimensional electron gas (DEG) channel in the semiconductor heterojunction is not damaged due to the trench groove formation.

  However, it is necessary to perform ion implantation with high acceleration energy of 200 keV or more. Taking typical silicon (Si) as an example of the dopant to be implanted, when the acceleration energy is 200 keV or more, it is necessary to generate and use divalent ions instead of monovalent ions as the implanted ion species. There is a tendency to increase.

  Furthermore, as the acceleration energy increases, the roughness of the surface of the sample subjected to the implantation also increases. Therefore, there is a need to reduce acceleration energy in ion implantation as much as possible.

  Therefore, there is a method of forming a trench for reducing the acceleration energy of ion implantation. In the structure of the present invention, the trench has the effect of reducing the projected range that the implanted ions should reach by the depth.

  When the trench groove is deep, it can have a depth to reach the drift layer 103, so that the degree of acceleration energy reduction during ion implantation can be extremely large. Certainly, when there is a contact portion between the trench groove and the semiconductor heterojunction channel, the connection portion is damaged in the process of forming the trench, and the connection resistance of that portion increases.

  However, the ion implantation region is selected so that the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted has a certain distance from the contact portion between the trench groove and the semiconductor heterojunction channel. In this case, the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted is hardly affected by an increase in connection resistance caused by trench formation damage.

Furthermore, the n-type conductive layer is formed by ion implantation with acceleration energy such that Di (μm), which is a projected range 118B of implanted ions, is longer than the trench depth Dt (μm) ( Di> Dt), an n ⁺ conduction path can be formed between the connection portion and the drain electrode 114 and the semiconductor layer conducted through the ion implantation region.

Further, by utilizing the two-stage ion implantation in combination with the trench structure, it is easy to form a conductive layer by ion implantation to the deep part of the device, and between the n-type conductive layer and the channel region into which the n-type impurity is not implanted. Reduction of the connection resistance in the connection portion can be ensured, and an n ⁺ conduction path between the connection portion and the semiconductor layer conducted with the drain electrode 114 is easily and reliably formed through the ion implantation region. I can do it.

(Example)
An example of this embodiment will be described. In the field effect transistor of this example, a (0001) plane (Ga plane) n-type GaN substrate is used as the substrate 101, and a GaN layer (1 × 10 ^{18 is used} as the high-concentration n-type collector layer 102 made of the first GaN-based semiconductor. cm ⁻³ Si added, film thickness 0.5 μm), a GaN layer (1 × 10 ¹⁷ cm ⁻³ Si added, film thickness 1.0 μm) as the drift layer 103 made of the second GaN-based semiconductor, AlGaN layer as the electric field relaxation layer 104 made of the third GaN-based semiconductor (Al composition ratio is changed stepwise so that the substrate 101 side is 0.3 and the surface side is 0, for example, the film thickness is 0.3 μm, for example) As a p-type electron barrier layer 105 made of a fourth GaN-based semiconductor, a GaN layer (1 × 10 ¹⁸ cm ⁻³ Mg added, film thickness 0.2 μm), an electron made of a fifth GaN-based semiconductor layer Traveling layer 06 is a GaN layer (film thickness 0.1 μm), an electron supply layer 107 made of a sixth semiconductor layer is an AlGaN layer (Al composition ratio 0.20, film thickness 0.02 μm), and a cap layer made of a seventh semiconductor layer. 116 is a GaN layer (0.002 μm), the source electrode 109 and the drain electrode 114 are Ti / Al (the thickness of the Ti layer is 0.01 μm, the thickness of the Al layer is 0.2 μm), and the first insulating film 110 is a SiON film. (Thickness 0.08 μm), 115 made of seventh and sixth GaN-based semiconductors as recesses, 0.025 μm of the electron supply layer 107 was removed, and Al ₂ O ₃ film (thickness 0. 01 μm), Ni / Au (Ni layer thickness 0.015 μm, Au layer thickness 0.4 μm) is used as the gate electrode 112, and SiON film (thickness 0.08 μm) is used as the protective film 113. It is produced by the.

  The electron conduction region 108 of this example was formed by implanting 28Si ions in the corresponding region through a 0.08 μm through film (SiN) and performing activation annealing at 1200 ° C. for 3 minutes. The following six types of samples with different ion implantation conditions corresponding to the claims were prepared.

The first sample has the structure shown in FIGS. 1 and ² , and was ion-implanted with an acceleration energy of 350 keV and a dose of 1E14 cm ⁻² . The implanted impurity reaches the drift layer 103 and has a concentration of 1E19 cm ^{−3 in} the p-barrier layer.

Further, the impurity concentration in 2DEG was 1E18 cm ⁻³ , and the connection resistance at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer was sufficiently low.

The second sample has the structure shown in FIGS. 1 and ² , and was ion-implanted with an acceleration energy of 300 keV and a dose of 1E16 cm ⁻² . The implanted impurities reach the drift layer 103 and have a concentration of 3E20 cm ^{−3 in} the p-barrier layer.

Furthermore, the impurity concentration in 2DEG was 1E20 cm ⁻³ , and the connection resistance at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer was sufficiently low.

The third sample has the structure of FIG. 3, and the first ion implantation (acceleration energy: 100 keV, dose amount: 1E16 cm ⁻² ) and the second ion implantation (acceleration energy: 300 keV, dose amount: 3E15 cm ^{−). 2} ) was performed.

In the first ion implantation (acceleration energy: 100 keV, dose amount: 1E16 cm ⁻² ), the ionization donor concentration is 1E19 cm ⁻³ at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer. The above conditions are satisfied, and the connection resistance between the n-type conductive layer and the semiconductor heterojunction interface (106/107 interface) 2DEG channel is sufficiently low.

In the second ion implantation (acceleration energy: 300 keV, dose amount: 3E15 cm ⁻² ), the implanted ions reach the drift layer 103 and are electrically connected to the drain electrode 114 through the connection portion 115 and the ion implantation region. An n ⁺ conduction path was formed between the layers.

The fourth sample has the structure shown in FIG. 4, and after forming a trench having a depth of 0.1 μm, ion implantation with an acceleration energy of 350 keV and a dose of 1E14 cm ⁻² was performed. The implanted impurity reaches the drift layer 103 and has a concentration of 1E19 cm ^{−3 in} the p-barrier layer.

Further, the impurity concentration in 2DEG was 1E18 cm ⁻³ , and the connection resistance at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer was sufficiently low.

The fifth sample has the structure shown in FIG. 4, and after forming a trench having a depth of 0.15 μm, ion implantation with an acceleration energy of 180 keV and a dose of 3E15 cm ⁻² was performed. The implanted impurity reaches the drift layer 103 and has a concentration of 1E20 cm ^{−3 in} the p-barrier layer.

Furthermore, the impurity concentration in 2DEG was 1E20 cm ⁻³ , and the connection resistance at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer was sufficiently low. Also, the acceleration energy was less than 200 keV.

The sixth sample has the structure shown in FIG. 5. After performing the first ion implantation (acceleration energy: 100 keV, dose amount: 1E16 cm ⁻² ), a 0.15 μm trench is formed, and then the second sample is formed. Ion implantation (acceleration energy: 180 keV, dose amount: 3E15 cm ⁻² ) was performed.

The implanted impurity reaches the drift layer 103 and has a concentration of 1E20 cm ^{−3 in} the p-barrier layer. Furthermore, the impurity concentration in 2DEG was 5E20 cm ⁻³ , and the connection resistance at the connection portion 115 between the semiconductor heterojunction interface (106/107 interface) and the n-type conductive layer was suppressed to be sufficiently lower than that in the fifth sample.

  Also, the acceleration energy was less than 200 keV. In addition, in this embodiment, ion implantation of 14N ions was used for element isolation or element isolation.

A 0.06 μm silicon nitride film (SiN) was used as the through film, and 14N ions were selectively implanted into a desired region with an acceleration energy of 30 keV and a dose of 2E14 cm ⁻² .

  With such a structure, low on-resistance and good high-frequency characteristics can be maintained by using a two-dimensional electron gas. The breakdown voltage of the current path through the p-type electron barrier layer 105 immediately below the source electrode 109 depends on the electric field relaxation layer 104 and the p-type electron barrier layer 105.

  In this structure, if the electric field relaxation layer 104 is further provided and the Al composition ratio is changed so as to gradually decrease from the substrate 101 side to the surface side, the conduction band (the valence band is caused by the piezo effect and the spontaneous polarization effect). Since it bends so as to be convex toward the vacuum level as if it were p-type doped, punch-through is further prevented and a higher breakdown voltage can be achieved.

  The breakdown voltage of the current path through the electron conduction region 108 is determined by the drift layer 103 (the drift layer 103 and the electric field relaxation layer 104 when the electric field relaxation layer 104 is provided), but there is no influence of the surface (interface). Therefore, the electric field distribution becomes uniform, and a high breakdown voltage can be expected up to a bulk value (3 MV / cm) of a breakdown voltage, and a high breakdown voltage can be realized even with a small chip size.

  Furthermore, since the length of the opposite side of the source electrode 109 is increased through the gate electrode 112, the electric field concentration in the vicinity of the gate electrode 112 can be reduced. Here, taking the third sample as an example, the formation of the electron conduction region 108 by ion implantation will be considered from the viewpoint of the electronic state of the semiconductor. Table 1 shows the physical property constants used in the analysis.

FIG. 13 shows a one-dimensional conduction band energy level along the upper and lower sides of the electron conduction region 108 of the device of this example, in a state where ion implantation is not performed, acceleration energy: 300 keV and dose amount: 3E15 cm. ^-2 deep ion implantation (second ion implantation) followed by activation annealing (1200 ° C. for 3 minutes) and acceleration energy in combination with deep ion implantation (second ion implantation): Three levels are graphed when surface layer ion implantation (first ion implantation) of 100 keV and a dose of 1E16 cm ⁻² is performed and activation annealing (1200 ° C. for 3 minutes) is performed.

  The distribution of the implanted ions is obtained by Monte Carlo calculation. The activation rate of the implanted ions is obtained from the experimental values obtained by actually measuring the holes, and the one-dimensional conduction band potential is obtained by taking the quantum mechanical effect as described above. Taking into account the ionized donor concentration distribution, the Schrodinger equation and the Poisson equation were combined to obtain a self-consistent solution.

  As for carrier statistics, two-dimensional quantum statistics are adopted for the two-dimensional electron gas (2DEG), and Fermi-Dirac statistics are adopted for the bulk electrons and holes. Impurities (donors and acceptors) were assumed to be completely ionized. For the polarization effect, Ambacher's model was adopted, and the polarization charge was introduced as a fixed charge. Table 1 shows the physical property constants used in the analysis.

First, when ion implantation is not performed, the conduction band potential of the GaN layer (added with 1 × 10 ¹⁸ cm ⁻³ Mg, film thickness 0.2 μm) of the p-type electron barrier layer 105 is sufficiently high, It can be seen that it functions as a barrier layer for maintaining the resistance. By the way, in order to form the electron conduction region 108 in this epi structure, ion implantation to a relatively deep part is necessary.

However, by increasing the acceleration energy, the ion implantation reaching the drift layer 103 by the ion implantation of acceleration energy: 300 keV has been achieved, and the dose amount is increased and the dose amount: 3E15 cm ⁻² is implanted. Thus, it can be seen that after the activation annealing, the acceptor of the p-type electron barrier layer 105 is sufficiently compensated by the implanted donor, and its potential can be reduced to a Fermi level or lower.

  However, the concentration of implanted donors in the device surface layer from the vicinity of the semiconductor heterojunction to the surface is still not sufficient, and the potential in that region has not been sufficiently reduced.

Next, in conjunction with deep ion implantation (second ion implantation), surface layer ion implantation (first ion implantation) with acceleration energy: 100 keV and dose amount: 1E16 cm ⁻² is performed, and activation annealing (1200 ° C. for 3 minutes). ), As can be seen from the graph, the conduction band potential of the device surface layer from the vicinity of the semiconductor heterojunction to the surface can be sufficiently reduced, and the connection resistance of the 2DEG-n type conductive layer connection is reduced. It also proves that the task has been fulfilled from the viewpoint of the electronic state.

  In this embodiment, an n-type GaN substrate having a (0001) plane (Ga plane) is used as the substrate 101, but a substrate such as a mixture of GaN, InN, AlN, and the above-mentioned three types of GaN-based semiconductors can be used. .

  However, if the lattice constant is significantly different from that of the semiconductor layer formed over the substrate 101, transition occurs and crystallinity deteriorates. Therefore, the composition of the substrate 101 used is the same as that of the semiconductor layer formed over the substrate 101 or It is preferable that the composition has a close value. Further, although the surface to be used may be a surface (N surface), caution is required in designing such that the direction of the piezo effect is reversed.

  Similarly, in this embodiment, a GaN layer is used as the high-concentration n-type collector layer 102. However, the high-concentration n-type collector layer includes GaN, InN, AlN, and the above three types of GaN-based layers such as an AlGaN layer and an InGaN layer A mixture of semiconductors or the like can be used.

Further, Si is added as an impurity, but as an n-type impurity, for example, Si, S, Se, O, or the like can be added. The concentration can be a desired value, but it is preferably added to a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more in order to reduce the resistance.

  Similarly, in this embodiment, a GaN layer is used as the drift layer 103. However, as the drift layer 103, a mixture of GaN, InN, AlN and the above three kinds of GaN-based semiconductors, such as an AlGaN layer or an InGaN layer, is used. it can.

Further, Si is added as an impurity, but as an n-type impurity, for example, Si, S, Se, O, or the like can be added. The concentration can be a desired value, but it is preferably added at a concentration of 1 × 10 ¹⁸ cm ⁻³ or less in order to relax the electric field. In particular, when priority is given to pressure resistance, it is preferable to add at a concentration of 1 × 10 ¹⁷ cm ⁻³ or less.

  Similarly, in this embodiment, an AlGaN layer (Al composition ratio is changed stepwise so that the substrate 101 side is 0.3 and the surface side is 0, the film thickness is 0.3 μm) is introduced as the electric field relaxation layer 104. As the layer 104, a mixture of GaN, InN, AlN, and the above three kinds of GaN-based semiconductors such as an AlGaN layer and an InGaN layer can be used.

  However, the electric field relaxation layer 104 needs to have a composition that generates negative polarization charges in order to enhance the electric field relaxation effect. When the Ga surface is on the source electrode 109 side and the N surface is on the substrate 101 side, the substrate 101 From the side to the source electrode 109 side, it is necessary to decrease the Al composition ratio, increase the In composition ratio, decrease the Al composition ratio, and increase the In composition ratio.

Further, Si is added as an impurity, but as an n-type impurity, for example, Si, S, Se, O, or the like can be added. The concentration can be a desired value, but it is preferably added at a concentration of 1 × 10 ¹⁸ cm ⁻³ or less in order to relax the electric field. In particular, when priority is given to pressure resistance, it is preferable to add at a concentration of 1 × 10 ¹⁷ cm ⁻³ or less.

Similarly, in this example, a GaN layer (1 × 10 ¹⁹ cm ⁻³ Mg added, film thickness 0.3 μm) was used as the p-type electron barrier layer 105, but an AlGaN layer was used as the p-type electron barrier layer 105. GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors, such as InGaN layers and InGaN layers.

Further, Mg is added as an impurity, but as a p-type impurity, for example, Be, C, Mg, or the like can be added. The concentration can be a desired value, but it is preferably added at a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more in order to maintain a barrier against electrons up to a high voltage.

  Similarly, in this embodiment, a GaN layer is used as the electron transit layer 106. However, as the electron transit layer, GaN, InN, AlN and a mixture of the above three kinds of GaN-based semiconductors, such as an AlGaN layer and an InGaN layer, are used. Can do.

In this embodiment, no impurity is added to the electron transit layer 106, but for example, Si, S, Se, O, etc. are added as n-type impurities, and, for example, Be, C, etc. are added as p-type impurities. It is also possible. However, since the mobility decreases due to the influence of Coulomb scattering when the impurity concentration in the electron transit layer increases, the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

  Similarly, although an AlGaN layer is used as the electron supply layer 107 in this embodiment, the electron supply layer 107 is made of GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors, such as an AlGaN layer or an InGaN layer. be able to.

  However, the electron supply layer 107 needs to be a substance or composition having a lower electron affinity than the electron transit layer 106. In this embodiment, since electrons are supplied by the piezo effect and the spontaneous polarization effect, no impurities are added to the electron supply layer 107. However, as n-type impurities, for example, Si, S, Se, As a p-type impurity such as O, for example, Be, C, Mg, or the like can be added.

  Similarly, although a GaN layer is used as the cap layer 116 in this embodiment, any GaN-based material having a higher electron affinity (a smaller band gap) than the material of the electron supply layer 107 is effective as the cap layer.

  Similarly, the thickness of each layer can be set to a desired thickness. However, when it is greatly different from the lattice constant of the substrate 101, it is preferable that the thickness be equal to or less than the critical film thickness at which dislocation occurs.

Further, the electron conductive region 108 of this example was formed by removing the corresponding region by dry etching and re-growing the GaN layer (added with 8 × 10 ¹⁷ cm ⁻³ Si). Any method can be used as long as the barrier layer 105 is disabled and electrons can flow toward the substrate 101.

  In this embodiment, Ti / Al is used for the source electrode 109 and the drain electrode 114. However, the source electrode 109 may be AlGaN as the electron supply layer 107, and the drain electrode 114 may be any metal that makes ohmic contact with the substrate 101. For example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.

  Similarly, Ni / Au is used as the gate electrode 112 in this embodiment. However, since the gate electrode 112 is not in direct contact with the semiconductor in this embodiment, a desired metal can be used. However, it is desirable that the gate insulating film 111 and the protective film 113 do not react.

  Further, in this embodiment, 0.025 μm of the carrier supply layer was removed during the fabrication of the recess structure, but the semiconductor thickness to be removed by the recess can be any thickness, up to the thickness of the carrier supply layer or more. It is possible to remove.

  However, if the semiconductor thickness to be removed is thin, the effect of improving the breakdown voltage due to the recess structure and the effect of reducing current collapse are reduced, and if the semiconductor thickness to be removed is thick, the decrease in carrier and mobility under the gate and the two-dimensional electron gas Since resistance increases due to extinction, the semiconductor thickness to be removed is preferably 30% to 90% of the originally formed semiconductor thickness.

  Further, in this embodiment, the gate electrode 112 is formed so that the ridges of the gate electrode 112 are longer from the source electrode 109 side to the drain electrode 114 side. However, the source side ridges are not involved in the effect of this embodiment. It is also possible to make it equal to or longer than the flange on the 114 side.

  However, if the length of the source-side ridge becomes longer, the gain decrease due to the increase of the gate capacitance increases with respect to the effect of improving the breakdown voltage and reducing the current collapse.

  The present invention is not limited to the present embodiment, and various modifications are allowed without departing from the scope of the present invention. Needless to say, the above-described embodiment and a plurality of modifications can be combined within a range in which the contents do not conflict with each other. Further, in the above-described embodiments and modifications, the structure of each part has been specifically described, but the structure and the like can be changed in various ways within a range that satisfies the present invention.

101 Substrate 102 made of GaN-based semiconductor High-concentration n-type collector layer 103 made of first GaN-based semiconductor Drift layer 104 made of second GaN-based semiconductor Electric field relaxation layer 105 made of third GaN-based semiconductor Fourth GaN P-type electron barrier layer 106 made of a GaN-based semiconductor, an electron transit layer 107 made of a fifth GaN-based semiconductor, an electron supply layer 108 made of a sixth GaN-based semiconductor, an electron conduction region 108A by the first ion implantation (surface layer ion implantation) Electron conduction region 108B Electron conduction region 109 by second ion implantation (deep ion implantation) 109 Source electrode 110 First insulation film 111 Gate insulation film 112 Gate electrode 113 Protective film 114 Drain electrode 115 2DEG-n ⁺ connection portion 116 Cap layer 117 made of GaN-based semiconductor Ion implantation trench 118 The projection range of the ion distance 1001 n-GaN substrate 1002 n ^- -GaN layer 1003 p-GaN layer 1004 AlN layer 1005 i-GaN layer 1006 n-GaN layer 1007 i-AlGaN layer 1008 ohmic electrode 1009 SiO ₂ film 1010 gate electrode

Claims (10)

It is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is parallel to the substrate surface,
The first semiconductor layer of the nitride semiconductor layer that is in contact with the gate electrode through the gate insulating film, and the second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode is a p-type nitride semiconductor layer A nitride semiconductor layer having a smaller electron affinity than the carrier traveling layer and the carrier traveling layer of the nitride semiconductor layer between the p-type nitride semiconductor layer and the source electrode or the gate electrode The third semiconductor layer is located, and at least one of the heterojunction interfaces of the third semiconductor layer, a two-dimensional electron gas is formed, and a heterojunction field effect transistor having this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers via the gate insulating film on the opposite side of the source electrode with respect to the gate electrode And
A trench structure is formed on the surface of the n-type conductive layer, and the bottom and side surfaces of the trench structure are in contact with the n-type conductive layer,
The n-type conductive layer is formed from the first semiconductor layer to the second semiconductor layer, and one end of the n-type conductive layer reaches the first semiconductor layer in the depth direction, and the n-type conductive layer The other end of the p-type nitride semiconductor layer reaches the second semiconductor layer deeper than the p-type nitride semiconductor layer,
The concentration of the n-type impurity injected into the connection portion between the n-type conductive layer and the channel region in which the n-type impurity is not implanted in the n-type conductive layer is 1 × 10 ¹⁸ cm ⁻³ or less,
A heterojunction field effect transistor characterized by It is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is parallel to the substrate surface,
The first semiconductor layer of the nitride semiconductor layer that is in contact with the gate electrode through the gate insulating film, and the second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode is a p-type nitride semiconductor layer A nitride semiconductor layer having a smaller electron affinity than the carrier traveling layer and the carrier traveling layer of the nitride semiconductor layer between the p-type nitride semiconductor layer and the source electrode or the gate electrode The third semiconductor layer is located, and at least one of the heterojunction interfaces of the third semiconductor layer, a two-dimensional electron gas is formed, and a heterojunction field effect transistor having this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers via the gate insulating film on the opposite side of the source electrode with respect to the gate electrode And
A trench structure is formed on the surface of the n-type conductive layer, and the bottom and side surfaces of the trench structure are in contact with the n-type conductive layer,
The n-type conductive layer is formed from the first semiconductor layer to the second semiconductor layer, and one end of the n-type conductive layer reaches the first semiconductor layer in the depth direction, and the n-type conductive layer The other end of the p-type nitride semiconductor layer reaches the second semiconductor layer deeper than the p-type nitride semiconductor layer,
In the connection portion between the n-type conductive layer and the channel region where the n-type impurity of the n-type conductive layer is not implanted, the concentration of the implanted n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more, or The ionized n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more,
A heterojunction field effect transistor characterized by It is a nitride semiconductor field effect transistor in which the traveling direction of electrons under the gate electrode which is a carrier is parallel to the substrate surface,
The first semiconductor layer of the nitride semiconductor layer that is in contact with the gate electrode through the gate insulating film, and the second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode is a p-type nitride semiconductor layer A nitride semiconductor layer having a smaller electron affinity than the carrier traveling layer and the carrier traveling layer of the nitride semiconductor layer between the p-type nitride semiconductor layer and the source electrode or the gate electrode The third semiconductor layer is located, and at least one of the heterojunction interfaces of the third semiconductor layer, a two-dimensional electron gas is formed, and a heterojunction field effect transistor having this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers via the gate insulating film on the opposite side of the source electrode with respect to the gate electrode And
A trench structure is formed on the surface of the n-type conductive layer, and the bottom and side surfaces of the trench structure are in contact with the n-type conductive layer,
The n-type conductive layer is formed from the first semiconductor layer to the second semiconductor layer, and one end of the n-type conductive layer reaches the first semiconductor layer in the depth direction, and the n-type conductive layer The other end of the p-type nitride semiconductor layer reaches the second semiconductor layer deeper than the p-type nitride semiconductor layer,
In the connection portion between the n-type conductive layer and the channel region where the n-type impurity of the n-type conductive layer is not implanted, the concentration of the implanted n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more, or The ionized n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more,
An n ⁺ conduction path is formed between the connection portion and the semiconductor layer conducted with the drain electrode through the n-type conductive layer;
A heterojunction field effect transistor characterized by The connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted has an n-type impurity concentration of 1 × 10 ¹⁹ cm ⁻³ ionized under a temperature condition of 5 ° C. or more and 35 ° C. or less. That's it,
The heterojunction field effect transistor according to claim 2 or 3. From the substrate side to the source electrode side of the p-type nitride semiconductor layer, the Al composition ratio is decreased, the In composition ratio is increased, the Al composition ratio is decreased, and the In composition ratio is increased. The In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) layer whose composition is modulated is composed of the second semiconductor layer of n-type GaN and the p-type GaN. Being disposed between the p-type nitride semiconductor layers;
The heterojunction field effect transistor according to any one of claims 1 to 4. The gate electrode flange other than the closest part of the gate electrode and the semiconductor layer is longer on the opposite side of the source electrode than on the source electrode side,
The heterojunction field effect transistor according to any one of claims 1 to 5. A nitride semiconductor field effect transistor in which a traveling direction of electrons under a gate electrode serving as a carrier is parallel to the substrate surface, a first semiconductor layer of a nitride semiconductor layer in contact with the gate electrode through a gate insulating film, and a drain electrode A second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode, with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or the gate electrode Between the carrier traveling layer of the nitride semiconductor layer and the third semiconductor layer of the nitride semiconductor layer having a lower electron affinity than the carrier traveling layer, and at least the heterojunction interface of the third semiconductor layer In one, a two-dimensional electron gas is formed, which is a method of manufacturing a heterojunction field effect transistor using this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers are formed on the opposite side of the source electrode with respect to the gate electrode via the gate insulating film. ,
The n-type conductive layer is formed by activating selectively ion-implanted n-type impurities by annealing,
The n-type conductive layer forms a trench structure in which the ion implantation region is in contact with the side surface and the bottom surface.
The n-type conductive layer is formed by ion implantation with acceleration energy such that a projected range Di (μm) of implanted ions is longer than a depth Dt (μm) of the trench structure (Di> Dt), and the implanted ions reach the second semiconductor layer deeper than the p-type nitride semiconductor layer;
An n-type impurity concentration implanted into a connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted is 1 × 10 ¹⁸ cm ⁻³ or less,
A method of manufacturing a heterojunction field effect transistor. A nitride semiconductor field effect transistor in which a traveling direction of electrons under a gate electrode serving as a carrier is parallel to the substrate surface, a first semiconductor layer of a nitride semiconductor layer in contact with the gate electrode through a gate insulating film, and a drain electrode A second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode, with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or the gate electrode Between the carrier traveling layer of the nitride semiconductor layer and the third semiconductor layer of the nitride semiconductor layer having a lower electron affinity than the carrier traveling layer, and at least the heterojunction interface of the third semiconductor layer In one, a two-dimensional electron gas is formed, which is a method of manufacturing a heterojunction field effect transistor using this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers are formed on the opposite side of the source electrode with respect to the gate electrode via the gate insulating film. ,
The n-type conductive layer is formed by activating selectively ion-implanted n-type impurities by annealing,
The n-type conductive layer forms a trench structure in which the ion implantation region is in contact with the side surface and the bottom surface.
The n-type conductive layer is formed by ion implantation with acceleration energy such that a projected range Di (μm) of implanted ions is longer than a depth Dt (μm) of the trench structure (Di> Dt), and the implanted ions reach the second semiconductor layer deeper than the p-type nitride semiconductor layer;
In the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted, the n-type impurity concentration to be implanted is 1 × 10 ²⁰ cm ⁻³ or more, or the n-type impurity concentration to be ionized is 1 × 10 ¹⁹ cm ⁻³ or more,
A method of manufacturing a heterojunction field effect transistor. A nitride semiconductor field effect transistor in which a traveling direction of electrons under a gate electrode serving as a carrier is parallel to the substrate surface, a first semiconductor layer of a nitride semiconductor layer in contact with the gate electrode through a gate insulating film, and a drain electrode A second semiconductor layer of the n-type nitride semiconductor layer that is electrically connected to the drain electrode or the drain electrode, with the p-type nitride semiconductor layer interposed therebetween, and the p-type nitride semiconductor layer and the source electrode or the gate electrode Between the carrier traveling layer of the nitride semiconductor layer and the third semiconductor layer of the nitride semiconductor layer having a lower electron affinity than the carrier traveling layer, and at least the heterojunction interface of the third semiconductor layer In one, a two-dimensional electron gas is formed, which is a method of manufacturing a heterojunction field effect transistor using this as a channel,
The first semiconductor layer and the n-type conductive layer forming a conduction path between the second semiconductor layers are formed on the opposite side of the source electrode with respect to the gate electrode via the gate insulating film. ,
The n-type conductive layer is formed by activating selectively ion-implanted n-type impurities by annealing,
The n-type conductive layer forms a trench structure in which the ion implantation region is in contact with the side surface and the bottom surface.
The n-type conductive layer implants ions with a first acceleration energy and implants ions with a second acceleration energy in combination with the first ion implantation in which the implanted ions reach deeper than the semiconductor heterointerface. Implanted and selectively formed by a second ion implantation that reaches deeper than the p-type nitride semiconductor layer and reaches the second semiconductor layer;
The first and second ion implantation regions overlap each other;
In the connection portion between the n-type conductive layer and the channel region into which the n-type impurity is not implanted, the n-type impurity concentration to be implanted is 1 × 10 ²⁰ cm ⁻³ or more, or the n-type impurity concentration to be ionized is 1 × 10 ¹⁹ cm ⁻³ or more,
Forming an n ⁺ conduction path between the connection portion and the semiconductor layer conducted with the drain electrode through the ion implantation region;
A method of manufacturing a heterojunction field effect transistor. The activation annealing treatment is performed at a temperature within a range of 1100 ° C. or more and less than 1300 ° C. after an annealing protective film (through film) that covers the entire epitaxial multilayer film sample to be annealed is formed. ,
A method for producing a heterojunction field effect transistor according to any one of claims 7 to 9.

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