[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP5560834B2 - Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device - Google Patents

Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device Download PDF

Info

Publication number
JP5560834B2
JP5560834B2 JP2010074797A JP2010074797A JP5560834B2 JP 5560834 B2 JP5560834 B2 JP 5560834B2 JP 2010074797 A JP2010074797 A JP 2010074797A JP 2010074797 A JP2010074797 A JP 2010074797A JP 5560834 B2 JP5560834 B2 JP 5560834B2
Authority
JP
Japan
Prior art keywords
insulating substrate
hole
diameter
plating
surface side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010074797A
Other languages
Japanese (ja)
Other versions
JP2011210794A (en
Inventor
大輔 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2010074797A priority Critical patent/JP5560834B2/en
Publication of JP2011210794A publication Critical patent/JP2011210794A/en
Application granted granted Critical
Publication of JP5560834B2 publication Critical patent/JP5560834B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

本発明は、絶縁基板、絶縁基板の製造方法、プリント配線基板および半導体装置に関する。   The present invention relates to an insulating substrate, a method for manufacturing the insulating substrate, a printed wiring board, and a semiconductor device.

近年、携帯電話、パソコン、ビデオ、ゲーム機等の電子機器は、使用部品の高密度化、薄型化および小型化が進み、それらを実装しているプリント配線基板等についても、配線の高密度化が求められている。また、上記のプリント配線基板は、一般には、絶縁基板にブラインドビアホールやスルーホール等の微小貫通孔を設け、この微小貫通孔中に析出させた金属によって各層間の配線の電気的接続が行われている。   In recent years, electronic devices such as mobile phones, personal computers, videos, game machines, etc. have been used with higher density, thinner and smaller parts, and the wiring density of printed wiring boards, etc. on which they are mounted has also increased. Is required. In addition, the above printed wiring board is generally provided with a minute through hole such as a blind via hole or a through hole in an insulating substrate, and the wiring between the layers is electrically connected by the metal deposited in the minute through hole. ing.

ところが、配線の高密度化に伴い、両面もしくは多層プリント配線基板の層間接続に使用されているスルーホールおよびブラインドビアホールもまた、より小径化および高アスペクト化が求められるようになってきた(例えば特許文献1)。   However, as the density of wiring increases, through holes and blind via holes used for interlayer connection of double-sided or multilayer printed wiring boards are also required to have smaller diameters and higher aspect ratios (for example, patents). Reference 1).

上述のブラインドビアホールやスルーホールにめっきを施すことにより電気的導通がはかられるが、ブラインドビアホールやスルホールをめっきにより充填されることが要求されている。しかしながら、プリント配線基板の小径化、薄型化および高アスペクト化のためめっきにより埋め込みされたブラインドビアホールやスルホールないに均一にめっきが形成されないでめっき内に気泡などが取り込まれることがあり長期接続信頼性が十分ではなかった。   Although electrical conduction can be achieved by plating the above-described blind via hole or through hole, it is required to fill the blind via hole or through hole with plating. However, because of the small diameter, thinning, and high aspect of the printed wiring board, there is a possibility that air bubbles may be taken into the plating without the formation of uniform plating without blind via holes or through holes embedded by plating. Was not enough.

特開2008−004800号公報JP 2008-004800 A

本発明は、上記事情に鑑みてなされたものであり、プリント配線基板の小径化、薄型化あるいは高アスペクト化に対応した積層板および積層板の製造方法であり、貫通孔内のめっき埋め込み性に優れ長期接続信頼性に優れたプリント配線基板および半導体装置を提供するものである。   The present invention has been made in view of the above circumstances, and is a laminate and a method for manufacturing a laminate corresponding to a reduction in diameter, thickness, or increase in aspect of a printed wiring board. It is an object of the present invention to provide a printed wiring board and a semiconductor device excellent in long-term connection reliability.

本発明による絶縁基板は、プリント配線基板に用いられる絶縁基板であって、
前記絶縁基板は貫通孔を有するとともに、前記貫通孔は、前記絶縁基板の一方の面側から、前記絶縁基板の他方の面側にいたる所定の深さ位置において最小径を有するとともに、
前記貫通孔は、前記絶縁基板の一方の面側から前記所定の深さ位置に向かって縮径し、前記所定の深さ位置から前記絶縁基板の他方の面側に向かって拡径している。
An insulating substrate according to the present invention is an insulating substrate used for a printed wiring board,
The insulating substrate has a through hole, and the through hole has a minimum diameter at a predetermined depth position from one surface side of the insulating substrate to the other surface side of the insulating substrate.
The through hole is reduced in diameter from one surface side of the insulating substrate toward the predetermined depth position, and is increased in diameter from the predetermined depth position toward the other surface side of the insulating substrate. .

この絶縁基板によれば、貫通孔は、前記絶縁基板の一方の面側から、前記絶縁基板の他方の面側にいたる所定の深さ位置において最小径を有するとともに、前記貫通孔は、前記絶縁基板の一方の面側から前記所定の深さ位置に向かって縮径し、前記所定の深さ位置から前記絶縁基板の他方の面側に向かって拡径している。これにより、絶縁基板の貫通孔内に孔径が細くなり、括れた形状を有するので、この貫通孔内にめっきを形成させるとき、まず、括れた部分で貫通孔壁面から成長しためっき同士の接触が始まり埋め込みが開始される。引き続き、めっきを続けることによりそれぞれの面側の表面に向かってめっきが成長していく。めっきが成長していく方向に対しては貫通孔が拡径しているため、成長途中に気泡を抱き込むことなく埋め込み性に優れたプリント配線基板を提供できる絶縁基板とすることができる。   According to this insulating substrate, the through hole has a minimum diameter at a predetermined depth position from one surface side of the insulating substrate to the other surface side of the insulating substrate, and the through hole is formed of the insulating substrate. The diameter is reduced from one surface side of the substrate toward the predetermined depth position, and the diameter is increased from the predetermined depth position toward the other surface side of the insulating substrate. As a result, the hole diameter is reduced in the through-hole of the insulating substrate and has a constricted shape. Therefore, when plating is formed in the through-hole, first, contact between the platings grown from the wall surface of the through-hole in the constricted portion occurs. Begins embedding. Subsequently, the plating grows toward the surface on each side by continuing the plating. Since the diameter of the through-hole is increased in the direction in which plating grows, an insulating substrate that can provide a printed wiring board having excellent embedding properties without embedding bubbles during the growth can be obtained.

また、前記絶縁基板の一方の面側に設けられた貫通孔の径(d2)と、所定の深さ位置に設けられた貫通孔の最小径(d1)との比(d1)/(d2)が0.5〜0.9であってもよい。また、前記絶縁基材の厚さを(t1)としたとき、(t1)が200μm以下であり、前記(d2)が100μm以下であり、(t1)/(d2)が2以上であってもよい。   Further, a ratio (d1) / (d2) between the diameter (d2) of the through hole provided on one surface side of the insulating substrate and the minimum diameter (d1) of the through hole provided at a predetermined depth position. May be 0.5 to 0.9. Further, when the thickness of the insulating substrate is (t1), (t1) is 200 μm or less, (d2) is 100 μm or less, and (t1) / (d2) is 2 or more. Good.

本発明による絶縁基板の製造方法は、プリント配線基板に用いられる絶縁基板を製造する方法であって、
絶縁基板と、前記絶縁基板の他方の面側にレーザを反射する反射部材を配置する工程と、
前記絶縁基材の一方の面側からレーザ孔あけ加工を行なって前記絶縁基板に貫通孔を形成する工程と、
前記反射部材に向かってさらにレーザ照射を続ける工程とを含み、
前記貫通孔は、前記絶縁基板の一方の面側から、前記絶縁基板の他方の面側にいたる所定の深さ位置において最小径を有するとともに、前記貫通孔は、前記絶縁基板の一方の面側から前記所定の深さ位置に向かって縮径し、前記所定の深さ位置から前記絶縁基板の他方の面側に向かって拡径している絶縁基板の製造方法を提供できる。
An insulating substrate manufacturing method according to the present invention is a method of manufacturing an insulating substrate used for a printed wiring board,
Disposing an insulating substrate and a reflecting member that reflects the laser on the other surface side of the insulating substrate;
A step of forming a through hole in the insulating substrate by performing laser drilling from one surface side of the insulating base;
Further continuing the laser irradiation toward the reflecting member,
The through hole has a minimum diameter at a predetermined depth position from one surface side of the insulating substrate to the other surface side of the insulating substrate, and the through hole is on one surface side of the insulating substrate. From the predetermined depth position, the diameter of the insulating substrate can be reduced, and the diameter of the insulating substrate can be increased from the predetermined depth position toward the other surface side of the insulating substrate.

絶縁基板の他方の面側にはレーザを反射する反射部材が配置されているので、絶縁基板の一方の面側からレーザを照射したとき、絶縁基板を通過したレーザは、他方の面側に配置されている反射部材で反射するのでレーザは、さらに絶縁基板の他方の面側から一方の面側に向かってレーザ加工を続けることなる。これにより、絶縁基板の一方の面側から他方の面側に向かって縮径する貫通孔と、絶縁基板の他方の面側から一方の面側に向かって縮径する貫通孔が合わさったような形状となり、前記貫通孔は、前記絶縁基板の一方の面側から、前記絶縁基板の他方の面側にいたる所定の深さ位置において最小径を有するとともに、前記貫通孔は、前記絶縁基板の一方の面側から前記所定の深さ位置に向かって縮径し、前記所定の深さ位置から前記絶縁基板の他方の面側に向かって拡径する絶縁基板の製造方法を提供することができる。   Since the reflection member that reflects the laser is disposed on the other surface side of the insulating substrate, when the laser is irradiated from one surface side of the insulating substrate, the laser that has passed through the insulating substrate is disposed on the other surface side. Since the laser beam is reflected by the reflecting member, the laser continues laser processing from the other surface side of the insulating substrate toward the one surface side. As a result, a through-hole whose diameter is reduced from one surface side of the insulating substrate toward the other surface side is combined with a through-hole whose diameter is reduced from the other surface side of the insulating substrate toward the one surface side. The through hole has a minimum diameter at a predetermined depth position from one surface side of the insulating substrate to the other surface side of the insulating substrate, and the through hole is one of the insulating substrates. It is possible to provide an insulating substrate manufacturing method in which the diameter is reduced from the surface side toward the predetermined depth position and the diameter is increased from the predetermined depth position toward the other surface side of the insulating substrate.

さらに、上記の絶縁基板に回路加工してプリント配線基板を提供することができる。   Furthermore, a printed wiring board can be provided by processing a circuit on the insulating substrate.

さらに、上記のプリント配線基板に半導体素子を搭載してなる半導体装置を提供することができる。   Furthermore, a semiconductor device in which a semiconductor element is mounted on the printed wiring board can be provided.

本発明によれば、プリント配線基板の小径化、薄型化あるいは高アスペクト化に対応した絶縁基板および絶縁基板の製造方法であり、貫通孔内のめっき埋め込み性に優れ長期接続信頼性に優れたプリント配線基板および半導体装置を提供することができる。   According to the present invention, there is provided an insulating substrate and a method for manufacturing an insulating substrate corresponding to a reduction in the diameter, thickness, or aspect ratio of a printed wiring board, and excellent printed embedding in a through hole and excellent long-term connection reliability. A wiring board and a semiconductor device can be provided.

本発明の一実施形態を示す絶縁基板の断面図である。It is sectional drawing of the insulated substrate which shows one Embodiment of this invention. 本発明の好適な実施形態の絶縁基板の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the insulated substrate of suitable embodiment of this invention. 本発明の好適な実施形態の絶縁基板の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the insulated substrate of suitable embodiment of this invention. 従来例を示すめっき埋め込みの工程断面図である。It is process sectional drawing of the plating embedding which shows a prior art example.

以下、本発明による絶縁基板、絶縁基板の製造方法、プリント配線基板および半導体装置の好適な実施形態について詳細に説明する。なお、図面の説明においては、同一要素には同一符号を付し、重複する説明を省略する。   Hereinafter, preferred embodiments of an insulating substrate, a method for manufacturing an insulating substrate, a printed wiring board, and a semiconductor device according to the present invention will be described in detail. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

はじめに、図1を参照して、本実施形態の絶縁基板21の概要について説明する。   First, the outline of the insulating substrate 21 of the present embodiment will be described with reference to FIG.

本実施形態の絶縁基板21では、プリント配線基板に用いられる絶縁基板21であって、絶縁基板21は貫通孔41を有している。貫通孔41は、絶縁基板21の一方の面側から(図中上面))、絶縁基板の他方の面側(図中下面)にいたる所定の深さ位置において最小径(d1)を有する。以下、図中上面を上面、図中下面を下面ともいう。貫通孔41は、絶縁基板21の上面から所定の深さ位置に向かって縮径し、所定の深さ位置から絶縁基板21の下面に向かって拡径している。なお、本実施形態では、絶縁基板21の上面には第一金属層11が、下面に第二金属層12がそれぞれ積層された積層体20を実施形態として説明してる。   The insulating substrate 21 of the present embodiment is an insulating substrate 21 used for a printed wiring board, and the insulating substrate 21 has a through hole 41. The through hole 41 has a minimum diameter (d1) at a predetermined depth position from one surface side of the insulating substrate 21 (upper surface in the drawing) to the other surface side (lower surface in the drawing) of the insulating substrate. Hereinafter, the upper surface in the drawing is also referred to as the upper surface, and the lower surface in the drawing is also referred to as the lower surface. The through hole 41 is reduced in diameter from the upper surface of the insulating substrate 21 toward a predetermined depth, and is expanded from the predetermined depth position toward the lower surface of the insulating substrate 21. In the present embodiment, the laminated body 20 in which the first metal layer 11 is laminated on the upper surface of the insulating substrate 21 and the second metal layer 12 is laminated on the lower surface is described as an embodiment.

次に、絶縁基板21の上面に設けられた貫通孔41の径を(d2)としたとき、最小径(d1)と(d2)との比(d1)/(d2)は、0.5〜0.9の範囲内であることが好ましく、さらに好ましくは0.5〜0.8である。絶縁基板21の上面に設けられた貫通孔41の径(d2)と、最小径(d1)との比がこの範囲にあることで、めっき埋め込み工程における貫通孔41のめっき埋め込み性が優れる。(d1)/(d2)が0.5よりも小さくなると、埋め込みめっきの早い段階から最小径(d1)のところで成長しためっきが接触する。その後、めっきが成長して埋め込みを開始するが、拡径部については側壁面からめっきが成長していくがめっきに時間がかかるため、貫通孔41内に不均一な部分があった場合、めっきの成長に差が生じ気泡を抱き込みやすくなる。また、(d1)/(d2)が0.9よりも大きくなると、最小径(d1)のところで、めっきが成長する間に、他の領域においてもめっきが成長しており、埋め込む距離が長くなるため成長途中で気泡を巻き込みやすくなる。絶縁基板21の上面に設けられた貫通孔41の径(d2)と、絶縁基板21の下面に設けられた貫通孔41の径を(d3)としたとき、(d2)≧(d3)であってもよい。   Next, when the diameter of the through hole 41 provided on the upper surface of the insulating substrate 21 is (d2), the ratio (d1) / (d2) of the minimum diameter (d1) to (d2) is 0.5 to It is preferably within the range of 0.9, and more preferably 0.5 to 0.8. Since the ratio of the diameter (d2) of the through hole 41 provided on the upper surface of the insulating substrate 21 to the minimum diameter (d1) is within this range, the plating embedding property of the through hole 41 in the plating embedding process is excellent. When (d1) / (d2) is smaller than 0.5, plating grown at the minimum diameter (d1) from the early stage of embedded plating comes into contact. After that, the plating grows and starts embedding. However, since the plating grows from the side wall surface for the enlarged diameter portion, the plating takes time, so if there is a non-uniform portion in the through hole 41, the plating is performed. A difference in the growth of the bubbles makes it easier to embrace bubbles. When (d1) / (d2) is larger than 0.9, the plating grows in other regions at the minimum diameter (d1) while the plating grows, and the embedding distance becomes longer. Therefore, it becomes easy to entrain bubbles during the growth. When the diameter (d2) of the through hole 41 provided on the upper surface of the insulating substrate 21 and the diameter of the through hole 41 provided on the lower surface of the insulating substrate 21 are (d3), (d2) ≧ (d3). May be.

また、所定の深さ位置に設けられた貫通孔41の最小径(d1)は、絶縁基板21の厚さ方向の略中央に設けられることが好ましい。最小径(d1)が、絶縁基板21の厚さ方向の略中央に設けられることにより、貫通孔41をめっきで埋め込むとき、成長を開始しためっきが最小径(d1)部で接触し、絶縁基板21の上面と下面へと貫通孔41が拡径する方向へとめっきが成長するので成長途上で気泡を抱き込むことなく貫通孔41をめっきで孔埋めすることが可能となる。   In addition, it is preferable that the minimum diameter (d1) of the through hole 41 provided at a predetermined depth position is provided at substantially the center in the thickness direction of the insulating substrate 21. Since the minimum diameter (d1) is provided at substantially the center in the thickness direction of the insulating substrate 21, when the through hole 41 is embedded by plating, the plating that has started to grow contacts the minimum diameter (d1) portion, and the insulating substrate Since the plating grows in a direction in which the diameter of the through-hole 41 expands to the upper surface and the lower surface of 21, the through-hole 41 can be filled with the plating without embedding bubbles during the growth.

絶縁基板21の厚さを(t1)としたとき、(t1)が200μm以下であり、絶縁基板21の上面に設けられた貫通孔41の径(d2)が100μm以下であり、(t1)/(d2)は、0.6以上であっても適用でき、また、2以上であって適用可能である。アスペクト比が大きくとも、例えば、絶縁基板の厚さが1.6mm、貫通孔41の径が0.4mmとしたとき、アスペクト比は4となるが、孔径が0.4mmと大きく、貫通孔41壁面に析出させるめっきの膜厚は一般的には20〜50μmであるため、従来は、貫通孔41をめっきで埋め込むことはしないで、貫通孔41壁面めっきを析出させそれぞれの面側の金属層と電気的導通をとる方法がとられている。そのため、アスペクト比が大きくともめっき付き性で問題となることは少ない。それに対して、例えば、孔径が50μm以下、絶縁層の厚さが100μm以下となると、ドリルにより孔加工は難しく、通常はレーザ加工にて孔加工を行なう。レーザ加工で行なう場合その加工の性質上レーザ照射面からレーザが抜けていく方向に孔径が縮径する傾向になる。一方の面から他方の面へ孔径が縮径している場合、孔埋めスルホールめっきをおこなうとき、成長を開始しためっきが初めに下面の金属層の領域で合流し、その後、拡径する方向へとめっきが成長していく。このとき、上面までめっきが成長する距離が長いため、成長途上で気泡をみ巻き込みやすくなる。これは、埋め込みまでのめっき時間が長いため、貫通孔41周縁部分への電流集中によるめっきの析出が過剰になり、気泡を抱き込みやすくなると考えられる。それに対して、本発明では、絶縁基板21の貫通孔41内に孔径が細くなり、括れた形状を有するので、この貫通孔41内にめっきを形成させるとき、まず、貫通孔41内壁面にめっきが成長を始め、次に、括れた部分で貫通孔41壁面から成長しためっき同士が接触し貫通孔41内へのめっき埋め込みが始まる。そして、めっきを続けることによりそれぞれの面側の表面に向かってめっきが成長していくが、めっきが成長していく方向に対しては貫通孔41が拡径しているため気泡などを巻き込むことなく貫通孔41をめっきで埋め込むことができ、信頼性に優れたプリント配線基板とすることができる。   When the thickness of the insulating substrate 21 is (t1), (t1) is 200 μm or less, the diameter (d2) of the through hole 41 provided in the upper surface of the insulating substrate 21 is 100 μm or less, and (t1) / (D2) is applicable even if it is 0.6 or more, and is applicable because it is 2 or more. Even if the aspect ratio is large, for example, when the thickness of the insulating substrate is 1.6 mm and the diameter of the through hole 41 is 0.4 mm, the aspect ratio is 4, but the hole diameter is as large as 0.4 mm. Since the film thickness of the plating deposited on the wall surface is generally 20 to 50 μm, conventionally, the through-hole 41 is not buried by plating, and the through-hole 41 wall plating is deposited to form a metal layer on each surface side. The method of taking electrical continuity is taken. Therefore, even if the aspect ratio is large, there is little problem with the plating property. On the other hand, for example, when the hole diameter is 50 μm or less and the thickness of the insulating layer is 100 μm or less, the hole processing is difficult with a drill, and the hole processing is usually performed by laser processing. When laser processing is performed, the hole diameter tends to decrease in the direction in which the laser exits from the laser irradiation surface due to the nature of the processing. When the hole diameter is reduced from one surface to the other surface, when performing hole-filling through-hole plating, the plating that has started to grow first merges in the region of the metal layer on the lower surface, and then expands in diameter. And plating grows. At this time, since the distance at which the plating grows up to the upper surface is long, air bubbles are easily trapped during the growth. This is because the plating time until filling is long, so that the deposition of plating due to the current concentration on the peripheral portion of the through hole 41 becomes excessive, and it is considered that air bubbles are easily held. On the other hand, in the present invention, since the hole diameter is reduced in the through hole 41 of the insulating substrate 21 and has a constricted shape, when plating is formed in the through hole 41, first, the inner wall surface of the through hole 41 is plated. Then, the platings grown from the wall surface of the through hole 41 come into contact with each other at the constricted portion, and plating embedding into the through hole 41 starts. And by continuing the plating, the plating grows toward the surface on each side. However, since the through-hole 41 is expanded in the direction in which the plating grows, air bubbles are involved. Therefore, the through hole 41 can be embedded by plating, and a printed wiring board having excellent reliability can be obtained.

次に、絶縁基板21の製造方法について説明する。   Next, a method for manufacturing the insulating substrate 21 will be described.

まず、絶縁基板21の上面に第一金属層11が積層され、下面に第二金属層12が積層された積層板20を用意する(図2(a))。絶縁基板21の厚さは、特に限定はされないが、20μm〜200μmが好ましく、より好ましくは30μm〜100μmである。   First, a laminated plate 20 is prepared in which the first metal layer 11 is laminated on the upper surface of the insulating substrate 21 and the second metal layer 12 is laminated on the lower surface (FIG. 2A). The thickness of the insulating substrate 21 is not particularly limited, but is preferably 20 μm to 200 μm, more preferably 30 μm to 100 μm.

積層板20の下面には、反射部材50が配置されている。図3では、模式的に積層板20と反射部材50とが離間して示しているが、レーザの反射効率を考慮すると、反射部材50は、積層板20と当接して配置されていることが好ましい。積層板20と当接して配置されていることによって、上面から下面へレーザが貫通孔41を形成し、反射部材で反射して絶縁基板21の下面から上面へレーザを効率よく反射させることが可能となる。また、反射の効率の面から、反射部材50は鏡面加工していることが好ましい。鏡面加工されている面の表面粗さRzは4.0μm以下が好ましく、より好ましくは2.0μm以下である。なお、表面粗さRzとは、JIS B0601で規定する10点平均粗さのことである。反射部材としては、特に限定はされないが、例えば、金属板が好ましく用いられ、金属板として、鉄、アルミニウム、ステンレス、銅、ニッケルなどが好ましく用いられ、これらのなかでも銅がより好ましく用いられる。   A reflecting member 50 is disposed on the lower surface of the laminated plate 20. In FIG. 3, the laminated plate 20 and the reflecting member 50 are schematically shown apart from each other. However, in consideration of the laser reflection efficiency, the reflecting member 50 may be disposed in contact with the laminated plate 20. preferable. By being disposed in contact with the laminated plate 20, the laser can form a through hole 41 from the upper surface to the lower surface, and can be reflected by the reflecting member to efficiently reflect the laser from the lower surface to the upper surface of the insulating substrate 21. It becomes. Moreover, it is preferable that the reflecting member 50 is mirror-finished from the viewpoint of the efficiency of reflection. The surface roughness Rz of the mirror-finished surface is preferably 4.0 μm or less, more preferably 2.0 μm or less. The surface roughness Rz is a 10-point average roughness defined by JIS B0601. Although it does not specifically limit as a reflecting member, For example, a metal plate is used preferably, Iron, aluminum, stainless steel, copper, nickel etc. are used preferably as a metal plate, Among these, copper is used more preferably.

積層板20には、上面から、レーザを照射することにより貫通孔41を形成する(図2(c))。加工する孔径は100μm以下が好ましく、より好ましくは50μm以下である。レーザとしては、例えば、COレーザ加工機、UVレーザ加工機、エキシマレーザ加工機などがあり、好ましくは、COレーザ加工機である。レーザの加工条件としては、好ましくはパルス幅1〜100μm、基準エネルギー0.5〜9.0mJであり、より好ましくはパルス幅1〜20μm、基準エネルギー1.0〜3.0mJである。ショット数は基材の厚みに合わせ適宜決定すればよい。レーザの入射面である、絶縁基板21の上面には第一金属層11として厚さが2μmの銅箔が積層されている。加工は、コンフォーマル法で行なうため第一金属層11には加工しようとする孔径に合わせて第一金属層11がエッチング除去されている(図2(b))。絶縁基板21の上面に設けられた孔は入射部に位置するため貫通孔41の径としては最大径を形成しやすい。絶縁基板21を分解させながら、絶縁基板21の下面に達っする。このとき、絶縁基板21の上面から下面に向かって貫通孔41は縮径していく。下面から出射したレーザは、反射部材50に達する。反射部材50に達したレーザ光は、反射部材を加工しながら同時に反射し再び絶縁基材21の下面から入射し絶縁基材21を加工させる。下面から入射したレーザ光は、上面に向かって貫通孔41は縮径しながら加工される。そのため、入射したときに形成される上面から下面に縮径する貫通孔41と、下面から上面に向かって縮径する貫通孔41が合わさった形状となる。貫通孔41は、絶縁基板21の上面から、絶縁基板の下面にいたる所定の深さ位置において最小径(d1)を形成する。貫通孔41は、絶縁基板21の上面から所定の深さ位置に向かって縮径し、所定の深さ位置から絶縁基板21の下面に向かって拡径している。 A through hole 41 is formed in the laminated plate 20 by irradiating a laser from the upper surface (FIG. 2C). The hole diameter to be processed is preferably 100 μm or less, more preferably 50 μm or less. Examples of the laser include a CO 2 laser processing machine, a UV laser processing machine, and an excimer laser processing machine, and a CO 2 laser processing machine is preferable. The laser processing conditions are preferably a pulse width of 1 to 100 μm and a reference energy of 0.5 to 9.0 mJ, more preferably a pulse width of 1 to 20 μm and a reference energy of 1.0 to 3.0 mJ. The number of shots may be appropriately determined according to the thickness of the substrate. A copper foil having a thickness of 2 μm is laminated as the first metal layer 11 on the upper surface of the insulating substrate 21 which is a laser incident surface. Since the processing is performed by a conformal method, the first metal layer 11 is removed by etching in accordance with the hole diameter to be processed in the first metal layer 11 (FIG. 2B). Since the hole provided on the upper surface of the insulating substrate 21 is located at the incident portion, the maximum diameter of the through hole 41 is easily formed. While the insulating substrate 21 is disassembled, the bottom surface of the insulating substrate 21 is reached. At this time, the diameter of the through hole 41 decreases from the upper surface to the lower surface of the insulating substrate 21. The laser emitted from the lower surface reaches the reflecting member 50. The laser light reaching the reflecting member 50 is simultaneously reflected while processing the reflecting member, and is incident again from the lower surface of the insulating base material 21 to process the insulating base material 21. Laser light incident from the lower surface is processed while the through hole 41 is reduced in diameter toward the upper surface. For this reason, a shape is formed in which the through-hole 41 that is reduced in diameter from the upper surface to the lower surface and the through-hole 41 that is reduced in diameter from the lower surface toward the upper surface are formed. The through hole 41 has a minimum diameter (d1) at a predetermined depth position from the upper surface of the insulating substrate 21 to the lower surface of the insulating substrate. The through hole 41 is reduced in diameter from the upper surface of the insulating substrate 21 toward a predetermined depth, and is expanded from the predetermined depth position toward the lower surface of the insulating substrate 21.

これにより、図3(a)に示すように、絶縁基板21の貫通孔41内に孔径が細くなり、括れた形状を有するので、この貫通孔41内にめっきを形成させるとき、まず、貫通孔41内壁面にめっきが成長を始める、次に、括れた部分でスルホール壁面から成長しためっき同士がくっつき埋め込みが始まる(図3(b))。めっきを続けることによりそれぞれの面側の表面に向かってめっきが成長していく。めっきが成長していく方向に対しては貫通孔41が拡径しているため埋め込み性に優れたプリント配線基板を提供できる絶縁基板21とすることができる(図3(c))。
また、絶縁基板21の最小径(d1)の位置は、レーザの照射時間で調整することができる。これは、レーザの照射時間が長くなると、反射したレーザが絶縁基板の下面からの加工時間が長くなり、その結果括れ位置が上方へと移動していく。絶縁基板の厚さ方向に対して、略中央に最小径(d1)が形成されるようレーザ加工条件を適宜選択することができる。そのため、絶縁層の厚さが厚く、孔径が小さい、すなわち、アスペクト比が大きい貫通孔41に対して好適である。
As a result, as shown in FIG. 3A, the diameter of the through hole 41 of the insulating substrate 21 is reduced and has a constricted shape. Therefore, when plating is formed in the through hole 41, first, the through hole is formed. The plating begins to grow on the inner wall surface 41. Next, the platings grown from the through-hole wall surface in the constricted portion stick to each other and begin to be embedded (FIG. 3B). By continuing the plating, the plating grows toward the surface on each side. With respect to the direction in which plating grows, the diameter of the through hole 41 is increased, so that it is possible to provide an insulating substrate 21 that can provide a printed wiring board excellent in embeddability (FIG. 3C).
The position of the minimum diameter (d1) of the insulating substrate 21 can be adjusted by the laser irradiation time. This is because when the laser irradiation time is increased, the reflected laser is processed for a longer time from the lower surface of the insulating substrate, and as a result, the constricted position moves upward. The laser processing conditions can be appropriately selected so that the minimum diameter (d1) is formed substantially at the center with respect to the thickness direction of the insulating substrate. Therefore, it is suitable for the through hole 41 having a thick insulating layer and a small hole diameter, that is, a large aspect ratio.

次に、本発明の効果を明らかにするために通常行なわれている方法について説明する。
通常、図4に示すように、積層板30は、単層絶縁層25と、単層絶縁層25の上面に第二金属層11が、下面には第二金属層12が積層されている。コンフォーマル法で行なう準備に関しては、本実施形態と同様である。上面の第二金属層11に対してレーザ加工を行なう。単層絶縁層25に設けられた孔は入射部に位置するため最大径を形成する。単層絶縁層であるから加工途中でのレーザ加工性は変わることなく単層絶縁層25を貫通する。レーザ加工が進んでも加工がしやすい絶縁層がないので単層絶縁層25は拡径することなく加工され、上面の第二金属層11から下面の第一金属層12に向かって縮径する貫通孔40が形成される。これによって、単層絶縁層の上面から下面にいたる深さ位置において最小径を形成することなく貫通孔40となる。
単層絶縁層の上面の第二金属層11から下面の第一金属層12に向かって一方的に縮径する貫通孔40であるため、孔埋めスルホールめっきをおこなうと、成長を開始しためっきは、最小径を形成している単層絶縁層の下面の第一金属層12との界面付近でめっきが接触する(図4(b))。次に、拡径する方向へとめっきが成長していく(図4(c))。このとき、上面までめっきが成長する距離が長いため、成長途上で気泡43を巻き込みやすくなる。これは、埋め込みまでのめっき時間が長いため、貫通孔40周縁部分への電流集中による過剰めっき析出発生し、気泡を抱き込みやすくなる。
Next, a method usually performed for clarifying the effect of the present invention will be described.
Usually, as shown in FIG. 4, the laminated plate 30 includes a single-layer insulating layer 25, a second metal layer 11 stacked on the upper surface of the single-layer insulating layer 25, and a second metal layer 12 stacked on the lower surface. The preparation performed by the conformal method is the same as that of the present embodiment. Laser processing is performed on the second metal layer 11 on the upper surface. Since the hole provided in the single-layer insulating layer 25 is located in the incident part, it forms the maximum diameter. Since it is a single layer insulating layer, the laser processing property during the processing does not change and penetrates the single layer insulating layer 25. Since there is no insulating layer that is easy to process even if laser processing proceeds, the single-layer insulating layer 25 is processed without expanding its diameter, and the diameter decreases from the second metal layer 11 on the upper surface toward the first metal layer 12 on the lower surface. A hole 40 is formed. Thereby, the through hole 40 is formed without forming a minimum diameter at a depth position from the upper surface to the lower surface of the single-layer insulating layer.
Since the through-hole 40 is unilaterally reduced in diameter from the second metal layer 11 on the upper surface of the single-layer insulating layer toward the first metal layer 12 on the lower surface, when hole filling through-hole plating is performed, The plating contacts in the vicinity of the interface with the first metal layer 12 on the lower surface of the single-layer insulating layer forming the minimum diameter (FIG. 4B). Next, the plating grows in the direction of expanding the diameter (FIG. 4C). At this time, since the distance at which the plating grows up to the upper surface is long, the bubbles 43 are easily involved in the growth process. This is because the plating time until filling is long, so that excessive plating precipitates due to current concentration in the peripheral portion of the through-hole 40, and air bubbles are easily taken in.

次に、本実施形態の絶縁基板21の各構成要素について詳細に説明する。   Next, each component of the insulating substrate 21 of this embodiment will be described in detail.

絶縁基板21は、無機繊維基材を含んでいてもよい。無機繊維基材としては、例えばガラス繊布、ガラス不繊布等のガラス繊維基材、あるいはガラス以外の無機化合物を成分とする繊布又は不繊布等の無機繊維基材があげられる。これらのなかでも、プリント配線基板としたときの剛性の面からガラス織布繊維基材が好ましい。
絶縁基板21の樹脂を構成する材料としては、例えば、熱硬化性樹脂と、硬化剤とを含んでいることが好ましい。熱硬化性樹脂としては、エポキシ樹脂、シアネート樹脂、フェノール樹脂などを単独あるいは複数組合わせて用いることができる。エポキシ樹脂としては、特に限定はされないが、例えば、絶縁基板用として一般に使用されている、例えば、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビスフェノールAD型エポキシ樹脂等のビスフェノール型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂、臭素化ビスフェノールA型エポキシ樹脂、臭素化フェノールノボラック型エポキシ樹脂等の臭素化型エポキシ樹脂、トリグリシジルイソシアネートなどの複素環式エポキシ樹脂のほか、脂環式型エポキシ樹脂、ビフェニル型エポキシ樹脂、ナフタレン型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等が挙げられる。これらを単独または2種類以上組み合わせて使用することができる。
前記シアネート樹脂としては、例えばハロゲン化シアン化合物とフェノール類とを反応させ、必要に応じて加熱等の方法でプレポリマー化することにより得ることができる。具体的には、ノボラック型シアネート樹脂、ビスフェノールA型シアネート樹脂、ビスフェノールE型シアネート樹脂、テトラメチルビスフェノールF型シアネート樹脂等のビスフェノール型シアネート樹脂等を挙げることができる。これらの中でもノボラック型シアネート樹脂が好ましい。これにより、架橋密度増加による耐熱性向上と、樹脂組成物等の難燃性を向上することができる。
なお、絶縁基板21として、以下のような樹脂フィルムを使用してよい。樹脂フィルムとしては、例えばポリイミド樹脂フィルム、ポリエーテルイミド樹脂フィルム、ポリアミドイミド樹脂フィルム等のポリイミド樹脂系樹脂フィルム、ポリアミド樹脂フィルム等のポリアミド樹脂系フィルム、ポリエステル樹脂フィルム等のポリエステル樹脂系フィルムが挙げられる。これら中でも主としてポリイミド樹脂系フィルムが好ましい。これにより、弾性率と耐熱性を特に向上することができる。
The insulating substrate 21 may include an inorganic fiber base material. As an inorganic fiber base material, inorganic fiber base materials, such as glass fiber base materials, such as glass fiber cloth and a glass non-woven cloth, or the fiber cloth or non-fiber cloth which use inorganic compounds other than glass as a component, are mention | raise | lifted, for example. Among these, a glass woven fiber base material is preferable from the viewpoint of rigidity when used as a printed wiring board.
As a material constituting the resin of the insulating substrate 21, for example, a thermosetting resin and a curing agent are preferably included. As the thermosetting resin, an epoxy resin, a cyanate resin, a phenol resin, or the like can be used alone or in combination. Although it does not specifically limit as an epoxy resin, For example, bisphenol type epoxy resins, such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol AD type epoxy resin, etc. which are generally used for insulating substrates, phenol Novolak-type epoxy resins, cresol novolak-type epoxy resins, etc. novolak-type epoxy resins, brominated bisphenol A-type epoxy resins, brominated phenol novolac-type epoxy resins, etc. brominated epoxy resins, and heterocyclic epoxy resins such as triglycidyl isocyanate In addition, alicyclic epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, glycidyl ester type epoxy resin and the like can be mentioned. These can be used alone or in combination of two or more.
The cyanate resin can be obtained by, for example, reacting a halogenated cyanide compound with a phenol and prepolymerizing it by a method such as heating as necessary. Specific examples include bisphenol type cyanate resins such as novolac type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethylbisphenol F type cyanate resin. Among these, novolac type cyanate resin is preferable. Thereby, the heat resistance improvement by a crosslinking density increase and flame retardance, such as a resin composition, can be improved.
As the insulating substrate 21, the following resin film may be used. Examples of the resin film include polyimide resin films such as polyimide resin films, polyetherimide resin films, polyamideimide resin films, polyamide resin films such as polyamide resin films, and polyester resin films such as polyester resin films. . Among these, a polyimide resin film is mainly preferable. Thereby, especially an elasticity modulus and heat resistance can be improved.

硬化剤としては、特に限定はされないが、例えば、絶縁基板用として一般に使用されている、アミノ基を有する硬化剤であって、メタフェニレンジアミン、パラフェニレンジアミン、パラキシレンジアミン、4,4’−ジアミノジフェニルメタン、4,4’−ジアミノジフェニルプロパン、4,4’−ジアミノジフェニルエーテル、4,4’−ジアミノジフェニルスルフォン、4,4’−ジアミノジシクロヘキサン、ビス(4−アミノフェニル)フェニルメタン、1,5−ジアミノナフタレン、メタキシリレンジアミン、パラキシレンナフタレン、1,1−ビス(4−アミノフェニル)シクロヘキサン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンなどが用いられる。耐熱性、硬化性等の点で、好ましい硬化剤は、4,4’−ジアミノジフェニルメタン、ジシアンジアミド、ジアミノジエチルジメチルフェニルメタンである。これらのうち何種類かを併用しても良い。   Although it does not specifically limit as a hardening | curing agent, For example, it is a hardening | curing agent which has an amino group generally used for insulating substrates, Comprising: Metaphenylenediamine, paraphenylenediamine, paraxylenediamine, 4,4'- Diaminodiphenylmethane, 4,4′-diaminodiphenylpropane, 4,4′-diaminodiphenyl ether, 4,4′-diaminodiphenylsulfone, 4,4′-diaminodicyclohexane, bis (4-aminophenyl) phenylmethane, 1, 5-Diaminonaphthalene, metaxylylenediamine, paraxylene naphthalene, 1,1-bis (4-aminophenyl) cyclohexane, dicyandiamide, diaminodiethyldimethylphenylmethane, and the like are used. In view of heat resistance, curability and the like, preferred curing agents are 4,4'-diaminodiphenylmethane, dicyandiamide, and diaminodiethyldimethylphenylmethane. Some of these may be used in combination.

また、絶縁基板21には無機充填材を含んでいてもよい。例えばタルク、焼成クレー、未焼成クレー、マイカ、ガラス等のケイ酸塩、酸化チタン、アルミナ、シリカ、溶融シリカ等の酸化物、炭酸カルシウム、炭酸マグネシウム、ハイドロタルサイト等の炭酸塩、水酸化アルミニウム、水酸化マグネシウム、水酸化カルシウム等の水酸化物、硫酸バリウム、硫酸カルシウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、窒化アルミニウム、窒化ホウ素、窒化ケイ素、窒化炭素等の窒化物、チタン酸ストロンチウム、チタン酸バリウム等のチタン酸塩等を挙げることができる。無機充填材として、これらの中の1種類を単独で用いることもできるし、2種類以上を併用したりすることもできる。これらの中でも特に、水酸化アルミニウム、シリカが好ましく、溶融シリカ(特に球状溶融シリカ)が低熱膨張性に優れる点で好ましい。その形状は破砕状、球状があるが、基材への含浸性を確保するために樹脂組成物の溶融粘度を下げるには球状シリカを使う等、その目的にあわせた使用方法が採用される。無機充填材の含有量は、樹脂成分100重量部に対して、30重量部以上、70重量部以下であることが好ましく、さらに好ましくは40重量部以上、60重量部以下である。   The insulating substrate 21 may contain an inorganic filler. For example, silicates such as talc, calcined clay, unfired clay, mica and glass, oxides such as titanium oxide, alumina, silica and fused silica, carbonates such as calcium carbonate, magnesium carbonate and hydrotalcite, aluminum hydroxide , Hydroxides such as magnesium hydroxide, calcium hydroxide, sulfates or sulfites such as barium sulfate, calcium sulfate, calcium sulfite, zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate, etc. Borate, aluminum nitride, boron nitride, silicon nitride, carbon nitride and other nitrides, strontium titanate, titanates such as barium titanate, and the like. As the inorganic filler, one of these can be used alone, or two or more can be used in combination. Among these, aluminum hydroxide and silica are particularly preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low thermal expansion. The shape is crushed and spherical, but in order to reduce the melt viscosity of the resin composition in order to ensure the impregnation property to the substrate, a usage method suitable for the purpose is used such as using spherical silica. The content of the inorganic filler is preferably 30 to 70 parts by weight, more preferably 40 to 60 parts by weight with respect to 100 parts by weight of the resin component.

無機充填材の平均粒子径は、特に限定されないが、0.05〜10μmが好ましく、特に0.3〜5μmが好ましい。この平均粒子径は、例えば粒度分布計(HORIBA製、LA−500)により測定することができる。   The average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.05 to 10 μm, and particularly preferably 0.3 to 5 μm. This average particle diameter can be measured, for example, by a particle size distribution meter (manufactured by HORIBA, LA-500).

また、無機充填材は、特に限定されないが、平均粒子径が単分散の無機充填材を用いることもできるし、平均粒子径が多分散の無機充填材を用いることができる。さらに平均粒子径が単分散及び/または、多分散の無機充填材を1種類または2種類以上併用したりすることもできる。絶縁基板21の厚さは、30μm〜200μmが好ましく、より好ましくは40μm〜120μmである。   The inorganic filler is not particularly limited, and an inorganic filler having a monodispersed average particle diameter can be used, and an inorganic filler having a polydispersed average particle diameter can be used. Furthermore, one or two or more inorganic fillers having an average particle size of monodisperse and / or polydisperse can be used in combination. The thickness of the insulating substrate 21 is preferably 30 μm to 200 μm, more preferably 40 μm to 120 μm.

金属層11、12としては、極薄金属箔を用いる場合は、金属種としては、ステンレス、ニッケル、アルミ、鉄、銅などがもちいられ、エッチング性などから銅がより好適に用いられる。金属箔の厚さは、2μm〜12μmが好ましく用いられる。 As the metal layers 11 and 12, when an ultrathin metal foil is used, as the metal species, stainless steel, nickel, aluminum, iron, copper or the like is used, and copper is more preferably used from the viewpoint of etching property. The thickness of the metal foil is preferably 2 μm to 12 μm.

次に、絶縁基板21を回路加工してなるプリント配線基板について説明する。   Next, a printed wiring board obtained by processing the insulating substrate 21 will be described.

図2に示すように、はじめに、表裏面に、第一および第二金属層11、12として厚さが2μmの銅箔が積層された積層体20を用意する(図2(a))。次に、図2(b)に示すように、絶縁基板21の上面の第二金属箔11に孔径に相当する形状にエッチング加工で除去する。次にレーザを用いて貫通孔41を形成する(図2(c))。次にめっきにより貫通孔41を埋め込むめっきを行なう(図3)。貫通孔41を孔埋めした絶縁基板に所望の配線回路をフォトリソグラフィー法を用いて形成し、次に、第一および第二金属層11、12をエッチング加工を行ない配線回路を形成した。次に、配線回路の一部を残して絶縁被覆層を形成し、絶縁被覆層で覆われていない開口部には金属表面処理をおこないプリント配線基板とした。   As shown in FIG. 2, first, a laminate 20 is prepared in which copper foil having a thickness of 2 μm is laminated on the front and back surfaces as first and second metal layers 11 and 12 (FIG. 2A). Next, as shown in FIG. 2B, the second metal foil 11 on the upper surface of the insulating substrate 21 is removed by etching into a shape corresponding to the hole diameter. Next, the through-hole 41 is formed using a laser (FIG.2 (c)). Next, plating for filling the through holes 41 by plating is performed (FIG. 3). A desired wiring circuit was formed on the insulating substrate in which the through hole 41 was filled by using a photolithography method, and then the first and second metal layers 11 and 12 were etched to form a wiring circuit. Next, an insulating coating layer was formed while leaving a part of the wiring circuit, and a metal surface treatment was performed on the opening not covered with the insulating coating layer to obtain a printed wiring board.

次に、プリント配線基板に半導体素子を搭載してなる半導体装置について説明する。   Next, a semiconductor device in which a semiconductor element is mounted on a printed wiring board will be described.

プリント配線基板に半導体素子を搭載してなる半導体装置は、特に限定されるものではないが、例えば、プリント配線基板と半導体素子がボンディングワイヤーにより接続された半導体装置や、プリント配線基板と半導体素子が半田バンプを介して接続されたフリップチップタイプの半導体装置等が挙げられる。以下、フリップチップタイプの半導体装置について一例を示す。   A semiconductor device in which a semiconductor element is mounted on a printed wiring board is not particularly limited. For example, a semiconductor device in which a printed wiring board and a semiconductor element are connected by a bonding wire, or a printed wiring board and a semiconductor element are connected. A flip chip type semiconductor device connected through solder bumps is exemplified. An example of a flip chip type semiconductor device will be described below.

フリップチップタイプの半導体装置は、プリント配線基板に半田バンプを有する半導体素子を実装し、半田バンプを介して、プリント配線基板と半導体素子とを接続する。そして、プリント配線基板と半導体素子との間には液状封止樹脂を充填し、半導体装置を形成する。半田バンプは、錫、鉛、銀、銅、ビスマスなどからなる合金で構成されることが好ましい。半導体素子とプリント配線基板との接続方法は、フリップチップボンダーなどを用いてプリント配線基板上の接続用電極部と半導体素子の半田バンプとの位置合わせを行ったあと、IRリフロー装置、熱板、その他加熱装置を用いて半田バンプを融点以上に加熱し、プリント配線基板と半田バンプとを溶融接合することにより接続する。尚、接続信頼性を良くするため、予めプリント配線基板上の接続用電極部に半田ペースト等、比較的融点の低い金属の層を形成しておいても良い。この接合工程に先んじて、半田バンプおよび、またはプリント配線基板上の接続用電極部の表層にフラックスを塗布することで接続信頼性を向上させることもできる。   In a flip chip type semiconductor device, a semiconductor element having a solder bump is mounted on a printed wiring board, and the printed wiring board and the semiconductor element are connected via the solder bump. A liquid sealing resin is filled between the printed wiring board and the semiconductor element to form a semiconductor device. The solder bump is preferably made of an alloy made of tin, lead, silver, copper, bismuth or the like. The method for connecting the semiconductor element and the printed wiring board is to align the connection electrode portion on the printed wiring board and the solder bump of the semiconductor element using a flip chip bonder, etc. In addition, the solder bumps are heated to the melting point or higher by using a heating device, and the printed wiring board and the solder bumps are connected by fusion bonding. In order to improve connection reliability, a metal layer having a relatively low melting point, such as solder paste, may be formed in advance on the connection electrode portion on the printed wiring board. Prior to this joining step, the connection reliability can be improved by applying flux to the solder bumps and / or the surface layer of the connection electrode portion on the printed wiring board.

以下、本発明を実施例及び比較例により説明するが、本発明はこれに限定されるものではない。   Hereinafter, although an example and a comparative example explain the present invention, the present invention is not limited to this.

(実施例1)
(1)絶縁基板として、ガラス繊維基材にエポキシ樹脂組成物を含浸したプリプレグの両面側に、金属層として厚さ2μmの銅箔を積層成形して、厚さが100μmの積層板を得た。
Example 1
(1) As an insulating substrate, a copper foil having a thickness of 2 μm was laminated as a metal layer on both sides of a prepreg in which a glass fiber base was impregnated with an epoxy resin composition to obtain a laminated plate having a thickness of 100 μm. .

(2)上記積層板に、炭酸ガスレーザー加工機(三菱電機社製、605GTXIII)によって、45μmの貫通孔を形成した。次に、無電解めっき、電解めっきを行ない貫通孔41をめっきによって埋め込んだ。次に、フォトリソグラフィ法で回路形成を行なった。次に、それぞれの面側に、ソルダーレジスト(太陽インキ製造社製PSR4000/AUS308)を形成し、半導体素子を実装する回路部分には開口部を設け、開口部にニッケル金メッキ処理を施し、50mm×50mmの大きさに切断し、プリント配線基板を得た。 (2) A 45 μm through-hole was formed in the laminate using a carbon dioxide laser processing machine (manufactured by Mitsubishi Electric Corporation, 605GTXIII). Next, electroless plating and electrolytic plating were performed, and the through holes 41 were filled by plating. Next, circuit formation was performed by photolithography. Next, a solder resist (PSR4000 / AUS308 manufactured by Taiyo Ink Manufacture Co., Ltd.) is formed on each surface side, an opening is provided in a circuit portion on which a semiconductor element is mounted, nickel gold plating is applied to the opening, and 50 mm × The printed wiring board was obtained by cutting into a size of 50 mm.

(3)半導体装置の製造
半導体素子(TEGチップ、サイズ15mm×15mm、厚み0.8mm)は、半田バンプをSn/Ag組成の共晶で形成し、回路保護膜をポジ型感光性樹脂(住友ベークライト社製CRC−8300)で形成したものを使用した。半導体装置の組み立ては、まず、半田バンプにフラックス材を転写法により均一に塗布し、次にフリップチップボンダー装置を用い、上記パッケージ基板上に加熱圧着により搭載した。次に、IRリフロー炉で半田バンプを溶融接合した後、液状封止樹脂(住友ベークライト社製、CRP−4152S)を充填し、液状封止樹脂を硬化させることで半導体装置を得た。尚、液状封止樹脂は、温度150℃、120分の条件で硬化させた。
(3) Manufacture of Semiconductor Device A semiconductor element (TEG chip, size 15 mm × 15 mm, thickness 0.8 mm) has a solder bump formed of a eutectic of Sn / Ag composition, and a circuit protective film formed of a positive photosensitive resin (Sumitomo). Bakelite CRC-8300) was used. In assembling the semiconductor device, first, a flux material was uniformly applied to the solder bumps by a transfer method, and then mounted on the package substrate by thermocompression bonding using a flip chip bonder device. Next, after solder bumps were melt-bonded in an IR reflow furnace, a liquid sealing resin (manufactured by Sumitomo Bakelite Co., Ltd., CRP-4152S) was filled and the liquid sealing resin was cured to obtain a semiconductor device. The liquid sealing resin was cured at a temperature of 150 ° C. for 120 minutes.

作成した半導体装置にもちいたプリント配線基板の各構成は表1に示すとおりである。各実施例および比較例により得られた半導体装置について、次の各評価を行った。各評価を、評価方法と共に以下に示す。得られた結果を表1に示す。   Each configuration of the printed wiring board used for the created semiconductor device is as shown in Table 1. Each of the following evaluations was performed on the semiconductor devices obtained in the examples and comparative examples. Each evaluation is shown below together with the evaluation method. The obtained results are shown in Table 1.

Figure 0005560834
Figure 0005560834

1.評価方法
(1)めっき埋め込み性
ビア部分の断面研磨をn=30で実施しビア内の埋め込み性を確認した。ボイドなしを◎、3μm以下のマイクロボイドがある場合を○、3μmより大きいボイドが発生した場合を×とした。
(2)温度サイクル導通試験
試験条件として、温度サイクル(−60℃〜150℃)、保持時間10分、温度変更時間20分の条件下で、温度サイクル試験機を用いて、n=5で1000サイクルまで導通試験を行ない導通抵抗を確認した。
1. Evaluation method (1) Plating embedding property Cross section polishing of the via portion was performed at n = 30, and the embedding property in the via was confirmed. The case where there was no void, the case where there was a micro void of 3 μm or less, and the case where a void larger than 3 μm was generated were marked as x.
(2) Temperature cycle continuity test As test conditions, a temperature cycle (−60 ° C. to 150 ° C.), a holding time of 10 minutes, and a temperature change time of 20 minutes were used. A continuity test was conducted until the cycle to confirm the continuity resistance.

表1から明らかなように、実施例1〜4は、埋め込み性が良好であった。これに対して比較例1〜2は、めっき埋め込み時にボイドが発生した。これは実施例1〜4では貫通孔が括れた形状を有するので、この貫通孔内にめっきを形成させるとき、まず、貫通孔内壁面にめっきが成長を始め、次に、括れた部分でスルホール壁面から成長しためっき同士がくっつき埋め込みが始まる。そして、めっきを続けることによりそれぞれの面側の表面に向かってめっきが成長していくことにより、めっきの成長過程で気泡などを巻き込むことがなかったと考えられる。それに対して、比較例1〜2では、貫通孔が一方の面から他方の面へ縮径していく形状であり、一方の面側までめっきが成長する距離が長いため、成長途上で気泡を巻き込みやすくなり、埋め込みまでのめっき時間が長いため、貫通孔周縁部分への電流集中によるめっき析出が過剰に発生し、気泡を抱き込みやすくなったと考えられる。半導体装置での、温度サイクル試験の結果で、埋め込みめっき中に気泡を抱き込んでいるものはサイクル試験でも10サイクルで不良となった。   As is clear from Table 1, Examples 1 to 4 had good embedding properties. On the other hand, in Comparative Examples 1 and 2, voids occurred when the plating was embedded. In Examples 1 to 4, since the through hole has a constricted shape, when plating is formed in the through hole, the plating first grows on the inner wall surface of the through hole, and then the through hole is formed in the constricted portion. The plating grown from the wall surface sticks to each other and embedding begins. And it is thought that the bubble etc. did not get involved in the growth process of plating because plating grew toward the surface of each surface side by continuing plating. On the other hand, in Comparative Examples 1 and 2, the through-hole has a shape that decreases in diameter from one surface to the other surface, and since the distance that the plating grows to one surface side is long, bubbles are generated during the growth. It is considered that the entrapment is easy and the plating time until embedding is long, so that plating deposition due to current concentration on the peripheral portion of the through-hole is excessively generated and the bubbles are easily held. As a result of the temperature cycle test in the semiconductor device, those in which bubbles were embedded in the embedded plating were defective in 10 cycles even in the cycle test.

11 第一金属層
12 第二金属層
20 積層板
21 絶縁基板
25 単層絶縁層
30 積層板
40 貫通孔
41 貫通孔
43 気泡
50 反射部材
d1 最小径
d2 絶縁基板の一方の面側に設けられた貫通孔の径
d3 絶縁基板の他方の面側に設けられた貫通孔の径
t1 絶縁基板の厚さ
11 First metal layer 12 Second metal layer 20 Laminated plate 21 Insulating substrate 25 Single layer insulating layer 30 Laminated plate 40 Through hole 41 Through hole 43 Air bubble 50 Reflective member d1 Minimum diameter d2 Provided on one surface side of the insulating substrate Diameter d3 of the through hole Diameter t1 of the through hole provided on the other surface side of the insulating substrate Thickness of the insulating substrate

Claims (4)

プリント配線基板に用いられ、金属層として2μm〜12μmの金属箔を有する絶縁基板を製造する方法であって、
絶縁基板と、前記絶縁基板の他方の面側に当接してレーザを反射する反射部材を配置する工程と、
前記絶縁基材の一方の面側からレーザ孔あけ加工を行なって前記絶縁基板に貫通孔を形成する工程と、
前記反射部材に向かってさらにレーザ照射を続ける工程とを含み、
前記貫通孔は、前記絶縁基板の一方の面側から、前記絶縁基板の他方の面側にいたる所定の深さ位置において最小径を有するとともに、前記貫通孔は、前記絶縁基板の一方の面側から前記所定の深さ位置に向かって縮径し、前記所定の深さ位置から前記絶縁基板の他方の面側に向かって拡径していることを特徴とする絶縁基板の製造方法。
A method for manufacturing an insulating substrate having a metal foil of 2 μm to 12 μm used as a metal layer for a printed wiring board,
An insulating substrate, disposing a reflecting member for reflecting the record over THE abuts the other surface of the insulating substrate,
A step of forming a through hole in the insulating substrate by performing laser drilling from one surface side of the insulating base;
Further continuing the laser irradiation toward the reflecting member,
The through hole has a minimum diameter at a predetermined depth position from one surface side of the insulating substrate to the other surface side of the insulating substrate, and the through hole is on one surface side of the insulating substrate. The method of manufacturing an insulating substrate, wherein the diameter is reduced from the predetermined depth position toward the predetermined depth position, and the diameter is increased from the predetermined depth position toward the other surface side of the insulating substrate.
前記反射部材に向かってさらにレーザ照射を続ける前記工程は、前記反射部材で、レーザを反射させ反射した前記レーザによってさらに前記絶縁基材の他方の面側から前記絶縁基材の一方の面側に向かってレーザ加工を行なう請求項に記載の絶縁基板の製造方法。 In the step of continuing further laser irradiation toward the reflecting member, the reflecting member reflects and reflects the laser from the other surface side of the insulating base material to the one surface side of the insulating base material. The method for manufacturing an insulating substrate according to claim 1 , wherein laser processing is performed toward the substrate. 前記貫通孔を、電気めっきによって埋め込む工程を含む請求項またはに記載の絶縁基板の製造方法。 The manufacturing method of the insulated substrate of Claim 1 or 2 including the process of embedding the said through-hole by electroplating. 前記反射部材は、鏡面加工された金属板である請求項ないしのいずれか一項に記載の絶縁基板の製造方法。 The reflecting member, manufacturing method of the insulating substrate according to any one of claims 1 is a metal plate which is mirror-finished 3.
JP2010074797A 2010-03-29 2010-03-29 Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device Expired - Fee Related JP5560834B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010074797A JP5560834B2 (en) 2010-03-29 2010-03-29 Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010074797A JP5560834B2 (en) 2010-03-29 2010-03-29 Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device

Publications (2)

Publication Number Publication Date
JP2011210794A JP2011210794A (en) 2011-10-20
JP5560834B2 true JP5560834B2 (en) 2014-07-30

Family

ID=44941578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010074797A Expired - Fee Related JP5560834B2 (en) 2010-03-29 2010-03-29 Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device

Country Status (1)

Country Link
JP (1) JP5560834B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013157366A (en) * 2012-01-27 2013-08-15 Kyocer Slc Technologies Corp Wiring board and packaging structure including the same
JP2013229421A (en) * 2012-04-25 2013-11-07 Kyocer Slc Technologies Corp Wiring board
JP2014139963A (en) * 2013-01-21 2014-07-31 Ngk Spark Plug Co Ltd Glass substrate manufacturing method
JP5846185B2 (en) 2013-11-21 2016-01-20 大日本印刷株式会社 Through electrode substrate and semiconductor device using the through electrode substrate
JP6387712B2 (en) * 2014-07-07 2018-09-12 イビデン株式会社 Printed wiring board
WO2019003729A1 (en) 2017-06-26 2019-01-03 株式会社村田製作所 Multilayer wiring board and method for manufacturing multilayer wiring board
CN111508925B (en) 2019-01-31 2024-04-23 奥特斯奥地利科技与系统技术有限公司 Component carrier and method for producing a component carrier
JP6992797B2 (en) * 2019-12-26 2022-01-13 大日本印刷株式会社 Through Silicon Via Substrate
TWI807464B (en) * 2020-11-06 2023-07-01 日商互應化學工業股份有限公司 Printed wiring board and manufacturing method of printed wiring board

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60133992A (en) * 1983-12-21 1985-07-17 Canon Inc Piercing device for printed circuit board
JP3621435B2 (en) * 1993-11-25 2005-02-16 シチズン時計株式会社 Package and manufacturing method thereof
JPH11168281A (en) * 1997-12-02 1999-06-22 Hitachi Aic Inc Manufacture of thin multilayer printed wiring board
JP3880242B2 (en) * 1998-05-20 2007-02-14 キヤノン株式会社 Through hole formation method
JP3004266B1 (en) * 1998-11-27 2000-01-31 京セラ株式会社 Wiring board and method of manufacturing the same
JP2002280743A (en) * 2001-03-21 2002-09-27 Toyota Industries Corp Multilayer printed wiring board and its manufacturing method
JP4256603B2 (en) * 2001-08-02 2009-04-22 イビデン株式会社 Manufacturing method of laminated wiring board
JP2003318501A (en) * 2002-04-26 2003-11-07 Nec Kansai Ltd Wiring board
JP2003347700A (en) * 2002-05-29 2003-12-05 Nec Kansai Ltd Wiring board
JP2004311919A (en) * 2003-02-21 2004-11-04 Shinko Electric Ind Co Ltd Through-hole filling method
TWI235019B (en) * 2004-07-27 2005-06-21 Unimicron Technology Corp Process of conductive column and circuit board with conductive column
TW200611612A (en) * 2004-09-29 2006-04-01 Unimicron Technology Corp Process of electrically interconnect structure
JP2006310779A (en) * 2005-03-29 2006-11-09 Kyocera Corp Circuit board and electronic device
JP5021216B2 (en) * 2006-02-22 2012-09-05 イビデン株式会社 Printed wiring board and manufacturing method thereof
JP2008159969A (en) * 2006-12-26 2008-07-10 Kyocera Corp Circuit board, electronic apparatus, and method of manufacturing circuit board
JP2009054689A (en) * 2007-08-24 2009-03-12 Kyocera Corp Wiring board, mounting board and mounting structure, and manufacturing method of wiring board
JP5181702B2 (en) * 2008-02-06 2013-04-10 株式会社村田製作所 Wiring board manufacturing method
KR20100070161A (en) * 2008-12-17 2010-06-25 삼성전기주식회사 Printed circuit board and manufacturing method thereof

Also Published As

Publication number Publication date
JP2011210794A (en) 2011-10-20

Similar Documents

Publication Publication Date Title
JP5560834B2 (en) Insulating substrate, method for manufacturing insulating substrate, printed wiring board, and semiconductor device
JP2011210795A (en) Laminated board, method of manufacturing the same, printed-wiring board, and semiconductor device
JP5150518B2 (en) Semiconductor device, multilayer wiring board, and manufacturing method thereof
JP4279893B2 (en) Manufacturing method of circuit component built-in module
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
TW201223380A (en) Multilayer wiring board and manufacturing method thereof
TW201242442A (en) Printed circuit board and method of manufacturing the same
US20120247818A1 (en) Printed wiring board
JP2013532901A (en) Heat dissipation circuit board and manufacturing method thereof
TW201247071A (en) Wiring board and method of manufacturing the same
JP4493923B2 (en) Printed wiring board
TW201218898A (en) Wiring substrate manufacturing method
JP4885366B2 (en) Wiring board manufacturing method
JP2001345560A (en) Wiring board, and its manufacturing method, and electronic component
JP2011100908A (en) Printed wiring board, and semiconductor device
US10477692B2 (en) Printed board, light source device, semiconductor device, and methods of manufacturing same
JP2005123547A (en) Interposer and multilayer printed wiring board
JP4353873B2 (en) Printed wiring board
JP5010669B2 (en) Wiring board and manufacturing method thereof
JP7089453B2 (en) Wiring board and its manufacturing method
JP4534575B2 (en) Wiring board manufacturing method
JP2007273896A (en) Wiring board
JP2002118368A (en) Wiring substrate and manufacturing method thereof
JP2014090079A (en) Printed wiring board
JP2004111471A (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131009

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131022

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131209

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140513

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140526

R150 Certificate of patent or registration of utility model

Ref document number: 5560834

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees