JP5556420B2 - Phase-locked loop circuit and method for controlling phase-locked loop circuit - Google Patents

Description

  The present invention relates to a PLL circuit having a wide oscillation frequency band.

  The VCO circuit is desired to have a wide oscillation frequency band. On the other hand, it is desirable to narrow the oscillation frequency band in order to prevent deterioration of phase noise and linearity. Therefore, conventionally, a technique is known that includes a plurality of VCO circuits and a plurality of variable capacitance elements, and switches to a VCO circuit or a variable capacitance element corresponding to a set oscillation frequency.

JP 2009-10599 A JP 2003-110424 A US Pat. No. 7,268,630

  However, when switching a VCO circuit, a variable capacitance element, or the like, complicated control for switching may be required. This is a problem because the circuit scale of the switching control circuit is increased, and the chip size of the semiconductor device may increase.

  The present invention has been made to solve at least one of the problems of the background art, and proposes to provide a PLL circuit having a wide oscillation frequency band and a method for controlling the PLL circuit.

The phase-locked loop circuit according to the present disclosure includes a first variable capacitor and a plurality of second variable capacitors having a variable range smaller than a variable range of the capacitance value of the first variable capacitor, and a plurality of second variable capacitors. variable range of the variable capacitance are respectively set to different ranges to cover a variable range of the first variable capacitance, a voltage controlled oscillator for generating an output signal having an oscillation frequency corresponding to the control voltage input Prepare. Further, a phase comparison unit that generates a control voltage based on a phase comparison result between the input output signal and the reference frequency signal is provided. In addition, based on the phase comparison result, it is detected whether or not the oscillation frequency of the output signal is locked to a predetermined set oscillation frequency, and in the period when the oscillation frequency of the output signal is not locked to the set oscillation frequency. A lock detection unit is provided that outputs a first level lock detection signal and outputs a second level lock detection signal during a period in which the oscillation frequency of the output signal is locked to the set oscillation frequency . Further, it is determined whether or not to switch the plurality of second variable capacitors according to the input control voltage, and it is determined which of the plurality of second variable capacitors is to be selected, and the plurality of second variable capacitors is selected . A selection unit that outputs a first selection signal for informing which of the variable capacitors is to be selected. Further, when the lock detection signal and the first selection signal are input, the first variable capacitor is selected in the coarse adjustment stage of the output signal, and the output signal is finely detected when the lock of the output signal is detected in the coarse adjustment stage. A selector unit is provided for selecting the second variable capacitor selected by the selection unit when the adjustment step is entered and the fine adjustment step is entered when the fine adjustment step is entered . Further, the selector unit notifies that the lock detection is detected in the coarse adjustment stage, divides the input lock detection signal and outputs a divided signal, a first selection signal, and a divided signal. bets are input, the first selection signal latched in response to a transition from the first level of the frequency division signal to the second level, Ru and a latch circuit for outputting a first selection signal latched to the voltage controlled oscillator .

  According to the PLL circuit of the present disclosure, it is possible to provide a PLL circuit capable of suppressing a chip size increase and having a wide oscillation frequency band. Furthermore, when re-selecting a variable capacitor that accompanies a change in the oscillation frequency band, if the changed oscillation frequency can be output using the same variable capacitor as the currently selected variable capacitor, switching of the variable capacitor is suppressed. Thus, it is possible to prevent a delay in operation time due to adjustment.

1 is a circuit diagram of an embodiment in a PLL circuit 1. FIG. FIG. 3 is a circuit diagram of an embodiment in the VCO block 3. It is a circuit diagram of one Example in selector SL1. It is a circuit diagram of one Example in buffer BUF1. It is a truth table of one Example in buffer BUF1. It is the characteristic view (the 1) of one Example in a varactor. It is the characteristic view (the 2) of one Example in a varactor. 4 is a decoding example of an embodiment in the decoder unit 41. FIG. FIG. 3 is a flowchart (No. 1) of an embodiment in the PLL circuit 1; FIG. 3 is a flowchart (part 2) of an embodiment in the PLL circuit 1; 3 is a timing chart (1) showing an operation of the PLL circuit 1; 3 is a timing chart (2) showing an operation of the PLL circuit 1; 3 is a timing chart (3) showing the operation of the PLL circuit 1; It is a truth table of one Example in flip-flop FF1a and latch FF1b.

  An embodiment according to the PLL circuit 1 of the present disclosure will be described with reference to FIGS. FIG. 1 shows a circuit diagram of a PLL circuit 1 according to the present embodiment. The PLL circuit 1 includes a PLL block 2 and a VCO block 3. The PLL block 2 includes a reference counter 21, a main counter 22, a phase comparator 23, a lock detector 24, a charge pump 25, and a low pass filter 26. A clock signal CKS, a data signal DATA, and a reset signal LE are input to the PLL circuit 1. The PLL circuit 1 is a 3wire-PLL, and various settings such as setting of the set frequency fS are performed by three signals of the clock signal CKS, the data signal DATA, and the reset signal LE. The reference counter 21 receives the input clock signal CLKR and outputs the divided input clock signal CLKN. The main counter 22 receives the output clock signal CLKO and outputs the divided internal clock signal CLKM. The phase comparator 23 receives the divided input clock signal CLKN and the divided internal clock signal CLKM. The phase difference signals UP and DN output from the phase comparator 23 are input to the charge pump 25, and the phase difference current IP is output from the charge pump 25. The phase difference current IP is input to the low-pass filter 26, and the control voltage VT is output from the low-pass filter 26 and input to the VCO block 3. The coincidence signal SD output from the phase comparator 23 is input to the lock detector 24. A lock detection signal LD is output from the lock detector 24 and input to the VCO block 3.

  The VCO block 3 includes a VT voltage detection unit 31, a selector unit 32, a switch unit 33, and a VCO (voltage controlled oscillator) 34. The control voltage VT is input to the VT voltage detection unit 31, and selection signals V1 to V3 are output. The selector unit 32 receives selection signals V1 to V3, a lock detection signal LD, and a reset signal LE, and outputs varactor switching signals VC0 to VC3. Varactor switching signals VC0 to VC3 and a control voltage VT are input to the switch unit 33. The control voltage VT output from the switch unit 33 is input to the VCO 34, and the output clock signal CLKO is output from the VCO 34.

  FIG. 2 shows a detailed circuit diagram of the VCO block 3. The VT voltage detection unit 31 includes inverters INV1 and INV2, buffers BUF1 and BUF2, a decoder unit 41, and a voltage change detection unit 51. A control voltage VT is input to the inverter INV1, and a signal OUT1 is output. A control voltage VT is input to the inverter INV2, and a signal OUT2 is output. The logical threshold voltage of the inverter INV1 is adjusted to a value (1 (V)) that matches a threshold voltage Vth1 described later. The signal OUT1 of the inverter INV1 is at a high level when the control voltage VT is smaller than 1 (V), and is at a low level when the control voltage VT is larger than 1 (V). Further, the logical threshold voltage of the inverter INV2 is adjusted to a value (2 (V)) that matches a threshold voltage Vth2 described later. The signal OUT2 of the inverter INV2 is at a high level when the control voltage VT is smaller than 2 (V), and is at a low level when the control voltage VT is larger than 2 (V). The buffer BUF1 receives a signal OUT1 or a signal CNT_OUT described later, and outputs a signal OUT21. The buffer BUF2 receives a signal OUT2 or a signal CNT_OUT described later, and outputs a signal OUT22.

  FIG. 4 shows a circuit diagram of the buffer BUF1. The signal OUT1 is input to the source of the P-channel field effect transistor P21 and the source of the N-channel field effect transistor N21. A signal CNT_OUT is input to the gate of the P-channel field effect transistor P21 through the inverter INV21. A signal CNT_OUT is input to the gate of the N-channel field effect transistor N21. The drain of the P-channel field effect transistor P21 and the drain of the N-channel field effect transistor N21 are connected and output to the outside of the buffer BUF1 as the signal OUT21 via the inverters INV22 and INV24. The drain of the P-channel field effect transistor P21 and the drain of the N-channel field effect transistor N21 are connected to the source of the P-channel field effect transistor P22 and the source of the N-channel field effect transistor N22 via inverters INV22 and INV23. Connected. A signal CNT_OUT is input to the gate of the P-channel field effect transistor P22. A signal CNT_OUT is input to the gate of the N-channel field effect transistor N22 via the inverter INV21. The drain of the P-channel field effect transistor P22 and the drain of the N-channel field effect transistor N22 are connected, and are connected to the drain of the P-channel field effect transistor P21 and the drain of the N-channel field effect transistor N21.

  FIG. 5 shows a truth table representing the operation of the buffer BUF1. As long as the signal CNT_OUT is at a low level, that is, 0, the output OUT21 holds the previous output. When the signal CNT_OUT is high level, that is, 1, when the input signal OUT1 is low level, that is, 0, the output OUT21 becomes low level, that is, 0. Further, when the signal CNT_OUT is at a high level, that is, 1, when the input signal OUT1 is at a high level, that is, 1, the output OUT21 is at a high level, that is, 1. The circuit configuration of the buffer BUF2 is the same as that of the buffer BUF1, and the input signal OUT1 of the buffer BUF1 is replaced with OUT2, and the output signal OUT21 is replaced with OUT22.

  The decoder unit 41 includes inverters INV3 to INV5 and NAND gates ND1 to ND3. The signal OUT21 is input to the NAND gate ND1 through the inverter INV4, the signal OUT22 is input through the inverter INV5, and the selection signal V1 is output. The NAND gate ND2 receives the signal OUT21 through the inverter INV3, and also receives the signal OUT22 and outputs the selection signal V2. The NAND gate ND3 receives the signals OUT21 and OUT22 and outputs the selection signal V3. The decoder unit 41 decodes the signals OUT21 and OUT22, and generates selection signals V1 to V3.

  FIG. 8 shows an example of decoding by the decoder unit 41. When the control voltage VT is in the range of 0 (V) to 1 (V), the selection signals V1 and V2 are high level and the selection signal V3 is low level. In addition, when the control voltage VT is in the range of 1 (V) to 2 (V), the selection signals V1 and V3 are at a high level and the selection signal V2 is at a low level. In addition, when the control voltage VT is in the range of 2 (V) to 3 (V), the selection signals V2 and V3 are at a high level and the selection signal V1 is at a low level.

  The voltage change detection unit 51 includes inverters INV51 to INV55 and NAND gates ND51 to ND53. The control voltage VT is input to the NAND gate ND51 as the signal V05 via the inverters INV51 and INV52, and the control voltage VT is input as the signal V25 via the inverter INV53. The logic threshold voltage of the inverter INV51 is adjusted to a value (0.5 (V)) smaller than a threshold voltage Vth1 described later. Further, the logical threshold voltage of the inverter INV53 is adjusted to a value (2.5 (V)) larger than a threshold voltage Vth2 described later. The signal V05 is a signal that is at a low level when the control voltage VT is smaller than 0.5V, and is at a high level when the control voltage VT is 0.5V or higher. The signal V25 is a signal that is low when the control voltage VT is greater than 2.5V, and is high when the control voltage VT is 2.5V or less. The output signal VLH of the NAND gate ND51 becomes a low level when the control voltage VT is 0.5V or more and 2.5V or less, and becomes a high level when the control voltage VT is less than 0.5V or more than 2.5V. . The signal VLH is input to a latch circuit 52 and selectors SL0 to SL3 described later.

  The inverters INV54 and INV55 and the NAND gates ND52 and ND53 included in the voltage change detection unit 51 operate as a latch circuit 52. The NAND gate ND52 receives the lock detection signal LD via the inverter INV54 and the output signal of the NAND gate ND53. The NAND gate ND53 receives the signal VLH via the INV 55 and the output signal of the NAND gate ND52. An output signal CNT_OUT of the NAND gate ND53 is input to the buffers BUF1 and BUF2.

  The selector unit 32 includes selectors SL0 to SL3. A signal VLH, a lock detection signal LD, and a reset signal LE are input to each of the selectors SL0 to SL3. The selector SL0 is supplied with the ground voltage VSS, the selector SL1 is supplied with the selection signal V1, the selector SL2 is supplied with the selection signal V2, and the selector SL3 is supplied with the selection signal V3. The varactor switching signal VC0B output from the selector SL0 is inverted by the inverter INV6 and output as the varactor switching signal VC0. The varactor switching signal VC0 output from the inverter INV6 is input to the control terminal of the switch SW0. Further, varactor switching signals VC1 to VC3 are output from the selectors SL1 to SL3 and input to the control terminals of the switches SW1 to SW3.

  The switch unit 33 includes switches SW0 to SW3. A control voltage VT is commonly input to each of the input terminals of the switches SW0 to SW3. The output terminals of the switches SW0 to SW3 are connected to the input terminals of the varactors VA0 to VA3 of the VCO 34, respectively. The switches SW0 to SW3 are switches that are turned on when the varactor switching signals VC0 to VC3 are at a high level and are turned off when the varactor switching signals VC0 to VC3 are at a low level.

  The VCO 34 includes inductors L1 and L2, varactors VA0 to VA3, transistors Tr1 and Tr2, and a constant current source CG1. One ends of the inductors L1 and L2 are commonly connected to the power supply voltage VCC. Varactors VA0 to VA3 are connected to the other ends of the inductors L1 and L2, respectively. The inductors L1 and L2 and the varactors VA0 to VA3 constitute a resonance circuit 35.

  The collector terminals of the transistors Tr1 and Tr2 are connected to the resonance circuit 35. The base terminal of the transistor Tr1 is connected to the collector terminal of the transistor Tr2, and the base terminal of the transistor Tr2 is connected to the collector terminal of the transistor Tr1. The emitter terminals of the transistors Tr1 and Tr2 are connected to the ground voltage VSS via the constant current source CG1. The oscillation signals generated by the resonance circuit are amplified by the transistors Tr1 and Tr2. An amplified oscillation signal is output as an output clock signal CLKO from the collector terminal of the transistor Tr2.

  The circuit configuration of the selector SL1 provided in the selector unit 32 will be described with reference to FIG. The selector SL1 includes a flip-flop with reset function (hereinafter flip-flop) FF1a, a latch with reset function (hereinafter latch) FF1b, inverters INV11 and INV12, a NAND gate ND11, and a delay unit DP. The inverter INV11 receives the lock detection signal LD and outputs the inverted lock detection signal LDX. The reset signal LE is input to the reset terminal L of the flip-flop FF1a, the lock detection signal LD is input to the input terminal CK, and the inverted lock detection signal LDX is input to the inverting input terminal XCK. A signal LO is output from the output terminal Q of the flip-flop FF1a, and an inverted signal LOX that is an inverted signal of the signal LO is output from the inverted output terminal QX. A truth table of the flip-flop FF1a is shown in FIG.

  The delay unit DP includes an even number of stages of inverters, and is a circuit that adds a delay time to an input signal and outputs the input signal. A lock detection signal LD is input to the delay unit DP, and a delay lock detection signal LDD with a delay time is output. The delay unit DP is a circuit for preventing generation of spike-like spike noise. The NAND gate ND11 receives the delay lock detection signal LDD and the signal LOX, and outputs a signal OUT. The signal OUT is inverted by the inverter INV12 and output as the inverted signal OUTX.

  The signal VLH is input to the reset terminal L of the latch FF1b, the selection signal V1 is input to the input terminal D, and the inverted signal OUTX is input to the clock terminal G. A varactor switching signal VC1 is output from the output terminal Q of the latch FF1b. The latch FF1b latches the selection signal V1 in accordance with the rising edge of the inverted signal OUTX, inverts it, and outputs it as the varactor switching signal VC1. A truth table of the latch FF1b is shown in FIG. Note that the configurations of the selectors SL2 and SL3 are the same as the configuration of the selector SL1, and thus detailed description thereof is omitted here.

  The circuit configuration of the selector SL0 will be described. The selector SL0 includes a latch with reset function (hereinafter referred to as a latch) FF0b instead of the latch FF1b in the selector SL1 of FIG. The reset signal VLH is input to the reset terminal L of the latch FF0b, the ground voltage VSS is input to the input terminal D, and the inverted signal OUTX is input to the clock terminal G. A varactor switching signal VC0B is output from the output terminal Q of the latch FF0b. The latch FF0b latches the ground voltage VSS in accordance with the rising edge of the inverted signal OUTX, and performs an operation of outputting a low-level varactor switching signal VC0B. Since the other configuration of the selector SL0 is the same as that of the selector SL1, detailed description thereof is omitted here.

  The varactors VA0 to VA3 will be described with reference to FIG. The varactors VA0 to VA3 are variable capacitance elements whose capacitance values change according to changes in the control voltage VT. The varactor VA0 is a coarse adjustment varactor, and the varactors VA1 to VA3 are fine adjustment varactors. FIG. 6A shows the relationship between the control voltage VT and the capacitance value in the varactor VA0. The varactor VA0 has a variable capacitance range CV0. The capacity variable range CV0 of the varactor VA0 has a one-to-one correspondence with the voltage range (0 to 3 (V)) of the control voltage VT. The capacity variable range CV0 of the varactor VA0 is divided into a plurality of divided capacity variable ranges CV0a to CV0c. Here, the value of the control voltage VT that defines the boundary between the divided capacitance variable ranges CV0c and CV0b is defined as a threshold voltage Vth1. In addition, the value of the control voltage VT that defines the boundary between the divided capacitance variable ranges CV0a and CV0b is defined as a threshold voltage Vth2. In the example of FIG. 4 of the present embodiment, a case where the threshold voltage Vth1 = 1 (V) and the threshold voltage Vth2 = 2 (V) will be described.

  FIG. 6B shows the relationship between the control voltage VT and the capacitance value in the varactors VA1 to VA3. Each of the varactors VA1 to VA3 has capacitance variable ranges CV1 to CV3. The variable ranges of the capacitance variable ranges CV1 to CV3 are smaller than the capacitance variable range CV0 of the capacitance value of the varactor VA0. Further, the capacitance variable ranges CV1 to CV3 are set to different ranges so as to cover the capacitance variable range CV0 of the varactor VA0. Then, the variable capacitance ranges CV1 to CV3 of the varactors VA1 to VA3 are set so as to correspond to the divided capacitance variable ranges CV0a to CV0c of the varactor VA0. In this embodiment, when the control voltage VT is 0.5 V or less and 2.5 V or more, the varactor is switched. The variable capacity ranges CV1 to CV3 of the varactors VA1 to VA3 are defined as variable capacity ranges in the region where the control voltage VT input to the varactor is 0.5V to 2.5V.

  The relationship between the control voltage VT and the oscillation frequency fVCO in the varactors VA0 to VA3 will be described with reference to FIG. FIG. 7A shows the relationship between the control voltage VT and the oscillation frequency fVCO in the varactor VA0. The varactor VA0 has a frequency variable range fV0. The frequency variable range fV0 is divided into a plurality of divided frequency variable ranges fV0a to fV0c. FIG. 7B shows the relationship between the control voltage VT and the oscillation frequency fVCO in the varactors VA1 to VA3. Each of the varactors VA1 to VA3 has a frequency variable range fV1 to fV3. The frequency variable ranges fV1 to fV3 of the varactors VA1 to VA3 are set so as to correspond to the divided frequency variable ranges fV0a to fV0c of the varactor VA0.

The operation of the VCO 34 will be described. The oscillation frequency fVCO of the resonance circuit 35 is given by the following equation by the inductance L of the inductors L1 and L2 and the capacitance C of any of the varactors VA0 to VA3.
fVCO = 1 / (2π × (L × C) ^1/2 ) (1) The capacity of the varactors VA0 to VA3 can be changed by the control voltage VT, and the oscillation frequency fVCO of the output clock signal CLKO. Can be controlled.

  The operation of the PLL circuit 1 according to the present invention will be described with reference to the flowcharts of FIGS. 9 and 10 and the timing charts of FIGS.

  In S1, the power supply voltage VCC rises and the circuit operation of the PLL circuit 1 is started (FIG. 11, time t0). Since the control voltage VT is not input, the signal V05 becomes low level and the signal VLH becomes high level (arrow Y1 in FIG. 11). The selectors SL1 to SL3 of the selector unit 32 are reset to a low level by the rise of the signal VLH. Further, since the varactor switching signal VC0B output from the selector SL0 is set to the low level, the varactor switching signal VC0 output via the inverter INV6 is set to the high level, and the switch SW0 is turned on (arrow Y3). . Therefore, initialization is performed from the setting for selecting one of the varactors VA1 to VA3 to the setting for selecting the varactor VA0 according to the rising edge of the signal VLH.

  In S3, the set frequency fS is set. The value of the set frequency fS can be set to an arbitrary value by the user or the like. When the setting of the setting frequency fS is completed, a high level reset signal LE is input to the PLL circuit 1 (FIG. 11, time t1). The set frequency fS set here is a voltage range in which the control voltage VT of the VCO block 3 is 0.5V to 2.5V when the varactor VA0 selected in the coarse adjustment stage (S5 to S13) described later is used. Shall enter.

  In S5, the PLL circuit 1 selects the varactor VA0 and operates as a coarse adjustment stage (S5 to S13) of the output clock signal CLKO. Since the control voltage VT operates in a voltage range of 0.5 V to 2.5 V, the signal V05 in the voltage change detection unit 51 is at a high level and the signal V25 is at a low level. As a result, the output signal VLH becomes low level.

  In S7, PLL tuning is performed. The operation of PLL tuning will be described. The reference counter 21 divides the input clock signal CLKR by N and outputs a divided input clock signal CLKN. The main counter 22 divides the output clock signal CLKO by M and outputs a divided internal clock signal CLKM. The phase comparator 23 compares the phase of the divided input clock signal CLKN and the divided internal clock signal CLKM, and outputs phase difference signals UP and DN having a pulse width corresponding to the phase comparison result.

  The charge pump 25 supplies a positive or negative phase difference current IP to the low-pass filter 26 in accordance with the phase difference signals UP and DN. That is, when the phase difference signal UP is input, a positive current is supplied, and when the phase difference signal DN is input, a negative current is supplied. The low-pass filter 26 integrates the phase difference current IP output from the charge pump 25 and outputs a control voltage VT.

  The VCO 34 generates an output clock signal CLKO having a frequency corresponding to the control voltage VT output from the low pass filter 26. Then, feedback control is performed so that the phase difference between the divided input clock signal CLKN and the divided internal clock signal CLKM is constant. Thus, PLL tuning is performed so that the oscillation frequency fVCO of the output clock signal CLKO matches the set frequency fS.

  In S9, in the coarse adjustment stage using the varactor VA0, the oscillation frequency fVCO is locked to the set frequency fS (FIG. 11, time t2). The value of the control voltage VT at this time is defined as a lock control voltage VTL1. In the explanation example of the present embodiment, a case where the lock control voltage VTL1 is 1.2 (V) will be described.

  In S <b> 11, the selection signals V <b> 1 to V <b> 3 are set by the VT voltage detection unit 31. The VT voltage detection unit 31 is a circuit that determines which one of the varactors VA1 to VA3 is selected according to the value of the input control voltage VT. Specifically, by using the inverters INV1 and INV2, the divided variable range corresponding to the value of the control voltage VT is selected from the divided capacitor variable ranges CV0a to CV0c. Then, by using the decoder unit 41, selection signals V1 to V3 for selecting a varactor corresponding to the selected division variable range are generated.

  In the example of this embodiment, since the case where the lock control voltage VTL1 is 1.2 (V) is described, the signal OUT1 output from the inverter INV1 and the signal OUT21 output from the buffer BUF1 are set to the low level. . Further, the signal OUT2 output from the inverter INV2 and the signal OUT22 output from the buffer BUF2 are set to the high level. Therefore, as shown in the decoding example of FIG. 8, the selection signals V1 and V3 are set to the high level, and the selection signal V2 is set to the low level. As a result, as shown in FIG. 6A, the divided capacitance variable range CV0b is selected as the divided variable range corresponding to the lock control voltage VTL1. Then, the varactor VA2 is selected as the varactor corresponding to the divided variable range CV0b.

  In S13, the lock detector 24 outputs a high level lock detection signal LD in response to the lock state being continued for a predetermined time LT. In the example of the present embodiment, lock detection is performed at time t3 in FIG. 11, and the lock detection signal LD transitions to a high level. Then, the process proceeds from the coarse adjustment stage to the fine adjustment stage (S15 to S29).

  In S15, the selector unit 32 generates varactor switching signals VC0 to VC3. The varactor switching signals VC1 to VC3 are generated by latching the selection signals V1 to V3 using the lock detection signal LD. The varactor switching signal VC0 is generated by latching the ground voltage VSS using the lock detection signal LD.

  A generation operation of the varactor switching signals VC1 to VC3 will be described. At time t3 in FIG. 11, the inversion signal LOX output from the flip-flop FF1a (FIG. 3) transitions to a high level in response to the lock detection signal LD transitioning to a high level (arrow Y5). Since the NAND gate ND11 receives the high level inversion signal LOX and the high level delay lock detection signal LDD, the signal OUT changes to low level and the inversion signal OUTX changes to high level (arrow Y7). In the latch FF1b of the selector SL1, in response to the rising edge of the inverted signal OUTX, the high level selection signal V1 is inverted and latched, and the varactor switching signal VC1 is maintained at the low level (arrow Y9). Similarly, in selector SL2, selection signal V2 is inverted and latched, and varactor switching signal VC2 is set to the high level (arrow Y9). Similarly, in selector SL3, selection signal V3 is inverted and latched, and varactor switching signal VC3 is maintained at the low level (arrow Y9). As a result, the selection signals V1 to V3 at the time of transition to the fine adjustment stage (time t3) are inverted and latched as varactor switching signals VC1 to VC3.

  In the latch FF0b of the selector SL0, the ground voltage VSS is inverted and latched in response to the rising edge of the inverted signal OUTX, so that the varactor switching signal VC0B transitions to a high level and the varactor switching signal VC0 is low. Transition to level (arrow Y11). Thereby, at the time of transition to the fine adjustment stage (time t3), an operation of switching to the varactor VA2 selected by the VT voltage detector 31 is performed.

  In S17 (FIG. 10), the varactor to be used is switched by switching the switches SW0 to SW3. In the example of this embodiment, at time t4 (FIG. 11), the switch SW2 is turned on and the switch SW0 is turned off, so that the varactor used is switched from the varactor VA0 to VA2.

  At this time, the varactor VA0 is switched to VA2 while the control voltage VT is at the lock control voltage VTL1. Then, since the oscillation frequency fVCO at the lock control voltage VTL1 after switching becomes a different value deviating from the set frequency fS, the lock is released (arrow Y20 in FIG. 7). Therefore, at time t4 (FIG. 11), the lock detection signal LD changes to the low level.

  In S19, PLL retuning is started in response to the unlocking. In retuning, the switched varactor VA2 is used. During the retuning, the selection signals V1 to V3 are reset in the VT voltage detection unit 31 (S20). In the example of the present embodiment, as shown in FIG. 7B, the lock control voltage VTL1 is changed to VTL2 by retuning (FIG. 7B, arrow Y21). Even in such a case, since the lock detection signal LD is at the high level and the signal CNT_OUT is at the low level, the output signals OUT21 and OUT22 of the buffers BUF1 and BUF2 are fixed. Thus, even when the value of the control voltage VT changes and crosses the threshold voltage during retuning, the values of the selection signals V1 to V3 do not change before and after retuning.

  In S21, the oscillation frequency fVCO is re-locked to the set frequency fS using the varactor VA2 after switching. The value of the control voltage VT at this time is defined as a lock control voltage VTL2 (FIG. 7B).

  In S25, the lock detection signal LD is output again from the lock detector 24. In the example of the present embodiment, the lock detection signal LD changes to the high level again at time t5 (FIG. 11).

  In S27, the selection of the varactor VA2 used at the time of retuning is maintained even after the relocking. In S29, the varactor VA2 used for retuning continues to lock the oscillation frequency fVCO to the set frequency fS (S29).

  In S31, it is determined whether or not a new PLL frequency setting has been performed in the PLL circuit 1. If it is determined that a new PLL frequency setting has not been performed (S31: NO), the process returns to S27 and the locked state is maintained. On the other hand, when it is determined that a new PLL frequency setting has been input (S31: YES), it is determined whether or not varactor switching is necessary (S33).

FIG. 12 shows a timing chart when switching of the varactor is unnecessary in S33 (S33: NO). When the control voltage VT corresponding to the newly set frequency is 0.5 V or more and 2.5 V or less, the varactor currently selected from the varactors VA1 to VA3 can be used as it is as the varactor for the newly set frequency. .
At time t21, the reset signal LE is input and the lock detection signal LD becomes low level. When the control voltage VT is not less than 0.5V and not more than 2.5V, the signal VLH is at a low level (arrow Y23 in FIG. 12). When the signal VLH is at a low level, the signal CNT_OUT is also at a low level (FIG. 12, arrow Y25), and the signals OUT21 and OUT22 do not change (FIG. 12, arrow Y27). Therefore, the outputs VC1 to VC3 of the selectors SL1 to SL3 do not change, the varactor is not changed, and the lock detection signal LD becomes high level at time t22 after a predetermined time LT has elapsed from time t21. Then, the selected varactor is continuously selected and the setting is maintained (S27 in FIG. 10).

FIG. 13 shows a timing chart when varactor switching is required in S33 (S33: YES). At time t31, when the reset signal LE is input and the control voltage VT corresponding to the lock detection signal new set frequency is less than 0.5V or above 2.5V, the signal VLH becomes high level (FIG. 13, arrow Y31). ), The signal CNT_OUT becomes high level (FIG. 13, arrow Y33). When the signal CNT_OUT becomes high level, the signals OUT21 and OUT22 change according to the control signal VT (FIG. 13, arrow Y35). Further, when the signal VLH becomes high level, the selectors SL0 to SL3 are reset, VC0 becomes high level, and VC1 to VC3 become low level (arrow Y37 in FIG. 13).
When only VC0 becomes high level, the varactor VA2 is switched to the varactor VA0, and a new PLL tuning operation is started (S5 in FIG. 9). Since the subsequent flow is the same as the flow described above, detailed description thereof is omitted here.

  The effect of the PLL circuit 1 according to the present embodiment will be described. In the PLL circuit 1, the VCO 34 includes a varactor VA0 for coarse adjustment and a plurality of varactors VA1 to VA3 for fine adjustment. When PLL tuning is started, the varactor VA0 is selected, and the coarse adjustment stage is set. In the coarse adjustment stage, the oscillation frequency band is widened, but the conversion sensitivity (Kv) is increased, the phase noise characteristic is deteriorated, and the linearity of the change of the oscillation frequency fVCO with respect to the control voltage VT is deteriorated. Then, one of the varactors VA1 to VA3 is selected in response to the initial lock detection, and the process proceeds to the fine adjustment stage. In the fine adjustment stage, the oscillation frequency band is narrowed, but the phase noise characteristics and the linearity of changes in the oscillation frequency fVCO are improved. As a result, it is possible to provide the PLL circuit 1 that oscillates in a wide frequency band and has low phase noise characteristics and high linearity. Therefore, it is possible to prevent problems such as a narrow lock range in the PLL circuit 1 and insufficient margin of the oscillation frequency range with respect to manufacturing variations. Furthermore, when re-selecting the fine-adjustment varactors VA1 to VA3 associated with the change of the oscillation frequency, if the changed oscillation frequency can be output using the same variable capacitance as the currently selected varactors VA1 to VA3, Suppress varactor switching. By suppressing the switching of the fine adjustment varactor, it is possible to prevent a delay in the operation time due to the adjustment.

  In the selector SL1 of the PLL circuit 1 according to the present embodiment, the flip-flop FF1a divides the input lock detection signal and outputs the inverted signal LOX. Further, the NAND gate ND11 and the inverter INV12 generate the inverted signal OUTX from the inverted signal LOX. Then, in response to the rising edge of the inverted signal OUTX, the selection signal V1 is latched in the latch FF1b. Similarly, selectors SL2 and SL3 latch selection signals V2 and V3. Thus, by controlling the latches of the selection signals V1 to V3 using a signal obtained by dividing the lock detection signal LD, the selection operation of the varactor selected at the time of detecting the initial lock can be held even after the relock detection. it can. Therefore, varactor switching control can be performed so that varactor switching is not performed after relock detection. Further, since the signal obtained by dividing the lock detection signal LD is used for the varactor switching control, the scale of the logic circuit necessary for signal generation can be reduced, and an increase in chip area can be suppressed.

  In the PLL circuit 1 according to the present embodiment, the lock detection signal LD is used for varactor switching control. Since the PLL block 2 and the VCO block 3 are circuits that are used as a set in configuring the PLL loop, the lock detection signal LD is an essential signal. Then, the lock detection signal LD, which is an essential signal, is diverted to varactor switching control, so that a new signal can be made unnecessary. Therefore, the scale of the logic circuit necessary for generating a signal used for varactor switching control can be reduced.

  Conventionally, when performing control for switching a plurality of varactors, there is a case where control for sequentially switching varactors is performed. In this case, the number of switching executions matches the number of varactors at the maximum. However, in the PLL circuit 1 according to the present embodiment, the switching control can be performed in two stages of the coarse adjustment stage and the fine adjustment stage, so that the switching operation can be simplified.

  In the PLL circuit 1 according to the present embodiment, the switches SW0 to SW3 are not connected in series with the inductors L1 and L2, the varactors VA0 to VA3, and the like in the resonance circuit 35. Therefore, it is possible to prevent a situation in which phase noise deterioration occurs due to the on resistance of the switches SW0 to SW3.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.

  Further, in the lock detector 24, the determination condition at the first lock may be made milder than the determination condition at the time of re-lock. This is because the initial lock is a lock for determining the varactor to be used and does not need to be locked accurately. In addition, a lock detector for detecting the initial lock with poor judgment conditions and a lock detector for detecting relock with strict judgment conditions may be provided, and the lock detector to be used may be switched. As a result, the time required for the rough adjustment can be shortened.

  Further, a comparator may be used instead of the inverters INV1 and INV2. In this case, the threshold voltages Vth1 and Vth2 may be used as the reference voltage for the comparator.

  The varactor VA0 is an example of a first variable capacitor, the varactors VA1 to VA3 are examples of a second variable capacitor, the VT voltage detector 31 is an example of a selection unit, and the selection signals V1 to V3 are examples of a first selection signal, The flip-flop FF1a is an example of a notification circuit, and the latch FF1b is an example of a latch circuit.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
A first variable capacitor and a plurality of second variable capacitors having a variable range smaller than a variable range of a capacitance value of the first variable capacitor, wherein the variable range of the plurality of second variable capacitors is the Different ranges are set so as to cover the variable range of the first variable capacitor, and it is possible to select which of the first variable capacitor and the plurality of second variable capacitors is used and input. A voltage-controlled oscillator that generates an output signal having an oscillation frequency according to the control voltage
A phase comparator that generates the control voltage based on a phase comparison result between the input output signal and a reference frequency signal;
A lock detection unit that detects whether or not the oscillation frequency of the output signal is locked to a preset oscillation frequency based on the phase comparison result;
A selection unit that determines whether or not to switch between the plurality of second variable capacitors according to the input control voltage, and determines which of the plurality of second variable capacitors is to be selected;
The output of the lock detection unit and the output of the selection unit are input, the first variable capacitor is selected in the coarse adjustment stage of the output signal, and the lock of the output signal is detected in the coarse adjustment stage And a selector unit that selects the second variable capacitor selected by the selection unit when the fine adjustment step proceeds to the fine adjustment step. A phase locked loop circuit characterized by that.
(Appendix 2)
The selection unit outputs a first selection signal for informing which of the plurality of second variable capacitors is to be selected;
The selector unit is a notification circuit for notifying that the lock detection is detected in the coarse adjustment stage;
The first selection signal and the output of the notification circuit are input, the first selection signal is latched in response to receiving notification from the notification circuit, and the latched first selection signal is sent to the voltage-controlled oscillator. The phase-locked loop circuit according to appendix 1, further comprising: a latch circuit for outputting.
(Appendix 3)
The lock detection unit outputs a first level lock detection signal during a period when the oscillation frequency of the output signal is not locked to the set oscillation frequency, and the oscillation frequency of the output signal becomes the set oscillation frequency. During the locked period, a second level lock detection signal is output,
The notification circuit divides the input lock detection signal and outputs a divided signal,
The phase-locked loop circuit according to appendix 2, wherein the latch circuit latches the first selection signal in response to a transition of the divided signal from the first level to the second level.
(Appendix 4)
The variable range of the first variable capacitor corresponds to the voltage range of the control voltage on a one-to-one basis,
The variable range of the first variable capacitor is divided into a plurality of divided variable ranges;
A variable range of the plurality of second variable capacitors is set so as to correspond to each of the divided variable ranges,
The selection unit detects the divided variable range corresponding to the input control voltage, and selects the second variable capacitor corresponding to the detected divided variable range. The phase-locked loop circuit according to any one of the above.
(Appendix 5)
The phase locked loop circuit according to appendix 1, wherein the selector unit re-shifts from the fine adjustment stage to the coarse adjustment stage in response to changing the value of the set oscillation frequency.
(Appendix 6)
The lock detection unit performs the lock detection by detecting that the oscillation frequency of the output signal matches the set oscillation frequency for a predetermined period,
The phase-locked loop circuit according to any one of appendices 1 to 5, wherein the predetermined period in the coarse adjustment stage is shorter than the predetermined period in the fine adjustment stage.
(Appendix 7)
A first variable capacitor and a plurality of second variable capacitors having a variable range smaller than a variable range of a capacitance value of the first variable capacitor, wherein the variable range of the plurality of second variable capacitors is the A control method for a voltage controlled oscillator that generates an output signal that is set in different ranges so as to cover a variable range of a first variable capacitor and that has an oscillation frequency corresponding to an input control voltage,
Generating the control voltage based on a phase comparison result between the output signal and a reference frequency signal;
Detecting whether the oscillation frequency of the output signal is locked to a preset oscillation frequency based on the phase comparison result; and
Determining whether or not to switch the plurality of second variable capacitors in accordance with the control voltage, and determining which of the plurality of second variable capacitors is to be selected;
The output of the lock detection unit and the output of the selection unit are input, the first variable capacitor is selected in the coarse adjustment stage of the output signal, and the lock of the output signal is detected in the coarse adjustment stage The output signal fine-adjusting step, and in the fine-adjusting step, the step of selecting the second variable capacitor selected by the selection unit when moving to the fine-adjusting step is provided. A method for controlling a phase-locked loop circuit.

DESCRIPTION OF SYMBOLS 1 PLL circuit 24 Lock detector 31 VT voltage detection part VA0 thru | or VA3 Varactor V1 thru | or V3 selection signal SL0 thru | or SL3 Selector FF1a and FF1b Flip-flop

Claims (4)

A first variable capacitor and a plurality of second variable capacitors having a variable range smaller than a variable range of a capacitance value of the first variable capacitor, wherein the variable range of the plurality of second variable capacitors is the A voltage-controlled oscillator configured to generate an output signal having an oscillation frequency corresponding to an input control voltage, each set in a different range so as to cover the variable range of the first variable capacitor;
A phase comparator that generates the control voltage based on a phase comparison result between the output signal and a reference frequency signal;
Based on the phase comparison result, it is detected whether or not the oscillation frequency of the output signal is locked to a predetermined set oscillation frequency, and the oscillation frequency of the output signal is not locked to the set oscillation frequency A lock detection unit that outputs a first level lock detection signal during a period, and outputs a second level lock detection signal during a period when the oscillation frequency of the output signal is locked to the set oscillation frequency ;
In accordance with the control voltage, it is determined whether or not to switch the plurality of second variable capacitors, and it is determined which of the plurality of second variable capacitors is to be selected, and the plurality of second variable capacitors is selected . A selection unit that outputs a first selection signal for informing which of the variable capacitors to select;
When the lock detection signal and the first selection signal are input, the first variable capacitor is selected in the coarse adjustment stage of the output signal, and the lock of the output signal is detected in the coarse adjustment stage And a selector unit for selecting the second variable capacitor selected by the selection unit when the fine adjustment step proceeds to the fine adjustment step .
The selector unit is
A notification circuit that notifies that the lock detection has been detected in the coarse adjustment step, divides the input lock detection signal, and outputs a divided signal;
The first selection signal and the divided signal are input, the first selection signal is latched in response to a transition of the divided signal from the first level to the second level, and the latched first selection is performed. A latch circuit for outputting a signal to the voltage controlled oscillator;
Phase locked loop circuit according to claim Rukoto equipped with. The variable range of the first variable capacitor corresponds to the voltage range of the control voltage on a one-to-one basis,
The variable range of the first variable capacitor is divided into a plurality of divided variable ranges;
A variable range of the plurality of second variable capacitors is set so as to correspond to each of the divided variable ranges,
The selection unit, according to claim 1, wherein the selecting the second variable capacitance for detecting the split variable range corresponding to the control voltage input, corresponding to the divided variable range detected Phase-locked loop circuit. 2. The phase-locked loop circuit according to claim 1, wherein the selector unit re-shifts from the fine adjustment stage to the coarse adjustment stage in response to changing a value of the set oscillation frequency. A first variable capacitor and a plurality of second variable capacitors having a variable range smaller than a variable range of a capacitance value of the first variable capacitor, wherein the variable range of the plurality of second variable capacitors is the A voltage-controlled oscillator control method for generating an output signal having an oscillation frequency corresponding to an input control voltage, each set in a different range so as to cover the variable range of the first variable capacitor,
And generating the control voltage based on the phase comparison result between the output signal and the reference frequency signal,
Based on the phase comparison result, it detects whether the oscillation frequency of the output signal is locked to the set oscillation frequency determined in advance,
In a period in which the oscillation frequency of the output signal is not locked to the set oscillation frequency, a first level lock detection signal is output, and in a period in which the oscillation frequency of the output signal is locked to the set oscillation frequency Outputs a second level lock detection signal,
In response to the control voltage, the plurality of second variable capacitance determines the necessity of switching the decide whether to select any of the plurality of second variable capacitance, the plurality second Outputting a first selection signal for informing which of the variable capacitors to select;
The lock detection signal is inputted said a first selection signal if, for selecting the first variable capacitance in the rough adjustment stage of the output signal, the lock of the output signal in the rough adjustment stage has been detected To the fine adjustment stage of the output signal, and in the fine adjustment stage, the second variable capacitor selected by the first selection signal in the case of moving to the fine adjustment stage is selected ,
Notifying that the lock detection is detected in the coarse adjustment step, dividing the input lock detection signal and outputting a divided signal;
The first selection signal and the frequency-divided signal are input, and the first selection signal is latched and latched in response to a transition of the frequency-divided signal from the first level to the second level. Output a selection signal to the voltage controlled oscillator
The method of the phase-locked loop circuit according to claim and this.

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