[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP5429890B2 - WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD - Google Patents

WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD Download PDF

Info

Publication number
JP5429890B2
JP5429890B2 JP2010541993A JP2010541993A JP5429890B2 JP 5429890 B2 JP5429890 B2 JP 5429890B2 JP 2010541993 A JP2010541993 A JP 2010541993A JP 2010541993 A JP2010541993 A JP 2010541993A JP 5429890 B2 JP5429890 B2 JP 5429890B2
Authority
JP
Japan
Prior art keywords
wiring
metal
horizontal wiring
horizontal
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010541993A
Other languages
Japanese (ja)
Other versions
JPWO2010067548A1 (en
Inventor
政道 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Institute of Technology NUC
Original Assignee
Kyushu Institute of Technology NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Institute of Technology NUC filed Critical Kyushu Institute of Technology NUC
Priority to JP2010541993A priority Critical patent/JP5429890B2/en
Publication of JPWO2010067548A1 publication Critical patent/JPWO2010067548A1/en
Application granted granted Critical
Publication of JP5429890B2 publication Critical patent/JP5429890B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、半導体チップを含む回路素子を配置し、該回路素子から垂直配線を介して接続される外部電極を有する電子デバイスパッケージに組み込んで用いるための配線用電子部品及びその製造方法に関する。   The present invention relates to an electronic component for wiring to be used by incorporating a circuit element including a semiconductor chip into an electronic device package having an external electrode connected to the circuit element via a vertical wiring, and a method for manufacturing the same.

外部接続用電極をおもて面に配置した電子デバイスパッケージ構造のように、LSIチップ搭載基板から離れて他方に電極を取り出す場合や、或いはウエハレベルチップサイズパッケージのようにLSIチップの能動面から離れて他方に電極を取り出す場合は、基板と離れて電極を取り出すための少なくとも垂直配線、あるいは再配線のための水平配線も含めた構造が必要である。一般的に電子デバイスパッケージ構造の垂直配線は基板に予め作りこんだ構造や樹脂封止後に樹脂を開口してメッキで埋める方法、さらにはシリコン基板を貫通させ、基板の両側に電極を取り出す構造が採られている（特許文献１参照）。   When an electrode is taken away from the LSI chip mounting board, such as an electronic device package structure in which external connection electrodes are arranged on the front surface, or from the active surface of the LSI chip, such as a wafer level chip size package When the electrode is taken out to the other side, a structure including at least vertical wiring for taking out the electrode away from the substrate or horizontal wiring for rewiring is required. In general, the vertical wiring of the electronic device package structure has a structure that is pre-fabricated on the substrate, a method in which a resin is opened after resin sealing and filled with plating, and a structure that penetrates a silicon substrate and takes out electrodes on both sides of the substrate. (See Patent Document 1).

現在の貫通電極形成は低抵抗金属を充填するためには低温処理が要求され、半導体プロセスへの適用は難しく、一方、貫通孔の絶縁方法は、高温処理が必要なため半導体の実装プロセスへの適用は困難である。このように、半導体基板への貫通電極の形成とその絶縁方法にはまだ課題が残されていて、貫通電極を必要とせずに配線することが望まれる。   Current through-electrode formation requires low-temperature processing to fill low-resistance metals, making it difficult to apply to semiconductor processes. On the other hand, through-hole insulation requires high-temperature processing, so it can be applied to semiconductor mounting processes. Application is difficult. As described above, there is still a problem in the formation of the through electrode on the semiconductor substrate and the insulation method thereof, and it is desired to perform wiring without requiring the through electrode.

このような問題を解決するために、特許文献２は、部品化した配線用電子部品を半導体基板上の所定位置に接続することにより、貫通電極を必要とせずに配線する技術を開示する。図３６及び図３７は、特許文献２に開示の電子デバイスパッケージを説明する図であり、図３６は、その製造途中の断面図であり、図３７は、完成した状態で示す断面図である。図３６に示すように、導電性材料の支持板に電鋳法により水平配線部（再配線）及び垂直配線部を成長させて、支持板と一体に連結した配線用電子部品を形成する。そして、この配線用電子部品を、半導体基板（多層有機基板）おもて面に形成した配線層上の所定位置に接続する。この後、図３７に示すように、回路素子（LSIチップ）を覆う樹脂を充填して樹脂封止した後、支持板を剥がすことにより電気的には個々の水平配線部及び垂直配線部に分離して構成する。この水平配線部により、垂直配線部先端とは異なる位置に外部接続用電極を設けることができる。これによって、簡潔に、しかもコスト的にも安く外部接続用電極をおもて面に配置した電子デバイスパッケージを製造することが可能となる。   In order to solve such a problem, Patent Document 2 discloses a technique of wiring without connecting a through electrode by connecting a wiring electronic component as a component to a predetermined position on a semiconductor substrate. 36 and 37 are diagrams for explaining the electronic device package disclosed in Patent Document 2, FIG. 36 is a cross-sectional view in the middle of its manufacture, and FIG. 37 is a cross-sectional view in a completed state. As shown in FIG. 36, a horizontal wiring portion (rewiring) and a vertical wiring portion are grown on a support plate made of a conductive material by electroforming, thereby forming an electronic component for wiring integrally connected to the support plate. The wiring electronic component is connected to a predetermined position on the wiring layer formed on the front surface of the semiconductor substrate (multilayer organic substrate). Thereafter, as shown in FIG. 37, the resin covering the circuit element (LSI chip) is filled and sealed with resin, and then electrically separated into individual horizontal wiring portions and vertical wiring portions by peeling off the support plate. And configure. With this horizontal wiring portion, an external connection electrode can be provided at a position different from the tip of the vertical wiring portion. This makes it possible to manufacture an electronic device package in which the external connection electrodes are arranged on the front surface in a simple and inexpensive manner.

このように、電子デバイスパッケージ構造形成のための垂直配線や水平配線などの追加工程を部品として集約させ、工程を簡素化し部品は専門メーカに任せることでコスト低減を実現することができる。この部品化によりウエハレベルチップサイズパッケージなどは前工程に近い設備が必要な工程をオフラインで部品に集約することができ、これによって、後工程メーカも大きな投資の必要なく参入できることになる。   In this way, additional processes such as vertical wiring and horizontal wiring for forming the electronic device package structure can be integrated as parts, the process can be simplified, and the parts can be left to a specialized manufacturer to achieve cost reduction. This componentization allows wafer level chip size packages and the like to consolidate processes that require equipment close to the previous process into parts offline, and this allows post-process manufacturers to enter without a large investment.

しかし、例示の配線用電子部品を製造するための電鋳法は非常に優れた方法ではあるものの、電鋳法自体にはノウハウが多く、現状では製造業者が限られているという問題がある。また、電子デバイスパッケージおもて面の水平配線部を保護するための保護膜を設ける場合、別途の工程として作成することが必要になる。   However, although the electroforming method for manufacturing the exemplified electronic component for wiring is a very excellent method, there is a problem that the electroforming method itself has a lot of know-how and the number of manufacturers is limited at present. Moreover, when providing the protective film for protecting the horizontal wiring part of the electronic device package front surface, it is necessary to create it as a separate process.

特開２００１−１２７２４３号公報JP 2001-127243 A 国際公開ＷＯ２００８／０６５８９６ Ａ１International Publication WO2008 / 065896 A1

本発明は、係る問題点を解決して、電子デバイスパッケージ構造形成のための垂直配線や水平配線などの追加工程を部品として集約させることを目的としている。また、電子デバイスパッケージのおもて面に形成した配線パターンを保護するための保護膜が必要な場合、簡潔に、しかもコスト的にも安く製造し、供給する。   An object of the present invention is to solve such problems and to aggregate additional processes such as vertical wiring and horizontal wiring for forming an electronic device package structure as parts. In addition, when a protective film for protecting the wiring pattern formed on the front surface of the electronic device package is necessary, the protective film is manufactured and supplied in a simple and inexpensive manner.

また、本発明は、電子デバイスパッケージに用いる配線用電子部品を、電鋳法を用いることなく従来より用いられている多層金属積層とかリソグラフィなどの通常の製造技術を用いて容易に作成可能にすることを目的としている。   In addition, the present invention makes it possible to easily produce electronic components for wiring used in an electronic device package by using conventional manufacturing techniques such as multilayer metal lamination and lithography that are conventionally used without using an electroforming method. The purpose is that.

本発明の配線用電子部品は、半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージに組み込んで用いる。この配線用電子部品は、支持板と、該支持板の上に剥離可能の接着剤を用いて貼り付けられる２層の水平配線用下層金属及び水平配線用上層金属をパターニングすることにより形成される水平配線部と、該水平配線部に接続された垂直配線部により構成する。２層からなる水平配線部及び垂直配線部は、少なくとも３層の金属層を積層した金属積層材を加工することにより形成する。水平配線用上層金属は、水平配線用下層金属とは異なるエッチングレートの金属から選ばれ、かつ水平配線用下層金属から形成した配線パターンをマスクとしてパターニングされる。   The electronic component for wiring according to the present invention is used by arranging a circuit element including a semiconductor chip and incorporating it in an electronic device package having a horizontal wiring portion and a vertical wiring portion connected to the circuit element and external electrodes. This electronic component for wiring is formed by patterning a support plate and two layers of a lower layer metal for horizontal wiring and an upper layer metal for horizontal wiring that are attached to the support plate using a peelable adhesive. It comprises a horizontal wiring part and a vertical wiring part connected to the horizontal wiring part. The two-layer horizontal wiring portion and the vertical wiring portion are formed by processing a metal laminated material in which at least three metal layers are laminated. The horizontal wiring upper layer metal is selected from metals having an etching rate different from that of the horizontal wiring lower layer metal, and is patterned using a wiring pattern formed from the horizontal wiring lower layer metal as a mask.

また、本発明の配線用電子部品の製造方法は、水平配線用下層金属と、水平配線用上層金属と、垂直配線用金属から成る少なくとも３層の金属層を積層した金属積層材を形成する。水平配線用下層金属のパターニングを行ない、かつ、水平配線用下層金属とは異なるエッチングレートの金属から選ばれる水平配線用上層金属のパターニングを、水平配線用下層金属パターンをマスクとして行って、水平配線用下層金属と水平配線用上層金属からなる２層の水平配線部パターンを形成する。水平配線部パターンを形成した金属積層材を、剥離可能の接着剤を用いて支持板の上に貼り付けた後、垂直配線用金属のパターニングを行って、水平配線部に接続された垂直配線部を形成する。   In the method of manufacturing an electronic component for wiring according to the present invention, a metal laminate is formed by laminating at least three metal layers composed of a lower layer metal for horizontal wiring, an upper layer metal for horizontal wiring, and a metal for vertical wiring. Patterning of the lower layer metal for horizontal wiring and patterning of the upper layer metal for horizontal wiring selected from metals having an etching rate different from that of the lower layer metal for horizontal wiring are performed using the lower layer metal pattern for horizontal wiring as a mask. A two-layer horizontal wiring portion pattern composed of a lower layer metal for horizontal wiring and an upper layer metal for horizontal wiring is formed. After the metal laminate with the horizontal wiring pattern formed is pasted onto a support plate using a peelable adhesive, the vertical wiring metal is patterned and the vertical wiring section connected to the horizontal wiring section. Form.

水平配線部パターンを形成した金属積層材を支持板の上に貼り付ける際に、該支持板に貼り付ける前に、薄膜テープの上に貼り付け、その後、この薄膜テープを剥離可能の接着剤を用いて支持板の上に貼り付けることができる。   When attaching the metal laminate with the horizontal wiring pattern on the support plate, attach it to the thin film tape before applying it to the support plate, and then apply an adhesive that can peel the thin film tape. Can be used and pasted on the support plate.

また、水平配線用上層金属とは異なるエッチングレートの金属から選ばれる水平配線用下層金属のパターニングを行った後、水平配線用上層金属パターンを形成する前の金属積層材を、薄膜テープの上に接着剤を用いて貼り付けることができる。この後、この金属積層材を接着した薄膜テープを、支持板の上に剥離可能の接着剤を用いて貼り付けた後、垂直配線用金属のパターニングを行ない、最後に、水平配線用上層金属のパターニングを行う。或いは、水平配線用下層金属のパターニングを行った金属積層材を、薄膜テープの上に接着剤を用いて貼り付けた後、垂直配線用金属のパターニング及び水平配線用上層金属のパターニングを行ない、最後に、このパターニングした金属積層材を接着した薄膜テープを、支持板の上に剥離可能の接着剤を用いて貼り付けることができる。   In addition, after patterning the lower layer metal for horizontal wiring selected from metals having an etching rate different from that of the upper layer metal for horizontal wiring, the metal laminate before forming the upper layer metal pattern for horizontal wiring is placed on the thin film tape. It can be pasted using an adhesive. After this, the thin film tape to which the metal laminate material is bonded is pasted onto the support plate using a peelable adhesive, and then the metal for vertical wiring is patterned, and finally the upper layer metal for horizontal wiring is formed. Perform patterning. Alternatively, after laminating the metal laminated material with the pattern of the lower layer metal for horizontal wiring on the thin film tape using an adhesive, patterning of the metal for vertical wiring and patterning of the upper layer metal for horizontal wiring is performed. Moreover, the thin film tape which adhere | attached this patterned metal laminated material can be affixed on a support plate using the peelable adhesive agent.

半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する本発明の電子デバイスパッケージ及びその製造方法において、配線用電子部品を、支持板と、該支持板の上に剥離可能の接着剤を用いて貼り付けられる２層の水平配線用下層金属及び水平配線用上層金属から形成される水平配線部、及び該水平配線部に接続された垂直配線部により構成する。水平配線部及び垂直配線部は、水平配線用下層金属と、該水平配線用下層金属とは異なるエッチングレートの金属から選ばれ、かつ水平配線用下層金属の配線パターンをマスクとしてパターニングされる水平配線用上層金属と、垂直配線用金属との少なくとも３層の金属層を積層した金属積層材を加工することにより形成される。配線用電子部品の垂直配線部を、基板上の配線層の所定位置に接続しかつ固定して樹脂封止した後、支持板を剥離することにより露出した水平配線部と接続される外部電極を形成する。   In the electronic device package of the present invention in which a circuit element including a semiconductor chip is arranged and a horizontal wiring part and a vertical wiring part connected to the circuit element and the external electrode are present and the manufacturing method thereof, the wiring electronic component is supported. A horizontal wiring portion formed from a lower layer metal for horizontal wiring and an upper layer metal for horizontal wiring, and a horizontal wiring portion connected to the horizontal wiring portion. It consists of a vertical wiring part. The horizontal wiring portion and the vertical wiring portion are selected from a lower layer metal for horizontal wiring and a metal having an etching rate different from that of the lower layer metal for horizontal wiring, and are patterned using the wiring pattern of the lower layer metal for horizontal wiring as a mask. It is formed by processing a metal laminate obtained by laminating at least three metal layers of an upper metal layer and a vertical wiring metal layer. After connecting the vertical wiring part of the wiring electronic component to a predetermined position of the wiring layer on the substrate and fixing and resin-sealing, external electrodes connected to the exposed horizontal wiring part by peeling the support plate Form.

配線用電子部品は、さらに、水平配線部を形成した金属積層材を貼り付けた薄膜テープを備え、支持板の上に貼り付ける際に、この薄膜テープを剥離可能の接着剤を用いて貼り付け、かつ、支持板を剥離することにより露出した薄膜テープを保護膜として用いることができる。   The wiring electronic component is further equipped with a thin film tape with a metal laminate that forms the horizontal wiring part, and this thin film tape is affixed using a peelable adhesive when affixing on the support plate. And the thin film tape exposed by peeling a support plate can be used as a protective film.

本発明によれば、電子デバイスパッケージ形成のための垂直配線や水平配線などの追加工程を部品として集約させることができる。また、電子デバイスパッケージのおもて面に形成した水平配線部（再配線）を保護するための保護膜が必要な場合、簡潔に、しかもコスト的にも安く製造し、供給することができる。   ADVANTAGE OF THE INVENTION According to this invention, additional processes, such as a vertical wiring and a horizontal wiring for electronic device package formation, can be integrated as components. Further, when a protective film for protecting the horizontal wiring portion (rewiring) formed on the front surface of the electronic device package is necessary, it can be manufactured and supplied simply and at low cost.

また、本発明は、電子デバイスパッケージに用いる配線用電子部品を、電鋳法を用いることなく従来より用いられている通常の製造技術を用いて容易に作成することができる。   Moreover, the present invention can easily produce an electronic component for wiring used in an electronic device package by using a normal manufacturing technique conventionally used without using an electroforming method.

また、本発明によれば、簡易な方法で、イメージセンサあるいは高放熱のパッケージのような基板と反対側に電極を取り出す必要のある半導体パッケージを製作できる。半導体基板に貫通孔を開けて金属材料を充填する貫通配線技術の必要も無く、半導体基板と反対側に容易に電極を取り出し、かつ配線することができる。   In addition, according to the present invention, it is possible to manufacture a semiconductor package that requires an electrode to be taken out on the opposite side of the substrate, such as an image sensor or a high heat dissipation package, by a simple method. There is no need for through wiring technology in which a through hole is formed in a semiconductor substrate and filled with a metal material, and an electrode can be easily taken out and wired on the opposite side of the semiconductor substrate.

本発明に基づき構成した配線用電子部品の第１の例を示す図であり、（Ａ）は斜視図、（Ｂ）は断面図、（Ｃ）は（Ｂ）中のＸ部を拡大した断面図をそれぞれ示している。It is a figure which shows the 1st example of the electronic component for wiring comprised based on this invention, (A) is a perspective view, (B) is sectional drawing, (C) is the cross section which expanded the X section in (B). Each figure is shown. ３層の金属層を貼り合わせたクラッド材を例示する図である。It is a figure which illustrates the clad material which bonded together the metal layer of three layers. 水平配線部パターン形成を示す図である。It is a figure which shows horizontal wiring part pattern formation. 金属積層材を、支持板の上に貼り付けた状態で示す図である。It is a figure which shows a metal laminated material in the state affixed on the support plate. 完成した配線用電子部品の第１の例の断面図である。It is sectional drawing of the 1st example of the electronic component for wiring completed. ３層の金属層をメッキにより形成した金属メッキ材を例示する図である。It is a figure which illustrates the metal plating material which formed the metal layer of 3 layers by plating. ３層の金属層を積層した金属積層材を例示する図である。It is a figure which illustrates the metal laminated material which laminated | stacked the metal layer of 3 layers. 水平配線部パターン形成を示す図である。It is a figure which shows horizontal wiring part pattern formation. 金属積層材を、薄膜テープの上に貼り付けた状態で示す図である。It is a figure which shows a metal laminated material in the state affixed on the thin film tape. 薄膜テープを支持板の上に貼り付けた状態で示す図である。It is a figure shown in the state which affixed the thin film tape on the support plate. 完成した配線用電子部品の第２の例を示す断面図である。It is sectional drawing which shows the 2nd example of the completed electronic component for wiring. ３層の金属層を積層した金属積層材を例示する図である。It is a figure which illustrates the metal laminated material which laminated | stacked the metal layer of 3 layers. 水平配線用下層金属パターン形成を示す図である。It is a figure which shows lower layer metal pattern formation for horizontal wiring. 金属積層材を、薄膜テープの上に貼り付けた状態で示す図である。It is a figure which shows a metal laminated material in the state affixed on the thin film tape. 薄膜テープを支持板の上に貼り付けた状態で示す図である。It is a figure shown in the state which affixed the thin film tape on the support plate. 垂直配線部のパターニングを行った状態で示す断面図である。It is sectional drawing shown in the state which patterned the vertical wiring part. 完成した配線用電子部品の第３の例を示す断面図である。It is sectional drawing which shows the 3rd example of the completed electronic component for wiring. ３層の金属層を積層した金属積層材を例示する図である。It is a figure which illustrates the metal laminated material which laminated | stacked the metal layer of 3 layers. 水平配線用下層金属パターン形成を示す図である。It is a figure which shows lower layer metal pattern formation for horizontal wiring. 金属積層材を、薄膜テープの上に貼り付けた状態で示す図である。It is a figure which shows a metal laminated material in the state affixed on the thin film tape. 垂直配線部のパターニングを行った状態で示す断面図である。It is sectional drawing shown in the state which patterned the vertical wiring part. 水平配線用上層金属パターン形成を示す図である。It is a figure which shows upper-layer metal pattern formation for horizontal wiring. 完成した配線用電子部品の第４の例を示す断面図である。It is sectional drawing which shows the 4th example of the completed electronic component for wiring. 基板上に、電子部品として半導体LSIチップを接着し、かつ接続した状態で示す図であり、（Ａ）は断面図を、（Ｂ）は斜視図を示している。2A and 2B are diagrams showing a state in which a semiconductor LSI chip is bonded and connected as an electronic component on a substrate, where FIG. 2A shows a cross-sectional view and FIG. 2B shows a perspective view. 配線用電子部品を、半導体LSIチップを装着した基板上に配置した状態で示す図である。It is a figure which shows the electronic component for wiring arrange | positioned on the board | substrate which mounted | wore with the semiconductor LSI chip. 配線用電子部品を、半導体LSIチップを装着した半導体基板上に接続した状態で示す図である。It is a figure which shows the electronic component for wiring in the state connected on the semiconductor substrate with which the semiconductor LSI chip | tip was mounted | worn. 樹脂封止した状態で示す図である。It is a figure shown in the state sealed with resin. 支持板を剥離した後の状態で示す図である。It is a figure shown in the state after peeling a support plate. 完成した電子デバイスパッケージを示す断面図である。It is sectional drawing which shows the completed electronic device package. 配線層を有するガラス基板の上に、イメージセンサが搭載されて接続された状態で示す図である。It is a figure shown in the state where the image sensor was mounted and connected on the glass substrate which has a wiring layer. ガラス基板上に配線用電子部品を配置した状態で示す図である。It is a figure shown in the state which has arrange | positioned the electronic component for wiring on the glass substrate. ガラス基板上に配線用電子部品を接続、固定した状態で示す図である。It is a figure shown in the state which connected and fixed the electronic component for wiring on the glass substrate. 固定後、樹脂封止した状態で示す図である。It is a figure shown in the resin-sealed state after fixation. 支持板を剥離した後の状態で示す図である。It is a figure shown in the state after peeling a support plate. 完成したイメージセンサチップパッケージを示す図である。It is a figure which shows the completed image sensor chip package. 特許文献２に開示の電子デバイスパッケージの製造途中の断面図である。10 is a cross-sectional view of the electronic device package disclosed in Patent Document 2 in the middle of its manufacture. 特許文献２に開示の電子デバイスパッケージを完成した状態で示す断面図である。It is sectional drawing shown in the state which completed the electronic device package disclosed by patent document 2. FIG.

以下、例示に基づき、本発明の配線用電子部品及びその製造方法を、順を追って説明する。図１は、本発明に基づき構成した配線用電子部品の第１の例を示す図であり、（Ａ）は斜視図、（Ｂ）は断面図、（Ｃ）は（Ｂ）中のＸ部を拡大した断面図をそれぞれ示している。図１は、１個の単体パターンを例示するが、実際の製造においては、多数個一体に連結された状態で作成され、その状態で電子デバイスパッケージに組み込んで製造した後、個々のチップに切断して切り分ける個片化を経て、最終製品として完成する。この配線用電子部品の第１の例は、支持板の上にパターニングした２層構成の水平配線部（水平配線用上層金属と水平配線用下層金属）、さらには、その上に、水平配線部に接続された垂直配線部を備えている。   Hereinafter, the electronic component for wiring and the manufacturing method thereof according to the present invention will be described in order based on the examples. FIG. 1 is a diagram showing a first example of an electronic component for wiring constructed according to the present invention, in which (A) is a perspective view, (B) is a cross-sectional view, and (C) is an X portion in (B). The cross-sectional view which expanded each is shown. FIG. 1 illustrates a single unit pattern. In actual manufacturing, a single unit pattern is formed in a state of being connected to one another, and is manufactured by being incorporated in an electronic device package in that state, and then cut into individual chips. After being cut into individual pieces, it is completed as a final product. A first example of this wiring electronic component is a two-layer horizontal wiring portion (an upper layer metal for horizontal wiring and a lower layer metal for horizontal wiring) patterned on a support plate, and further a horizontal wiring portion on the horizontal wiring portion. And a vertical wiring portion connected to the.

次に、このような配線用電子部品の第１の例の製造について、図２〜図５を参照して、順次説明する。まず、図２に示すように、水平配線用下層金属（例えば、薄膜銅）と、水平配線用上層金属（例えば、薄膜ニッケル）と、垂直配線用金属（例えば、厚膜銅）から成る少なくとも３層の金属層を貼り合わせたクラッド材を形成する。クラッド材とは、周知のように、異なる種類の金属を圧接加工により張り合わせた材料のことである。   Next, the manufacture of the first example of such an electronic component for wiring will be sequentially described with reference to FIGS. First, as shown in FIG. 2, at least 3 made of a lower layer metal for horizontal wiring (for example, thin film copper), an upper layer metal for horizontal wiring (for example, thin film nickel), and a metal for vertical wiring (for example, thick film copper). A clad material is formed by laminating the metal layers. As is well known, the clad material is a material in which different kinds of metals are bonded together by pressure welding.

但し、本発明は、上述したようなクラッド材に限らず、３層の金属層を一体に積層したものであれば、どのような金属積層材も使用可能である。図６は、３層の金属積層材をメッキにより形成した金属メッキ材を例示する図である。金属メッキ材の形成は、図６（Ａ）に示すような垂直配線用金属となる金属単板（例えば、銅板）からスタートする。この垂直配線用金属に対して、図６（Ｂ）に示すように、最初に、水平配線用上層金属（例えば、ニッケル）をメッキし、その次に、水平配線用下層金属（例えば、銅）をメッキする。これによって、３層の金属積層材を金属メッキ材によって構成する。   However, the present invention is not limited to the clad material as described above, and any metal laminate material can be used as long as three metal layers are integrally laminated. FIG. 6 is a diagram illustrating a metal plating material formed by plating a three-layer metal laminated material. The formation of the metal plating material starts from a single metal plate (for example, a copper plate) that is a metal for vertical wiring as shown in FIG. As shown in FIG. 6B, the vertical wiring metal (for example, nickel) is first plated on the vertical wiring metal, and then the horizontal wiring lower layer metal (for example, copper). Plating. As a result, the three-layer metal laminated material is constituted by the metal plating material.

図３は、水平配線部パターン形成を示す図である。水平配線部パターン形成のために、最初に、水平配線用下層金属のパターニングをリソグラフィにより実施する。このため、水平配線用下層金属の表面に（図中の下側に）レジストを塗布し、パターンを露光、現像してさらにエッチングを行い、レジストを除去して、水平配線用下層金属の配線パターンを完成させる。この際、水平配線用上層金属（例えば、ニッケル）は、水平配線用下層金属（例えば、銅）とは異なるエッチングレートの金属から選ばれる。エッチング液を選択することにより、水平配線用上層金属をエッチングすることなく、水平配線用下層金属のみをエッチングすることが可能である。さらに、水平配線用上層金属は、エッチングストッパのように機能するので、垂直配線用金属と水平配線用下層金属が同一金属（例えば、銅）で形成されていても、垂直配線用金属がエッチングされることはない。   FIG. 3 is a diagram illustrating the formation of the horizontal wiring pattern. In order to form a horizontal wiring pattern, first, patterning of the lower layer metal for horizontal wiring is performed by lithography. Therefore, a resist is applied to the surface of the lower layer metal for horizontal wiring (on the lower side in the figure), the pattern is exposed, developed, further etched, the resist is removed, and the lower layer metal wiring pattern for horizontal wiring To complete. At this time, the horizontal wiring upper layer metal (for example, nickel) is selected from metals having an etching rate different from that of the horizontal wiring lower layer metal (for example, copper). By selecting an etching solution, it is possible to etch only the lower layer metal for horizontal wiring without etching the upper layer metal for horizontal wiring. Furthermore, since the upper wiring metal for horizontal wiring functions as an etching stopper, even if the vertical wiring metal and the lower wiring metal are formed of the same metal (for example, copper), the vertical wiring metal is etched. Never happen.

次に、水平配線用上層金属のパターニングを実施する。この水平配線用上層金属パターンは、上記のようにして形成された水平配線用下層金属パターンをマスクとしてエッチングするのみで形成することができる。また、エッチング液を選択することにより、垂直配線用金属をエッチングすることなく、水平配線用上層金属のみをエッチングすることが可能である。結果的に、水平配線用下層金属と水平配線用上層金属の両方のパターンは、全く同じパターンとなり、重なる形となる。   Next, patterning of the upper layer metal for horizontal wiring is performed. This horizontal wiring upper layer metal pattern can be formed only by etching using the horizontal wiring lower layer metal pattern formed as described above as a mask. Further, by selecting the etching solution, it is possible to etch only the upper layer metal for horizontal wiring without etching the metal for vertical wiring. As a result, the pattern of both the lower layer metal for horizontal wiring and the upper layer metal for horizontal wiring are exactly the same pattern and overlap each other.

次に、図４に示すように、水平配線部パターンを形成した金属クラッド材を、支持板の上に、接着剤を用いて貼り付ける。この貼り付けは、水平配線部パターン形成側を支持板側に面するように行う。支持板としては、板状のシリコン基板とかガラスのような絶縁体或いは導電体のいずれも用いることができるが、例えば、ステンレス板を用いることにより、電子デバイスパッケージの製造中に、より強い剛性を得ることができる。この支持板は、電子デバイスパッケージ製造のための樹脂封止工程後に、剥離して除去する。接着剤は、容易に剥離可能のものであり、所定の温度（例えば、高熱）で剥離し易い材質のものから選択され、例えば、熱カプセル入り接着剤又は熱可塑性の接着剤を用いる。   Next, as shown in FIG. 4, the metal clad material on which the horizontal wiring portion pattern is formed is pasted on the support plate using an adhesive. This affixing is performed so that the horizontal wiring pattern forming side faces the support plate. As the support plate, either a plate-like silicon substrate or an insulator or a conductor such as glass can be used. For example, by using a stainless steel plate, stronger rigidity can be obtained during the manufacture of an electronic device package. Can be obtained. This support plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package. The adhesive is easily peelable and is selected from materials that are easily peeled off at a predetermined temperature (for example, high heat). For example, a heat-capsuled adhesive or a thermoplastic adhesive is used.

次に、垂直配線部のパターニングを行う。図５は、完成した配線用電子部品の第１の例の断面図である。垂直配線部のパターニングは、リソグラフィによって行う。このため、垂直配線用金属の表面に、垂直配線部形成用のレジストを塗布し、パターンを露光、現像してさらにエッチングを行い、レジストを除去して、垂直配線用金属の配線パターンを完成させる。エッチング液を選択することにより、水平配線用上層金属をエッチングすることなく、垂直配線用金属のみをエッチングすることが可能である。例示の構成は、支持板で支持しているために、垂直配線部のエッチングが可能となっている。このとき垂直配線部はエッチング形状改善（垂直配線部の高さが高い場合裾野が広がり易い）のために多層構造としても良い。例えば、垂直配線部は銅/アルミニュームとし、水平配線部はニッケル/銅の全体として４層構造とすることができる。   Next, the vertical wiring part is patterned. FIG. 5 is a cross-sectional view of a first example of a completed wiring electronic component. Patterning of the vertical wiring portion is performed by lithography. Therefore, a resist for forming a vertical wiring portion is applied to the surface of the metal for vertical wiring, the pattern is exposed, developed, and further etched to remove the resist, thereby completing a wiring pattern for the metal for vertical wiring. . By selecting the etching solution, it is possible to etch only the metal for vertical wiring without etching the upper layer metal for horizontal wiring. Since the illustrated configuration is supported by the support plate, the vertical wiring portion can be etched. At this time, the vertical wiring portion may have a multi-layer structure in order to improve the etching shape (when the height of the vertical wiring portion is high, the base tends to spread). For example, the vertical wiring portion can be made of copper / aluminum, and the horizontal wiring portion can be made of nickel / copper as a whole with a four-layer structure.

これによって、支持板の上にパターニングした２層構成の水平配線部（水平配線用上層金属と水平配線用下層金属）、さらには、その上に、水平配線部に接続された垂直配線部が形成される。   As a result, a horizontal wiring portion having a two-layer structure (an upper layer metal for horizontal wiring and a lower layer metal for horizontal wiring) patterned on the support plate and a vertical wiring portion connected to the horizontal wiring portion are formed thereon. Is done.

このように、２層構成の水平配線部と１層の垂直配線部の少なくとも３層の金属積層材を用いることにより、特許文献２のような電鋳法を用いること無く、通常のリソグラフィを用いて、垂直配線部と共に水平配線部を有する配線用電子部品の製造が可能となる。なお、水平配線用下層金属及び水平配線用上層金属は導電性を有する必要があることに加えて、水平配線用下層金属は水平配線用上層金属のエッチング用マスクとして使用できるものであれば、水平配線用下層金属と水平配線用上層金属の組み合わせは、例示した銅とニッケルの組み合わせ以外にも、例えばＣｕとＡｕ，ＡｇやＣｒとＣｕ、ＣｒとＮｉ等選択エッチング製の高い材料の組合せであれば良い。また、垂直配線用金属としては、水平配線用上層金属とは異なる材質であれば、水平配線用下層金属と同一であっても問題はなく、例えば銅などの導電性金属が使用可能である。また、水平配線用下層金属と水平配線用上層金属は、いずれも単一金属層により形成する必要は必ずしも無く、いずれかの表面にＡｕやＡｇ等といった導電性の良い金属を形成することも可能である。   Thus, by using at least three layers of metal laminates of a horizontal wiring portion having a two-layer structure and a vertical wiring portion having one layer, normal lithography can be used without using an electroforming method as in Patent Document 2. Thus, it is possible to manufacture a wiring electronic component having a horizontal wiring portion together with a vertical wiring portion. In addition to the fact that the lower layer metal for horizontal wiring and the upper layer metal for horizontal wiring need to have conductivity, the lower layer metal for horizontal wiring can be used as an etching mask for the upper layer metal for horizontal wiring. The combination of the lower layer metal for wiring and the upper layer metal for horizontal wiring may be a combination of high materials made of selective etching such as Cu and Au, Ag, Cr and Cu, Cr and Ni, etc. It ’s fine. Further, as long as the metal for vertical wiring is different from the upper layer metal for horizontal wiring, there is no problem even if it is the same as the lower layer metal for horizontal wiring. For example, a conductive metal such as copper can be used. Moreover, it is not always necessary to form the lower layer metal for horizontal wiring and the upper layer metal for horizontal wiring by a single metal layer, and it is possible to form a metal having good conductivity such as Au or Ag on any surface. It is.

次に、このような配線用電子部品の第２の例の製造について、図７〜図１１を参照して、順次説明する。まず、図７に示すように、図２或いは図６を参照して上述したように、水平配線用下層金属（例えば、薄膜銅）と、水平配線用上層金属（例えば、薄膜ニッケル）と、垂直配線用金属（例えば、厚膜銅）から成る少なくとも３層の金属層からなる金属積層材を形成する。   Next, the manufacture of the second example of such an electronic component for wiring will be sequentially described with reference to FIGS. First, as shown in FIG. 7, as described above with reference to FIG. 2 or FIG. 6, the lower layer metal for horizontal wiring (for example, thin film copper), the upper layer metal for horizontal wiring (for example, thin film nickel), and the vertical A metal laminate made of at least three metal layers made of a wiring metal (for example, thick film copper) is formed.

図８は、水平配線部パターン形成を示す図である。この水平配線部パターン形成は、図３を参照して上述したように行う。水平配線用下層金属と水平配線用上層金属の両方の全く同じパターンが、重なるように形成される。   FIG. 8 is a diagram illustrating the formation of the horizontal wiring pattern. The horizontal wiring portion pattern formation is performed as described above with reference to FIG. The same pattern of both the lower layer metal for horizontal wiring and the upper layer metal for horizontal wiring is formed so as to overlap.

次に、図９に示すように、水平配線パターンを形成した金属積層材を、薄膜テープの上に、接着剤を用いて貼り付ける。貼り付ける薄膜テープとしては、ポリイミドテープなどに代表される薄膜フィルムの絶縁基材が望ましい。また、薄膜テープは、例示したような一層の薄膜フィルムに限らず、接着剤により接着した２層（或いはそれ以上）の薄膜フィルムの絶縁基材テープにより構成することも可能である。   Next, as shown in FIG. 9, the metal laminated material in which the horizontal wiring pattern is formed is pasted onto the thin film tape using an adhesive. As the thin film tape to be attached, an insulating base material of a thin film represented by a polyimide tape or the like is desirable. Further, the thin film tape is not limited to the single-layer thin film as illustrated, but may be constituted by an insulating base tape of a two-layer (or more) thin film bonded with an adhesive.

薄膜テープは、完成製品（電子デバイスパッケージ）において水平配線部（再配線）を覆う保護膜として機能する。即ち、この薄膜テープと、水平配線パターンを形成した金属積層材は剥離しないので、例えば、熱硬化系（変性エポキシ系）接着剤のような、接着強度の大きな接着剤を用いて貼り付ける。   The thin film tape functions as a protective film that covers the horizontal wiring portion (rewiring) in the finished product (electronic device package). That is, since this thin film tape and the metal laminated material on which the horizontal wiring pattern is formed are not peeled off, they are pasted using an adhesive having a high adhesive strength such as a thermosetting (modified epoxy) adhesive.

次に、図１０に示すように、水平配線部パターンを形成した金属積層材を強固に接着した薄膜テープを、支持板の上に剥離可能の接着剤を用いて貼り付ける。この貼り付けは、薄膜テープ側を支持板側に面するように行う。支持板としては、図４を参照して説明したような材質のものであり、板状のシリコン基板とかガラスのような絶縁体或いは導電体のいずれも用いることができる。この支持板は、電子デバイスパッケージ製造のための樹脂封止工程後に、剥離して除去する。接着剤は、容易に剥離可能のものを用いる。例えば、上述したような、所定の温度（例えば、高熱）で剥離し易い材質のものであり、例えば、熱カプセル入り接着剤又は熱可塑性の接着剤を用いる。   Next, as shown in FIG. 10, a thin film tape firmly bonded to the metal laminate on which the horizontal wiring portion pattern is formed is pasted onto the support plate using a peelable adhesive. This pasting is performed so that the thin film tape side faces the support plate side. The support plate is made of the material described with reference to FIG. 4, and either a plate-like silicon substrate, an insulator such as glass, or a conductor can be used. This support plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package. An adhesive that can be easily peeled is used. For example, it is made of a material that is easily peeled off at a predetermined temperature (for example, high heat) as described above. For example, a heat-capsuled adhesive or a thermoplastic adhesive is used.

次に、垂直配線部のパターニングを行う。図１１は、完成した配線用電子部品の第２の例を示す断面図である。垂直配線部のパターニングは、図５を参照して上述したように、リソグラフィによって行う。これによって、支持板の上に剥離可能に接着された薄膜テープの上に、パターニングした２層構成の水平配線部（水平配線用上層金属と水平配線用下層金属）が強固な接着剤により固定され、さらには、その上に、水平配線部に接続された垂直配線部が形成される。なお、水平配線部と薄膜テープを固定する接着剤は、それらの間にあれば十分であり、図示されているように水平配線部相互の間にもはみ出した接着剤は必ずしも必要ではないが、このはみ出した接着剤によって、より強固な固定が可能となる。   Next, the vertical wiring part is patterned. FIG. 11 is a cross-sectional view showing a second example of the completed wiring electronic component. The patterning of the vertical wiring portion is performed by lithography as described above with reference to FIG. As a result, the patterned two-layer horizontal wiring portion (horizontal wiring upper layer metal and horizontal wiring lower layer metal) is fixed on the thin film tape that is peelably bonded onto the support plate with a strong adhesive. Further, a vertical wiring portion connected to the horizontal wiring portion is formed thereon. In addition, the adhesive that fixes the horizontal wiring portion and the thin film tape is sufficient if it is between them, and the adhesive protruding between the horizontal wiring portions as shown in the drawing is not necessarily required, The protruding adhesive allows more firm fixation.

このように、支持部は、薄膜テープ（例えば、絶縁基材テープ）と、この裏側（配線パターン形成面の反対側）に剥離可能の接着剤を用いて貼り付けた支持板（補強板）との２層構成となる。この支持部は、電子デバイスパッケージ製造中に、複数個の水平配線部及び垂直配線部を一体に結合するよう機能するだけでなく、垂直配線部をパターニングする際の支持構成としても機能する。この支持板は、電子デバイスパッケージ製造のための樹脂封止工程後に、剥離して除去する。薄膜テープは、電子デバイスパッケージの保護膜として残される。   As described above, the support portion includes a thin film tape (for example, an insulating base tape) and a support plate (reinforcing plate) attached to the back side (opposite side of the wiring pattern forming surface) using a peelable adhesive. This is a two-layer structure. This support portion not only functions to integrally couple a plurality of horizontal wiring portions and vertical wiring portions during manufacturing of the electronic device package, but also functions as a support structure when patterning the vertical wiring portions. This support plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package. The thin film tape is left as a protective film of the electronic device package.

次に、このような配線用電子部品の第３の例の製造について、図１２〜図１７を参照して、順次説明する。図１２に示すように、まず、上述の第２の例と同様に、水平配線用下層金属（例えば、薄膜銅）と、水平配線用上層金属（例えば、薄膜ニッケル）と、垂直配線用金属（例えば、厚膜銅）から成る少なくとも３層の金属層からなる金属積層材を形成する。   Next, the manufacture of the third example of such a wiring electronic component will be sequentially described with reference to FIGS. As shown in FIG. 12, first, as in the second example described above, a lower layer metal for horizontal wiring (for example, thin film copper), an upper layer metal for horizontal wiring (for example, thin film nickel), and a metal for vertical wiring ( For example, a metal laminate made of at least three metal layers made of thick film copper) is formed.

図１３は、水平配線用下層金属パターン形成を示す図である。この下層金属パターン形成は、リソグラフィにより行う。この際、上述した第１の例と同様に、水平配線用上層金属（例えば、ニッケル）は、水平配線用下層金属（例えば、銅）とは異なるエッチングレートの金属から選ばれる。エッチング液を選択することにより、水平配線用上層金属をエッチングすることなく、水平配線用下層金属のみをエッチングすることが可能である。さらに、水平配線用上層金属は、エッチングストッパのように機能するので、垂直配線用金属と水平配線用下層金属が同一金属（例えば、銅）で形成されていても、垂直配線用金属がエッチングされることはない。   FIG. 13 is a diagram showing formation of a lower layer metal pattern for horizontal wiring. This lower layer metal pattern is formed by lithography. At this time, as in the first example described above, the horizontal wiring upper layer metal (for example, nickel) is selected from a metal having an etching rate different from that of the horizontal wiring lower layer metal (for example, copper). By selecting an etching solution, it is possible to etch only the lower layer metal for horizontal wiring without etching the upper layer metal for horizontal wiring. Furthermore, since the upper wiring metal for horizontal wiring functions as an etching stopper, even if the vertical wiring metal and the lower wiring metal are formed of the same metal (for example, copper), the vertical wiring metal is etched. Never happen.

次に、図１４に示すように、下層金属パターンを形成した金属積層材を、上述の第２の例と同様に、薄膜テープの上に、接着強度の大きな接着剤を用いて貼り付ける。薄膜テープは、完成製品（電子デバイスパッケージ）において水平配線部（再配線）を覆う保護膜として機能する。   Next, as shown in FIG. 14, the metal laminated material on which the lower layer metal pattern is formed is pasted on the thin film tape using an adhesive having a high adhesive strength, as in the second example. The thin film tape functions as a protective film that covers the horizontal wiring portion (rewiring) in the finished product (electronic device package).

次に、図１５に示すように、第２の例と同様に、下層金属パターンを形成した金属積層材を強固に接着した薄膜テープを、支持板の上に容易に剥離可能の接着剤を用いて貼り付ける。この支持板は、電子デバイスパッケージ製造のための樹脂封止工程後に、剥離して除去する。   Next, as shown in FIG. 15, as in the second example, an adhesive that can be easily peeled on the support plate is used for the thin film tape firmly bonded to the metal laminate on which the lower layer metal pattern is formed. And paste. This support plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package.

次に、図１６に示すように、第２の例と同様に、垂直配線部のパターニングを行う。   Next, as shown in FIG. 16, the vertical wiring portion is patterned in the same manner as in the second example.

次に、水平配線部上層金属のパターニングを行う。図１７は、完成した配線用電子部品の第３の例を示す断面図である。水平配線部上層金属のパターニングは、垂直配線部をマスクとして、上層金属の全面エッチングにより行なう。これによって垂直配線部の直下以外の上層金属は削除される。水平配線部は、上述したようにパターニングした下層金属と、垂直配線部直下の上層金属により形成される。これによって、支持板の上に剥離可能に接着された薄膜テープの上に、水平配線部と水平配線部に接続された垂直配線の電子部品が完成する。   Next, the horizontal wiring portion upper layer metal is patterned. FIG. 17 is a cross-sectional view showing a third example of a completed wiring electronic component. The patterning of the upper layer metal in the horizontal wiring portion is performed by etching the entire upper layer metal using the vertical wiring portion as a mask. As a result, the upper layer metal other than directly below the vertical wiring portion is deleted. The horizontal wiring portion is formed by the lower layer metal patterned as described above and the upper layer metal immediately below the vertical wiring portion. As a result, the horizontal wiring portion and the electronic component of the vertical wiring connected to the horizontal wiring portion are completed on the thin film tape that is detachably bonded on the support plate.

このように、支持部は、第２の例と同様に、薄膜テープ（例えば、絶縁基材テープ）と、この裏側（配線パターン形成面の反対側）に剥離可能の接着剤を用いて貼り付けた支持板（補強板）との２層構成となる。   In this way, as in the second example, the support portion is pasted with a thin film tape (for example, an insulating base tape) and a peelable adhesive on the back side (opposite side of the wiring pattern forming surface). It becomes a two-layer structure with a support plate (reinforcing plate).

次に、このような配線用電子部品の第４の例の製造について、図１８〜図２３を参照して、順次説明する。図１８に示すように、まず、上述の第２或いは第３の例と同様に、水平配線用下層金属（例えば、薄膜銅）と、水平配線用上層金属（例えば、薄膜ニッケル）と、垂直配線用金属（例えば、厚膜銅）から成る少なくとも３層の金属層からなる金属積層材を形成する。   Next, the manufacture of the fourth example of such a wiring electronic component will be sequentially described with reference to FIGS. As shown in FIG. 18, first, as in the second or third example described above, the lower layer metal for horizontal wiring (for example, thin film copper), the upper layer metal for horizontal wiring (for example, thin film nickel), and the vertical wiring A metal laminate made of at least three metal layers made of a working metal (for example, thick film copper) is formed.

図１９は、水平配線用下層金属パターン形成を示す図である。この下層金属パターン形成は、上述の第３の例の図１３と同様にリソグラフィによって行う。   FIG. 19 is a diagram showing formation of a lower layer metal pattern for horizontal wiring. This lower layer metal pattern is formed by lithography in the same manner as in the third example shown in FIG.

次に、図２０に示すように、下層金属パターンを形成した金属積層材を、第３の例の図１４と同様に、薄膜テープの上に、接着強度の大きな接着剤を用いて貼り付ける。   Next, as shown in FIG. 20, the metal laminated material on which the lower layer metal pattern is formed is pasted onto the thin film tape using an adhesive having a high adhesive strength, as in FIG. 14 of the third example.

次に、図２１に示すように、第３の例の図１６と同様に、垂直配線部のパターニングを行う。但し、この第４の例の垂直配線部のパターニングは、支持板の上に貼り付ける前に行う点で、第３の例とは相違する。   Next, as shown in FIG. 21, the vertical wiring portion is patterned in the same manner as in FIG. 16 of the third example. However, the patterning of the vertical wiring portion of the fourth example is different from the third example in that it is performed before being attached on the support plate.

次に、図２２に示すように、水平配線部上層金属のパターニングを行う。水平配線部上層金属のパターニングは、第３の例の図１７と同様に、垂直配線部をマスクとして、上層金属の全面エッチングにより行なう。これによって垂直配線部の直下以外の上層金属は削除される。水平配線部は、上述したようにパターニングした下層金属と、垂直配線部直下の上層金属により形成される。これによって、支持板の上に剥離可能に接着された薄膜テープの上に、水平配線部と水平配線部に接続された垂直配線の電子部品が完成する。   Next, as shown in FIG. 22, patterning of the upper layer metal of the horizontal wiring portion is performed. Patterning of the upper layer metal of the horizontal wiring portion is performed by etching the entire surface of the upper layer metal using the vertical wiring portion as a mask, as in FIG. 17 of the third example. As a result, the upper layer metal other than directly below the vertical wiring portion is deleted. The horizontal wiring portion is formed by the lower layer metal patterned as described above and the upper layer metal immediately below the vertical wiring portion. As a result, the horizontal wiring portion and the electronic component of the vertical wiring connected to the horizontal wiring portion are completed on the thin film tape that is detachably bonded on the support plate.

そして、最後に、図２３に示すように、この薄膜テープを、支持板の上に容易に剥離可能の接着剤を用いて貼り付ける。図２３は、完成した配線用電子部品の第４の例を示す断面図である。この支持板は、電子デバイスパッケージ製造のための樹脂封止工程後に、剥離して除去する。この第４の例の配線用電子部品は、完成した状態では、上述の第３の例と同一構成を有しているが、第３の例とは支持板の貼り付け順序を異にしている。   And finally, as shown in FIG. 23, this thin film tape is affixed on a support plate using the easily peelable adhesive. FIG. 23 is a cross-sectional view showing a fourth example of the completed wiring electronic component. This support plate is peeled off and removed after the resin sealing step for manufacturing the electronic device package. The wiring electronic component of the fourth example has the same configuration as that of the above-described third example in a completed state, but the support plate is attached in a different order from the third example. .

次に、電子デバイスパッケージの製造について、上述の配線電子部品の第２の例或いは第３の例を用いる場合を例として、説明する。図２４は、基板上に、電子部品として半導体チップ（LSIチップ）を接着し、かつ接続した状態で示す図であり、（Ａ）は断面図を、（Ｂ）は斜視図を示している。例示の基板は、上面に配線層を形成したシリコン基板（半導体基板）として例示している。   Next, the manufacture of the electronic device package will be described by taking as an example the case of using the second example or the third example of the wiring electronic component described above. 24A and 24B are diagrams showing a state in which a semiconductor chip (LSI chip) is bonded and connected as an electronic component on a substrate, where FIG. 24A is a cross-sectional view and FIG. 24B is a perspective view. The illustrated substrate is exemplified as a silicon substrate (semiconductor substrate) having a wiring layer formed on the upper surface.

半導体基板上に配線層を形成するために、半導体基板の全面に、配線パターンとなるべき金属のシード層を形成する（例えばスパッタ層あるいはナノ金属材料を塗膜）。このシード層としては、例えば、銅メッキを可能とする金、銀、銅、パラジューム箔を用いることができる。配線層のパターンはシード層の上にレジストを塗布し、パターンを露光、現像してさらにエッチングを行い、レジストを除去して完成させる。このシード層の上にメッキにより配線層を成長させる。或いは、ナノ金属粒子で直接シード層をパターニングにしてリソグラフィ工程を省略することもできる。この直接パターニングは、有機溶媒中に銅等のナノ金属粒子を含有させて、それをプリンターで実用されているインクジェット法で所望のパターンを描く方法である。   In order to form a wiring layer on the semiconductor substrate, a metal seed layer to be a wiring pattern is formed on the entire surface of the semiconductor substrate (for example, a sputtered layer or a nano metal material is coated). As the seed layer, for example, gold, silver, copper, or palladium foil that enables copper plating can be used. The wiring layer pattern is completed by applying a resist on the seed layer, exposing and developing the pattern, further etching, removing the resist. A wiring layer is grown on the seed layer by plating. Alternatively, the lithography process can be omitted by patterning the seed layer directly with nano metal particles. This direct patterning is a method in which nano metal particles such as copper are contained in an organic solvent and a desired pattern is drawn by an ink jet method which is practically used in a printer.

半導体LSIチップは、基板上の配線層とはフリップチップボンド接続するものとして例示している。このフリップチップボンド接続に代えて、基板上の配線層に、ボンディングワイヤ接続電極となるボンディング用金属パッド部を形成して、ボンディングワイヤにより接続することも可能である。この場合、配線層上の金属パッド部と半導体LSIチップは、例えば、Ａｕボンディングワイヤにより接続される。   The semiconductor LSI chip is illustrated as being flip-chip bonded to the wiring layer on the substrate. Instead of this flip chip bond connection, it is also possible to form a bonding metal pad portion to be a bonding wire connection electrode on the wiring layer on the substrate and connect it by a bonding wire. In this case, the metal pad portion on the wiring layer and the semiconductor LSI chip are connected by, for example, an Au bonding wire.

図２５は、上述の配線用電子部品の第２の例（図１１参照）或いは第３の例（図１７参照）を、半導体LSIチップを装着した基板（図２４参照）上に配置した状態で示す図である。なお、ここでは、配線用電子部品の第２の例或いは第３の例を用いるものとして説明するが、配線用電子部品の第１の例（図５参照）も同様に用いることができる。   FIG. 25 shows a state in which the second example (see FIG. 11) or the third example (see FIG. 17) of the above-described wiring electronic component is placed on a substrate (see FIG. 24) on which a semiconductor LSI chip is mounted. FIG. In addition, although it demonstrates as what uses the 2nd example or 3rd example of the electronic component for wiring here, the 1st example (refer FIG. 5) of the electronic component for wiring can be used similarly.

図２６は、配線用電子部品を、半導体LSIチップを装着した半導体基板上に接続した状態で示す図である。なお、図示したように、基板側を裏面として、その上に配置される配線用電子部品側をおもて面と称する。基板上面に形成した配線層の所定の位置には、配線用電子部品の垂直配線部が固定され、かつ電気的に接続される。垂直配線部を固定及び接続する手法としては、（１）超音波による接合、（２）銀ペースト等の導電性ペーストによる接続、（３）半田接続、（４）半導体基板側に設けた接続電極用金属パッド部に凹部を設ける一方、配線用電子部品側は凸部を設けて挿入圧着あるいは挿入してカシメる方法、により行うことができる。   FIG. 26 is a diagram showing the wiring electronic component connected to a semiconductor substrate on which a semiconductor LSI chip is mounted. As shown in the figure, the substrate side is referred to as the back surface, and the wiring electronic component side disposed thereon is referred to as the front surface. A vertical wiring portion of the wiring electronic component is fixed and electrically connected to a predetermined position of the wiring layer formed on the upper surface of the substrate. As a method for fixing and connecting the vertical wiring portion, (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, and (4) connection electrode provided on the semiconductor substrate side While the metal pad portion for the wiring is provided with a concave portion, the wiring electronic component side can be formed by a method of providing a convex portion and inserting and crimping or caulking by inserting.

図２７は、樹脂封止した状態で示す図である。一体に連結されている垂直配線部が配線層の所定の位置に固定された後、この状態で、基板の上面は、支持部の薄膜テープ及び水平配線部下面までトランスファーモールドされ、或いは液状樹脂（材質は、例えばエポキシ系）を用いて樹脂封止される。   FIG. 27 is a diagram showing the resin-sealed state. After the integrally connected vertical wiring portion is fixed at a predetermined position of the wiring layer, in this state, the upper surface of the substrate is transfer-molded to the thin film tape of the support portion and the lower surface of the horizontal wiring portion, or a liquid resin ( The material is resin-sealed using, for example, an epoxy system.

図２８は、支持板を剥離した後の状態で示す図である。例えば、所定の温度を加えることにより、支持板を剥離する。これにより図２８の上側に露出した薄膜テープは、完成製品の保護膜として機能する。配線用電子部品の第１の例（図５参照）を用いた場合には、この保護膜は存在しない。配線用電子部品の第１の例を用いた場合であって、かつ保護膜を必要とする場合、この段階で保護膜（材質は、例えばソルダーレジスト）を形成することができる。   FIG. 28 is a diagram showing the state after the support plate is peeled off. For example, the support plate is peeled off by applying a predetermined temperature. Thus, the thin film tape exposed on the upper side of FIG. 28 functions as a protective film of the finished product. When the first example of the electronic component for wiring (see FIG. 5) is used, this protective film does not exist. When the first example of the electronic component for wiring is used and a protective film is required, a protective film (a material is, for example, a solder resist) can be formed at this stage.

図２９は、完成した電子デバイスパッケージを示す断面図である。図２９に示すように、おもて面側においては、保護膜（薄膜テープ）に穴を空け、開口により露出した水平配線部と接続される外部接続用電極（バンプ電極）を形成する。この水平配線部により、垂直配線部先端とは異なる位置に外部接続用電極を設けることができる。保護膜が無くても、例えば樹脂入り半田を使えば、他のパッケージを接続することは可能である。   FIG. 29 is a cross-sectional view showing a completed electronic device package. As shown in FIG. 29, on the front surface side, a hole is formed in the protective film (thin film tape), and external connection electrodes (bump electrodes) connected to the horizontal wiring portion exposed through the openings are formed. With this horizontal wiring portion, an external connection electrode can be provided at a position different from the tip of the vertical wiring portion. Even if there is no protective film, it is possible to connect other packages by using, for example, resin-containing solder.

以上、基板として半導体シリコン基板を用いる場合を例として説明したが、このような基板としては、特許文献２に開示のような多層有機基板とか或いはリードフレームを用いることも可能である。多層有機基板を用いた際には、スルーホール内部の導体層を介して基板上面の配線層に接続される外部接続用電極を、基板裏面側においても容易に形成することができる。多層有機基板は、複数層から成る基板の各層に、それぞれ配線パターンを形成した後これらの基板を貼り合わせ、必要に応じて各層の配線パターンを接続するためのスルーホールを形成したものである。このスルーホールの内部には導体層が形成され、この導体層が裏面側に形成された端面電極部であるランドと接続されている。   The case where a semiconductor silicon substrate is used as an example has been described above. However, as such a substrate, a multilayer organic substrate as disclosed in Patent Document 2 or a lead frame can be used. When a multilayer organic substrate is used, an external connection electrode connected to the wiring layer on the upper surface of the substrate via the conductor layer inside the through hole can be easily formed on the back surface side of the substrate. The multilayer organic substrate is a substrate in which a wiring pattern is formed on each layer of a substrate composed of a plurality of layers, and then these substrates are bonded together, and through holes for connecting the wiring patterns of each layer are formed as necessary. A conductor layer is formed inside the through hole, and the conductor layer is connected to a land which is an end face electrode portion formed on the back surface side.

このように、本発明は、例示の配線用電子部品を用いることにより、おもて面側の水平配線部に接続された外部接続用電極を形成すること、さらには、このような水平配線部を保護する保護膜を容易に形成することが可能になる。   Thus, the present invention forms an external connection electrode connected to the front surface side horizontal wiring portion by using the exemplified wiring electronic component, and further, such a horizontal wiring portion. It is possible to easily form a protective film for protecting the film.

次に、本発明の配線用電子部品の第２の例或いは第３の例をイメージセンサチップパッケージに用いた場合を、図３０〜図３５を参照して説明する。図３０は、配線層を有するガラス基板（又は光透過性の良い透明樹脂基板）の上に、イメージセンサのような電子部品が搭載されて接続された状態で示す図である。イメージセンサは、受光面を下側に向けて配置する。透明ガラス基板上の配線層は、図２４を参照して上述した半導体基板上の配線層と同様な方法で形成することができる。ガラス基板に形成した配線層をボンディングパッド領域として、イメージセンサ（半導体LSIチップ）のような電子部品を固定しかつ電気的に接続する。   Next, a case where the second or third example of the electronic component for wiring according to the present invention is used in an image sensor chip package will be described with reference to FIGS. FIG. 30 is a diagram showing a state in which an electronic component such as an image sensor is mounted and connected on a glass substrate having a wiring layer (or a transparent resin substrate having good light transmission). The image sensor is arranged with the light receiving surface facing downward. The wiring layer on the transparent glass substrate can be formed by the same method as the wiring layer on the semiconductor substrate described above with reference to FIG. An electronic component such as an image sensor (semiconductor LSI chip) is fixed and electrically connected using a wiring layer formed on a glass substrate as a bonding pad region.

図３１は、ガラス基板上に配線用電子部品の第２の例或いは第３の例を配置した状態で示す図である。なお、ここでは、配線用電子部品の第２の例或いは第３の例を用いるものとして説明するが、配線用電子部品の第１の例（図５参照）も同様に用いることができる。   FIG. 31 is a diagram showing a state in which the second example or the third example of the electronic component for wiring is arranged on the glass substrate. In addition, although it demonstrates as what uses the 2nd example or 3rd example of the electronic component for wiring here, the 1st example (refer FIG. 5) of the electronic component for wiring can be used similarly.

図３２は、ガラス基板上に配線用電子部品を接続、固定した状態で示す図である。この接続は、図２６を参照して前述したように行う。   FIG. 32 is a diagram showing a state in which the wiring electronic component is connected and fixed on the glass substrate. This connection is performed as described above with reference to FIG.

図３３は、固定後、樹脂封止した状態で示す図である。図２７を参照して前述したようにして、ガラス基板と薄膜テープの間の空間を満たすようにトランスファーモールドされ、或いは液状樹脂（材質は、例えばエポキシ系）を用いて樹脂封止される。   FIG. 33 is a diagram showing the resin-sealed state after fixing. As described above with reference to FIG. 27, transfer molding is performed so as to fill a space between the glass substrate and the thin film tape, or resin sealing is performed using a liquid resin (material is, for example, epoxy).

図３４は、支持板を剥離した後の状態で示す図である。支持板を剥離することにより、上側に露出した薄膜テープは、完成製品の保護膜として機能する。配線用電子部品の第１の例（図５参照）を用いた場合には、この保護膜は存在しない。配線用電子部品の第１の例を用いた場合であって、かつ保護膜を必要とする場合、この段階で保護膜を形成することができる。   FIG. 34 is a view showing the state after the support plate is peeled off. By peeling the support plate, the thin film tape exposed on the upper side functions as a protective film for the finished product. When the first example of the electronic component for wiring (see FIG. 5) is used, this protective film does not exist. In the case where the first example of the electronic component for wiring is used and a protective film is required, the protective film can be formed at this stage.

次に、図３５に示すように、天地（上下）逆転させる。図３５は、完成したイメージセンサチップパッケージを示す図である。図３５の下側に位置するおもて面側においては、保護膜に穴を空け、開口により露出した配線と接続される外部接続用のバンプ電極を形成する。この後、個々のチップに切断して切り分ける個片化を経た後に、製品として完成させる。   Next, as shown in FIG. 35, it is reversed upside down. FIG. 35 is a view showing a completed image sensor chip package. On the front surface side located on the lower side of FIG. 35, a hole is formed in the protective film, and a bump electrode for external connection connected to the wiring exposed through the opening is formed. Thereafter, the product is completed after being cut into individual chips and separated into pieces.

図３０において上述したガラス基板に代えて、ヒートシンクとして機能する高放熱基板を用いることにより、高放熱型チップパッケージに具体化することができる。実施例３は、ヒートシンク、ヒートスプレッダー等として機能する高放熱基板を用いた点でのみ実施例２とは相違する（図示省略）。   In place of the glass substrate described above with reference to FIG. 30, a high heat dissipation chip package can be realized by using a high heat dissipation substrate that functions as a heat sink. Example 3 is different from Example 2 only in that a high heat dissipation substrate that functions as a heat sink, a heat spreader, or the like is used (not shown).

これによって、ヒートシンクとして機能する高放熱基板に、高放熱型のLSIチップが実装されて、貫通電極の必要なく、高放熱基板とは反対側のおもて面に外部接続用電極を形成した高放熱型チップパッケージが完成する。   As a result, a high heat dissipation type LSI chip is mounted on a high heat dissipation substrate that functions as a heat sink, and there is no need for through electrodes, and an external connection electrode is formed on the front surface opposite to the high heat dissipation substrate. A heat dissipation chip package is completed.

以上、本開示にて幾つかの実施の形態及び実施例を単に一例として詳細に説明したが、本発明の新規な教示及び有利な効果から実質的に逸脱せずに、その実施の形態には多くの改変例が可能である。
Although several embodiments and examples have been described in detail in the present disclosure by way of example only, the embodiments thereof are not substantially deviated from the novel teachings and advantageous effects of the present invention. Many variations are possible.

Claims (21)

半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージに組み込んで用いるための配線用電子部品において、
支持板と、該支持板の上に剥離可能の接着剤を用いて貼り付けられる２層の水平配線用下層金属及び水平配線用上層金属をパターニングすることにより形成される水平配線部と、該水平配線部に接続された垂直配線部により構成し、
前記水平配線部及び垂直配線部は、少なくとも３層の金属層を積層した金属積層材を加工することにより形成し、前記水平配線用上層金属は、前記水平配線用下層金属とは異なるエッチングレートの金属から選ばれることから成る配線用電子部品。In an electronic component for wiring to be used by arranging a circuit element including a semiconductor chip and incorporating it into an electronic device package in which a horizontal wiring portion and a vertical wiring portion connected to the circuit element and an external electrode are present,
A horizontal wiring portion formed by patterning a support plate, two layers of a lower layer metal for horizontal wiring and an upper layer metal for horizontal wiring, which are attached to the support plate using a peelable adhesive; Consists of a vertical wiring part connected to the wiring part,
The horizontal wiring portion and the vertical wiring portion are formed by processing a metal laminated material in which at least three metal layers are stacked, and the horizontal wiring upper layer metal has an etching rate different from that of the horizontal wiring lower layer metal. Electronic parts for wiring consisting of metal. さらに、前記水平配線部を形成した前記金属積層材に貼り付ける薄膜テープを備え、前記支持板の上に貼り付ける際、この薄膜テープを剥離可能の接着剤を用いて貼り付ける請求項１に記載の配線用電子部品。 Furthermore, the thin film tape which affixes on the said metal laminated material in which the said horizontal wiring part was formed is provided, and when affixing on the said support plate, this thin film tape is affixed using the adhesive which can be peeled. Wiring electronic components. 前記薄膜テープは、前記電子デバイスパッケージにおいて水平配線部を覆う保護膜として機能する請求項２に記載の配線用電子部品。 The electronic component for wiring according to claim 2, wherein the thin film tape functions as a protective film that covers a horizontal wiring portion in the electronic device package. 前記水平配線用下層金属及び前記水平配線用上層金属から形成される水平配線部パターン、及び垂直配線用金属から形成される垂直配線部パターンは、いずれもリソグラフィにより形成される請求項１に記載の配線用電子部品。 2. The horizontal wiring portion pattern formed from the horizontal wiring lower layer metal and the horizontal wiring upper layer metal and the vertical wiring portion pattern formed from the vertical wiring metal are both formed by lithography. Electronic components for wiring. 前記水平配線用下層金属と前記水平配線用上層金属の両方の水平配線部パターンは、同じパターンの重なる形となる請求項１に記載の配線用電子部品。 2. The wiring electronic component according to claim 1, wherein the horizontal wiring portion patterns of both the lower wiring metal for the horizontal wiring and the upper metal for the horizontal wiring overlap each other. 前記支持板として、板状のシリコン基板、ガラスのような絶縁体或いは導電体のいずれかを用いる請求項１に記載の配線用電子部品。 The wiring electronic component according to claim 1, wherein a plate-like silicon substrate, an insulator such as glass, or a conductor is used as the support plate. 前記薄膜テープとして、一層の薄膜フィルム或いは接着剤により接着した２層以上の薄膜フィルムの絶縁基材を用いる請求項１に記載の配線用電子部品。 The wiring electronic component according to claim 1, wherein the thin film tape is a single layer thin film or an insulating base material of two or more thin films bonded by an adhesive. 半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージに組み込んで用いるための配線用電子部品の製造方法において、
水平配線用下層金属と、水平配線用上層金属と、垂直配線用金属から成る少なくとも３層の金属層を積層した金属積層材を形成し、
水平配線用下層金属のパターニングを行い、
前記水平配線用下層金属とは異なるエッチングレートの金属から選ばれる水平配線用上層金属のパターニングを、前記水平配線用下層金属パターンをマスクとして行って、前記水平配線用下層金属と前記水平配線用上層金属からなる水平配線部パターンを形成し、
前記水平配線部パターンを形成した前記金属積層材を、剥離可能の接着剤を用いて支持板の上に貼り付けた後、前記垂直配線用金属のパターニングを行って、前記水平配線部に接続された垂直配線部を形成することからなる配線用電子部品の製造方法。In a method of manufacturing an electronic component for wiring to be used by arranging a circuit element including a semiconductor chip and incorporating it in an electronic device package having a horizontal wiring portion and a vertical wiring portion connected to the circuit element and external electrodes,
Forming a metal laminate in which at least three metal layers made of a lower wiring metal for horizontal wiring, an upper metal for horizontal wiring, and a metal for vertical wiring are stacked;
Patterning the lower layer metal for horizontal wiring,
Patterning of the upper metal for horizontal wiring selected from the metal having an etching rate different from that of the lower metal for horizontal wiring is performed using the lower metal pattern for horizontal wiring as a mask, and the lower metal for horizontal wiring and the upper layer for horizontal wiring Form a horizontal wiring pattern made of metal,
After the metal laminate having the horizontal wiring pattern formed thereon is attached to a support plate using a peelable adhesive, the metal for vertical wiring is patterned to be connected to the horizontal wiring section. A method of manufacturing a wiring electronic component comprising forming a vertical wiring portion. 前記水平配線部パターンを形成した前記金属積層材を前記支持板の上に貼り付ける際に、該支持板に貼り付ける前に、薄膜テープの上に貼り付け、その後、この薄膜テープを剥離可能の接着剤を用いて前記支持板の上に貼り付ける請求項８に記載の配線用電子部品の製造方法。 When the metal laminate material with the horizontal wiring pattern formed thereon is attached to the support plate, it is attached to the thin film tape before being attached to the support plate, and then the thin film tape can be peeled off. The manufacturing method of the electronic component for wiring of Claim 8 affixed on the said support plate using an adhesive agent. 前記薄膜テープは、前記電子デバイスパッケージにおいて水平配線部を覆う保護膜として機能する請求項９に記載の配線用電子部品の製造方法。 The method of manufacturing an electronic component for wiring according to claim 9, wherein the thin film tape functions as a protective film that covers a horizontal wiring portion in the electronic device package. 前記水平配線用下層金属及び前記水平配線用上層金属から形成される水平配線部パターン、及び前記垂直配線用金属から形成される垂直配線部パターンは、いずれもリソグラフィにより形成される請求項８に記載の配線用電子部品の製造方法。 9. The horizontal wiring part pattern formed from the horizontal wiring lower layer metal and the horizontal wiring upper layer metal and the vertical wiring part pattern formed from the vertical wiring metal are both formed by lithography. Manufacturing method of electronic parts for wiring. 前記水平配線用下層金属と前記水平配線用上層金属の両方の水平配線部パターンは、同じパターンの重なる形となる請求項８に記載の配線用電子部品の製造方法。 9. The method of manufacturing an electronic component for wiring according to claim 8, wherein horizontal wiring portion patterns of both the lower wiring metal for horizontal wiring and the upper metal for horizontal wiring are overlapped with each other. 前記支持板として、板状のシリコン基板、ガラスのような絶縁体或いは導電体のいずれかを用いる請求項８に記載の配線用電子部品の製造方法。 The method of manufacturing an electronic component for wiring according to claim 8, wherein a plate-like silicon substrate, an insulator such as glass, or a conductor is used as the support plate. 半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージに組み込んで用いるための配線用電子部品の製造方法において、
水平配線用下層金属と、水平配線用上層金属と、垂直配線用金属から成る少なくとも３層の金属層を積層した金属積層材を形成し、
水平配線用上層金属とは異なるエッチングレートの金属から選ばれる水平配線用下層金属のパターニングを行い、
水平配線用下層金属パターンを形成した金属積層材を、薄膜テープの上に接着剤を用いて貼り付け、
この金属積層材を接着した薄膜テープを、支持板の上に剥離可能の接着剤を用いて貼り付けた後、前記垂直配線用金属のパターニング及び水平配線用上層金属のパターニングを行うことからなる配線用電子部品の製造方法。In a method of manufacturing an electronic component for wiring to be used by arranging a circuit element including a semiconductor chip and incorporating it in an electronic device package having a horizontal wiring portion and a vertical wiring portion connected to the circuit element and external electrodes,
Forming a metal laminate in which at least three metal layers made of a lower wiring metal for horizontal wiring, an upper metal for horizontal wiring, and a metal for vertical wiring are stacked;
Perform patterning of the lower layer metal for horizontal wiring selected from metals with different etching rates from the upper layer metal for horizontal wiring,
Paste the metal laminate with the lower layer metal pattern for horizontal wiring onto the thin film tape using an adhesive,
Wiring formed by pasting the thin film tape to which the metal laminate is bonded using a peelable adhesive on the support plate, and then patterning the metal for vertical wiring and patterning the upper layer metal for horizontal wiring. Method for manufacturing electronic parts. 半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージに組み込んで用いるための配線用電子部品の製造方法において、
水平配線用下層金属と、水平配線用上層金属と、垂直配線用金属から成る少なくとも３層の金属層を積層した金属積層材を形成し、
水平配線用上層金属とは異なるエッチングレートの金属から選ばれる水平配線用下層金属のパターニングを行い、
水平配線用下層金属パターンを形成した金属積層材を、薄膜テープの上に接着剤を用いて貼り付け、
前記垂直配線用金属のパターニング及び水平配線用上層金属のパターニングを行ない、そして、
このパターニングした金属積層材を接着した薄膜テープを、支持板の上に剥離可能の接着剤を用いて貼り付けることからなる配線用電子部品の製造方法。In a method of manufacturing an electronic component for wiring to be used by arranging a circuit element including a semiconductor chip and incorporating it in an electronic device package having a horizontal wiring portion and a vertical wiring portion connected to the circuit element and external electrodes,
Forming a metal laminate in which at least three metal layers made of a lower wiring metal for horizontal wiring, an upper metal for horizontal wiring, and a metal for vertical wiring are stacked;
Perform patterning of the lower layer metal for horizontal wiring selected from metals with different etching rates from the upper layer metal for horizontal wiring,
Paste the metal laminate with the lower layer metal pattern for horizontal wiring onto the thin film tape using an adhesive,
Patterning the metal for vertical wiring and patterning the upper layer metal for horizontal wiring; and
A method of manufacturing an electronic component for wiring, comprising attaching a thin film tape to which a patterned metal laminate is bonded using a peelable adhesive on a support plate. 半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージにおいて、
配線用電子部品を、支持板と、該支持板の上に剥離可能の接着剤を用いて貼り付けられる２層の水平配線用下層金属及び前記水平配線用上層金属から形成される水平配線部、及び該水平配線部に接続された垂直配線部により構成し、
前記水平配線部及び前記垂直配線部は、水平配線用下層金属と、該水平配線用下層金属とは異なるエッチングレートの金属から選ばれ、かつ前記水平配線用下層金属の配線パターンをマスクとしてパターニングされる水平配線用上層金属と、垂直配線用金属との少なくとも３層の金属層を積層した金属積層材を加工することにより形成され、
前記配線用電子部品の前記垂直配線部を、基板上の配線層の所定位置に接続しかつ固定して樹脂封止した後、前記支持板を剥離することにより露出した前記水平配線部と接続される前記外部電極を形成したことから成る電子デバイスパッケージ。In an electronic device package in which a circuit element including a semiconductor chip is arranged and a horizontal wiring part and a vertical wiring part connected to the circuit element and an external electrode are present,
A horizontal wiring portion formed of a support plate, a two-layer horizontal wiring lower layer metal and a horizontal wiring upper layer metal that are attached to the support plate using a peelable adhesive; And a vertical wiring portion connected to the horizontal wiring portion,
The horizontal wiring portion and the vertical wiring portion are selected from a lower layer metal for horizontal wiring and a metal having an etching rate different from that of the lower layer metal for horizontal wiring, and are patterned using the wiring pattern of the lower layer metal for horizontal wiring as a mask. Formed by processing a metal laminate in which at least three metal layers of a horizontal wiring upper layer metal and a vertical wiring metal are laminated,
The vertical wiring portion of the wiring electronic component is connected to a predetermined position of the wiring layer on the substrate and fixed and sealed with resin, and then connected to the horizontal wiring portion exposed by peeling the support plate. An electronic device package formed by forming the external electrode. 前記配線用電子部品は、さらに、前記水平配線部を形成した前記金属積層材を貼り付けた薄膜テープを備え、前記支持板の上に貼り付ける際に、この薄膜テープを剥離可能の接着剤を用いて貼り付け、かつ、前記支持板を剥離することにより露出した前記薄膜テープを保護膜として用いる請求項１６に記載の電子デバイスパッケージ。 The wiring electronic component further includes a thin film tape to which the metal laminate material on which the horizontal wiring portion is formed is pasted, and an adhesive capable of peeling the thin film tape when pasted on the support plate. The electronic device package according to claim 16, wherein the thin film tape that is attached by using and exposed by peeling off the support plate is used as a protective film. 配線層を有する前記基板がガラス基板又は光透過性の良い透明樹脂基板であり、該基板上に配置される回路素子がイメージセンサである請求項１６に記載の電子デバイスパッケージ。 The electronic device package according to claim 16, wherein the substrate having a wiring layer is a glass substrate or a transparent resin substrate having good light transmission, and the circuit element disposed on the substrate is an image sensor. 配線層を有する前記基板がヒートシンク或いはヒートスプレッダーとして機能する高放熱基板であり、該基板上に配置される回路素子が高放熱型のLSIチップである請求項１６に記載の電子デバイスパッケージ。 The electronic device package according to claim 16, wherein the substrate having a wiring layer is a high heat dissipation substrate that functions as a heat sink or a heat spreader, and the circuit element disposed on the substrate is a high heat dissipation LSI chip. 半導体チップを含む回路素子を配置して、該回路素子と外部電極に接続される水平配線部及び垂直配線部が内在する電子デバイスパッケージの製造方法において、
配線用電子部品を、支持板と、該支持板の上に剥離可能の接着剤を用いて貼り付けられる２層の水平配線用下層金属及び前記水平配線用上層金属から形成される水平配線部、及び該水平配線部に接続された垂直配線部により構成し、
前記水平配線部及び前記垂直配線部は、水平配線用下層金属と、該水平配線用下層金属とは異なるエッチングレートの金属から選ばれ、かつ前記水平配線用下層金属の配線パターンをマスクとしてパターニングされる水平配線用上層金属と、垂直配線用金属との少なくとも３層の金属層を積層した金属積層材を加工することにより形成され、
前記配線用電子部品の前記垂直配線部を、基板上の配線層の所定位置に接続しかつ固定して樹脂封止した後、前記支持板を剥離することにより露出した前記水平配線部と接続される前記外部電極を形成したことから成る電子デバイスパッケージの製造方法。In a method for manufacturing an electronic device package in which a circuit element including a semiconductor chip is arranged and a horizontal wiring part and a vertical wiring part connected to the circuit element and an external electrode are present,
A horizontal wiring portion formed of a support plate, a two-layer horizontal wiring lower layer metal and a horizontal wiring upper layer metal that are attached to the support plate using a peelable adhesive; And a vertical wiring portion connected to the horizontal wiring portion,
The horizontal wiring portion and the vertical wiring portion are selected from a lower layer metal for horizontal wiring and a metal having an etching rate different from that of the lower layer metal for horizontal wiring, and are patterned using the wiring pattern of the lower layer metal for horizontal wiring as a mask. Formed by processing a metal laminate in which at least three metal layers of a horizontal wiring upper layer metal and a vertical wiring metal are laminated,
The vertical wiring portion of the wiring electronic component is connected to a predetermined position of the wiring layer on the substrate and fixed and sealed with resin, and then connected to the horizontal wiring portion exposed by peeling the support plate. An electronic device package manufacturing method comprising forming the external electrode. 前記配線用電子部品は、さらに、前記水平配線部を形成した前記金属積層材に貼り付けた薄膜テープを備え、前記支持板の上に貼り付ける際に、この薄膜テープを剥離可能の接着剤を用いて貼り付け、かつ、前記支持板を剥離することにより露出した前記薄膜テープを保護膜として用いる請求項２０に記載の電子デバイスパッケージの製造方法。
The wiring electronic component further includes a thin film tape attached to the metal laminated material on which the horizontal wiring portion is formed, and an adhesive capable of peeling the thin film tape when being attached on the support plate. 21. The method of manufacturing an electronic device package according to claim 20, wherein the thin film tape exposed by attaching and peeling the support plate is used as a protective film.
JP2010541993A 2008-12-10 2009-12-03 WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD Expired - Fee Related JP5429890B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010541993A JP5429890B2 (en) 2008-12-10 2009-12-03 WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2008314400 2008-12-10
JP2008314400 2008-12-10
JP2009056248 2009-03-10
JP2009056248 2009-03-10
JP2010541993A JP5429890B2 (en) 2008-12-10 2009-12-03 WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD
PCT/JP2009/006580 WO2010067548A1 (en) 2008-12-10 2009-12-03 Electronic component for wiring, method for manufacturing the electronic component, electronic device package to be used with the electronic component packaged therein, and method for manufacturing the electronic device package

Publications (2)

Publication Number Publication Date
JPWO2010067548A1 JPWO2010067548A1 (en) 2012-05-17
JP5429890B2 true JP5429890B2 (en) 2014-02-26

Family

ID=42242545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010541993A Expired - Fee Related JP5429890B2 (en) 2008-12-10 2009-12-03 WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD

Country Status (3)

Country Link
JP (1) JP5429890B2 (en)
TW (1) TW201025516A (en)
WO (1) WO2010067548A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6314070B2 (en) * 2014-10-07 2018-04-18 新光電気工業株式会社 Fingerprint recognition semiconductor device, method for manufacturing fingerprint recognition semiconductor device, and semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206599A (en) * 1991-11-14 1993-08-13 Hitachi Chem Co Ltd Printed wiring board metal foil and manufacture thereof and manufacture of wiring board provided with metal foil
JPH085664A (en) * 1994-06-22 1996-01-12 Hitachi Chem Co Ltd Inspection board for semiconductor device and its production
JPH1167823A (en) * 1997-08-08 1999-03-09 Hitachi Chem Co Ltd Manufacture of wiring board with bump and semiconductor package
WO2000076279A1 (en) * 1999-06-03 2000-12-14 Toyo Kohan Co.,Ltd. Process for producing printed wiring board, ic card and printed wiring substrate
JP2006086339A (en) * 2004-09-16 2006-03-30 Tdk Corp Multilayer substrate and its manufacturing method
WO2008065896A1 (en) * 2006-11-28 2008-06-05 Kyushu Institute Of Technology Method for manufacturing semiconductor device having dual-face electrode structure and semiconductor device manufactured by the method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206599A (en) * 1991-11-14 1993-08-13 Hitachi Chem Co Ltd Printed wiring board metal foil and manufacture thereof and manufacture of wiring board provided with metal foil
JPH085664A (en) * 1994-06-22 1996-01-12 Hitachi Chem Co Ltd Inspection board for semiconductor device and its production
JPH1167823A (en) * 1997-08-08 1999-03-09 Hitachi Chem Co Ltd Manufacture of wiring board with bump and semiconductor package
WO2000076279A1 (en) * 1999-06-03 2000-12-14 Toyo Kohan Co.,Ltd. Process for producing printed wiring board, ic card and printed wiring substrate
JP2006086339A (en) * 2004-09-16 2006-03-30 Tdk Corp Multilayer substrate and its manufacturing method
WO2008065896A1 (en) * 2006-11-28 2008-06-05 Kyushu Institute Of Technology Method for manufacturing semiconductor device having dual-face electrode structure and semiconductor device manufactured by the method

Also Published As

Publication number Publication date
TW201025516A (en) 2010-07-01
JPWO2010067548A1 (en) 2012-05-17
WO2010067548A1 (en) 2010-06-17

Similar Documents

Publication Publication Date Title
KR101193416B1 (en) Three-dimensionally integrated semiconductor device and method for manufacturing the same
JP2592038B2 (en) Semiconductor chip mounting method and substrate structure
US6706564B2 (en) Method for fabricating semiconductor package and semiconductor package
US8230591B2 (en) Method for fabricating an electronic device substrate
JP3813402B2 (en) Manufacturing method of semiconductor device
KR101150322B1 (en) Semiconductor chip package and manufacturing method thereof
JP4171499B2 (en) Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
JP6244147B2 (en) Manufacturing method of semiconductor device
JP2005209689A (en) Semiconductor device and its manufacturing method
JP2005217225A (en) Semiconductor device and method for manufacturing the same
JP2008016729A (en) Manufacturing method for semiconductor device with double-sided electrode structure
JP4498378B2 (en) Substrate and manufacturing method thereof, circuit device and manufacturing method thereof
US6271057B1 (en) Method of making semiconductor chip package
US20040124516A1 (en) Circuit device, circuit module, and method for manufacturing circuit device
JP5665020B2 (en) Manufacturing method of electronic parts for wiring
JP2010245157A (en) Component for wiring and method of manufacturing the same, and electronic device package used by incorporating the component for wiring and method of manufacturing the same
JP5429890B2 (en) WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE PACKAGE USING THE WIRING ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD
JP2008198916A (en) Semiconductor device and manufacturing method thereof
JP5491722B2 (en) Semiconductor device package structure and manufacturing method thereof
WO2010058595A1 (en) Electronic component for wiring and method for manufacturing same, and electronic device package with built-in electronic component for wiring and method for manufacturing same
JP2010161101A (en) Wiring electronic component, method of manufacturing the same, electronic device package used with the wiring electronic component incorporated, and method of manufacturing the same
CN215266271U (en) Front and back chip integrated packaging structure based on copper foil carrier plate
JP5115241B2 (en) Electronic component mounting method
JP5982414B2 (en) Semiconductor device package structure and manufacturing method thereof
JP5121857B2 (en) Substrate and manufacturing method thereof, circuit device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121116

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131126

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131128

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees