JP5427394B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 29
- 238000007650 screen-printing Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 28
- 239000011800 void material Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Description
本発明の要部は、半導体基板1の裏面に形成されるバンプ電極9に係るものなので以下の図面も、半導体基板1の全体の記載は省略して、発明の要部であるバンプ電極9周囲についてのみ記載して説明を進める。先ず、図1(a)に示すように、その内部に拡散処理等により種々の半導体素子が形成された半導体基板1の主面に、酸化膜等からなる第1の絶縁膜2を介して、第1の配線3を形成する。第1の配線3は、例えばAlまたはCu等を主体とする金属層から成り、半導体基板1内に形成された半導体素子と電気的に接続され、その表面には保護用の絶縁膜4が形成される。この場合、図1(b)に示すように、絶縁膜4の上部に接着層10を介してガラス、シリコン、プラスチック等から成る支持体11を形成しても良い。
5 開口部 6 第2の絶縁膜 7 第2の配線 8 ハンダ層
9 バンプ電極 10 接着層 11 支持体 12 傾斜部
21 半導体基板 22 第1の配線 24 開口部 25 第2の絶縁膜
26 第2の配線 27 ハンダ層 28 バンプ電極 29 ボイド
30 保護膜 31 残存気体
Claims (7)
- 半導体基板の主面に第1の絶縁膜を介して第1の配線を形成する工程と、
前記第1の配線を露出するために、前記半導体基板の裏面から当該半導体基板に開口部を形成する工程と、
前記開口部及び前記裏面上に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上に、前記第1の配線と接続し前記開口部内から前記裏面上まで延在する第2の配線を形成する工程と、
前記第1の配線上の前記第2の配線の一部並びに当該第2の配線の一部から延在する前記開口部の側壁の前記第2の配線と接続し、前記裏面上の前記第2の配線上から該第2の配線の外側の前記裏面領域上まで延在するハンダ層を形成する工程と、
前記ハンダ層をリフローする工程と、を含むことを特徴とする半導体装置の製造方法。 - 半導体基板の主面に第1の絶縁膜を介して第1の配線を形成する工程と、
前記第1の配線を露出するために、前記半導体基板の裏面から当該半導体基板に開口部を形成する工程と、
前記開口部及び前記裏面上に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上に、前記第1の配線と接続し前記開口部内から前記裏面上まで延在する第2の配線を形成する工程と、
前記開口部を除く前記半導体基板の前記裏面上の前記第2の配線を含む前記裏面領域上にハンダ層を形成する工程と、
前記ハンダ層をリフローする工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記ハンダ層が前記第2の配線を含む前記裏面領域上に前記開口部を囲んで形成されていることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記ハンダ層がスクリーン印刷法で形成されることを特徴とする請求項1乃至請求項3のいずれかに記載の半導体装置の製造方法。
- 前記ハンダ層がディスペンス法で形成されることを特徴とする請求項1乃至請求項3のいずれかに記載の半導体装置の製造方法。
- 前記開口部が前記裏面側で広く、主面側で狭くなる傾斜面を有していることを特徴とする請求項1乃至請求項5のいずれかに記載の半導体装置の製造方法。
- 前記開口部が円筒状に形成されていることを特徴とする請求項1乃至請求項6のいずれかに記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008297573A JP5427394B2 (ja) | 2008-11-21 | 2008-11-21 | 半導体装置の製造方法 |
CN200910208198.1A CN101740426B (zh) | 2008-11-21 | 2009-11-02 | 半导体装置的制造方法 |
US12/591,491 US8193084B2 (en) | 2008-11-21 | 2009-11-20 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008297573A JP5427394B2 (ja) | 2008-11-21 | 2008-11-21 | 半導体装置の製造方法 |
Publications (2)
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US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101366461B1 (ko) | 2012-11-20 | 2014-02-26 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR101607981B1 (ko) | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지 |
US9219044B2 (en) * | 2013-11-18 | 2015-12-22 | Applied Materials, Inc. | Patterned photoresist to attach a carrier wafer to a silicon device wafer |
JP2017069380A (ja) * | 2015-09-30 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10134708B2 (en) | 2016-08-05 | 2018-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with thinned substrate |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
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JPH05200974A (ja) * | 1992-01-28 | 1993-08-10 | Fujitsu Ltd | スクリーン印刷方法 |
JP3267167B2 (ja) * | 1995-09-20 | 2002-03-18 | 富士通株式会社 | 半導体装置とその製造方法 |
TW396462B (en) * | 1998-12-17 | 2000-07-01 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
US6380060B1 (en) * | 2000-03-08 | 2002-04-30 | Tessera, Inc. | Off-center solder ball attach and methods therefor |
JP2002100860A (ja) * | 2000-09-22 | 2002-04-05 | Ibiden Co Ltd | プリント配線板の製造方法 |
JP2002353606A (ja) * | 2002-05-27 | 2002-12-06 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2005303258A (ja) * | 2004-03-16 | 2005-10-27 | Fujikura Ltd | デバイス及びその製造方法 |
CN1832658A (zh) * | 2005-03-10 | 2006-09-13 | 3M创新有限公司 | 一种双层金属的柔性印刷电路板及其制造方法 |
TWI288447B (en) * | 2005-04-12 | 2007-10-11 | Siliconware Precision Industries Co Ltd | Conductive bump structure for semiconductor device and fabrication method thereof |
JP2007165696A (ja) | 2005-12-15 | 2007-06-28 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
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US8193084B2 (en) | 2012-06-05 |
US20100130000A1 (en) | 2010-05-27 |
CN101740426B (zh) | 2012-05-30 |
CN101740426A (zh) | 2010-06-16 |
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