JP5419730B2 - Thin film transistor - Google Patents

Description

The present invention relates to a thin film transistor motor, in particular, it relates to a structure of a thin film transistor used in a semiconductor device such as an electro-optical display device, a semiconductor component such as a liquid crystal display or an organic EL display.

  A thin film transistor (Thin Film Transistor: TFT) using a thin film semiconductor layer is used for a pixel switching element of a liquid crystal display device, and the TFT is formed as follows, for example.

  A gate electrode material is formed by sputtering, and a gate electrode is formed by photolithography and etching. Next, an SiN film serving as a gate insulating film, an amorphous silicon film serving as an i-type semiconductor, and an N-type amorphous silicon film serving as an N-type semiconductor are formed by plasma CVD (Chemical Vapor Deposition). Further, a source / drain electrode material is formed by sputtering, and a source / drain electrode is formed by photolithography and etching. The N-type amorphous silicon film in the region between the source and drain electrodes is removed by dry etching. Further, a desired resist pattern is formed by photolithography and unnecessary portions are removed by etching. Next, a SiN film serving as a protective film is formed by plasma CVD. As described above, an inverted staggered TFT using amorphous silicon for the channel portion silicon thin film can be formed.

  In recent years, in order to realize a narrow frame and cost reduction of a liquid crystal display device and an organic EL (Electro-Luminescence) display device, driving not only as a pixel switching element but also a source driver and a gate driver using a TFT. A display device in which a circuit is formed on the same glass substrate as a pixel portion has been developed.

  Compared with a TFT used as a pixel switching element, a larger driving voltage is continuously applied to the TFT in the driving circuit for a long time, so that the electrical characteristics are greatly deteriorated. For this reason, it has also been proposed to manufacture a TFT having higher stability by using microcrystalline silicon by a plasma CVD method as the channel portion silicon thin film in the TFT described above. Such a TFT (microcrystalline silicon TFT) in which microcrystalline silicon is formed on a channel part silicon thin film has a TFT compared with a TFT (amorphous silicon TFT) in which amorphous silicon is formed on a channel part silicon thin film. It has a feature that a change with time of the threshold voltage (Vth) generated by continuously applying a voltage to the gate electrode can be suppressed to a small value.

  However, since the band gap of microcrystalline silicon TFT is narrower than that of amorphous silicon, the microcrystalline silicon TFT has an interface between the microcrystalline silicon and the N-type amorphous silicon when a reverse bias is applied to the gate electrode. There is a problem that hole injection is easily caused by band-to-band tunneling and leakage current increases. Patent Document 1 discloses that by interposing amorphous silicon between microcrystalline silicon and N-type amorphous silicon, mismatching of the interface band gap can be reduced and leakage current can be suppressed. Yes.

  Here, in the case of displaying an image on a liquid crystal panel, there is a problem of light leakage current generated when the TFT is irradiated with light from the backlight on the back surface.

  When light from the backlight is irradiated to the microcrystalline silicon film or the amorphous silicon film, electron-hole pairs are generated in the semiconductor. The generated electrons move to the drain electrode to which a positive voltage is applied, and the generated holes move to the zero-potential source electrode, resulting in a light leakage current. If this light leakage current flows when the gate electrode is fixed at 0 potential or a negative voltage, there is a problem that the voltage written in the electrode of the pixel capacitor, that is, the charge accumulated in the capacitor disappears due to the light leakage current. Occurs and normal image display cannot be performed.

  In order to prevent the occurrence of this light leakage current, it is conceivable to dispose the semiconductor layer in a region included in the gate electrode in plan view. When the semiconductor layer is disposed so as to exist only in the region included in the gate electrode, it is natural that light from the backlight is normally blocked by the gate electrode formed of metal and does not reach the semiconductor layer. For this reason, no light leakage current occurs.

However, an arrangement in which a semiconductor layer including a microcrystalline silicon layer exists only in a region included in the gate electrode causes a new problem. In the conventional structure, the side surface of the microcrystalline silicon film is in contact with the drain electrode made of metal, and is in the off state, that is, the drain electrode has a positive voltage, the source electrode has a zero voltage, and the gate electrode has a negative voltage. In this state, a large electric field is applied because the end of the microcrystalline silicon film on the drain electrode side is close to the gate electrode. For this reason, holes are injected from the drain electrode into the microcrystalline silicon film beyond the Schottky barrier at the Schottky connection portion between the drain electrode and the microcrystalline silicon film, resulting in leakage current. The hole mobility of the microcrystalline silicon film is very large as compared to the case of an amorphous silicon (about ^{0.001cm 2 / Vs) (0.1~2cm 2} / Vs) for, in the microcrystalline silicon TFT, This leakage current becomes larger than that of a TFT using an amorphous silicon film. For this reason, there is a problem that normal image display cannot be performed.

As a solution to such a problem, a microcrystalline silicon TFT as disclosed in Patent Document 2 is disclosed. That is, an insulating film (SiO ₂ film) is formed on all side surfaces of the microcrystalline silicon film, amorphous silicon, and N-type amorphous silicon that are stacked semiconductor layers. With this structure, leakage current generated when holes are injected from the drain electrode into the microcrystalline silicon film can be suppressed. The structure is formed by forming a SiO ₂ film on the entire surface by plasma CVD, and then removing the SiO ₂ film formed on the surface (upper surface) of the semiconductor layer by an etch back method. Only the SiO ₂ film is left.

JP 2005-322845 A JP 2009-124121 A

However, in the case of manufacturing by the method as in Patent Document 2, an etching process for removing the insulating film on the upper surface of the semiconductor layer is required after forming the SiO ₂ film as the insulating film, which increases the cost, and plasma CVD. In this method, since a thick SiO ₂ film is not formed on the side surface, there is a problem in mass productivity, and the SiO ₂ film formed on the surface (upper surface) is removed by a dry etching method. There is a problem that the surface of the type amorphous silicon receives ion damage from the plasma.

The present invention has been made to solve the above-described problems. In a TFT in which a microcrystalline silicon film is formed on a gate electrode, an etching process is not required for forming a side insulating film, and mass production is achieved. An object of the present invention is to provide an excellent TFT capable of suppressing damage to the upper silicon film.

  The present invention is a thin film transistor comprising a gate electrode and a semiconductor layer stacked on the gate electrode through a gate insulating film in a region encompassed by the gate electrode in plan view, the semiconductor layer comprising: And an upper amorphous semiconductor layer and a lower microcrystalline semiconductor layer, and further comprising an insulating film formed on a side surface of the microcrystalline semiconductor layer and below the lower surface of the amorphous semiconductor layer. .

  According to the present invention, there is provided a thin film transistor comprising a gate electrode and a semiconductor layer stacked on the gate electrode via a gate insulating film in a region encompassed by the gate electrode in plan view, The layer includes an upper amorphous semiconductor layer and a lower microcrystalline semiconductor layer, and an insulating film formed on a side surface of the microcrystalline semiconductor layer and below the lower surface of the amorphous semiconductor layer. By providing further, a thin film transistor having good off characteristics in which an insulating film is formed on the side surface of the microcrystalline semiconductor layer without damaging the surface of the upper amorphous semiconductor layer can be obtained.

It is a top view which shows the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is a top view which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is sectional drawing according to process which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is sectional drawing according to process which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is sectional drawing according to process which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is sectional drawing according to process which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 1 of this invention. It is an expanded sectional view which shows the pixel part of the active matrix type TFT substrate for liquid crystal displays incorporating the gate driver which concerns on Embodiment 2 of this invention.

<A. Embodiment 1>
<A-1. Configuration>
As Embodiment 1 of the present invention, an active matrix TFT substrate with a built-in gate driver in a liquid crystal display device using liquid crystal as a display element will be described as an example. FIG. 1 shows a planar structure of a TFT array substrate. A gate driver unit 24 and a pixel unit 23 are formed in the TFT. Further, as shown in FIG. 1, the source wiring 14 and the gate wiring 3 are wired so as to cross each other.

  FIG. 2 is a diagram illustrating a planar structure of the pixel unit 23. As shown in the figure, an active matrix TFT substrate as a thin film transistor according to the present invention is formed on a gate electrode 2, a gate wiring 3 connected to the gate electrode 2, an auxiliary capacitance electrode 5, and the gate electrode 2. A microcrystalline silicon film 8 as a microcrystalline semiconductor layer, a source electrode 11 and a drain electrode 12 formed thereon, a source wiring 14 connected to the source electrode 11, and a pixel drain contact hole reaching the drain electrode 12 17, a source terminal contact hole 18 reaching the source terminal (not shown), a gate terminal contact hole 19 reaching the gate terminal (not shown), and the drain electrode 12 via the pixel drain contact hole 17. Through the transmissive pixel electrode 20 connected to the gate terminal contact hole 19 Comprising Te gate terminal portion and the gate terminal pad 21 to be connected to the (not shown), and a source terminal pad 22 connected to the source terminal portion (not shown) via the source terminal contact hole 18.

FIG. 3 is a diagram showing the structure of the AA cross section in FIG. As shown in FIG. 3, an active matrix TFT substrate as a thin film transistor according to the present invention includes a gate electrode 2 made of a metal film, a gate wiring 3, an image scanning signal on a transparent insulating substrate 1 made of glass, plastic or the like. Are input at least selectively, and a gate insulating film 6 made of silicon nitride (SiN) or silicon oxide (SiO ₂ ) is laminated.

  A microcrystalline silicon film 8 serving as a microcrystalline semiconductor layer is formed on gate electrode 2 with gate insulating film 6 interposed therebetween. Further, a non-doped amorphous silicon film 9 as an amorphous semiconductor layer and an N-type amorphous silicon film 10 to which an impurity is added as an amorphous semiconductor layer are stacked. The N-type amorphous silicon film 10 is formed so as to be separated from the channel portion 13. The semiconductor layer including the microcrystalline silicon film 8, the amorphous silicon film 9, and the N-type amorphous silicon film 10 is formed in a region included in the gate electrode 2 in plan view.

  An insulating film 81 is formed on the side surface of the microcrystalline silicon film 8 including the lower surface of the amorphous silicon film 9.

  A source electrode 11 and a drain electrode 12 are stacked in contact with the N-type amorphous silicon film 10, the amorphous silicon film 9, the insulating film 81, and the gate insulating film 6, respectively. Further, a source wiring 14 connected to the source electrode 11 and a source terminal portion 15 connected to the source wiring 14 and for inputting a video signal from the outside are further formed.

  An interlayer insulating film 16 made of SiN is laminated so as to cover them. The interlayer insulating film 16 is provided with a plurality of openings, a pixel drain contact hole 17 reaching the drain electrode 12, a source terminal contact hole 18 reaching the source terminal 15, and a gate terminal contact hole reaching the gate terminal 4. 19 are provided.

  Further, a transmissive pixel electrode 20 made of a transparent conductive film connected to the drain electrode 12 through the pixel drain contact hole 17, and a gate terminal pad 21 connected to the gate terminal portion 4 through the gate terminal contact hole 19 A source terminal pad 22 connected to the source terminal portion 15 through the source terminal portion contact hole 18 is provided.

  The active matrix TFT substrate configured as described above and a counter substrate (not shown) provided with a color filter for color display, a counter electrode, and the like are bonded to each other through a certain gap (cell gap). By injecting and sealing liquid crystal into this, a semiconductor device which is an optical display device for display use is manufactured.

<A-2. Manufacturing method>
Next, a procedure for manufacturing the pixel portion 23 of the active matrix TFT substrate incorporating the gate driver according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 4, first, the transparent insulating substrate 1 such as a glass substrate is cleaned using a cleaning liquid or pure water, and an Al alloy film is formed on the transparent insulating substrate 1 by sputtering to a thickness of 200 nm. In the second photolithography process, the Al alloy film is patterned to form the gate electrode 2, the gate wiring 3, the gate terminal portion 4, and the auxiliary capacitance electrode 5.

Next, the gate insulating film 6 is formed. The gate insulating film 6 is a laminated film of SiN and SiO ₂ . Of the gate insulating film 6, SiN is formed by a plasma CVD method in which SiH ₄ gas and NH ₃ gas are mixed, and the SiO ₂ film is formed by mixing SiH ₄ gas and N ₂ O gas. The conditions of the plasma CVD method are a substrate temperature of 200 to 400 ° C., a pressure of 100 to 200 Pa, a frequency of 13.56 MHz, and a power density of 0.1 W / cm ² . The film thickness is 100 nm for both the SiN film and the SiO ₂ film.

Next, a microcrystalline silicon film 8 to be a semiconductor active film is formed. The microcrystalline silicon film 8 is a plasma CVD apparatus, and the substrate temperature is 200 to 400 ° C., the pressure is 100 to 150 Pa, the frequency is 13.56 MHz, the power density is 0.1 W / cm ² , and the flow rate ratio between SiH ₄ gas and H ₂ gas is set. 1: 200 to 300, preferably SiH ₄ gas, H ₂ gas, and Ar gas are deposited at a flow ratio of 1: 100 to 300: 200 to 300, respectively. When Ar gas is mixed, a microcrystalline silicon film 8 having higher crystallinity at a higher temperature can be obtained. In the first embodiment, the deposition was performed at a substrate temperature of 300 ° C., a pressure of 150 Pa, and a SiH ₄ / H ₂ / Ar gas flow ratio of 1: 100: 250. The film thickness of the microcrystalline silicon film 8 was 30 nm.

Next, an amorphous silicon film 9 and an N-type amorphous silicon film 10 are deposited on the microcrystalline silicon film 8 (not shown). The amorphous silicon film 9 is a plasma CVD apparatus, and has a substrate temperature of 200 to 400 ° C., a pressure of 100 to 150 Pa, a frequency of 13.56 MHz, a power density of 0.1 W / cm ² , and a flow rate ratio of SiH ₄ gas and H ₂ gas. 1: 5 to 50, the N-type amorphous silicon film 10 has a substrate temperature of 200 to 400 ° C., a pressure of 100 to 150 Pa, a frequency of 13.56 MHz, a power density of 0.1 W / cm ² , SiH ₄ gas and H ₂ gas. the flow ratio of PH ₃ (phosphine) gas 1: 2-50: may be deposited at 3-20. In the first embodiment, the amorphous silicon film 9 has a substrate temperature of 300 ° C. and a pressure of 150 Pa, the SiH ₄ / H ₂ gas flow ratio is 1:20, and the N-type amorphous silicon film 10 has a substrate temperature of 300 ° C. and a pressure. Deposition was performed at 200 Pa, with a SiH ₄ / H ₂ / PH ₃ gas flow rate of 1:10:15. Note that the gate insulating film 6, the microcrystalline silicon film 8, the amorphous silicon film 9, and the N-type amorphous silicon film 10 were continuously formed while being kept in vacuum by the same plasma CVD apparatus. When a film is continuously formed while maintaining a vacuum, impurity contamination, oxidation, and the like of the film are suppressed, and a semiconductor film and an insulating film with good film quality can be obtained.

  As shown in FIG. 5, the microcrystalline silicon film 8, the amorphous silicon film 9, and the N-type amorphous silicon film 10 are patterned and formed in a shape that is a constituent element of the TFT by the second photolithography process. As shown in FIG. 5, the resist 7 is used. In this photolithography process, a semiconductor film, that is, a microcrystalline silicon film 8, an amorphous silicon film 9, and an N-type amorphous silicon film 10 are formed in a region included in the gate electrode 2 in plan view.

Next, as shown in FIG. 6, an insulating film 81 is formed on the side surface of the microcrystalline silicon film 8. The insulating film 81 is a parallel plate type plasma generator, the substrate temperature is room temperature to 200 ° C., the pressure is 1 to 150 Pa, the frequency is 13.56 MHz, the power density is 0.1 to 0.5 W / cm ² , and the flow rate of O ₂ gas is set. It was formed by oxidizing the side surface of the microcrystalline silicon film 8 at 10 to 200 sccm. In the first embodiment, with the resist 7 left, the substrate temperature was room temperature, the pressure was 50 Pa, the frequency was 13.56 MHz, the power density was 0.2 W / cm ² , and the flow rate of O ₂ gas was 100 sccm for 5 minutes. By this oxidation process, an insulating film (SiO ₂ film) 81 was formed in a thickness of 5 nm in the direction of arrow B in FIG. This 5 nm insulating film 81, which is an SiO ₂ film, protrudes 3 nm on the side surface of the microcrystalline silicon film 8 from the lower surface of the amorphous silicon film 9 to the outside in plan view of the microcrystalline silicon film 8. 2 nm was formed under the lower surface of the quality silicon film 9. Further, the side surfaces of the amorphous silicon film 9 and the N-type amorphous silicon film 10 are hardly oxidized by this oxidation process. This is because the microcrystalline silicon film 8 includes many crystal grain boundaries, and oxygen enters the inside of the microcrystalline silicon film 8 along the grain boundaries, so that the oxidation rate becomes higher than that of amorphous silicon. is there. The oxidation time of this oxygen plasma is preferably set to 10 minutes or less. The oxygen plasma also ashes the resist 7 and the film thickness becomes thin. Therefore, when the oxidation is performed for a long time, the resist 7 disappears and the surface of the N-type amorphous silicon film 10 is damaged. It is necessary to determine the oxidation time of the oxygen plasma within a range where the resist 7 does not disappear.

After the SiO ₂ film as the insulating film 81 is formed, a TFT is manufactured by a normal process. After removing the resist 7 with a sulfuric acid solution or the like, as shown in FIG. 7, after forming an Al alloy film to be the source electrode 11 and the drain electrode 12, the source electrode is patterned by the third photolithography process. 11, a drain electrode 12, a source wiring 14, a source terminal portion 15, and a TFT channel portion 13 are formed. The channel portion 13 is formed by etching the N-type amorphous silicon film 10 after forming the source electrode 11 and the drain electrode 12.

  Next, as shown in FIG. 3, after the interlayer insulating film 16 is formed as a passivation film, patterning is performed by a fourth photolithography process, and at least the pixel drain contact hole 17 penetrating to the surface of the drain electrode 12 is formed. The source terminal portion contact hole 18 that penetrates to the surface of the source terminal portion 15 and the gate terminal portion contact hole 19 that penetrates to the surface of the gate terminal portion 4 are formed simultaneously.

  Finally, in FIG. 3, after forming a transparent conductive film, patterning is performed by a fifth photolithography process so that the transmissive pixel is electrically connected to the drain electrode 12 through the pixel drain contact hole 17. The electrode 20 and the pattern of the gate terminal pad 21 and the source terminal pad 22 that are electrically connected through the source terminal contact hole 18 and the gate terminal contact hole 19 are formed, respectively. Thus, an active matrix TFT substrate that is suitably used as a liquid crystal display device application is completed. The completed TFT substrate may be subjected to heat treatment at a temperature of about 200 to 350 ° C.

  This is preferable because electrostatic charges, stresses, and the like accumulated on the entire substrate can be removed or relaxed, the electrical specific resistance of the metal film can be lowered, and the TFT characteristics can be improved and stabilized. Although the manufacturing method of the pixel portion 23 has been described here, the gate driver portion 24 is also formed at the same time. Although the parallel plate type plasma generator is used in the first embodiment, an inductively coupled plasma generator may be used.

Further, it may be oxidized with ozone (O ₃ ) instead of oxygen plasma. When oxidizing with O ₃ , in a single wafer or batch type oxidation furnace, the substrate temperature is room temperature to 400 ° C., atmospheric pressure, and air containing an O ₃ concentration of 10 to 200 g / m ³ is supplied at a flow rate of 0.5 to 10 liters. / Min. In this case, there is no problem even if there is moisture in the air containing O ₃ . When the substrate temperature is room temperature, atmospheric pressure, and air containing an O ₃ concentration of 100 g / m ³ is oxidized at a flow rate of 2 liters / minute, the thickness of the SiO ₂ film as the insulating film 81 (the length of the arrow B in FIG. 6) Was 4 nm.

  The microcrystalline silicon film 8 is preferably formed with a thickness of 30 nm or less. Since the microcrystalline silicon film 8 has a high hole mobility as described above, the off-resistance in the channel direction is small, which causes an increase in leakage current. When the thickness of the microcrystalline silicon film 8 is reduced, the resistance in the channel direction can be increased, so that leakage current can be reduced.

  In the configuration described above, the manufacturing process of the channel etch type TFT has been described here, but an etch stopper type TFT may be used.

  In the microcrystalline silicon TFT thus completed, the drain electrode 12 and the side surface of the microcrystalline silicon film 8 are not in direct contact while sufficiently suppressing the light leakage current, so that a large electric field is applied. Leakage current due to holes due to the lowering of the Schottky barrier is suppressed, and a high-quality liquid crystal display can be realized.

<A-3. Effect>
According to the first embodiment of the present invention, the gate electrode 2 and the semiconductor layer stacked on the gate electrode 2 via the gate insulating film 6 in the region included in the gate electrode 2 in plan view. The semiconductor layer includes an N-type amorphous silicon film 10 which is an upper amorphous semiconductor layer, an amorphous silicon film 9, and a microcrystalline silicon film 8 which is a lower microcrystalline semiconductor layer. And an insulating film 81 formed on the side surface of the microcrystalline silicon film 8 and below the lower surface of the amorphous silicon film 9, so that the insulating film 81 is formed on the side surface of the microcrystalline silicon film 8. Thus, a thin film transistor having good off characteristics can be obtained.

  Further, since the surface of the upper N-type amorphous silicon film 10 is not damaged, the electrical connection characteristics between the source electrode 11 and the drain electrode 12 and the N-type amorphous silicon film 10 are not deteriorated. .

  Further, according to the first embodiment of the present invention, in the method of manufacturing a thin film transistor, (a) a step of forming the gate electrode 2 and (b) a gate in a region included in the gate electrode 2 in plan view. An N-type amorphous silicon film 10 that is an upper amorphous semiconductor layer, an amorphous silicon film 9, and a microcrystalline silicon that is a lower microcrystalline semiconductor layer via a gate insulating film 6 on the electrode 2 A step of laminating a semiconductor layer including the film 8 and a step (c) of oxidizing the side surface of the microcrystalline silicon film 8 to form the insulating film 81 make it possible to form a microcrystal without an etching step. A thick insulating film 81 can be formed on the side surface of the silicon film 8, and a thin film transistor having good off characteristics can be obtained at low cost.

  In addition, according to the first embodiment of the present invention, in the method for manufacturing a thin film transistor, the step (b) uses a resist 7 to deposit the stacked semiconductor layers in a region included in the gate electrode 2 in plan view. In step (c), the resist 7 is used to oxidize the side surfaces of the microcrystalline silicon film 8 to form the insulating film 81. Also, the resist 7 used in the patterning step is arranged, and the surface of the upper N-type amorphous silicon film 10 is not damaged, and the source electrode 11, the drain electrode 12 and the N-type amorphous silicon film 10 are not damaged. A thin film transistor with good electrical connection characteristics can be obtained.

  Further, according to the first embodiment of the present invention, in the method of manufacturing a thin film transistor, the step (c) is a step of forming the insulating film 81 by oxidizing the side surface of the microcrystalline silicon film 8 using oxygen plasma. As a result, on the surface where the microcrystalline silicon film 8 and the drain electrode 12 in the vicinity of the gate electrode 2 are in contact with each other, generation of leakage current due to holes is suppressed at low cost, and a high-quality liquid crystal display can be obtained.

<B. Second Embodiment>
<B-1. Configuration>
As an embodiment 2 of the present invention, an active matrix TFT substrate with a built-in gate driver in a liquid crystal display device using a liquid crystal as a display element will be described as an example. The detailed description of the structure and manufacturing method similar to those of the first embodiment is omitted.

  FIG. 8 is an enlarged cross-sectional view of the pixel portion 23 of the TFT substrate. The difference from the first embodiment is that, as indicated by C in FIG. 8, the insulating film 82 is formed up to the upper surface side and the lower surface side of the portion in contact with the side surface of the microcrystalline silicon film 8, and has a bird's beak shape. That is. The active matrix TFT substrate configured as described above and a counter substrate (not shown) having a color filter for color display, a counter electrode, and the like are bonded to each other through a certain gap (cell gap). By injecting and sealing the liquid crystal therein, a semiconductor device which is an optical display device for display applications is manufactured.

<B-2. Manufacturing method>
Next, a procedure for manufacturing the pixel portion 23 of the active matrix TFT substrate incorporating the gate driver according to the second embodiment of the present invention will be described.

  The semiconductor film of FIGS. 4 to 5, that is, the microcrystalline silicon film 8, the amorphous silicon film 9, and the N-type amorphous silicon film 10 are formed by the same process as in the first embodiment until patterning with the resist 7. To do.

Next, an insulating film 82 is formed on the side surface of the microcrystalline silicon film 8. As shown in FIG. 6, the insulating film 82 is a parallel plate type plasma generator with the resist 7 left, and the substrate temperature is 150 ° C., the pressure is 50 Pa, the frequency is 13.56 MHz, and the power density is 0.3 W / cm. ² , O ₂ gas is formed at a flow rate of 100 sccm by oxidizing the side surfaces of the microcrystalline silicon film 8. That is, the substrate temperature and power density are set higher than those in the first embodiment. The oxidation time is 5 minutes as in the first embodiment. By this oxidation process, an insulating film (SiO ₂ film) 82 was formed as shown in FIG. This insulating film 82, which is a SiO ₂ film, is 4 nm on the side surface of the microcrystalline silicon film 8 from the lower surface of the amorphous silicon film 9 to the outer side in the plan view of the microcrystalline silicon film 8; A thickness of 3.5 nm was formed under the lower surface of 9.

In the second embodiment, since the set temperature at the time of oxidation is higher than that in the first embodiment, oxygen atoms are not only the crystal grain boundaries of the microcrystalline silicon film 8, but also the upper and lower gate insulating films 6 and amorphous. It also diffuses to the interface with the silicon film 9. Therefore, an insulating film (SiO ₂ film) 82 having a bird's beak shape at both interfaces as shown in FIG. 8C is obtained. In the second embodiment, the oxidation time is the same 5 minutes as in the first embodiment. However, in the second embodiment, the resist is cured because the substrate temperature is high. For this reason, the time during which the resist 7 is ashed and thinned becomes longer and can be oxidized for a longer time.

If the oxidation time is lengthened, the side surfaces of the amorphous silicon film 9 and the N-type amorphous silicon film 10 may be oxidized due to the high substrate temperature. When oxidized for 10 minutes, the side surfaces of the amorphous silicon film 9 and the N-type amorphous silicon film 10 were oxidized by 1.5 to 2 nm. As described above, when the SiO ₂ film is formed on the side surfaces of the amorphous silicon film 9 and the N-type amorphous silicon film 10 when the oxidation time is long, the diluted fluorination is performed before the source / drain electrodes are deposited. in hydrochloric acid (HF) may be removed SiO ₂ film on the side surface. Since the subsequent structure, manufacturing process, and method thereof are the same as those in the first embodiment, description thereof will be omitted. In the configuration described above, the manufacturing process of the channel etch type TFT has been described here, but an etch stopper type TFT may be used.

  In the microcrystalline silicon TFT thus completed, the hole injection from the drain electrode to the microcrystalline silicon film 8 is suppressed and good off characteristics can be obtained as in the first embodiment, and the insulating film 82 can be obtained. Has a bird's beak shape at the interface with the microcrystalline silicon film 8, the distance from the gate electrode 2 at the end of the microcrystalline silicon film 8 increases, and the electric field applied between the drain and gate electrodes. Therefore, there is an effect that the reliability of the transistor is improved and the product has a longer operating life.

<B-3. Effect>
According to the second embodiment of the present invention, in the thin film transistor, the insulating film 82 has a bird's beak shape that sinks into the lower surface side of the microcrystalline silicon film 8, so that it is applied at the end of the microcrystalline silicon film 8. Since the electric field is reduced, generation of leakage current can be suppressed, and the reliability of the transistor can be improved.

  Further, according to the second embodiment of the present invention, in the method for manufacturing a thin film transistor, the step of (c) oxidizing the side surface of the microcrystalline silicon film 8 to form the insulating film 81 By forming the insulating film 82 having a bird's beak shape that sinks into the lower surface side, the electric field applied at the end of the microcrystalline silicon film 8 is reduced. Reliability can be improved.

<C. Modification>
In the first and second embodiments, the gate insulating film 6 is formed of a two-layer laminated film of silicon nitride (SiN) and silicon oxide (SiO ₂ ) film. However, the gate insulating film 6 is formed of silicon nitride or silicon oxide. You may form only with a film | membrane. Further, if the insulating films 81 and 82 in contact with the microcrystalline silicon film 8 are SiO ₂ films containing Ar or silicon oxide films (SiOx) containing less oxygen, the crystallinity of the microcrystalline silicon film 8 is improved. A microcrystalline silicon TFT having good characteristics can be obtained. Furthermore, the present invention is also effective in organic EL because leakage current due to holes can be suppressed.

  DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate, 2 Gate electrode, 3 Gate wiring, 4 Gate terminal part, 5 Auxiliary capacity electrode, 6 Gate insulating film, 7 Resist, 8 Microcrystalline silicon film, 9 Amorphous silicon film, 10 N-type amorphous Silicon film, 11 source electrode, 12 drain electrode, 13 channel part, 14 source wiring, 15 source terminal part, 16 interlayer insulating film, 17 pixel drain contact hole, 18 source terminal part contact hole, 19 gate terminal part contact hole, 20 transmissive pixel electrode, 21 gate terminal pad, 22 source terminal pad, 23 pixel portion, 24 gate driver portion, 81, 82 insulating film.

Claims (2)

A gate electrode;
A thin film transistor including a semiconductor layer stacked on the gate electrode through a gate insulating film in a region included in the gate electrode in a plan view;
The semiconductor layer includes an upper amorphous semiconductor layer and a lower microcrystalline semiconductor layer,
An insulating film formed on the side surface of the microcrystalline semiconductor layer and below the lower surface of the amorphous semiconductor layer;
Thin film transistor. The insulating film has a bird's beak shape that sinks into the lower surface side of the microcrystalline semiconductor layer.
The thin film transistor according to claim 1.

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