JP5401991B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having an n-channel MOSFET or a p-channel MOSFET in which a gate electrode is made of a metal silicide film and distortion is applied to a channel region.

  In the development of advanced CMOSFET (complementary MOSFET) devices in which miniaturization of transistors is progressing, deterioration of drive current due to depletion of polysilicon (poly-Si) gate electrodes has become a problem. Therefore, a technique for preventing the deterioration of the drive current by avoiding depletion of the electrode by applying a so-called metal gate electrode which is a gate electrode composed of a metal or a metal compound has been studied.

As materials used for the metal gate electrode, pure metals, metal nitrides, silicide materials, and the like have been studied. In any case, the threshold voltage (V _th ) of the n-channel MOSFET and the p-channel MOSFET is set. Must be set to an appropriate value.

Therefore, recently, a technique related to a full silicide electrode in which poly-Si is completely silicided with Ni, Hf, W or the like as a metal gate electrode has attracted attention. For example, US Pat. No. 5,0064,636 discloses a Ni silicide electrode in which SiO ₂ is used as a gate insulating film and a poly-Si electrode into which impurities such as P and B are implanted as a gate electrode is completely silicided with Ni. Proposed. In the MOSFET having this gate electrode, (1) the manufacturing process is highly consistent with the manufacturing process of the conventional CMOSFET, and (2) the threshold voltage can be controlled by adding impurities to the polysilicon before silicidation. Is disclosed. For these reasons, the Ni full silicide electrode is considered as a promising metal gate electrode material. In the metal gate electrode technology described above, the gate electrode is prevented from being depleted and the gate insulating film is substantially thinned to increase the speed of the transistor.

  On the other hand, in recent years, new high performance technologies other than this miniaturization technology have been proposed. As such a technique, a method (piezoresistive effect) for improving mobility by distorting a channel region by applying stress has been proposed. Generally, when tensile (compression) stress is applied in a direction parallel to the channel region to distort this region, electron mobility improves (deteriorates) and hole mobility deteriorates (improves). It has been known. The piezoresistive effect uses this phenomenon.

  Thus, several techniques for improving the performance of MOSFETs using this phenomenon have been proposed (see JP 2002-198368 A and JP 2003-86708 A). In Japanese Patent Laid-Open No. 2002-198368, a silicon nitride film is used as a stopper film at the time of opening a contact hole, and a strong tensile stress is applied to the silicon nitride film to distort the channel region and improve electron mobility. Proposed n-channel MOSFETs (hereinafter referred to as “nMOSFETs”) have been proposed.

  Japanese Patent Laid-Open No. 2003-86708 discloses a semiconductor in which an nMOSFET is covered with a silicon nitride film having tensile stress, and a p-channel MOSFET (hereinafter referred to as “pMOSFET”) is covered with a silicon nitride film having compressive stress. An apparatus is disclosed. In this semiconductor device, the mobility of both carriers can be improved and the performance of both nMOSFET and pMOSFET can be improved.

  As described above, a combination of the metal gate electrode technology and the mobility improvement technology by stress control can be an effective method for improving the performance of the next generation CMOS device.

  However, as can be seen in the above-mentioned JP-A-2002-198368 and JP-A-2003-86708, applying a strong stress (strain) to the channel region by simply combining the silicon nitride film with the metal gate electrode as it is It was difficult.

  The reason will be described below. FIG. 33A shows a conventional MOSFET (nMOSFET). In this MOSFET, a gate electrode 107 is formed on the surface of the silicon substrate 101 partitioned by the element isolation region 102 via a gate insulating film 106. Further, gate sidewalls 108 are formed on both side surfaces of the gate electrode 107, an impurity diffusion layer 103 serving as a source / drain region is formed in the surface region of the silicon substrate 101, and a silicide layer 105 is formed on the impurity diffusion layer 103. ing. A silicon nitride film 109 is formed so as to cover the gate electrode 107, the gate sidewall 108 and the impurity diffusion layer 103. Note that the gate length of the transistor in FIG. 33A is 30 nm, and the dimensions of the other portions are typical for a 45-nm generation transistor.

  FIG. 33 (b) shows each part of the silicon nitride film [silicon nitride film (A) on the gate electrode, silicon nitride film (B) on the gate sidewall, source / drain regions] in the MOSFET of FIG. 33 (a). It is the calculation result which showed the stress which the upper silicon nitride film (c)] gives to a channel region. A structural analysis tool (software name: ANSYS) using a finite element method was used for this stress calculation. Here, a silicon nitride film having a tensile stress was used.

  The vertical axis of FIG. 33 (b) shows the tensile stress as positive and the compressive stress as negative. As is clear from the figure, the stress applied to the channel region is mainly caused by the silicon nitride film (c) existing on the source / drain region, and the silicon nitride film (a) above the gate electrode A compressive stress is applied in the direction of cancellation. As a result, the tensile stress of the silicon nitride film (c) and the compressive stress of the silicon nitride film (a) cancel each other, resulting in a problem that the stress applied to the net channel region is reduced. It was.

  FIG. 33B shows a case where a silicon nitride film in which compressive stress is generated mainly on the gate electrode and (c) tensile stress is generated on the source / drain regions is shown. However, contrary to FIG. 33 (b), the same phenomenon occurred even when a silicon nitride film in which tensile stress occurs on the gate electrode and compressive stress occurs on the source / drain regions is provided. . In particular, the cancellation of tensile stress and compressive stress is a metal that has a larger elastic modulus (Young's modulus) than the conventional polycrystalline silicon film (polysilicon film) as the gate electrode in order to suppress depletion of the gate electrode. And when using a metal silicide film.

  The present invention has been made to solve the above-described problems. The object of the present invention is to optimize the stress and arrangement of the film around the gate electrode so that a large stress (strain) is applied to the channel region even when a metal silicide film is used as the gate electrode to suppress gate depletion. It aims to become. Another object of the present invention is to improve carrier mobility (electron mobility, hole mobility) and improve the performance of nMOSFETs and pMOSFETs.

One embodiment of the present invention
A semiconductor substrate;
A gate electrode provided on the semiconductor substrate and made of metal silicide;
A gate insulating film provided between the semiconductor substrate and the gate electrode;
Gate sidewalls provided on opposite sides of the gate electrode;
Source / drain regions provided on both sides of the semiconductor substrate across the gate electrode;
Have
The present invention relates to a semiconductor device including an n-channel MOSFET configured as described in (1), (2), or (3) below.
(1) having a compressive stress film only on the gate electrode;
(2) having a tensile stress film only on at least one of the gate sidewall and the source / drain region;
(3) A compressive stress film is formed on the gate electrode, and a tensile stress film is formed on at least one of the gate sidewall and the source / drain region.

Another embodiment of the present invention is:
A semiconductor substrate;
A gate electrode provided on the semiconductor substrate and made of metal silicide;
A gate insulating film provided between the semiconductor substrate and the gate electrode;
Gate sidewalls provided on opposite sides of the gate electrode;
Source / drain regions provided on both sides of the semiconductor substrate across the gate electrode;
Have
The present invention relates to a semiconductor device including a p-channel MOSFET configured as described in (A), (B), or (C) below.
(A) having a tensile stress film only on the gate electrode;
(B) having a compressive stress film only on at least one of the gate sidewall and the source / drain region;
(C) A tensile stress film is formed on the gate electrode, and a compressive stress film is formed on at least one of the gate sidewall and the source / drain region.

  In an nMOSFET, a stress can be effectively applied to a channel region by providing a compressive stress film on a gate electrode and a tensile stress film on at least one of a gate sidewall and a source / drain region.

  In the pMOSFET, a stress can be effectively applied to the channel region by providing a tensile stress film on the gate electrode and a compressive stress film on at least one of the gate sidewall and the source / drain region.

  And it becomes possible to add a strong distortion to the channel region of nMOSFET and pMOSFET. As a result, the carrier mobility can be increased, and the performance of the nMOSFET and pMOSFET can be improved.

It is sectional drawing which shows 14th Example. It is sectional drawing which shows a 1st reference example. It is a figure showing the stress added to the channel area | region of the semiconductor device of a 1st reference example and a prior art. It is a figure which shows the manufacturing method of a 1st reference example. It is sectional drawing which shows the 2nd reference example. It is a figure which shows the manufacturing method of the 3rd reference example. It is sectional drawing which shows a 3rd reference example. It is a figure which shows the manufacturing method of the 3rd reference example. It is sectional drawing which shows the 4th reference example. It is a figure which shows the manufacturing method of the 4th reference example. It is sectional drawing which shows the 5th reference example. It is a figure which shows the manufacturing method of the 5th reference example. It is sectional drawing which shows 6th Example. It is sectional drawing which shows a 6th reference example. It is sectional drawing which shows 8th Example. It is sectional drawing which shows 9th Example. It is sectional drawing which shows 10th Example. It is sectional drawing which shows 11th Example. It is a figure which shows the manufacturing method of 11th Example. It is a figure which shows the manufacturing method of 11th Example. It is a figure which shows the manufacturing method of 11th Example. It is a figure which shows the manufacturing method of 11th Example. It is sectional drawing which shows a 7th reference example. It is a figure which shows the manufacturing method of the 7th reference example. It is a figure which shows the manufacturing method of the 7th reference example. It is a figure which shows the manufacturing method of the 7th reference example. It is sectional drawing which shows 13th Example. It is a figure which shows the manufacturing method of 13th Example. It is a figure which shows the manufacturing method of 13th Example. It is a figure which shows the manufacturing method of 14th Example. It is sectional drawing which shows 15th Example. It is a figure which shows the manufacturing method of 15th Example. FIG. 33A is a cross-sectional view showing a conventional MOSFET. FIG. 33 (b) is a diagram showing stress applied to the channel region by the silicon nitride film provided on each part of the conventional MOSFET.

Explanation of symbols

1, 101 Silicon substrate 2, 102 Element isolation region 3, 106 Gate insulating film 4, 6 poly-Si film 5, 7 Silicon oxide film 8 Extension diffusion layer 9, 108 Gate sidewall 10 N-type impurity layer 11 Metal film 12, 105 Silicide layer 13 Interlayer insulating film 14 Full silicide gate electrodes 15 and 19 Stress-containing films 16 and 18 having compressive stress Stress-containing films 15a and 18a having tensile stress Stress relaxation portions 15b and 18b Stress unrelaxed portions 17 p-type impurity layer 20 n-channel field effect transistor 30 p-channel field effect transistor 31 interlayer insulating films 41, 43, 44 resist film 51 boundary portion 52 between gate electrode and film 52 uppermost portion 107 of gate side wall gate electrode 103 impurity diffusion layer 109 silicon nitride film

  The semiconductor device of the present invention includes an nMOSFET, a pMOSFET, or both an nMOSFET and a pMOSFET. Hereinafter, each MOSFET will be described in detail.

(NMOSFET)
The nMOSFET (n-channel MOSFET) of the present invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate and made of metal silicide, and a gate insulating film provided between the semiconductor substrate and the gate electrode. In addition, gate sidewalls are provided on both side surfaces of the gate electrode and the gate insulating film, and source / drain regions are provided on both sides of the gate electrode in the semiconductor substrate.

This nMOSFET is configured as in the following (1), (2) or (3).
(1) A compressive stress film is provided only on the gate electrode, and no compressive stress film is formed on the gate sidewall and the source / drain regions.
(2) A tensile stress film is provided only on at least one of the gate sidewall and the source / drain region, and no tensile stress film is formed on the gate electrode.
(3) A compressive stress film is formed on the gate electrode, and a tensile stress film is formed on at least one of the gate sidewall and the source / drain region.

  That is, the nMOSFET of the present invention has three modes: the configuration of (1), the configuration of (2), and the configuration of (3). It has any one of the above configurations (1) to (3).

  In the case where the nMOSFET of the present invention has the configuration (1), since the compressive stress film does not exist on the gate sidewall and the source / drain region, the stress applied to the channel region by the compressive stress film on the gate electrode. However, it is not diminished by the compressive stress film on the gate sidewall and the source / drain region. For this reason, compared with the conventional nMOSFET provided with the compressive stress film on the gate electrode, the gate sidewall, and the source / drain region, a large stress can be applied to the channel region.

  When the nMOSFET of the present invention has the configuration (2), since there is no tensile stress film on the gate electrode, the channel region is loaded by the tensile stress film existing on the gate sidewall and the source / drain region. Stress is not diminished by the tensile stress film on the gate electrode. For this reason, compared with the conventional nMOSFET provided with the tensile stress film | membrane on a gate electrode, a gate side wall, and a source / drain area | region, a big stress can be loaded to a channel area | region.

  In the case where the nMOSFET of the present invention has the configuration (3), a compressive stress film existing on the gate electrode and a tensile stress film existing on at least one of the gate sidewall and the source / drain region. Due to the synergistic action, a larger stress can be applied to the channel region. In the case of (3) above, a compressive stress film may be laminated in addition to the tensile stress film above at least one of the gate sidewall and the source / drain region.

  In the case of (1) or (3) above, the channel region of the nMOSFET is pulled and extended. Materials for the compressive stress film of the present invention include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, hafnium. Examples thereof include oxides, tantalum oxides, zirconium oxides, silicon oxides, and nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide).

  In the case of (2) above, the channel region of the nMOSFET is stretched by being pulled. Materials for the tensile stress film of the present invention include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, hafnium. Examples thereof include oxides, tantalum oxides, zirconium oxides, silicon oxides, and nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide).

  In the present invention, whether it is a tensile stress film or a compressive stress film depends on the film formation method, film formation conditions (for example, temperature, pressure, plasma power, etc.) and material composition (for example, main component, impurity component). Etc.). Therefore, even if the same element is contained, a tensile stress film or a compressive stress film can be obtained depending on the above conditions.

(PMOSFET)
The pMOSFET (p-channel MOSFET) of the present invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate and made of metal silicide, and a gate insulating film provided between the semiconductor substrate and the gate electrode. In addition, gate sidewalls are provided on both side surfaces of the gate electrode and the gate insulating film, and source / drain regions are provided on both sides of the gate electrode in the semiconductor substrate.

This pMOSFET is configured as shown in (A), (B), or (C) below.
(A) A tensile stress film is provided only on the gate electrode, and no tensile stress film is formed on the gate sidewall and the source / drain regions.
(B) A compressive stress film is provided only on at least one of the gate sidewall and the source / drain region, and no compressive stress film is formed on the gate electrode.
(C) A tensile stress film is formed on the gate electrode, and a compressive stress film is formed on at least one of the gate sidewall and the source / drain region.

  That is, the pMOSFET of the present invention has three embodiments in the case of adopting the configuration (A), the configuration (B), and the configuration (C). Has one of the configurations (A) to (C).

  In the case where the pMOSFET of the present invention has the configuration (A) described above, there is no tensile stress film on the gate sidewall and the source / drain region, so the stress applied to the channel region by the tensile stress film on the gate electrode. Is not diminished by the tensile stress film on the gate sidewalls and the source / drain regions. For this reason, compared with the conventional pMOSFET provided with the tensile stress film | membrane on a gate electrode, a gate side wall, and a source / drain area | region, a big stress can be loaded to a channel area | region.

  In the case where the pMOSFET of the present invention has the configuration (B), since there is no compressive stress film on the gate electrode, the channel region is loaded by the compressive stress film existing on the gate sidewall and source / drain regions. The stress is not reduced by the compressive stress film on the gate electrode. For this reason, compared with the conventional pMOSFET provided with the compressive stress film on the gate electrode, the gate sidewall, and the source / drain region, a larger stress can be applied to the channel region.

  When the pMOSFET of the present invention has the configuration (C), a tensile stress film existing on the gate electrode and a compressive stress film existing on at least one of the gate sidewall and the source / drain region Due to the synergistic action, a larger stress can be applied to the channel region. In the case of (C) above, a tensile stress film may be laminated in addition to the compressive stress film above at least one of the gate sidewall and the source / drain region.

  In the case of (A) or (C) above, the channel region of the pMOSFET is compressed and contracted. Materials for the tensile stress film of the present invention include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, hafnium. Examples thereof include oxides, tantalum oxides, zirconium oxides, silicon oxides, and nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide).

  In the case of (B) above, the channel region of the pMOSFET is compressed and contracted. Materials for the compressive stress film of the present invention include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, hafnium. Examples thereof include oxides, tantalum oxides, zirconium oxides, silicon oxides, and nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide).

  In the present invention, whether it is a tensile stress film or a compressive stress film depends on the film formation method, film formation conditions (for example, temperature, pressure, plasma power, etc.) and material composition (for example, main component, impurity component). Etc.). Therefore, even if the same element is contained, a tensile stress film or a compressive stress film can be obtained depending on the above conditions.

  The semiconductor device of the present invention may include an nMOSFET and a pMOSFET. In this case, the nMOSFET may have any of the above configurations (1) to (3), and the pMOSFET may have any of the above configurations (A) to (C). In this semiconductor device, the nMOSFET and the pMOSFET may operate separately, or the nMOSFET and the pMOSFET may constitute a CMOSFET.

The silicide constituting the gate electrode of the nMOSFET or pMOSFET of the present invention is at least one selected from the group consisting of Ni, Cr, Cu, Ir, Rh, Ti, Zr, Hf, V, Ta, Nb, Mo and W. The silicide of these elements can be used. Specific examples of the silicide include NiSi, Ni ₂ Si, Ni ₃ Si, NiSi ₂ , WSi ₂ , TiSi ₂ , VSi ₂ , CrSi ₂ , ZrSi ₂ , NbSi ₂ , MoSi ₂ , TaSi ₂ , CoSi, CoSi ₂ , _PtSi, Pt 2 _Si, and the like _Pd 2 Si. Further, the silicide may contain a trace component such as an impurity.

As the gate insulating film of the nMOSFET or pMOSFET of the present invention, for example, a silicon oxide film, a silicon nitride film, a metal oxide, a metal silicate, a metal oxide, or a high dielectric constant insulating film in which nitrogen is introduced into a metal silicate is used. Can do. The “high dielectric constant insulating film” refers to an insulating film having a relative dielectric constant (about 3.6 in the case of SiO ₂ ) larger than that of SiO ₂ widely used as a gate insulating film in a semiconductor device. Typically, the dielectric constant of the high dielectric constant insulating film can be several tens to thousands. As the high dielectric constant insulating film, for example, HfSiO, HfSiON, HfZrSiO, HfZrSiON, ZrSiO, ZrSiON, HfAlO, HfAlON, HfZrAlO, HfZrAlON, ZrAlO, ZrAlON, or the like can be used.

Next, examples and reference examples of the present invention will be described in detail with reference to the drawings. The first to fifth reference examples are semiconductor devices having nMOSFETs, the sixth, eighth to tenth embodiments and sixth reference examples are semiconductor devices having pMOSFETs, the eleventh , thirteenth to fifteenth embodiments and the seventh reference example are A semiconductor device having a CMOSFET provided with an nMOSFET and a pMOSFET will be described.

(First Reference Example)
FIG. 2 is a cross-sectional view showing a semiconductor device including the nMOSFET of the first reference example. This nMOSFET has a gate electrode 14 formed through a gate insulating film 3 on a region isolated by the element isolation region 2 of the silicon substrate 1, and this gate electrode 14 is composed of a metal silicide layer. . Further, gate sidewalls 9 are formed on both sides of the gate electrode 14, and n-type impurity layers 10 constituting source / drain regions are formed in the surface regions on both sides of the substrate 1 across the gate electrode 14. Has been. A silicide layer 12 is formed on the n-type impurity layer 10, and an n-channel field effect transistor is constituted by these components. Further, in this reference example, a compressive stress film 15 having a compressive stress is formed in a concave portion formed of the gate sidewall 9 and the upper portion of the gate electrode 14. This configuration corresponds to the configuration (1) described in the above “nMOSFET”. Further, the entire surface of the silicon substrate 1 is covered with interlayer insulating films 13 and 31.

Next, the effect in this reference example will be described. FIG. 3 shows calculation results comparing the stress applied to the channel region when the film 15 on the gate electrode in FIG. 2 has compressive stress (this reference example) and when it has tensile stress (prior art). The gate length of the transistor of FIG. 2 used for this calculation was 30 nm, and the dimensions of the other portions were typical for a 45 nm generation transistor. In addition, a structural analysis tool (software name: ANSYS) using a finite element method was used for the stress calculation.

In FIG. 3, the channel stress on the vertical axis represents the stress applied to the channel region, with zero when no stress, positive when tensile stress, and negative when compressive stress. As can be seen from FIG. 3, in this reference example, the channel region is pulled by having the compressive stress film on the gate electrode, and in this reference example, a stronger tensile stress is applied to the channel region than in the prior art. Thereby, the channel region is greatly strained in the tensile direction, and the electron mobility in the channel region of the nMOSFET can be greatly improved.

The effect of the actual sample in this reference example can be confirmed by using a convergent electron diffraction method as described in, for example, Japanese Patent Application Laid-Open No. 2000-9664. This method obtains the strain and stress of the Si crystal lattice from the diffraction pattern obtained by irradiating the focused electrons onto the Si substrate directly under the gate insulating film, and measures the strain at a specific site with a spatial resolution of about 10 nm. be able to. By comparing the strain amount of the Si crystal lattice measured by the focused electron diffraction method between the sample in this reference example and the sample from which the compressive stress film 15 on the gate electrode is removed, the effect of the actual sample in this reference example Can be confirmed.

4A to 4K are cross-sectional views showing the manufacturing process of the nMOSFET of the first reference example. First, the element isolation region 2 was formed on the surface region of the silicon substrate 1 by using STI (Shallow Trench Isolation) technology. Subsequently, a gate insulating film 3 was formed on the surface of the silicon substrate from which the elements were separated. The gate insulating film 3 can be, for example, a high dielectric constant insulating film containing silicon, hafnium, aluminum, titanium, zirconium, tantalum, or the like, a silicon oxide film, or a laminated structure thereof.

  Next, as shown in FIG. 4A, a poly-Si film 4 having a thickness of 80 nm was formed on the gate insulating film. The poly-Si film 4 may be ion-implanted with an n-type impurity element as necessary. Thereafter, as shown in FIG. 4B, a laminated film including a silicon oxide film 5 having a thickness of 10 nm, a poly-Si film 6 having a thickness of 100 nm, and a silicon oxide film 7 having a thickness of 50 nm was formed.

  As shown in FIG. 4C, the laminated film was processed into shapes such as a gate electrode and a gate insulating film using a lithography technique and an RIE (Reactive Ion Etching) technique. Subsequently, ion implantation was performed, and the extension diffusion layer region 8 was formed in a self-aligned manner using the gate electrode as a mask.

  Further, as shown in FIG. 4D, a silicon nitride film and a silicon oxide film were sequentially deposited on the entire surface. Then, gate sidewalls 9 were formed on both side surfaces of the gate electrode facing each other by etching back. In this state, ion implantation was performed again, and an n-type impurity diffusion layer (source / drain region) 10 was formed through activation annealing.

Next, as shown in FIG. 4 (e), a metal film 11 is deposited on the entire surface by sputtering, and the gate electrode, the gate sidewall film, and the STI are used as masks by the salicide technique to have a thickness of only about the source / drain region. A 40 nm silicide layer 12 was formed (FIG. 4F). In this reference example, the silicide layer 12 is made of Ni monosilicide (NiSi) that can minimize the contact resistance. In the silicide layer, Co silicide or Ti silicide may be used instead of Ni silicide.

  Further, as shown in FIG. 4G, an interlayer insulating film 13 of a silicon oxide film is formed on the entire surface by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 4H, the interlayer insulating film 13 was flattened by the CMP technique, and the interlayer insulating film was etched back to expose poly-Si 4 as a gate electrode material.

  Next, as shown in FIG. 4I, a Ni film (not shown) was deposited on the entire surface in order to silicide poly-Si4. Thereafter, heat treatment was performed to sufficiently react poly-Si and Ni to form a silicide. Next, the Ni full silicide electrode 14 was formed by carrying out the wet etching removal of the excess Ni film | membrane which was not silicidation reaction in heat processing.

Next, as shown in FIG. 4J, the compressive stress film 15 was deposited on the recess formed by the gate sidewall 9 and the Ni full silicide electrode 14 and the interlayer insulating film 13. In this reference example, the compressive stress film 15 is an insulating film having a compressive stress, and is mainly a silicon nitride film formed by plasma chemical vapor deposition. Materials for the compressive stress film 15 include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, and hafnium oxide. Oxides, tantalum oxides, zirconium oxides, silicon oxides, nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide), and the like. By using these materials, the compressive stress film can have a larger compressive stress.

  Next, as shown in FIG. 4K, the compressive stress film 15 on the interlayer insulating film 13 is removed by a CMP technique. The reason why the compressive stress film 15 other than the upper part of the gate electrode 14 can be removed in this way is that the boundary surface 51 between the gate electrode 14 and the compressive stress film 15 is the highest on the top of the gate sidewall 9 (based on the semiconductor substrate). This is because it is lower than (part) 52. Finally, the structure shown in FIG. 2 can be obtained by laminating the interlayer insulating film 31 on the entire surface. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(Second reference example)
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device including an nMOSFET according to the second reference example. In this reference example, unlike the first reference example, a tensile stress having a tensile stress for applying a tensile strain to the channel region on the silicide layer 12 and the sidewall 9 formed on the source / drain region. The film 16 exists, and the tensile stress film 16 does not exist on the gate electrode 14. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration (2) described in the above “nMOSFET”. In the nMOSFET of the second reference example, compressive strain is not applied to the channel region as compared with the case where the tensile stress film 16 exists on the gate electrode 14. Therefore, the channel region can be greatly distorted, and the electron mobility in the channel region of the nMOSFET can be improved.

6A to 6D are cross-sectional views showing the manufacturing process of the nMOSFET of the second reference example. Since the steps up to the formation of the source / drain diffusion layers are the same as those in the first reference example (FIGS. 4A to 4F), the description thereof will be omitted, and the description will be given from the next step (FIG. 6A). To do.

  As shown in FIG. 6A, a tensile stress film 16 having a tensile stress was formed on the entire surface by a CVD (Chemical Vapor Deposition) method. The tensile stress film 16 is mainly a silicon nitride film formed by plasma chemical vapor deposition.

  Thereafter, as shown in FIG. 6B, a silicon oxide interlayer insulating film 13 is formed by a CVD (Chemical Vapor Deposition) method. The interlayer insulating film 13 was planarized by CMP technique as shown in FIG. 6C, and the interlayer insulating film was etched back to expose poly-Si 4 serving as a gate electrode.

  Next, as shown in FIG. 6D, a Ni film (not shown) was deposited on the entire surface. Then, silicidation was performed by sufficiently reacting poly-Si and Ni by heat treatment. Thereafter, the Ni full silicide electrode 14 was formed by performing wet etching removal of the surplus Ni film that was not subjected to the silicidation reaction in the heat treatment. Finally, the structure shown in FIG. 5 was obtained by laminating the interlayer insulating film 31. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(Third reference example)
FIG. 7 is a cross-sectional view showing a third reference example. This reference example, has a 1 change of the second reference example, site compressive stress film 15 thereof having a compressive stress was not present on the gate electrode 14 upper and the interlayer insulating film 13 in the second reference example The point added above is different from the second reference example. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration (3) described in the above “nMOSFET”. In this reference example, the compressive stress film 15 having a compressive stress exists on the gate electrode 14. Further, since the boundary surface 51 between the gate electrode 14 and the compressive stress film 15 is lower than the uppermost portion 52 of the gate sidewall 9, the direction of the stress finally applied to the channel region by the compressive stress film 15 stretches the substrate. It becomes the tensile direction. Therefore, the channel region can be further distorted compared to the second reference example, and the electron mobility in the channel region of the nMOSFET can be further improved.

FIG. 8 is a cross-sectional view showing the manufacturing process of the nMOSFET of the third reference example. The process up to the formation process of the full silicide gate electrode 14 is the same as that of the second reference example (FIGS. 4A to 4F and FIGS. 6A to 6D), and therefore the description thereof is omitted. A description will be given from FIG.

  As shown in FIG. 8, a compressive stress film 15 was deposited on the recess formed by the gate sidewall 9 and the full silicide electrode 14 and the interlayer insulating film 13. The compressive stress film 15 is an insulating film having a compressive stress, and is mainly a silicon nitride film formed by plasma chemical vapor deposition. Finally, the structure shown in FIG. 7 can be obtained by laminating the interlayer insulating film 31. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(4th reference example)
FIG. 9 is a cross-sectional view showing a fourth reference example. This reference example is one modification of the third reference example. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration (3) described in the above “nMOSFET”. The difference between the present reference example and the third reference example is that portions other than the portion immediately above the gate electrode 14 of the compressive stress film 15 are removed. In the third reference example, the compressive stress film 15 existing in a portion other than directly above the gate electrode 14 gives compressive strain to the channel region, and in some cases, the effect of the tensile stress film 16 may be reduced. On the other hand, in this reference example, since the compressive stress film 15 other than just above the gate electrode 14 is removed, no compressive strain is applied to the channel region. Therefore, the channel region of this reference example can be distorted more greatly than the third reference example, and the electron mobility in the channel region of the nMOSFET can be further improved.

FIG. 10 is a cross-sectional view showing the manufacturing process of the nMOSFET of the fourth reference example. The process up to the formation of the compressive stress film 15 is the same as that of the third reference example (FIGS. 4A to 4F, FIGS. 6A to 6D, and FIG. 8), so the description is omitted. The process (FIG. 10) will be described.

  As shown in FIG. 10, the compressive stress film 15 on the interlayer insulating film 13 was removed by a CMP technique. The reason why the compressive stress film 15 other than the upper portion of the gate electrode 14 can be removed in this manner is that the boundary surface 51 between the gate electrode 14 and the compressive stress film 15 is lower than the uppermost portion 52 of the gate sidewall 9. Finally, the structure shown in FIG. 9 was obtained by laminating the interlayer insulating film 31 on the entire surface. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(5th reference example)
FIG. 11 is a cross-sectional view showing a fifth reference example. This reference example is one modification of the third reference example. The difference between the present reference example and the third reference example is that the film existing on the interlayer insulating film 13 is the stress relaxation film 15a and has no stress. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration (3) described in the above “nMOSFET”. The stress relaxation film 15a is equivalent to other films having no stress such as an interlayer insulating film in that it has no stress inside. The presence of the stress relaxation film 15a can be confirmed by the method described in Japanese Patent Laid-Open No. 2000-9664 as will be described later.

In the third reference example, the compressive stress film 15 having a compressive stress (existing on the interlayer insulating film 13) existing in a portion other than directly above the gate electrode 14 gives a compressive strain to the channel region. On the other hand, in this reference example, only the tensile stress film 16 and the stress relaxation film 15a exist in the portion other than the portion directly above the gate electrode 14 (portion on the gate sidewall and the source / drain region). Is not added. Therefore, the channel region of this reference example can be distorted more greatly than the third reference example, and the electron mobility in the channel region of the nMOSFET can be further improved.

FIG. 12 is a cross-sectional view showing the manufacturing process of the nMOSFET of the fifth reference example. The process up to the formation of the compressive stress film 15 is the same as that of the third reference example (FIGS. 4A to 4F, FIGS. 6A to 6D, and FIG. 8), so the description is omitted. The process (FIG. 12) will be described.

  As shown in FIG. 12, after forming the compressive stress film, ion implantation Iim was performed on the compressive stress film using ions such as silicon, germanium, argon, or xenon. Here, the implantation energy of the ion implantation is set so that the ion arrival depth is about the thickness of the compressive stress film 15 on the interlayer insulating film 13 (so that the ions do not reach the portion sandwiched by the gate sidewalls). ) Adjusted. Further, the ion implantation amount was adjusted so that the stress of the compressive stress film 15 was sufficiently relaxed.

By adjusting the ion implantation conditions in this manner, the compressive stress film 15b can be formed on the portion sandwiched between the gate sidewalls, and the stress relaxation film 15a can be formed on the compressive stress film. The compressive stress film 15 b on the gate electrode 14 is formed in a recess formed by the gate sidewall 9 and the full silicide electrode 14, so that the film thickness is thicker than that on the interlayer insulating film 13. . Therefore, if ion implantation conditions are set as in this reference example, the compressive stress of the portion of the compressive stress film 15b sandwiched between the gate sidewalls 9 on the gate electrode 14 is not relaxed, and the interlayer insulating film 13 is formed. Only the existing film 15a can relieve stress.

The existence and effect of the stress relaxation film 15a in this reference example can be confirmed by using, for example, a convergent electron diffraction method described in Japanese Patent Application Laid-Open No. 2000-9664. That is, the sample of this reference example and the sample that has not undergone stress relaxation in the portion corresponding to the film 15a are measured by the convergent electron diffraction method. And the effect in the actual sample in this reference example can be confirmed by comparing the distortion amount of Si crystal lattice.

  Finally, the structure shown in FIG. 11 could be obtained by laminating the interlayer insulating film 31 on the entire surface. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(Sixth embodiment)
FIG. 13 is a cross-sectional view showing the configuration of the pMOSFET according to the sixth embodiment. This pMOSFET has a gate electrode 14 formed through a gate insulating film 3 on a region isolated by the element isolation region 2 of the silicon substrate 1, and the gate electrode 14 is formed of a metal silicide layer. Yes. Further, gate sidewalls 9 are formed on both sides of the gate electrode 14, and p-type impurity layers 17 constituting source / drain regions are formed in the surface regions on both sides of the substrate 1 across the gate electrode 14. Has been. A silicide layer 12 is formed on the p-type impurity layer 17, and a p-channel field effect transistor is constituted by these components. Furthermore, in this embodiment, a tensile stress film 18 having a tensile stress is formed on the gate electrode 14. That is, the configuration of the semiconductor device of this example corresponds to the configuration of (A) described in the above “pMOSFET”. Further, the entire surface of the silicon substrate 1 is covered with interlayer insulating films 13 and 31.

  Materials for the tensile stress film 18 include carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, and hafnium oxide. Oxides, tantalum oxides, zirconium oxides, silicon oxides, nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide), and the like. By using these materials, the tensile stress film can have a large tensile stress.

Next, effects of the present embodiment will be described below. The sixth embodiment, the orientation of the stress of the first reference example and the tensile stress film 18 is only reverse, size and extent of the effect is in the same as in the first embodiment. That is, since the tensile stress film 18 having a tensile stress gives a compressive strain to the channel region, the hole mobility in the channel region of the pMOSFET is greatly improved. In addition, the effect in the actual sample in a present Example can be confirmed by the method of Unexamined-Japanese-Patent No. 2000-9664 similarly to the 1st reference example, for example.

Next, a method for manufacturing a semiconductor device including the pMOSFET of the sixth embodiment will be described. Since the manufacturing method of the present embodiment is different from the first reference example only in the polarity of the MOSFET, a detailed manufacturing procedure is omitted. The tensile stress film 18 is an insulating film having a tensile stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition. As the material of the tensile stress film 18, those listed as being applicable for forming the tensile stress film 16 in the second reference example can be appropriately used.

(Sixth reference example)
FIG. 14 is a cross-sectional view showing a configuration of a pMOSFET according to a sixth reference example. In this reference example, unlike the sixth embodiment, there is a compressive stress film 19 for applying compressive strain to the channel region on the silicide layer 12 and the gate sidewall 9 formed on the source / drain region. The compressive stress film 19 does not exist on the gate electrode 14. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration of (B) described in the above “pMOSFET”.

In this reference example, a tensile strain is not applied to the channel region as compared with the case where the compressive stress film 19 exists on the gate electrode 14. Therefore, the channel region can be greatly distorted, and the hole mobility in the channel region of the pMOSFET can be improved.

Next, a method for manufacturing a semiconductor device including the pMOSFET of the sixth reference example will be described. Since this reference example differs from the second reference example only in the polarity of the MOSFET, a detailed manufacturing procedure is omitted. In the sixth reference example, the compressive stress film 19 is an insulating film having a compressive stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition. As a material of the compressive stress film 19, those mentioned as being applicable for forming the compressive stress film 15 in the first reference example can be appropriately used.

(Eighth embodiment)
FIG. 15 is a sectional view showing an eighth embodiment. This embodiment is a modification of the sixth reference example. In this embodiment, a tensile stress film 18 having a tensile stress that did not exist in the sixth reference example is added on the gate electrode 14 and the interlayer insulating film 13. That is, the configuration of the semiconductor device of this example corresponds to the configuration of (C) described in the above “pMOSFET”.

In this embodiment, since the tensile stress film 18 having a tensile stress is present on the gate electrode 14, the channel region can be greatly distorted as compared with the sixth reference example. As a result, the hole mobility in the channel region of the pMOSFET can be further improved.

Next, a method for manufacturing a semiconductor device including the pMOSFET of the eighth embodiment will be described. Since the present embodiment differs from the third reference example only in the polarity of the MOSFET, a detailed manufacturing procedure is omitted. The tensile stress film 18 is an insulating film having a tensile stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition. As the material of the tensile stress film 18, those listed as being applicable for forming the tensile stress film 16 in the second reference example can be appropriately used.

(Ninth embodiment)
FIG. 16 is a sectional view showing a ninth embodiment. This embodiment is a modification of the eighth embodiment. That is, the configuration of the semiconductor device of this example corresponds to the configuration of (C) described in the above “pMOSFET”. The difference between this embodiment and the eighth embodiment is that the portions other than the portion directly above the gate electrode 14 of the tensile stress film 18 are removed. In the eighth embodiment, the tensile stress film 18 having a tensile stress existing in a portion other than directly above the gate electrode 14 gives a tensile strain to the channel region, and in some cases, the effect of the compressive stress film 19 may be reduced. In contrast, in this embodiment, since the tensile stress film 18 other than the portion directly above the gate electrode 14 is removed, no tensile strain is applied to the channel region. Therefore, the channel region can be distorted more greatly in this embodiment than in the eighth embodiment, and the hole mobility in the channel region of the pMOSFET can be further improved.

Next, a method for manufacturing a semiconductor device including the pMOSFET of the ninth embodiment will be described. Since this embodiment is different from the fourth reference example only in the polarity of the MOSFET, a detailed manufacturing procedure is omitted. The tensile stress film 18 is an insulating film having a tensile stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition. As the material of the tensile stress film 18, those listed as being applicable for forming the tensile stress film 16 in the second reference example can be appropriately used.

(Tenth embodiment)
FIG. 17 is a sectional view showing the tenth embodiment. This embodiment is a modification of the eighth embodiment. The difference between this embodiment and the eighth embodiment is that the film existing on the interlayer insulating film 13 is the stress relaxation film 18a and has no stress. That is, the configuration of the semiconductor device of this example corresponds to the configuration of (C) described in the above “pMOSFET”.

  In the eighth embodiment, the tensile stress film 18 having a tensile stress existing in a portion other than directly above the gate electrode 14 gives a tensile strain to the channel region. On the other hand, in this embodiment, only the compressive stress film 19 and the stress relaxation film 18a exist in the portions other than the portion immediately above the gate electrode 14 (portions on the gate sidewall and the source / drain regions). For this reason, no tensile strain is applied to the channel region. Therefore, the channel region can be distorted more greatly in this embodiment than in the eighth embodiment, and the hole mobility in the channel region of the pMOSFET can be further improved.

Next, a method for manufacturing a semiconductor device including the pMOSFET of the tenth embodiment will be described. Since this embodiment differs from the fifth reference example only in the polarity of the MOSFET, a detailed manufacturing procedure is omitted. The tensile stress film 18b is an insulating film having a tensile stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition.

(Eleventh embodiment)
FIG. 18 is a cross-sectional view showing a configuration of a CMOSFET including an nMOSFET and a pMOSFET according to the eleventh embodiment. As shown in FIG. 18, this nMOSFET has a gate electrode 14 formed on a region isolated by an element isolation region 2 of a silicon substrate 1 via a gate insulating film 3, and this gate electrode 14 is made of metal. It is composed of a silicide layer. Further, gate sidewalls 9 are formed on both sides of the gate electrode 14, and n-type impurity layers 10 constituting source / drain regions are formed in the surface regions on both sides of the substrate 1 across the gate electrode 14. Has been. A silicide layer 12 is formed on the n-type impurity layer 10, and an n-channel field effect transistor 20 is composed of these components.

  Similarly, the pMOSFET has a gate electrode 14 formed through a gate insulating film 3 on a region isolated by the element isolation region 2 of the silicon substrate 1, and the gate electrode 14 is composed of a metal silicide layer. Has been. Further, gate sidewalls 9 are formed on both sides of the gate electrode 14, and p-type impurity layers 17 constituting source / drain regions are formed in the surface regions on both sides of the substrate 1 across the gate electrode 14. Has been. A silicide layer 12 is formed on the p-type impurity layer 17, and a p-channel field effect transistor 30 is constituted by these components.

  In this embodiment, a compressive stress film 15 having compressive stress is formed on the gate electrode 14 of the nMOSFET, and a tensile stress film 18 having tensile stress is formed on the gate electrode 14 of the pMOSFET. That is, the configuration of the semiconductor device of this example corresponds to the configuration (1) described in the “nMOSFET” and the configuration (A) described in the “pMOSFET”. Further, the entire surface of the silicon substrate 1 is covered with interlayer insulating films 13 and 31.

Next, the effect in a present Example is demonstrated. In the nMOSFET, as in the first reference example, the compressive stress film 15 having a compressive stress above the gate electrode gives a tensile stress to the channel region, so that the channel region is distorted in the tensile direction and the electron mobility can be improved. Further, in the pMOSFET, as in the sixth embodiment, the tensile stress film 18 having the tensile stress above the gate electrode gives a compressive stress to the channel region, so that the channel region is distorted in the compression direction and the hole mobility is improved. it can. In the present embodiment, these synergistic effects can provide excellent movement characteristics as a whole CMOSFET.

  Next, a method for manufacturing a semiconductor device including the CMOSFET of the eleventh embodiment will be described. 19 to 22 are cross-sectional views showing a manufacturing process of a semiconductor device provided with the CMOSFET of the eleventh embodiment.

  First, the element isolation region 2 was formed on the surface region of the silicon substrate 1 by using STI (Shallow Trench Isolation) technology. Subsequently, a gate insulating film 3 was formed on the surface of the silicon substrate from which the elements were separated. The gate insulating film 3 can be, for example, a high dielectric constant insulating film containing silicon, hafnium, aluminum, titanium, zirconium, tantalum, or the like, a silicon oxide film, or a laminated structure thereof.

  Next, as shown in FIG. 19A, a poly-Si film 4 having a thickness of 80 nm was formed on the gate insulating film 3. An impurity element may be ion-implanted into the poly-Si film 4 as necessary. Thereafter, as shown in FIG. 19B, a laminated film including a silicon oxide film 5 having a thickness of 10 nm, a poly-Si film 6 having a thickness of 100 nm, and a silicon oxide film 7 having a thickness of 50 nm was formed. Thereafter, as shown in FIG. 19C, the laminated film was processed into the shape of the gate electrode by using the lithography technique and the RIE (Reactive Ion Etching) technique.

  Next, using the gate electrode as a mask, ion implantation of n-type impurity and p-type impurity was performed on both sides of each gate electrode to form the extension diffusion layer region 8 in a self-aligned manner. Further, as shown in FIG. 19D, a silicon nitride film and a silicon oxide film are sequentially deposited, and then etched back to form gate sidewalls 9 on both side surfaces of each gate electrode. In this state, ion implantation of n-type impurities and p-type impurities is performed again on both sides of each gate electrode and gate sidewall, and an n-type impurity diffusion layer 10 and a p-type impurity diffusion layer 17 are formed through activation annealing. .

  Next, as shown in FIG. 20A, a metal film 11 is deposited on the entire surface by sputtering, and a thickness of about 40 nm is formed only on the source / drain diffusion layer by the salicide technique using the gate electrode, gate sidewall and STI as a mask. The silicide layer 12 was formed (FIG. 20B). The silicide layer 12 is Ni monosilicide (NiSi) that can have the lowest contact resistance. As the silicide layer 12, Co silicide or Ti silicide may be used instead of Ni silicide.

  Further, as shown in FIG. 20C, an interlayer insulating film 13 of a silicon oxide film is formed by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 20D, the interlayer insulating film 13 was planarized by the CMP technique. Then, poly-Si4 was exposed by performing etch back of the interlayer insulating film.

  Next, as shown in FIG. 21A, a Ni film (not shown) was deposited. Thereafter, heat treatment was performed to sufficiently react poly-Si and Ni to perform silicidation. Thereafter, the Ni full silicide electrode 14 was formed by performing wet etching removal of the surplus Ni film that was not subjected to the silicidation reaction by heat treatment.

  Next, as shown in FIG. 21B, a compressive stress film 15 was deposited on the recess formed by the gate sidewall 9 and the Ni full silicide electrode 14 and the interlayer insulating film 13. The compressive stress film 15 is an insulating film having a compressive stress, and is a silicon nitride film formed mainly by a plasma chemical vapor deposition method. The material of the compressive stress film 15 includes carbon silicide, oxygen silicide, nitrogen silicide, hydrogenated products of these silicides (carbon silicide, oxygen silicide, nitrogen silicide), aluminum oxide, hafnium oxide. Tantalum oxide, zirconium oxide, silicon oxide, nitrogen additives of these oxides (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide), and the like.

  Next, as shown in FIG. 21C, a resist film 41 to be an etching mask for the compressive stress film 15 was formed using a known photolithography technique. Next, the compressive stress film 15 deposited on the p-channel field effect transistor 30 was removed by dry etching to obtain the structure shown in FIG.

  Next, the resist film 41 was removed, and a tensile stress film 18 having a tensile stress was formed as shown in FIG. Here, the tensile stress film 18 is an insulating film having a tensile stress, and is a silicon nitride film formed mainly by a thermal chemical vapor deposition method or an atomic layer deposition method. As the material of the tensile stress film 18, those listed as being applicable for forming the tensile stress film 18 in the sixth embodiment can be appropriately used.

  Next, as shown in FIG. 22C, the compressive stress film 15 and the tensile stress film 18 on the interlayer insulating film 13 were removed by the CMP technique. Finally, the structure shown in FIG. 18 was obtained by laminating the interlayer insulating film 31. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

  In the description of the manufacturing method of this embodiment, the compressive stress film 15 is deposited, and then the tensile stress film 18 is deposited. It is obvious that a change such as depositing the compressive stress film 15 is possible after depositing.

( Seventh reference example)
FIG. 23 is a cross-sectional view showing a configuration of a semiconductor device including a CMOSFET according to a seventh reference example. In this reference example, contrary to the eleventh embodiment, a tensile stress film 16 having a tensile stress on the silicide layer 12 and the side wall 9 of the n-channel field effect transistor 20 and a silicide layer of the p-channel field effect transistor 30. A compressive stress film 19 having a compressive stress exists on 12 and the gate sidewall 9. Also, the films 16 and 19 do not exist on the gate electrodes 14 of both field effect transistors 20 and 30. That is, the configuration of the semiconductor device of this reference example corresponds to the configuration (2) described in the “nMOSFET” and the configuration (B) described in the “pMOSFET”.

In the seventh reference example, compressive strain is not applied to the channel region as compared with the case where the tensile stress film 16 exists on the gate electrode 14 of the n-channel field effect transistor 20. Therefore, the channel region can be greatly distorted, and the electron mobility in the channel region of the nMOSFET can be further improved.

  Further, a tensile strain is not applied to the channel region as compared with the case where the compressive stress film 19 exists on the gate electrode 14 of the p-channel field effect transistor. Therefore, the channel region can be greatly distorted, and the hole mobility in the channel region of the pMOSFET can be further improved.

24 to 26 are cross-sectional views illustrating the manufacturing steps of the semiconductor device including the CMOSFET of the seventh reference example. The steps up to the manufacturing process of the source / drain diffusion layer are the same as those in the eleventh embodiment (FIGS. 19A to 19D and FIGS. 20A to 20D), so the description is omitted and the next step ( A description will be given from FIG.

  First, as shown in FIG. 24A, a tensile stress film 16 having a tensile stress was formed on the entire surface by a CVD (Chemical Vapor Deposition) method. The tensile stress film 16 is mainly a silicon nitride film formed by plasma chemical vapor deposition.

  Next, as shown in FIG. 24B, a resist film 43 serving as an etching mask for the tensile stress film 16 was formed using a known photolithography technique. Next, the tensile stress film 16 existing on the p-channel field effect transistor 30 was removed by dry etching.

Next, the resist film 43 was removed (FIG. 24C), and a compressive stress film 19 having a compressive stress was formed (FIG. 25A). Here, the compressive stress film 19 is an insulating film having a compressive stress, and is mainly a silicon nitride film formed by thermal chemical vapor deposition or atomic layer deposition. As the material of the compressive stress film 19, those mentioned as being applicable for forming the compressive stress film 15 in the first reference example can be appropriately used.

  Next, a resist film 44 serving as an etching mask for the compressive stress film 19 was formed using a known photolithography technique so as to cover the p-channel field effect transistor 30 (FIG. 25B). Then, the compressive stress film 19 existing on the n-channel field effect transistor 20 was removed by dry etching. Subsequently, the resist film 44 was removed to obtain the structure shown in FIG.

  Furthermore, as shown in FIG. 26A, an interlayer insulating film 13 of a silicon oxide film was formed by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 26B, the interlayer insulating film 13 is planarized by CMP technique, and the interlayer insulating film is etched back to expose the poly-Si 4 of the gate electrode.

  Next, as shown in FIG. 26C, a Ni film (not shown) was deposited on the entire surface. Thereafter, heat treatment was performed to sufficiently react poly-Si and Ni to perform silicidation. The Ni full silicide electrode 14 was formed by performing wet etching removal of the excess Ni film that did not undergo the silicidation reaction in this heat treatment. Finally, an interlayer insulating film 31 was laminated to obtain the structure shown in FIG. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(Thirteenth embodiment)
FIG. 27 is a sectional view showing a thirteenth embodiment. This embodiment is a modification of the seventh reference example. In this embodiment, a compressive stress film 15 having a compressive stress that did not exist in the seventh reference example is present on the gate electrode 14 and the interlayer insulating film 13 in the nMOSFET region 20. That is, the configuration of the semiconductor device of this example corresponds to the configuration (3) described in the “nMOSFET” and the configuration (C) described in the “pMOSFET”. For this reason, in this embodiment, the channel region can be greatly distorted as compared with the seventh reference example, and the electron mobility in the channel region of the nMOSFET can be further improved.

Further, a tensile stress film 18 having a tensile stress that did not exist in the seventh reference example exists on the gate electrode 14 and the interlayer insulating film 13 in the pMOSFET region 30. For this reason, in this embodiment, the channel region can be greatly distorted as compared with the seventh reference example, and the hole mobility in the channel region of the pMOSFET can be further improved.

28 and 29 are cross-sectional views showing the manufacturing process of a semiconductor device provided with the CMOSFET of the thirteenth embodiment. Processes up to the formation process of the full silicide gate electrode 14 are the same as in the seventh reference example (FIGS. 19A to 19D, FIGS. 20A to 20D, FIGS. 24A to 24C, FIG. 25 (a) to (c) and FIGS. 26 (a) to (c)), description thereof will be omitted, and description will be made from the next step (FIG. 28).

  As shown in FIG. 28A, a compressive stress film 15 was deposited on the entire surface. This compressive stress film 15 is an insulating film having a compressive stress, and is mainly a silicon nitride film formed by plasma chemical vapor deposition. Next, as shown in FIG. 28B, a resist film 43 serving as an etching mask for the compressive stress film 15 was formed using a known photolithography technique.

  Next, the compressive stress film 15 existing on the p-channel field effect transistor 30 was removed by dry etching to obtain a structure shown in FIG. Next, as shown in FIG. 29A, the resist film 43 was removed, and a tensile stress film 18 was formed. Here, the tensile stress film 18 is an insulating film having a tensile stress, and is mainly a silicon nitride film formed by a thermal chemical vapor deposition method or an atomic layer deposition method. As the material of the tensile stress film 18, those listed as being applicable to the formation of the tensile stress film 18 in the sixth embodiment can be appropriately used.

  Next, a resist film 44 serving as an etching mask for the tensile stress film 18 was formed using a known photolithography technique so as to cover the p-channel field effect transistor 30 (FIG. 29B). Next, the tensile stress film 18 existing on the n-channel field effect transistor 20 was removed by dry etching. Subsequently, the resist film 44 was removed to obtain the structure shown in FIG. Finally, by laminating the interlayer insulating film 31, the structure shown in FIG. 27 was obtained. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(14th embodiment)
FIG. 1 is a sectional view showing a fourteenth embodiment. This embodiment is a modification of the thirteenth embodiment. The difference between this embodiment and the thirteenth embodiment is that the portions other than the portion immediately above the gate electrode 14 of the compressive stress film 15 and the tensile stress film 18 are removed. That is, the configuration of the semiconductor device of this example corresponds to the configuration (3) described in the “nMOSFET” and the configuration (C) described in the “pMOSFET”.

  In the thirteenth embodiment, the compressive stress film 15 existing in a portion other than the portion directly above the gate electrode 14 of the n-channel field effect transistor 20 gives a compressive strain to the channel region, and in some cases, the effect of the tensile stress film 16 can be reduced. There is sex. On the other hand, in this embodiment, since the compressive stress film 15 is removed in a portion other than directly above the gate electrode 14, no compressive strain is applied to the channel region. Therefore, the channel region can be greatly distorted in this embodiment compared to the thirteenth embodiment, and the electron mobility in the channel region of the nMOSFET can be further improved.

  In the thirteenth embodiment, the tensile stress film 18 existing in a portion other than the portion directly above the gate electrode 14 of the p-channel field effect transistor 30 gives a tensile strain to the channel region, and in some cases, the effect of the compressive stress film 19 is reduced. there's a possibility that. On the other hand, in this embodiment, the tensile stress film 18 is removed except for the portion directly above the gate electrode 14, so that no tensile strain is applied to the channel region. Therefore, compared to the thirteenth embodiment, the present embodiment can greatly distort the channel region, and the hole mobility in the channel region of the pMOSFET can be further improved.

FIG. 30 is a cross-sectional view showing a process for manufacturing a semiconductor device including the CMOSFET of the fourteenth embodiment. Up to the process of forming the tensile stress film 18, the same steps as in the third reference example (FIGS. 19 (a) to (d), FIGS. 20 (a) to (d), FIGS. 24 (a) to (c), and FIG. (A) to (c), FIGS. 26 (a) to (c), FIGS. 28 (a) to (c), and FIGS. 29 (a) to (c)), the description thereof will be omitted, and the next step (FIG. 30).

  As shown in FIG. 30, the compressive stress film 15 and the tensile stress film 18 on the interlayer insulating film 13 were removed by the CMP technique. Finally, an interlayer insulating film 31 was laminated to obtain the structure shown in FIG. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

(15th embodiment)
FIG. 31 is a sectional view showing the fifteenth embodiment. This embodiment is a modification of the thirteenth embodiment. The difference between this embodiment and the thirteenth embodiment is that the films existing on the interlayer insulating film 13 are the stress relaxation film 18a and the stress relaxation film 15a, respectively, and the stress relaxation films 15a and 18a have stress. That is not the point. That is, the configuration of the semiconductor device of this example corresponds to the configuration (3) described in the “nMOSFET” and the configuration (C) described in the “pMOSFET”.

  In the thirteenth embodiment, the compressive stress film 15 having a compressive stress existing in a portion other than the portion immediately above the gate electrode 14 on the n-channel field effect transistor 20 gives a compressive strain to the channel region. There is a possibility of diminishing 16 effects. On the other hand, according to this modified example, since the stress of the stress relaxation film 15a is relaxed, no compressive strain is applied to the channel region.

  In the thirteenth embodiment, the tensile stress film 18 having a tensile stress existing in a portion other than the portion directly above the gate electrode 14 of the p-channel field effect transistor 30 gives a tensile strain to the channel region. There is a possibility of diminishing the effect of the membrane 19. On the other hand, in this modified example, since the stress of the stress relaxation film 18a existing in a portion other than directly above the gate electrode 14 is relaxed, no tensile strain is applied to the channel region.

  Therefore, the channel region of the nMOSFET 20 and the pMOSFET 30 can be greatly distorted in this embodiment compared to the thirteenth embodiment. As a result, the electron mobility in the channel region of the nMOSFET and the hole mobility in the channel region of the pMOSFET can be further improved.

  FIG. 32 is a cross-sectional view showing a manufacturing process of a semiconductor device provided with the CMOSFET of the fifteenth embodiment of the present invention. Steps similar to those of the thirteenth embodiment up to the steps of forming the compressive stress film 15 and the tensile stress film 18 (FIGS. 19A to 19D, FIGS. 20A to 20D, and FIGS. c), FIGS. 25 (a)-(c), FIGS. 26 (a)-(c), FIGS. 28 (a)-(c), and FIGS. The next step (FIG. 32) will be described.

  After the above steps, as shown in FIG. 32, ions were implanted into the compressive stress film 15 and the tensile stress film 18 using ions such as silicon, germanium, argon, or xenon. Here, the ion implantation energy was such that the ion arrival depth was approximately the thickness of the compressive stress film 15 and the tensile stress film 18 on the interlayer insulating film 13. The amount of ion implantation was set to such an extent that the stress of the compressive stress film 15 and the tensile stress film 18 was sufficiently relaxed.

  Here, the compressive stress film 15 and the tensile stress film 18 on the gate electrode 14 are formed in a recess formed by the gate sidewall 9 and the Ni full silicide electrode 14. For this reason, the film thickness is thicker than that on the interlayer insulating film 13. Therefore, by setting the ion implantation conditions as in this embodiment, the stress of the compressive stress film 15 and the tensile stress film 18 existing immediately above the gate electrode 14 is not relaxed, and the compressive stress on the interlayer insulating film 13 is reduced. Only the film 15 and the tensile stress film 18 can relieve stress. Finally, the structure shown in FIG. 32 can be obtained by laminating the interlayer insulating film 31 on the entire surface. Thereafter, contact holes were opened, contact plugs were formed, and then necessary wiring was formed thereon.

In the eleventh and thirteenth to fifteenth embodiments and the seventh reference example , the nMOSFET has the configuration (1), the pMOSFET has the configuration (A), the nMOSFET has the configuration (2), and the pMOSFET has the configuration (B). The semiconductor device having the configuration of (2) or the semiconductor device in which the nMOSFET has the configuration of (3) and the pMOSFET has the configuration of (C) has been described. However, the semiconductor device of the present invention is not limited to this. That is, when the semiconductor device of the present invention includes an nMOSFET and a pMOSFET, the nMOSFET may take any of the configurations (1) to (3), and the pMOSFET may take any of the configurations (A) to (C).

As described above, the embodiments and reference examples of the present invention have been described. When an n-channel MOSFET is manufactured, a silicon semiconductor substrate having a plane orientation of (100) is used as the semiconductor substrate, and the gate length direction is <100>. It is preferable to do so. By adopting such a configuration, the improvement rate of the electron mobility with respect to the unit stress is improved. Therefore, even when a stress application film having the same size is used, a higher driving current can be realized.

  In the case of manufacturing a p-channel MOSFET, it is preferable to use a silicon semiconductor substrate with a plane orientation of (100) as the semiconductor substrate and a gate length direction of <110>. By adopting such a configuration, the improvement rate of the hole mobility with respect to the unit stress is improved. Therefore, even when a stress applying film having the same size is used, higher transistor performance can be realized.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the technical scope of the present invention.

  This application claims priority based on Japanese Patent Application No. 2007-027882 filed on Feb. 7, 2007, the entire disclosure of which is incorporated herein.

Claims (4)

A semiconductor substrate;
A gate electrode provided on the semiconductor substrate and made of metal silicide;
A gate insulating film provided between the semiconductor substrate and the gate electrode;
Gate sidewalls provided on opposite sides of the gate electrode;
Source / drain regions provided on both sides of the semiconductor substrate across the gate electrode;
Have
A p-channel MOSFET configured as shown in (A) or (C) below is provided,
A semiconductor device, wherein a boundary surface between the gate electrode and the tensile stress film is lower than an uppermost portion of the gate sidewall.
(A) A tensile stress film is provided only on the gate electrode.
(C) A tensile stress film is formed on the gate electrode, and a compressive stress film is formed on at least one of the gate sidewall and the source / drain region. The semiconductor substrate is a silicon semiconductor substrate having a plane orientation of (100),
The semiconductor device according to claim 1, wherein the p-channel MOSFET is configured such that a gate length direction is <110>. an n-channel MOSFET;
A semiconductor device according to claim 1 or 2,
A semiconductor device comprising: At least one of the compressive stress film and the tensile stress film is
From carbon silicide, oxygen silicide, nitrogen silicide, hydrogenation of these silicides, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, silicon oxide and nitrogen additions of these oxides the semiconductor device according to any one of claim 1 to 3, characterized in that it comprises at least one substance selected from the group consisting.

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