JP5494086B2 - Nonvolatile storage device and nonvolatile memory controller - Google Patents

Description

  The present invention relates to a nonvolatile memory device using a nonvolatile semiconductor memory such as a flash memory, and a nonvolatile memory controller that controls the nonvolatile memory.

  In recent years, a memory card as a non-volatile storage device equipped with a NAND type flash memory which is a rewritable non-volatile memory has expanded its market as a storage medium for digital cameras and mobile phones.

  Non-volatile storage devices are also used in non-memory card markets such as SSDs that replace HDDs and embedded memories that are directly mounted on host devices, as the cost per bit decreases with the miniaturization of semiconductor processes. Application is expanding.

  The following items are listed as features of the NAND type flash memory.

・ Non-volatile memory with the largest capacity and low bit cost among semiconductor memories ・ Data reliability has decreased with the miniaturization of semiconductor processes.

  In the NAND flash memory, one memory cell can be configured with the square of (2F) where F is the minimum processing dimension of the semiconductor process. This makes the NAND flash memory the lowest bit cost and the largest memory among the semiconductor memories. In recent years, as a process driver, manufacturing has been performed using the most advanced process rules of semiconductor processes.

  As a result, the NAND flash memory has begun to be used in systems that have used other memories. For example, program code that requires high-speed random access is stored in a NOR flash memory, and user data that requires a large capacity is stored only in a single NAND flash memory. It has been replaced. The capacity of the installed NAND flash memory is sufficiently smaller than the required capacity of the NOR flash memory, and even if the program code installed in the NOR flash memory is stored in the NAND flash memory, there is little influence, and the NAND flash memory is used. This is because even if a device is incorporated, the cost merit of eliminating the NOR flash memory is great.

  The increase in capacity of NAND flash memory is largely due to miniaturization of semiconductor processes. However, miniaturization of semiconductor processes is not only a merit, but also a problem of a decrease in data reliability. As the miniaturization progresses, the data retention characteristic decreases, and the characteristic deterioration due to the rewrite process advances. The memory cell of the flash memory has a configuration with a floating gate that holds electrons in a nonvolatile manner between the control gate of the MOS type transistor and the base, and data is erased and written by exchanging electrons between the base and the floating gate. Do. When data is read from the memory cell of the flash memory, the amount of current flowing through the transistor constituting the flash memory is determined and read.

  Since data erasing and writing are repeated for the memory cell of the flash memory, electrons move between the base and the floating gate, and the insulating film (hereinafter referred to as the gate insulating film) between the base and the floating gate is deteriorated. When the gate insulating film deteriorates, electrons leak from the floating gate to the substrate via the defects present in the gate insulating film, and the write efficiency decreases due to the influence of the electrons trapped in the defects in the gate insulating film. It becomes a factor of decreasing reliability.

  Despite these demerits, the strength of overwhelming bit-rates can be an advantage, so the use of flash memory with advanced miniaturization is expanding even if measures for improving data reliability are incorporated.

  From the above features, a mechanism for improving the reliability of data is required. It can also be seen that the required performance (capacity / data reliability) differs depending on the type of data stored in the flash memory.

  Patent Document 1 discloses a technique for improving data retention characteristics by providing a mechanism for accurately detecting data deterioration of memory cells.

  Patent Document 2 discloses a technique for improving data retention characteristics by performing refresh timing as an opportunity for rewriting processing of another block in order to guarantee data of a block to be read only.

JP 2005-141864 A Japanese Patent Laid-Open No. 10-302484

  However, in the configurations of Patent Documents 1 and 2, there is no guarantee as to the degree of deterioration of the physical block that is the data copy destination in the refresh process after the deterioration is detected.

  The present invention can maintain high data retention reliability even when data is copied by applying refresh processing to data that requires high data retention reliability such as an area used only for reading. An object of the present invention is to provide a nonvolatile memory device and a nonvolatile memory controller.

In order to achieve this object, a nonvolatile memory controller for controlling a rewritable nonvolatile memory according to the present invention is a nonvolatile memory controller for controlling a rewritable nonvolatile memory, and is a logical address that can be designated from the outside. An address conversion table for associating the physical address of the nonvolatile memory, an error recognition / correction unit for recognizing the degree of deterioration of data stored in the nonvolatile memory, and a control unit for controlling the nonvolatile memory; , an external interface unit for communicating logical addresses and data with the outside, and the area designation table for managing the leveling prohibition region, and no deterioration block table leveling prohibited area only consists, the leveling process is the leveling prohibited area logical addresses to prohibit been stored, the leveling prohibited area The lossless block table of use, said the physical address stored for use in performing the refresh process for the leveling prohibited area, the error recognition and correction section corresponds to the logical address stored in the leveling prohibited area data Whether or not the error bit present in the non-volatile memory is dedicated to the leveling prohibition area when the error recognition / correction unit determines that the error bit is greater than or equal to the threshold. The data corresponding to the logical address having an error bit greater than or equal to the threshold value in the physical address stored in the non-degraded block table is refreshed .

  According to the present invention, a physical block that is not deteriorated is reserved exclusively for a data area that requires high data retention reliability that is used only for reading, thereby refreshing data used only for reading. It is possible to copy data to a physical block that has not deteriorated. It can meet the demand for high data retention reliability.

The figure which showed the structure of the non-volatile memory device of Embodiment 1. The figure which showed the structure of the address conversion table of the non-volatile storage device of Embodiment 1. The figure which showed the structure of the invalid block table of the non-volatile storage device of Embodiment 1 The figure which showed the structure of the area | region designation | designated table of the non-volatile storage device of Embodiment 1. The figure which showed the structure of the non-deteriorating block table of the non-volatile storage device of Embodiment 1. Flowchart of write processing of nonvolatile storage device of embodiment 1 Flowchart of read processing of nonvolatile storage device of Embodiment 1 Flowchart of refresh process of nonvolatile memory device of embodiment 1 Flowchart of normal refresh processing of the nonvolatile memory device according to the first embodiment Flowchart of read-only refresh process of nonvolatile memory device of the present invention Graph of flash memory rewrite times and data retention period

(Embodiment 1)
The nonvolatile memory device of this embodiment will be described with reference to the drawings.

  FIG. 1 shows a configuration of a nonvolatile memory device of the present invention.

<1. Configuration of Nonvolatile Storage Device>
A memory card 101 which is a nonvolatile storage device includes a controller 102 and a flash memory unit 103. The controller 102 is a non-volatile memory controller, and controls the interface with the external host device of the memory card 101 and controls the flash memory unit 103.

  The flash memory unit 103 includes a flash memory that is a nonvolatile memory. Although not shown, the flash memory is composed of a plurality of physical blocks, and the physical block is composed of a plurality of memory cells. The physical block is a data erasing unit in the flash memory.

  The memory card 101 writes data to the flash memory unit 103 and reads data from the flash memory unit 103 in response to control of writing and reading data specifying an address from the outside of the memory card 101.

  The controller 102 includes a host interface unit 104, a flash memory control unit 105, a buffer memory 106, an ECC 107, a control unit 108, an address conversion table 109, an invalid block table 110, a bad block table 111, an area designation table 112, and a no deterioration block table 113. , An erase count table 114.

  The host interface unit 104 controls an interface with a host device outside the memory card 101. The flash memory control unit 105 controls the flash memory unit 103. The buffer memory 106 is a volatile buffer memory for temporarily storing data when transferring write data from the outside of the memory card 101 and read data to the outside of the memory card 101 to and from the flash memory unit 103. It is.

  The ECC 107 is an ECC circuit that generates an ECC code to be added when writing data to the flash memory unit 103 and performs ECC correction of the data read when reading data from the flash memory unit 103.

  The control unit 108 controls the entire inside of the controller 102.

  The address conversion table 109 records a correspondence between an address (hereinafter referred to as a logical address) designated from the outside of the memory card 101 and a physical block address (hereinafter referred to as a physical address) of the flash memory unit 103.

  The invalid block table 110 records a list of physical block addresses in which valid data is not written in the flash memory unit 103 and is not a bad block and is not managed by the non-degraded block table 113.

  The defective block table 111 records a list of physical addresses of physical blocks of defective blocks in the flash memory unit 103.

  The area designation table 112 divides a logical address designated from the outside of the memory card 101 into a plurality of areas, and indicates whether the application of the leveling process is permitted or prohibited for the data of each divided area. is there.

  The non-degraded block table 113 records a list of addresses of physical blocks to which valid data is not written. It is a table of physical block addresses for refreshing data of read-only physical blocks.

  The erase count table 114 is a table in which the number of rewrites of all physical blocks included in the flash memory unit 103 is recorded.

<2. Configuration example of various tables>
FIG. 2 is a diagram illustrating an example of the configuration of the address conversion table 109. The address conversion table 109 is a set of data of the logical block address 201 and the physical block address 202. The logical address is divided into logical block addresses in units equal to the capacity of the physical block of the flash memory unit 103, and used as data of the logical block address 201. A set of physical block addresses 202 of the flash memory unit 103 corresponding to each of them constitutes one record. The data corresponding to the logical block address 0000h is stored in the physical block at the address 0000h in the flash memory unit 103, and the data corresponding to the logical block address 0001h is stored in the physical block at the address 0010h in the flash memory unit 103. Further, the logical block address is managed from 0000h to 1F39h.

  FIG. 3 is a diagram illustrating an example of the configuration of the invalid block table 110. Stores addresses 0123h, 0456h,... Of physical blocks of invalid data in the flash memory unit 103. Here, the address of the physical block in the flash memory unit 103 is in the range of 0000h to 1FFFh, and 2000h is treated as an invalid value in 110 of the invalid block table.

  The configuration of the defective block table 111 stores the address of the physical block of the defective data in the flash memory unit 103 as in the invalid block table 110.

  FIG. 4 is a diagram showing an example of the configuration of the area specification table 112. A set of a head logical address 401, a final logical address 402, and a leveling 403 constitutes one record. Leveling 403 defines whether leveling is prohibited or permitted for the address area from the first logical address 401 to the last logical address 402. Leveling 403 is prohibited in correspondence with logical addresses from 0000h of the first logical address 401 to 0001h of the final logical address 402. Leveling 403 is permitted in correspondence with logical addresses from 0002h of the first logical address 401 to 1F29h of the final logical address 402. Leveling 403 is prohibited in correspondence with logical addresses from 1F30h of the first logical address 401 to 1F39h of the final logical address 402.

  Here, it is assumed that the program code is stored after the logical address 1F30h. That is, data rewriting occurs in the area after the logical address 1F30h only when the program is updated, and the rewriting frequency is low. In addition, it is assumed that the logical addresses 0000h and 0001h have a file system boot code recorded therein. Again, the frequency of rewriting is low. In this way, the area where the frequency of rewriting is low is set as the leveling prohibited area. Note that the area designation table 112 has a configuration that can be arbitrarily set.

  FIG. 5 is a diagram illustrating an example of the configuration of the non-degraded block table 113. A physical block address of 1F00h is stored as a physical block address for refreshing data of a read-only physical block among physical blocks of invalid data in the flash memory unit 103.

  Since the configuration of the erase count table 114 is not directly related to the present embodiment, a description thereof will be omitted.

<3. Write / Read Processing and Refresh Processing>
FIG. 6 is a flowchart of the operation of the control unit 108 in the data writing process to the memory card 101. The memory card 101 starts a writing process in response to a write command specifying a logical address from a host device outside the memory card 101.

  The process 601 will be described. The control unit 108 determines a write destination physical block. Specifically, from among the physical block addresses registered in the invalid block table 110, a physical block having a physical block address with a smaller number of rewrites indicated in the erase count table 114 (hereinafter referred to as a write destination physical block). Select and confirm.

  Next, the process 602 will be described. Write data from the host device. The control unit 108 transfers the write data transferred from the host device to the write destination physical block of the flash memory unit 103 for writing. At this time, when the write data from the host device is less than the physical block unit, the data already written in the flash memory unit 103 is used and written to the flash memory unit 103 in the physical block unit. The reason why such processing is necessary is that data can be rewritten only in units of data erasure in the flash memory unit 103. Since data rewrite occurs at this time, the number of rewrites in the erase count table 114 corresponding to the write destination physical block is increased by "1" and updated.

  Next, processing 603 will be described. The address conversion table 109 and the invalid block table 110 are updated. The control unit 108 updates the physical address of the address conversion table 109 corresponding to the logical block address designated by the host device by replacing the physical block address of the write destination physical block.

  FIG. 7 is a flowchart of the operation of the control unit 108 in the data reading process for the memory card 101. The memory card 101 starts read processing by a read command designating a logical address from a host device outside the memory card 101.

  Processing 701 will be described. The control unit 108 determines a physical block to be read from. Specifically, the physical block of the physical block address of the address conversion table 109 corresponding to the logical block address designated by the host device (hereinafter referred to as a read source physical block) is determined.

  Next, processing 702 will be described. Data is read from the flash memory unit 103. Data is read from the read source physical block of the flash memory unit 103 and transferred to the host device.

  The determination process 703 will be described. It is determined whether or not a bit error of a threshold value or more has occurred during the read processing period of processing 702. The ECC data is added to the read data from the flash memory unit 103 every predetermined unit. The ECC 107 performs ECC correction every reading of a predetermined unit. There is an upper limit to the correction capability of the ECC 107. The threshold used in the determination process 703 is set to a value lower than the upper limit of the correction capability of the ECC 107. This is because the number of correction bits has increased due to bit errors due to the deterioration of data retention characteristics, but the error is caused by writing the corrected data back to the flash memory unit 103 at the correctable stage before exceeding the upper limit of the correction capability. It is determined whether or not a refresh process for setting the number of bits to “0” is necessary. If it is determined in the determination process 703 that the bit error is less than the threshold, the read process is terminated.

  If it is determined in the determination process 703 that a bit error greater than or equal to the threshold value has occurred, the refresh process of the process 704 is performed, and the read process ends.

  FIG. 8 is a flowchart of the refresh process of process 704.

  The determination process 801 will be described. It is determined whether it is a leveling prohibited area. The control unit 108 determines whether the logical block address designated by the host is a leveling prohibited area or a permitted area with reference to the area designation table 112. Leveling is processing for the purpose of smoothing the number of erasures of physical blocks in the flash memory unit 103. Specifically, the number of times of erasure is small because it has been written but not rewritten, but the physical block data in which valid data is stored is moved to another physical block with a large number of erasures. This is a process of invalidating data in a physical block with a small number of erasures and effectively using the physical block, and is generally called static wear leveling.

  If it is determined in the determination process 801 that it is a leveling prohibited area, a process 802 is performed, and a read-only refresh process is performed. If it is determined in the determination process 801 that it is a leveling permitted area, a process 803 is performed, and a normal refresh process is performed.

  FIG. 9 is a flowchart of the normal refresh process of process 803.

  Processing 901 will be described. A physical block to be a copy destination is determined from the invalid block table 110. As described in the writing process of FIG. 6, the addresses in the address conversion table 109 and the invalid block table 110 are exchanged and the erase count table 114 is updated for writing from the host device. Stores the physical block address of a physical block that has been degraded. In the normal refresh process, a physical block that has deteriorated due to data writing from the host device is selected.

  Processing 902 will be described. Copy the data to be refreshed. Data is copied from the read-source physical block determined in process 701 to the physical block selected in process 901.

  Processing 903 will be described. The address conversion table 109 and the invalid block table 110 are updated. The control unit 108 updates the physical address of the read-out physical block and the physical block address of the physical block to which data has been copied by the refresh process.

  FIG. 10 is a flowchart of the read-only refresh process 802.

  The process 1001 will be described. The physical block that is the copy destination is determined from the non-degraded block table 113. Since the number of times of erasing the physical block stored in the non-degraded block table 113 is small, the degree of degradation is low. In the read-only refresh process, a physical block with little deterioration is selected.

  The process 1002 will be described. Copy the data to be refreshed. Data is copied from the read-out physical block in process 701 to the physical block selected in process 1001.

  The processing 1003 will be described. The address conversion table 109 and the non-degraded block table 113 are updated. The control unit 108 updates the physical address of the read-out physical block and the physical block address of the physical block to which data has been copied by the refresh process.

  Since the read-source physical block that is the target of this read-only refresh process is the physical block in which the data of the logical address in the leveling prohibited area has been written, the number of erasures is small. Therefore, the number of erasures of the physical block address recorded in the non-degraded block table 113 after the table update is small.

  For reference, FIG. 11 shows a graph of the relationship between the number of rewrites and the data retention period. When the number of rewrites is small, the data retention period is long, but as the number of rewrites increases, the data retention period becomes shorter.

  By performing the control according to this embodiment, when the bit error of read-only data in which important data is stored increases, the bit error can be temporarily set to “0” by the refresh process. Furthermore, it is possible to copy data to a physical block with a small number of rewrites, which is not deteriorated, by the refresh process, and to maintain data retention characteristics at a high level. be able to.

  INDUSTRIAL APPLICABILITY The present invention is useful for a nonvolatile storage device with high user convenience that can maintain data retention reliability for data in an area that requires high data retention reliability among the nonvolatile storage devices. .

101 Memory Card 102 Controller 103 Flash Memory Unit 104 Host Interface Unit 105 Flash Memory Control Unit 106 Buffer Memory 107 ECC
108 Control Unit 109 Address Conversion Table 110 Invalid Block Table 111 Bad Block Table 112 Area Designation Table 113 Non-Degraded Block Table 114 Erase Count Table

Claims (11)

A nonvolatile memory controller for controlling a rewritable nonvolatile memory,
An address conversion table associating a logical address that can be designated from the outside with a physical address of the nonvolatile memory;
An error recognition / correction unit for recognizing the degree of deterioration of data stored in the nonvolatile memory;
A control unit for controlling the nonvolatile memory;
An external interface that communicates logical addresses and data with the outside;
An area specification table for managing leveling prohibited areas;
It consists of a non-degrading block table dedicated to leveling prohibited areas,
The leveling prohibition area stores a logical address that prohibits leveling processing,
Wherein the leveling prohibited area dedicated lossless block table, a physical address used when performing a refresh process for the leveling prohibition region are stored,
The error recognition / correction unit
Determining whether an error bit present in data corresponding to a logical address stored in the leveling prohibited area is equal to or greater than a threshold;
The controller is
When it is determined that the error recognition / correction unit is equal to or greater than the threshold value,
A nonvolatile memory controller characterized by refreshing data corresponding to a logical address having an error bit equal to or greater than the threshold value in a physical address stored in a non-degrading block table dedicated to the leveling prohibited area of the nonvolatile memory. A physical address in which data corresponding to a logical address having an error bit greater than or equal to the threshold is written,
2. The nonvolatile memory controller according to claim 1, wherein after the leveling process is completed, the leveling process is registered in a non-degrading block table dedicated to the leveling prohibited area. When data is written to the leveling prohibited area from the outside,
The nonvolatile memory controller according to claim 1, wherein the data is written to a physical address stored in a non-degrading block table dedicated to the leveling prohibited area. When data is written to the leveling prohibited area from the outside,
The physical address of the address conversion table corresponding to the logical address to be written from the outside,
4. The nonvolatile memory controller according to claim 3, wherein the nonvolatile memory controller is registered in a non-degrading block table dedicated to the leveling prohibited area. The logical address data of the leveling prohibited area managed by the area specification table is as follows:
5. The nonvolatile memory controller according to claim 4, wherein writing is prohibited only for reading. The nonvolatile memory controller further includes:
2. The nonvolatile memory controller according to claim 1, further comprising: an erase count table that manages the erase count corresponding to the physical address, and an invalid table that stores physical addresses that do not store valid data. The nonvolatile memory controller is
Of the physical addresses stored in the address conversion table,
Physical addresses with a small number of erases managed in the erase number table are
As a physical address subject to leveling processing,
The nonvolatile memory controller according to claim 6, wherein the data stored in the leveling process target physical address is moved to the physical address stored in the invalid table. The nonvolatile memory controller is
A physical address corresponding to a logical address managed in the area designation table is
The nonvolatile memory controller according to claim 7, wherein the physical address is not set as the leveling processing target physical address. The logical address of the leveling prohibited area managed by the area specification table is
9. The nonvolatile memory controller according to claim 8, wherein the nonvolatile memory controller can be rewritten from the outside. The nonvolatile memory controller according to any one of claims 1 to 9,
A storage unit having a rewritable nonvolatile memory device;
A non-volatile storage device. The non-volatile memory device is
The nonvolatile memory device according to claim 10, wherein the nonvolatile memory device is a NAND type flash memory.

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