JP5492672B2 - Design method of high-frequency switch circuit - Google Patents

Description

The present invention is a mobile phone, to a method of designing a high-frequency switch circuits used in wireless communication devices such as a data communication card.

  Many types of mobile phone communication systems are used in various countries around the world. For example, the GSM system which is the 2.5th generation digital communication system, the CDMA system which is the third generation, the WCDMA system, the TD-SCDMA system, etc. There is. Also, the frequency band used is not unified, for example, 850 MHz band, 900 MHz band, 1.8 GHz band, 1.9 GHz band in the GSM system, and 800 MHz band, 1.9 GHz band, 2 GHz band in the CDMA system, In the WCDMA system, 800 MHz band, 900 MHz band, 1.5 GHz band, 1.7 GHz band, 1.9 GHz band, and 2 GHz band are used, and in the TD-SCDMA system, 1.9 GHz band and 2 GHz band are used.

  Therefore, in order to receive mobile phone services all over the world, mobile phone terminals compatible with a plurality of communication systems and a plurality of frequency bands are required, and the demand for multi-mode and multi-band terminals is expanding. A plurality of communication systems, baseband ICs, RFICs, and the like that are compatible with a plurality of frequency bands have been developed, and these include a plurality of transceivers.

  On the other hand, as a terminal antenna, a method of covering all these frequency bands with one or a plurality of antennas is generally used. Therefore, an antenna switch that switches between a transceiver and an antenna is widely used.

  The antenna switch circuit plays a role of switching between an antenna and a transmission / reception terminal by a control signal from a baseband IC, RFIC, etc., and a high-frequency switch unit that makes a transmission path conductive or non-conductive, and the high-frequency switch unit It is composed of a control circuit or a logic decoder circuit for transmitting a control signal to the.

  In the high frequency switch portion of the antenna switch circuit, a semiconductor switch element such as a diode or FET is used as the high frequency switch element. The semiconductor switch element is turned on or off in accordance with a control signal and functions as a switch. Here, the semiconductor switch element behaves as a low-resistance element when in the ON state, and behaves as a low-capacitance element when in the OFF state. In the following description, the resistance value of the semiconductor switch element in the ON state is referred to as ON resistance, and the capacitance value of the switch element in the OFF state is referred to as OFF capacity. By switching between these ON states and OFF states, a desired antenna terminal and a transmission / reception terminal are switched by connecting or disconnecting necessary paths.

  Hereinafter, an SPmT (Single-Pole m-Throw) switch will be described as an example of a conventional high-frequency switch circuit. Note that m is a natural number.

  FIG. 9 shows a conventional high-frequency switch circuit. 9, PC is a common terminal, P1 to Pm are individual terminals, VC1 to VCm are control terminals, and a high frequency switch comprising n FETs Q11 to Q1n,..., Qm1 to Qmn with their sources and drains connected to each other. A series switch element group 11 to 1m composed of elements is connected between the common terminal PC and any one of the individual terminals P1 to Pm. It is assumed that the series switch element group connected between the series switch element group 11 and the series switch element group 1m is 1k, and the series switch element group adjacent thereto is 1 (k + 1). Note that k is a natural number.

  In the high-frequency switch circuit having such a configuration, the control terminals VC1 to VCm are set so that the series switch element group between one individual terminal and the common terminal is turned on and the other series switch element groups are turned off. By applying a predetermined control voltage signal, a desired transmission path is set as a passing path. For example, when the passage between the common terminal PC and the individual terminal P1 is used, a control voltage signal for turning on the FETs Q11 to Q1n is given to the control terminal VC1, the series switch element group 11 is turned on, and the remaining FET Q12 is turned on. By giving the control terminals VC2 to VCm a control voltage signal in which .about.Qmn is turned off, the series switch element groups 12 to 1m are turned off.

Generally, in a high-frequency switch circuit, harmonic distortion caused by nonlinear distortion generated in a high-frequency switch element, IMD, as well as an insertion characteristic of a passing path, an isolation characteristic corresponding to leakage from a passing path to a non-passing path, etc. (Inter
Modulation Distortion (intermodulation distortion) characteristics and the like are required to be in a desired range. Here, the harmonic distortion refers to an unnecessary leakage signal level of a frequency signal that is an integral multiple of the signal frequency transmitted through the passage path.

  By the way, when such a high-frequency switch circuit is used for the antenna switch circuit, a very high transmission power is input to supply the transmission power to the antenna. For example, in the 850 MHz and 900 MHz modes of the GSM system, a maximum of 35 dBm (about 3.16 W) is supplied to the antenna switch circuit.

  When such a high-power signal is input to the high-frequency switch circuit, the transmission signal is also distorted due to minute non-linearity of the high-frequency switch element, and spurious harmonic distortion is generated at a frequency that is an integral multiple of the input signal frequency. . Since the harmonic distortion signal becomes an interference wave for other applications using the corresponding frequency band, the generation amount thereof is legally strictly regulated as an allowable level of unnecessary radiation.

  On the other hand, in order to perform simultaneous transmission and reception in the UMTS system, the antenna switch circuit has a configuration in which one transmission / reception terminal and an antenna terminal are connected, and a transmission frequency band and a reception frequency band are separated by a duplexer separately connected to the transmission / reception terminal. . Since the transmission frequency signal is blocked by the duplexer and the frequency is different from the reception frequency, reception interference does not normally occur.

  However, when an interference signal flows from the antenna terminal, it is not blocked by the duplexer, and reception interference occurs. When the transmission frequency is fTX, the reception frequency is fRX, and m1 and n1 are natural numbers, a frequency signal (spurious) corresponding to | m1 · fTX ± n1 · fRX | exists and flows into the antenna switch circuit. When a transmission frequency signal is transmitted, an interference signal in the reception frequency band is generated due to the nonlinearity of the antenna switch circuit. This is called out-of-band blocking, and electrical specifications are important as IMD characteristics, which are imposed on the antenna switch circuit in UMTS applications.

  The generation factors of harmonic distortion and IMD as described above are due to the non-linearity of the high-frequency switch element and have the same generation mechanism, and the same method can be applied to improve these characteristics. Therefore, the description will be given by taking harmonic distortion as an example.

  Of the harmonic distortions, the second and third harmonics are particularly important. Higher-order harmonics can be a problem if they occur greatly, but if measures are taken for low-order second- and third-order harmonics, linearity can be improved and higher-order harmonics are also reduced at the same time. This is because there are many things that can be done.

  Although the generation mechanism differs between the second harmonic and the third harmonic, the third harmonic will be described here. Harmonic distortion is generated by the non-linearity of the ON resistance and the non-linearity of the OFF capacitance of the semiconductor switch element that constitutes the high-frequency switch circuit. In particular, the harmonic distortion generated by the non-linearity of the OFF capacity increases as the OFF capacity increases. In addition, since the amount of increase with respect to the increase in the OFF capacity increases as the harmonic order increases, the OFF capacity is preferably as small as possible. The ON resistance and OFF capacity are determined by the device characteristics used. For example, when a GaAsFET is used as the high-frequency switch element, the OFF capacitance of the GaAsFET in the OFF state is generally minute, and is a value of about 0.1 pF to 0.3 pF at most. However, since the ON resistance and the OFF capacitance are in a trade-off relationship, reducing only one corresponds to changing the device and is difficult.

  As a method of improving the distortion characteristics, the size of the high-frequency switch element is increased to lower the ON resistance, and the high-frequency switch elements are connected in series so that the ON resistance and the OFF capacitance are constant. It is known that a reduction effect can be obtained by reducing the ratio of applied power.

  In FIG. 10, the horizontal axis represents the number of GaAs FETs that are high-frequency switching elements connected in series (the number of stack stages), and the vertical axis represents the generation amount of the third harmonic distortion when the number of stages is one, and the number of stack stages and the OFF state The simulation value of the relationship with the difference ((DELTA) 3fo) with the 3rd harmonic generated from a high frequency switch element is shown. FIG. 10 shows a case where only the number of stack stages is increased while keeping the gate width of the GaAsFET as a high-frequency switching element constant, and the ON resistance increases in proportion to the increase in the number of stages. The case where the gate width of the FET is increased and the ON resistance does not increase is indicated by a broken line.

  As shown in FIG. 10, it can be seen that in any case, if the number of stack stages is increased, the third harmonic generated from the high-frequency switch element in the OFF state is reduced.

  However, when only the number of stack stages is increased, since the ON resistance increases, there is a problem that the insertion loss increases, and the strain generation amount in the ON state also deteriorates. It is known that. Therefore, by increasing the gate width of the FET in proportion to the increase in the number of stack stages, a method is adopted in which the ON resistance is kept constant and the insertion loss characteristic is not deteriorated. In addition, since the gate width in the ON state increases and the allowable current increases in proportion thereto, the amount of distortion can be reduced. Therefore, the distortion characteristics can be improved by increasing the number of stacked FET stages and increasing the gate width.

However, increasing the number of FET stack stages and increasing the gate width causes a new problem of increasing the area of the high-frequency switch circuit. FIG. 11 shows SP6T (Single
Pole 6 Throw: Single-pole 6-throw) Switch layout diagram, FIG. 11A shows a case where the number of stack stages is two, FIG. 11B shows a case where the number of stack stages is three, and the gate width is 1.5 times wider Is shown. In FIG. 11, detailed structures such as FET gate control electrodes and wirings are omitted, and the layout sizes are compared.

  As can be seen from FIG. 11, when the number of stack stages is increased and the gate width is increased, the layout area of the entire switch increases and is nearly doubled. When such a high frequency switch circuit is manufactured on a semiconductor substrate, the layout area is directly connected to the cost.

  Thus, simply increasing the number of high-frequency switch elements connected in series is a very effective method from the viewpoint of improving the distortion characteristics, but it is understood that the occupied area increases and the cost increases. .

  As a method for preventing an increase in the number of high-frequency switch elements connected in series, Patent Document 1 discloses an SPDT switch as shown in FIG. As shown in FIG. 12, the individual terminal P1 is a transmission terminal, and the individual terminal P2 is a reception terminal. Since a large amount of power is supplied to the transmission terminal P1, when the passage between the individual terminal P1 and the common terminal PC is used, the switch element group 12 connected between the common terminal PC and the individual terminal P2 in the OFF state. Is configured in a multi-stage stack so as to have a sufficient withstand voltage against transmission power. In FIG. 10, a two-stage stack is used. On the other hand, at the time of reception, since the power passing between the individual terminal P2 and the common terminal PC is weak power, the switch element 11 connected between the common terminal PC and the individual terminal P1 that is in the OFF state in this state has a high breakdown voltage. Is not required, and the number of stack stages of the switch element 11 is set smaller than that of the switch element 11.

  In such a conventional example, high power is supplied to the common terminal from one of the two paths to be switched, but it can be used only in an operating condition in which the same power is not supplied from the other terminal. Technology. In other words, an individual terminal for a transmission signal that requires high power or low distortion characteristics is limited to one path, and this method cannot be applied to a multiport or multiband switch as it is.

  Similarly, Patent Document 2 describes another high-frequency switch circuit. FIG. 13 shows this type of high-frequency switch circuit. As shown in FIG. 13, between the common terminal PC and the transmission terminal, the switch element 11 having one stack stage and the series switch element groups 11A to 11C having three stack stages are connected, and the common terminal PC and the reception terminal are connected. A switch element 12 having one stack stage and series switch element groups 12A to 12C having four stack stages are connected between the terminals. As described above, the number of stack stages of the switch elements of the transmission path and the number of stack stages of the switch elements of the reception path are often changed, and Non-Patent Document 1 also discloses an example thereof.

JP-A-8-70245 JP 2007-129571 A

D. Gotch, T. Goh, R. Jackson, “State-of-the-Art Low Loss, High Isolation SP6T Switch for Handset Application” European Conference on Wireless Technology 2004, Amsterdom, pp 17-20, 2004

As described above, in a high-frequency switch circuit that switches a large number of individual terminals, the distortion characteristics deteriorate as the number of individual terminals increases, and the number of stack stages must be increased in order to improve the distortion characteristics. On the other hand, when the number of stack stages is increased, there is a problem that the layout size increases and the cost increases as the chip area increases. The present invention is to solve the above problems, suppressing an increase in cost, and an object thereof is to provide a method of designing a good high-frequency switch circuits strain characteristics.

In order to achieve the above object, a high-frequency switch circuit according to a first invention of the present application includes one or more common terminals, three or more individual terminals including a transmission terminal or a transmission / reception terminal, and the common terminal and the individual terminals. A high-frequency switch circuit including a high-frequency switch unit that is connected between and switched between a connected state and a non-connected state by a control signal input from a control terminal, the high-frequency switch unit comprising a field-effect transistor Are connected in series in two or more, and the high-frequency switch unit connected between the common terminal and one of the individual terminals has n high-frequency switch elements in series (n is a natural number of 2 or more, the same applies hereinafter). The high-frequency switch unit configured by the connected first series switch element group and connected between the common terminal and another one of the individual terminals is n + A plurality of high-frequency switch elements connected in series to each other, and a gate width of the high-frequency switch elements constituting the second series switch element group is set to the first series switch element group. In the design method of the high frequency switch circuit set wider than the gate width of the high frequency switch element constituting the switch element group, the number of the second series switch element groups is the cumulative frequency probability distribution of the area of the high frequency switch section. It is characterized by setting from the cost coefficient obtained by dividing by.

  According to the method for designing a high frequency switch circuit of the present invention, in a high frequency switch circuit that switches between three or more individual terminals consisting of a transmission terminal or a transmission / reception terminal, distortion characteristics that deteriorate as the number of individual terminals increases and distortion characteristics are improved. It is possible to finely adjust the trade-off relationship of the number of stacked stages of FETs used for the series switch element, and to achieve an optimum strain characteristic while suppressing an increase in chip area.

  The high-frequency switch circuit designed according to the present invention has a small chip area and the distortion characteristics are set so that the desired characteristics can be obtained. can do.

It is explanatory drawing of the SPmT switch which is the 1st Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention. It is explanatory drawing of SP6T switch which is the 2nd Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention. It is explanatory drawing of the simulation result of the 3rd harmonic characteristic of the Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention, and a prior art example. It is a figure explaining the design method of the high frequency switch circuit of this invention. FIG. 6 is a layout diagram of an SP6T switch that is a second embodiment of the high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention. It is another explanatory drawing of SP6T switch of the Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention. It is explanatory drawing of the 3rd Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention. It is explanatory drawing of the 4th Example of the high frequency switch circuit by the design method of the high frequency switch circuit of this invention. It is explanatory drawing of the SPmT switch by a prior art example. It is explanatory drawing of the simulation result of the 3rd harmonic characteristic of a prior art example. It is a layout diagram of a conventional SP6T switch. It is explanatory drawing of the conventional SPDT switch. It is explanatory drawing of another conventional high frequency switch circuit.

The high-frequency switch circuit according to the design method of the high- frequency switch circuit of the present invention comprises a high-frequency switch unit connected between a common terminal and a transmission terminal or between a common terminal and a transmission / reception terminal, with series switch element groups having different numbers of stack stages. ing. In addition, the high frequency switch circuit design method of the present invention is configured to determine the number of series switch element groups having different numbers of stack stages based on the cost factor. Examples of the present invention will be described in detail below.

FIG. 1 is an explanatory diagram of an SPmT switch circuit which is a first embodiment of a high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention. Switching between the common terminal PC and the m individual terminals P1 to Pm is performed by the m control terminals VC1 to VCm. A series switch element group 11 having an n-stage (n is a natural number of 2 or more) multi-stage stack configuration is connected between the individual terminal P1 and the common terminal PC. The series switch element group 11 connects the sources and drains of the FETs Q11 to Q1n, which are high-frequency switch elements, to each other, and the gates of the FETs are connected to the control terminal VC1 via resistors.

  Like the series switch element group 11, the sources and drains of the FETs Qk1 to Qkn are connected to each other between the kth individual terminal Pk (k is a natural number satisfying 1 <k <m) and the common terminal PC. The series switch element group 1k connected to the control terminal VCk via a resistor is connected to the gate of each FET. Further, between the (k + 1) th individual terminal P (k + 1) and the common terminal PC, the sources and drains of the FETs (k + 1) 1 to Q (k + 1) (n + 1) are connected to each other, and the respective FETs are connected. The series switch element group 1 (k + 1) connected to the control terminal VC (k + 1) through a resistor is connected to the gate. The series switch element group in which the sources and drains of the (n + 1) -stage FETs are connected to each other is connected to the (k + 1) th to mth individual terminals P (k + 1) to Pm.

The FETs used for the series switch element groups 11 to 1m are designed at least as follows.
P _max > 2 {N (Vp−VC)} ² / Zo
Here, N is the number of stacked FET stages, Vp is the pinch-off voltage of the FET used, VC is the switching voltage, and Zo is the characteristic impedance. In general, Zo is 50Ω. Pmax is the maximum power supplied to the common terminal PC. The switching voltage VC is a control voltage of the high-frequency switch element. If the potential on the RF line through which the RF signal flows is V0 and the control voltage when the high-frequency switch element is turned off is VOFF, VC = V0−VOFF. . For example, if V0 = 0V, that is, the GND potential and VOFF = −6V, VC = 6V. Another example of the same VC is V0 = 6V and VOFF = 0V. The pinch-off voltage Vp may be expressed as a negative value in the case of an n-channel depletion mode GaAsFET, but the Vp is a positive value. That is, Vp is 0.5 to 1.0 V with respect to a negative value of about −0.5 V to −1.0 V. For example, if Pmax = 36 dBm (= 4 W), Vp = 0.8 V, and N = 3, VC> 4.13 V. The condition of VC> 4.13 V shown in this example is the minimum necessary voltage, and in actuality, more than this may be necessary depending on the process and device rules used.

  If comprised in this way, compared with the case where the number of stack stages of all the series switch element groups is set to n, there exists a series switch element group which set the number of stack stages to n + 1, thereby improving the distortion characteristics. On the other hand, compared to the case where the stack dances of all the series switch element groups are set to n + 1, the increase in the layout size can be suppressed by the series switch element group having the stack stage number n.

  Note that the number k of series switch element groups where n is the number of stack stages and the number m-k of series switch element groups where the number of stack stages is n + 1 are determined by the cost factor described below.

  Next, an SP6T switch will be described as a more specific example. FIG. 2 is an explanatory diagram of the SP6T switch. Series switch element groups 11, 12, and 13 consisting of two-stage stack FETs are used for the individual terminals P1 to P3, and series switch element groups 14, 15, and 16 consisting of three-stage stack FETs are used for the individual terminals P4 to P6. ing.

  The high-frequency switch circuit according to the present embodiment configured as described above has a configuration in which all series switch element groups are constituted by three-stage stack FETs, or a conventional high-frequency switch in which all series switch element groups are constituted by two-stage stack FETs. Compared with the circuit, it is as follows.

Assume that the amount of third-harmonic generation per stage of a switch FET having a unit gate width is −97.5 dBc per 20 dBm input. The relationship of harmonics when increasing the number of stages with the same gate width is 3rd order harmonic fluctuation = −40 × log ₁₀ (N) (dB) when the number of stages is N. For example, in the case of a two-stage stack ( For N = 2), it is -12.04 (dB). This is a harmonic improvement of 12.04 dB compared to the single-stage FET.

On the other hand, when increasing the gate width with the same number of stages, assuming that the ratio to the unit gate width is Wg, the third harmonic fluctuation = 10 × log ₁₀ (Wg) (dB), so for example, the gate width ratio is doubled ( If Wg = 2), the deterioration is 3.02 dB compared to the unit gate width.

Further, the third harmonic fluctuation for the number M of paths in the OFF state can be calculated by the same method as the increase in the gate width, and the third harmonic fluctuation = 10 × log ₁₀ (M) (dB). When the number of OFF routes is 2 as compared with the case where the number of routes is 1, the deterioration is 3.02 (dB).

Using such a relationship, an example of a high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention (2-stack & 3-stack mixed), a conventional example of a two-stage stack FET (2-stack), three stages FIG. 3 shows the simulation results of the conventional stack FET (3-stack). In FIG. 3, an allowable value required for a generally used high-frequency switch circuit is indicated by a thick wavy line.

  As shown in the figure, for an input of 35 dBm, the conventional example of the two-stage stack FET is -69.5 dBc, and the conventional example of the three-stage stack FET is -74.8 dBc. It can be seen that it is .9 dBc. In this case, it can be seen that the conventional example of the three-stage stack FET and the present embodiment satisfy the desired specifications.

によって求められる。ここで求めるｆは３次高調波に対する歩留に相当する。そこで歩留ｆで高周波スイッチ回路のサイズを割ると、コストに相当する値が求められる。ここではこれをコスト係数と呼ぶことにする。 By the way, in the manufacturing process, variations in the manufacturing process occur. Therefore, by assuming a standard deviation and distribution, a statistical property considering variation is given. Assuming that the standard deviation is σ = 1 dB and assuming that the variation follows a normal distribution, an index of yield is introduced. The cumulative frequency probability distribution satisfying the desired characteristics (specifications) is 3fo for the value of the third harmonic, Spec for the allowable value of the third harmonic, and σ for the standard deviation.

Sought by. F obtained here corresponds to the yield with respect to the third harmonic. Therefore, when the size of the high-frequency switch circuit is divided by the yield f, a value corresponding to the cost is obtained. Here, this is called a cost coefficient.

  Next, let's compare layout sizes. As described above, when the number of stack stages increases, it is necessary to increase the gate width, resulting in an increase in area. Accordingly, in the three-stage stack FET, there is a concern that the layout size becomes large and the cost is increased, but the yield of the third-order harmonic characteristics is improved. On the other hand, in the two-stage stack FET, the layout size is reduced and cost reduction can be expected, but the yield of the third harmonic characteristic is lowered. Therefore, by setting the number of series switch element groups of the three-stage stack FET to a desired number, a high frequency switch circuit that does not have a large layout area and obtains a desired third harmonic characteristic can be obtained.

  Next, a method for determining the number of two-stage stack FETs and three-stage stack FETs will be described. As an example, consider the case of an SP6T switch. FIG. 4 is a graph illustrating a method for setting the number of three-stage stack FETs when the series switch element group of SP6T switches is configured by a two-stage stack FET and a three-stage stack FET. As shown in FIG. 4, by increasing the number of three-stage stack FETs, the layout area becomes larger and the size ratio compared to the case where all series switch element groups are constituted by two-stage stack FETs (k = 0). Becomes larger. On the other hand, by increasing the number of three-stage stack FETs, the yield of the third harmonic characteristics is also improved. Therefore, when a value obtained by dividing the layout area by the yield (referred to as a cost coefficient) is compared, in the case where the number of the two-stage stack FETs is 0, in the case of 2 to 3 better results than in the case of 6 It turns out that it becomes.

  In this way, a semiconductor switch circuit with good third-harmonic characteristics can be obtained at a lower cost than when the high-frequency switch circuit is configured with only a two-stage stack FET or only with a three-stage stack FET. I understand that

  In the SP6T switch, the layout in the case of three 2-stage stack FETs and three 3-stage stack FETs is as shown in FIG. Moreover, in order to improve the isolation between the individual terminals, a shunt switch can be provided at the individual terminal. As shown in FIG. 6, the individual terminal P1 has a shunt switch 1S composed of switch elements Q11S and Q12S, the individual terminal P2 has a shunt switch 2S composed of switch elements Q21S, Q22S and Q23S, and the individual terminal P4 has an individual terminal P4. The shunt switch 4S including the switch elements Q41S and Q42S may be connected to the individual terminal P5 and the shunt switch 5S including the switch elements Q51S, Q52S, and Q53S may be connected to the individual terminal P5.

  Note that no shunt switch is connected to the individual terminal P3 and the individual terminal P6, the shunt switches 1S and 4S are composed of FETs having a two-stage stack structure, and the shunt switches 2S and 5S are composed of FETs having a three-stage stack structure. However, various modifications can be made to obtain the desired isolation characteristics.

  In FIG. 6, one end of the switch element is a ground terminal. This is one of the switch configurations when the DC potential of the common terminal PC and the individual terminals P1 to P6 through which high-frequency signals flow is biased to 0V. In the case of the biasing method, a generally well-known method of inserting a DC blocking capacitor between the ground terminal and the ground terminal may be applied.

  Although the third harmonic characteristic has been described above, the generation mechanism of the IMD3 (Third Intermodulation Distortion) characteristic among the IMD characteristics is the same as that of the third harmonic characteristic. It is possible to optimize the trade-off between characteristics and size.

FIG. 7 shows a third embodiment of the high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention, and is further provided on the individual terminal side of one series switch element group 16 of the SP6T switch of the second embodiment shown in FIG. By providing the switch elements 17 and 18, it branches to two individual terminals, the individual terminal 6A and the individual terminal 6B, to form an SP7T switch.

  In this embodiment, the number of stack stages is two, three, and four stages of series switch element groups. However, as in the first embodiment, the number of series switch element groups is the layout. It can be set as appropriate in consideration of the size and third harmonic characteristics.

FIG. 8 shows a fourth embodiment of the high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention. A voltage generation circuit 200 and a control logic circuit 100 are added to the semiconductor switch circuit described in the first embodiment of the high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention. The voltage generation circuit 200 is provided to compensate for the insufficient voltage when the externally supplied voltage (VDD) is insufficient when driving the series switch element group of the present invention. The control logic circuit 100 is for decoding a control signal supplied for the purpose of switching a plurality of paths. The polarity of the power supply voltage supplied from the outside is usually a positive voltage, but the voltage generating circuit may be a positive voltage boosting circuit that further boosts this voltage or a negative voltage generating circuit whose polarity is inverted. A simple method is to use a charge pump for mounting on an integrated circuit.

  The control logic circuit generates a control signal having a different voltage and a different number of bits from a control signal supplied from the outside, and includes a decoder circuit, a level shift circuit, a buffer circuit, and the like. The control signal corresponds to either a parallel control signal or a serial control signal, which is selected by a desired function as a switch circuit. These voltage generation circuit and control logic circuit are preferably formed on the same chip as the switch circuit because it can be miniaturized most, but it is preferable to select a device process suitable for each function. It is also possible to form the switch circuit with GaAs IC and the voltage generation circuit with silicon IC.

In the above description of the embodiments of the high-frequency switch circuit according to the high-frequency switch circuit design method of the present invention, the configuration of the high-frequency switch circuit has been limited to the SPmT switch configuration having one common terminal PC. Needless to say, the present invention can be similarly applied to a plurality of DPmT (Double Pole Throw) and 3PmT (3 Pole Throw) switches.

PC: common terminal, P1, P2-Pm, P6A, P6B: individual terminal, 11-16: series switch element group, VC1, VC2-VCm, VC6A, VC6B: control terminal

Claims (1)

One or two or more common terminals, three or more individual terminals consisting of transmission terminals or transmission / reception terminals, connected between the common terminals and the individual terminals, connected by a control signal input from the control terminal, A high-frequency switch circuit including a high-frequency switch unit for switching a connection state,
In the high-frequency switch unit, two or more high-frequency switch elements composed of field effect transistors are connected in series,
The high-frequency switch unit connected between the common terminal and one of the individual terminals is a first series switch element in which n (n is a natural number of 2 or more, the same shall apply hereinafter) number of the high-frequency switch elements are connected in series. Composed of groups,
The high-frequency switch unit connected between the common terminal and another one of the individual terminals is configured by a second series switch element group in which n + 1 or more high-frequency switch elements are connected in series.
A high-frequency switch circuit design method in which a gate width of the high-frequency switch element constituting the second series switch element group is set wider than a gate width of the high-frequency switch element constituting the first series switch element group In
The number of the second series switch element groups is set from a cost coefficient obtained by dividing the area of the high-frequency switch section by the cumulative frequency probability distribution .

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