JP5489786B2 - Decoding device - Google Patents

Description

  The present invention relates to a decoding apparatus, and more particularly to a technique for correcting an error of error data included in a digital signal when the encoded digital signal transmitted or recorded is received or reproduced.

    In recent years, digitalization of television broadcasting and radio broadcasting has been promoted, and various digital broadcasting services including terrestrial digital television broadcasting have been started in Japan. In Japan and Europe and the United States, error correction codes are used for transport streams (hereinafter also referred to as TS) defined by MPEG2 (Moving Picture Experts Group Phase 2), which is an international standard for compression coding as a terrestrial digital broadcasting system. The signal is transmitted in the form of an OFDM (Orthogonal Frequency Division Multiplexing) signal after performing signal processing such as conversion, interleaving, and digital modulation.

  In particular, digital terrestrial television broadcasting in Japan is implemented by the ISDB-T (Integrated Services Digital Broadcasting for Terrestrial Television Broadcasting) system.

  As digital broadcasting progresses, error correction is one of the important technologies, and improvement of error correction capability is required in many systems. As an error correction method in digital communication, a concatenated code system is often used. A concatenated code is a method of performing two-stage encoding consisting of an inner code and an outer code. As a typical example of a concatenated code system, a convolutional code is used as an inner code and a block code is used as an outer code. A Solomon (hereinafter also referred to as RS) code is used, and an interleaver is inserted between the inner code and the outer code.

  A receiver error correction apparatus for the above-described signal is realized by a configuration of an inner code decoder (for example, a Viterbi decoder), a deinterleaver, and an outer code decoder (for example, an RS decoder).

  In the above-described concatenated code system, it is known that error correction capability can be improved by devising a decoding method. Specific methods are an RS decoding method using known error position information and an iterative decoding method.

  In the RS decoding method using the former known error position information, when a burst error is output from the inner code decoder, the data adjacent to each other at the time of input is time-direction at the time of output by regular data rearrangement by the deinterleaver. The error data position (arrangement) in the TS packet is treated as known error position information (hereinafter also referred to as an erasure), and error correction is performed by the outer code decoder. There has been proposed a technique for improving the error correction capability by using the above-described erasure when performing (see, for example, Patent Document 1).

  On the other hand, the latter iterative decoding method is realized by a configuration that is used when convolutional decoding is performed again by the inner code decoder using the decoding result of the outer code decoder as a prior probability sequence, and is a problem of the convolutional code. It is shown to be effective for correcting burst errors that occur during decoding (see, for example, Patent Document 2).

JP 2004-215240 A (summary, FIG. 1) Japanese Patent Laying-Open No. 2009-200732 (summary, FIG. 15)

  However, both Patent Document 1 and Patent Document 2 function as performance improvement only when there is a packet in which RS decoding can be corrected, and it is not an effective method for packets before that.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a decoding device that can further improve error correction capability.

The decoding device according to the present invention provides:
An inner code decoder that receives the demodulated data and performs convolutional decoding to output first decoded data;
A first data rearrangement circuit that regularly rearranges the order of the first decoded data and outputs first rearranged decoded data;
An error packet identification signal for performing block decoding based on the first rearranged decoded data and outputting second decoded data and indicating whether or not there is an error in a packet composed of the second decoded data An outer code decoder for generating
The second decoded data and the error packet identification signal are rearranged according to a rule reverse to that of the first data rearrangement circuit, and the second rearranged decoded data and the rearrangement error packet identification signal are output. A data relocation circuit;
A delay element for delaying the first decoded data and outputting the first delayed decoded data;
An error position detector that detects an error position from the first delayed decoded data, the second rearranged decoded data, and the rearranged error packet identification signal, and outputs error position estimated value data;
A third data rearrangement circuit that regularly rearranges the order of the error position estimation value data and outputs rearrangement error position estimation value data;
The first data rearrangement circuit regularly rearranges the order of the second rearrangement decoded data,
The outer code decoder is
Block decoding is performed on the rearranged decoded data obtained by rearranging the second rearranged decoded data by the first data rearrangement circuit based on the rearranged error position estimated value data. It is characterized by.

  According to the present invention, when performing outer code decoding again, it is possible to use an outer code decoding method using an erasure for a packet before a packet whose outer code decoding can be error corrected at the first time. Further improvement is possible.

It is a block diagram which shows the structure of the decoding apparatus of Embodiment 1 of this invention. It is a block diagram which shows the structural example of the outer code decoder of FIG. It is a block diagram which shows the structural example of the error position detector of FIG. It is a block diagram which shows the structure of the decoding apparatus of Embodiment 2 of this invention. It is a block diagram which shows the structure of the decoding apparatus of Embodiment 3 of this invention.

  Hereinafter, a decoding device to which the present invention is applied will be described with respect to an embodiment of the present invention. In the following embodiments, a Viterbi algorithm is applied as the decoding algorithm of the inner code decoder, and RS decoding is applied as the decoding algorithm of the outer code decoder. The invention is not limited to this.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a decoding apparatus according to Embodiment 1 of the present invention. The illustrated decoding apparatus decodes demodulated data, and includes an inner code decoder 11, a data changeover switch 12, deinterleavers 13a and 13b, an outer code decoder 14, interleavers 15a and 15b, The output of the outer code decoder 14 is decoded data having a delay element 16 and an error position detector 17.

Next, the operation of the decoding apparatus according to this embodiment will be described.
The demodulator (not shown) reproduces the carrier, clock, etc. from the OFDM modulation signal received from the outside, and also converts the signal on the time axis into the signal on the frequency axis by Fourier transforming the OFDM signal, and differential demodulation And synchronous demodulation processing. Next, the differentially and synchronously demodulated signals are regularly rearranged by a frequency and time deinterleaver, and then converted into bit data by a demapping process. Since the bit data after demapping is hierarchically transmitted by transmitting a plurality of layers having different transmission characteristics at the same time, a bit deinterleaver is provided for each specified layer information (up to three systems: A layer, B layer, C layer). Dummy data is inserted into the mask portion of the data string implemented in order to make the coding rate variable on the transmission side by regular data rearrangement and depunctured, and the data is stored in the buffer for each layer. When data for one TS packet is accumulated, the data is output to the subsequent stage from the hierarchical buffer corresponding to the hierarchical level. When no data for one TS packet is accumulated in any hierarchical buffer, a null TS packet is output to the subsequent stage.

  The inner code decoder 11 decodes the data convolved on the transmission side using the Viterbi algorithm with respect to the output from the above-described hierarchical buffer, and outputs decoded data Da. The Viterbi algorithm can be decoded by sequentially calculating the state transition probability based on the likelihood information included in the input demodulated data, and selecting the maximum likelihood path from the calculated state transition probability. However, the Viterbi algorithm has a tendency to increase the probability of occurrence of a burst error caused by error correction at the time of error correction depending on the state of the transmission path.

  Data decoded by the Viterbi algorithm is regularly rearranged by a deinterleaver 13a as a data rearrangement circuit provided for each layer, and is output as rearranged decoded data Dab. Note that the deinterleave 13a applied to terrestrial digital broadcasting in Japan has 12 stages, and the delay amount of each stage is 1 TS packet, so the adjacent data in the input data string is the output data string. The data order is rearranged so that the adjacent positions are shifted by 1 TS packet in the time direction. That is, even when there is a burst error in the decoded data Da from the inner code decoder 11, the error data is regularly distributed in the output data string of the deinterleaver 13a.

  The outer code decoder 14 performs block decoding based on the rearranged decoded data Dab and outputs the decoded data Db, and also indicates an error packet identification signal Es indicating whether or not there is an error in the packet composed of the decoded data Db. Is generated.

  As shown in FIG. 2, the outer code decoder 14 includes a decoding unit 41, an erasure correction decoding unit 42, an error packet identification signal generation unit 43, an error position information selection unit 44, and a selection unit 45.

  The decoding unit 41 performs error correction processing by the RS decoding algorithm on the TS packet output from the deinterleaver 13a using the redundant data added on the transmission side, and outputs the decoded data to the selection unit 45 as TS data. To do. At this time, if error correction is possible, error position information (erasure) is output to the erasure correction decoding unit 42.

The erasure correction decoding unit 42 calculates the error position of the next TS packet from the error position information (erasure) output from the decoding unit 41, and is added on the transmission side to the TS packet output from the deinterleaver 13a. Error correction processing is performed by the RS decoding algorithm using the redundant data and the calculated error position information, and the decoded data is output to the selection unit 45 as TS data.
The erasure correction decoding unit 42 also calculates the error position of the next TS packet using the error position estimation value output from the error position information selection unit 44, and outputs the TS packet output from the deinterleaver 13a. On the other hand, error correction processing is performed by the RS decoding algorithm using the redundant data added on the transmission side and the calculated error position information, and the decoded data is output to the selection unit 45 as TS data.

The error packet identification signal generation unit 43 calculates a syndrome for the decoded TS data output from the decoding unit 41 and the erasure correction decoding unit 42 to identify whether or not the TS packet has an error ( Error packet identification signal) Es is generated.
The generated error packet identification signal Es is output to the interleaver 15a.
The error packet identification signal generation unit 43 also determines which of the TS data output from the decoding unit 41 and the TS data output from the erasure correction decoding unit 42 is decoded into correct TS data by error correction, A selection signal based on the determination result is output.
The selection unit 45 selects either TS data output from the decoding unit 41 or TS data output from the erasure correction decoding unit 42 based on the selection signal, and outputs the selected data as decoded data Db.
Note that the error packet identification signal generation unit 43 performs the same operation as the syndrome generation unit 41a included in the decoding unit 41 that decodes using redundant data added on the transmission side, and is therefore shared with the syndrome generation unit 41a. You may comprise.

  The error position information selection unit 44 selects a predetermined number of error position information in the TS packet to be processed based on the input error position estimation value Epb. For example, a predetermined number of error position estimation values Epb having a large value are selected, error position information corresponding to the selected error position estimation value Epb is calculated, and output to the erasure correction decoding unit 42. The “predetermined number” may be designated from the outside, may be set in advance, or may be adaptively changed according to the state of the transmission path.

  The above-described example is merely an example, and the present invention is not limited to this.

  The interleavers 15a and 15b receive the error packet identification signal Es and the decoded data Db, respectively, which are output from the outer code decoder 14, and both rearrange the data according to the same rule (the rule opposite to that of the deinterleaver 13a). An arrangement error packet identification signal Esb and rearranged decoded data Dbb are output.

  The delay element 16 delays the decoded data Da of the inner code decoder 11 and outputs delayed decoded data Dad synchronized with the decoded data Db rearranged by the interleaver 15b.

  The error position detector 17 detects an error position from the delayed decoded data Dad output from the delay element 16, the rearranged error packet identification signal Esb output from the interleavers 15a and 15b, and the rearranged decoded data Dbb. An estimated value is calculated, and error position estimated value data Ep indicating the calculated error position estimated value is output.

  FIG. 3 is an example of a block diagram showing the configuration of the error position detector 17. The illustrated error position detector 17 includes an exclusive OR calculator 51, a different data detector 52, a state discriminator 53, and a delay element 54.

The exclusive OR calculator 51 calculates an exclusive OR of the input delayed decoded data Dad and rearranged decoded data Dbb.
When the delayed decoded data Dad and the rearranged decoded data Dbb are the same, the output signal from the exclusive OR calculator 51 becomes the logical value “0”, and when they are different, the logical value “1”.
The different data detector 52 detects whether or not the input data (delayed decoded data Dad and rearranged decoded data Dbb) is different data based on the output of the exclusive OR calculator 51, and the detection result is obtained. The signal shown is output. Although the exclusive OR calculator 51 has been described as an example, the present invention is not limited to this. For example, it may be configured by an alternative operation such as a comparator or a differencer as an alternative.

  The state discriminator 53 calculates an index representing the probability that the current data is error data from the signal from the different data detector 52 and the rearranged error packet identification signal Esb output from the interleaver 15a.

  For example, the state discriminator 53 operates so as to provide an index indicating the probability that the current data is error data in three stages: when estimating that there is no error, when estimating it as a single error, and when estimating as continuous error. You may do it. Instead, in the same way as above, in addition to the case of estimating no error and the case of single-shot error, the case of estimating the above continuous error is classified into a plurality of stages according to the number of consecutive times. You may operate | move so that said parameter | index may be given in four steps or more. When classifying in a plurality of stages according to the number of consecutive errors, for example, a plurality of threshold values are set, and it is determined to which stage the number of consecutive errors belongs according to a comparison result with each threshold value.

A more specific example of the operation of the state discriminator 53 will be shown.
When the different data detector 52 determines that the data is the same (the output signal of the different data detector 52 is “0”), and the error packet identification signal Esb indicates “no error”, the inner code decoder Since it is found that there is no error in the 11 decoded data Da, the error data index is set to “0” and the internal burst error counter 53a is initialized.

  If the different data detector 52 determines that the data is different (the output signal of the different data detector 52 is “1”) and the error packet identification signal Esb indicates “no error”, the inner code decoder Although there is an error in the 11 decoded data Da, since it can be seen that the error has been corrected by the outer code decoder 14, the error data index is set to “0” and the burst error counter 53a is counted up.

  If the different data detector 52 determines that the data is the same (the output signal of the different data detector 52 is “0”), but the error packet identification signal Esb indicates “in error”, the inner code It can be seen that there is an error in the decoded data Da of the decoder 11 and the packet data cannot be corrected even by the outer code decoder 14. Here, when the burst error counter 53a determines the state only with data prior to the current data, if the burst error counter 53a is counted, the probability of a burst error is high, so the error data index is set to “0.7”. If not counted, the probability of a single error is high, so “0.2” is set. In the case where two burst error counters 53a are provided (in FIG. 3, the second burst error counter 53b is indicated by a dotted line block) and state determination is performed using the data before and after the current data, both burst error counters 53a and 53a If 53b is counting up, the probability of being in the middle of a burst error is very high, so the error data index is set to “1.0”, and if either one of the burst error counters 53a or 53b is counting up, Since the probability of being the end of a burst error is high, the error data index is set to “0.5”. If both burst error counters 53a and 53b are not counted, the probability of a single error is high, so the error data index is “0. 2 ”.

  The above-described example is merely an example, and the present invention is not limited to this.

  The delay element 54 delays the rearranged decoded data Dbb output from the interleaver 15b to synchronize with the error position estimated value data Ep output from the state discriminator 53, and outputs the delayed decoded data Dc.

  The switch 12 selects the decoded data Da from the inner code decoder 11 at the first outer code decoding, and selects the decoded data Dc output from the error position detector 17 at the second time and thereafter. In this way, data that has been once error-corrected by the outer code decoder 14 can be prevented from being subjected to error correction processing again, and performance degradation due to repetition can be prevented.

The deinterleaver 13a regularly rearranges the input data (decoded data Dc) in the same manner as described above. The deinterleaver 13b rearranges the order of the error position estimated value data Ep output from the error position detector 17 according to the same rules as the deinterleaver 13a.
The outer code decoder 14 performs RS decoding on the decoded data Dcb rearranged by the deinterleaver 13a based on the error position estimated value Ep rearranged by the deinterleaver 13b. Since this decoding is performed on the data corresponding to the data once decoded by the outer code decoder 14, it can be said to be “re-decoding”.

  As described above, according to the decoding apparatus of the present embodiment, the data Dab (delayed data Dad) decoded by the inner code decoder 11 and the data Db (rearranged data Db decoded by the outer code decoder 14). ), In other words, the difference between the two is taken, and the error packet identification signal Es calculated at the time of outer code decoding is also used, so that the data Da decoded by the inner code decoder 11 is obtained. Error code can be detected with high accuracy, and an outer code decoding method using an erasure can be used for a packet before a packet whose outer code decoding is error-correctable at the first time when performing outer code decoding again. Thus, the error correction capability can be further improved.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing the configuration of the decoding apparatus according to Embodiment 2 of the present invention. In FIG. 4, the same components as those of the decoding apparatus according to Embodiment 1 shown in FIG.

  The decoding apparatus according to the present embodiment includes a memory (storage element) 21 that stores demodulated data, and a switch 22 that switches the demodulated data and data from the memory 21, and is an error that is one of the outputs of the error position detector 17. The difference from Embodiment 1 is that the deinterleaver 13b (FIG. 1) to which the position estimated value data Ep is input is not provided, and the error position estimated value data Ep is input to the inner code decoder 11.

  The memory 21 stores the demodulated data so that the inner code decoder 11 performs convolution decoding by the Viterbi algorithm again. The switch 22 selects the demodulated data input at the time of the first inner code decoding, and selects the demodulated data stored in the memory 21 after the second time. By doing so, the inner code decoder 11 can repeatedly perform error correction processing.

  The operation of the inner code decoder 11 using the first demodulated data is the same as in the first embodiment, but the second and subsequent operations of the inner code decoder 11 are included in the input demodulated data. In the process of selecting the maximum likelihood path from the state transition probability calculated based on the likelihood information, a state different from the data indicated by the current state transition direction based on the error position estimated value data Ep from the error position detector 17 A predetermined value is added to, subtracted from, or multiplied by the state transition probability calculated so as to select data indicating the transition direction. The predetermined value is preferably determined based on the error position estimated value data Ep, but may be given from the outside or set in advance.

  Thus, according to the decoding apparatus of the present embodiment, the error position detector 17 can accurately detect the error position of the data decoded by the inner code decoder, and the error position estimated value from the error position detector 17 can be detected. It is determined that the data in which the error is detected in the decoded data Da of the first inner code decoder 11, that is, the data estimated that there is an error is caused by the error correction by the inner code decoding, and the portion The weight of the index when selecting the maximum likelihood path is changed so that the reverse decoding result is obtained with respect to the data of the data, that is, weighting is performed so that it is difficult to select data indicating the wrong transition state direction at the first time. Thus, the error correction capability can be improved. Furthermore, since error position detection is effective for a packet before a packet that can be error-corrected by outer code decoding, the error correction capability can be further improved.

Embodiment 3 FIG.
FIG. 5 is a block diagram showing the configuration of the decoding apparatus according to Embodiment 3 of the present invention. In FIG. 5, the same components as those in the decoding apparatuses according to Embodiment 1 and Embodiment 2 shown in FIGS.

  The decoding apparatus according to the present embodiment includes a memory 21 that stores demodulated data, and a switch 22 that switches the demodulated data and data from the memory 21, and an error position estimated value Ep that is one of the outputs of the error position detector 17. Is also input to the inner code decoder 11, which is different from the first embodiment. On the other hand, it differs from the second embodiment shown in FIG. 4 in that a data interleaver 13b is added.

  The operations of the memory 21 and the switch 22 are the same as those described in the second embodiment. The second and subsequent operations of the inner code decoder 11 are the same as those described in the second embodiment.

  As described above, according to the decoding apparatus of the present embodiment, the error position estimation value Ep from the error position detector 17 is the data in which the error of the decoded data Da of the first inner code decoder 11 is detected, that is, the error It is determined that the data estimated to have existed because of erroneous correction by inner code decoding, and the weighting of the index when selecting the maximum likelihood path so that the reverse decoding result is obtained with respect to the data of that portion It is possible to improve error correction capability by changing. Furthermore, since error position detection is effective for a packet before a packet that can be error-corrected by outer code decoding, the error correction capability can be further improved.

  In addition, when the outer code is decoded again, the outer code decoding method using the erasure can be used for the packet before the packet that can be error corrected at the first time. It becomes possible to do.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  11 inner code decoder, 12 switch, 13a, 13b deinterleaver, 14 outer code decoder, 15a, 15b interleaver, 16 delay element, 17 error position detector, 21 memory, 22 switch, 51 exclusive OR operator, 52 different data detector, 53 state discriminator, 54 delay element.

Claims (12)

An inner code decoder that receives the demodulated data and performs convolutional decoding to output first decoded data;
A first data rearrangement circuit that regularly rearranges the order of the first decoded data and outputs first rearranged decoded data;
An error packet identification signal for performing block decoding based on the first rearranged decoded data and outputting second decoded data and indicating whether or not there is an error in a packet composed of the second decoded data An outer code decoder for generating
The second decoded data and the error packet identification signal are rearranged according to a rule reverse to that of the first data rearrangement circuit, and the second rearranged decoded data and the rearrangement error packet identification signal are output. A data relocation circuit;
A delay element for delaying the first decoded data and outputting the first delayed decoded data;
An error position detector that detects an error position from the first delayed decoded data, the second rearranged decoded data, and the rearranged error packet identification signal, and outputs error position estimated value data;
A third data rearrangement circuit that regularly rearranges the order of the error position estimation value data and outputs rearrangement error position estimation value data;
The first data rearrangement circuit regularly rearranges the order of the second rearrangement decoded data,
The outer code decoder is
Block decoding is performed on the rearranged decoded data obtained by rearranging the second rearranged decoded data by the first data rearrangement circuit based on the rearranged error position estimated value data. A decoding device characterized by the above. An inner code decoder that receives the demodulated data and performs convolutional decoding to output first decoded data;
A first data rearrangement circuit that regularly rearranges the order of the first decoded data and outputs first rearranged decoded data;
An error packet identification signal for performing block decoding based on the first rearranged decoded data and outputting second decoded data and indicating whether or not there is an error in a packet composed of the second decoded data An outer code decoder for generating
The second decoded data and the error packet identification signal are rearranged according to a rule reverse to that of the first data rearrangement circuit, and the second rearranged decoded data and the rearrangement error packet identification signal are output. A data relocation circuit;
A delay element for delaying the first decoded data and outputting the first delayed decoded data;
An error position detector that detects an error position from the first delayed decoded data, the second rearranged decoded data, and the rearranged error packet identification signal, and outputs error position estimated value data;
A storage element for storing and holding the demodulated data,
The inner code decoder performs convolutional decoding on the demodulated data input via the storage element according to the error position estimation value data, and generates re-decoded data;
The outer code decoder rearranges the data obtained by rearranging the re-decoded data by the first rearrangement circuit and the second rearrangement-decoded data by the first rearrangement circuit. A decoding device, wherein block decoding is performed on data obtained by selecting one of the data obtained by the above. The first rearrangement circuit selects one of the re-decoded data and the second rearranged-decoded data, and rearranges the selected data;
The decoding apparatus according to claim 2, wherein the outer code decoder performs block decoding on the data rearranged by the first rearrangement circuit. A storage element for storing and holding the demodulated data;
The inner code decoder performs convolutional decoding on the demodulated data input via the storage element according to the error position estimation value data, and generates re-decoded data;
The outer code decoder rearranges the data obtained by rearranging the re-decoded data by the first rearrangement circuit and the second rearrangement-decoded data by the first rearrangement circuit. The decoding apparatus according to claim 1, wherein block decoding is performed on data selected from any of the data obtained by the above. The first relocation circuit includes:
Select one of the re-decoded data and the second rearranged decoded data, and rearrange the selected data;
The decoding apparatus according to claim 4, wherein the outer code decoder performs block decoding on the data rearranged by the first rearrangement circuit.   6. The outer code decoder includes an error position information selection unit that calculates and selects a predetermined number of error position information based on the rearranged error position estimation value data. The decoding device described. The error position detector is
A different data detector that detects whether the first delayed decoded data and the second rearranged decoded data are different data and outputs a signal indicating a detection result;
A state discriminator that calculates an index indicating the probability that the current data is error data from the signal indicating the detection result from the different data detector and the rearranged error packet identification signal;
A delay element that delays the data rearranged by the second data rearrangement circuit input to the error position detector to synchronize with the signal of the state discriminator. 6. The decoding device according to any one of 6. The state discriminator indicates whether the current data belongs to when there is no error, a single error, or a continuous error, and in the case of the continuous error, it is further classified according to the number of consecutive times The decoding apparatus according to claim 7, wherein an index indicating which of a plurality of stages is output as the error position estimation value. The decoding apparatus according to any one of claims 1 to 8, wherein the outer code decoder performs Reed-Solomon decoding. 9. The outer code decoder performs Reed-Solomon decoding using error position information calculated based on the rearranged error position estimated value data. The decoding apparatus in any one of. The decoding apparatus according to any one of claims 1 to 8, wherein the inner code decoder includes: convolutional decoding based on a Viterbi algorithm. The inner code decoder is:
In the process of selecting the maximum likelihood path from the state transition probability calculated based on the likelihood information included in the input demodulated data, based on the error position estimate from the error position detector,
7. A predetermined value is added to, subtracted from, or multiplied by and divided from the calculated state transition probability so as to select data indicating a state transition direction different from the data indicating the current state transition direction. The decoding device described.

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