JP5482815B2 - Power MOSFET drive circuit and element value determination method thereof - Google Patents

Description

  The present invention relates to a drive circuit that constitutes a bridge circuit that drives an inductive load and that is driven by a voltage-driven power MOSFET to which a freewheel diode is connected, and a method for determining an element value thereof.

  The semiconductor switching element is turned on / off according to a control signal applied to the control terminal. At this time, since the semiconductor switching element has a parasitic element in its structure and its peripheral circuit, the semiconductor switching element cannot be kept off even in a period that should be originally turned off and may be turned on erroneously. This is called a self-turn-on phenomenon, which increases switching loss and switching noise, or in the worst case, degrades or breaks down a circuit. A technique for suppressing such self-turn-on is provided (see, for example, Patent Document 1).

  In the technique described in Patent Document 1, the gate-source voltage rise phenomenon due to capacitive coupling that occurs in the voltage application state between the drain and source of a voltage-driven transistor (Q10 in Patent Document 1) The rise of the gate-source voltage is suppressed by short-circuiting.

  When short-circuiting between the gate and source of this voltage-driven transistor, it is realized by turning on the transistor (Q20 in Patent Document 1) connected between the gate and source. Thereby, if the gate-source voltage of the transistor Q10 can be made lower than the threshold voltage of the transistor Q10, self-turn-on can be suppressed. In addition, Patent Document 2 is presented as a related technique of the present application.

JP 2002-290224 A JP 2003-188699 A

  However, if a parasitic inductance exists in the source terminal in a state where the drain and source of the transistor Q10 are short-circuited, a self-turn-on phenomenon may occur. In this case, when the recovery current irr flowing through the diode connected in reverse parallel to the transistor Q10 flows through the parasitic inductance Ls, an induced electromotive force of voltage v = Ls × di / dt (Ls is a parasitic inductance value) is generated in the parasitic inductance. Arise. When this voltage v exceeds the threshold voltage of the transistor Q10, a self turn-on phenomenon occurs.

  In particular, the technique described in Patent Document 1 cannot cope with a case where a power MOSFET whose recovery current changes sharply, such as an SJ (Super Junction) -MOSFET, is driven. When such an element is driven, since the current change di / dt corresponding to the time change is large, the voltage v generated in the parasitic inductance is increased, and the self-turn-on caused by the voltage v is increased. This is because a phenomenon occurs.

  The present invention has been made in view of the above circumstances, and the purpose of the present invention is to prevent self-turn-on caused by a voltage generated according to a time change of a current flowing through a parasitic inductance even when a power MOSFET is driven at high speed. It is an object of the present invention to provide a power MOSFET drive circuit capable of preventing the occurrence and a method for determining an element value thereof.

  According to a first aspect of the present invention, a voltage-driven first power MOSFET and a second power MOSFET are half-bridge connected between the first power supply line and the second power supply line, and inductive between the first power MOSFET and the second power MOSFET. A drive circuit for driving a drive target formed by connecting a load is intended. According to the first aspect of the present invention, the first energization switch circuit is configured to be able to turn on and off the power supply voltage using the potential of the low potential side reference terminal of the first power MOSFET as the reference potential, and supply the power supply voltage. A first on switch and a first off switch are connected in series between the terminal and the low potential side reference terminal.

The first charge injection / discharge circuit is connected between the first energization switch circuit and the control terminal of the first power MOSFET, and adjusts the speed at which charges are injected / discharged to / from the control terminal. The first impedance switching unit is connected between the control terminal of the first power MOSFET and the low-potential side reference terminal, and the first charge injection / discharge circuit for the impedance between the control terminal and the low-potential side reference terminal. The first impedance state ( which includes at least one of resistive and inductive states) higher than the first impedance state and the open state where the impedance is higher than that of the first impedance state are switched.

  On the other hand, the second energization switch circuit is configured to be capable of energizing on and releasing the power supply voltage with the potential of the low potential side reference terminal of the second power MOSFET as the reference potential, and the power supply voltage supply terminal, the low potential side reference terminal, The second on switch and the second off switch are connected in series between the two.

The second charge injection / discharge circuit is connected between the second energization switch circuit and the control terminal of the second power MOSFET, and adjusts the speed at which charges are injected / discharged to the control terminal. The second impedance switching unit is connected between the control terminal of the second power MOSFET and the low-potential side reference terminal, and a second charge injection / discharge circuit for the impedance between the control terminal and the low-potential side reference terminal. (the proviso second impedance state includes at least one of resistive and inductive) second impedance state of the predetermined higher impedance switched between high open state impedance than the second impedance.

The control means controls the switch states of the first and second energization switch circuits and the switching states of the first and second impedance switching units. The control means
(A) Turn on the kth on switch and turn off the kth off switch. (B) Turn off the kth on switch from on and then turn on the kth off switch. (C) Turn on the kth off switch from on and off at the same time. The switching control including (A) to (C) in which the k impedance switching unit is changed from the open state to the kth impedance state and the mth on switch is turned on (where k is 1 or 2, and m is the other).

  For this reason, the control means turns on the k-th power MOSFET in the section (A) and then turns on the k-th off switch after turning off the k-th on switch in the k-th energization switch circuit in the section (B). Then, the charge is discharged from the control terminal of the k-th power MOSFET through the k-th charge injection / discharge circuit. Thereafter, in the section (C), the charge is applied to the control terminal of the m-th power MOSFET by turning on the m-th on switch. When the k-th power switch is turned on, the k-th impedance switching unit is changed from the open state to the k-th impedance state at the same time, so that the rise of the gate-source voltage of the k-th power MOSFET is increased. It can be suppressed by a predetermined impedance. In this case, in particular, the gate-source voltage of the k-th power MOSFET can be suppressed below the threshold voltage. Even when the power MOSFET is driven at high speed, it is possible to prevent the occurrence of self-turn-on due to the voltage generated according to the time change of the current flowing through the parasitic inductance.

  As in the second aspect of the invention, in the section (B), after the k-th on switch is turned off, the k-th off switch is turned on, the k-th impedance switching unit is kept open, and the m-th off switch is turned on. In the section (C), the kth switch may be switched from the open state to the kth impedance state at the same time as the kth off switch is turned off.

  As in the third aspect of the present invention, in the section (B), after the k-th on switch is turned off, the k-th off switch is turned on and the k-th impedance switching unit is changed from the open state to the k-th impedance state. In the section of switching (C), the k-th off switch may be turned off from on. Then, a predetermined kth impedance state can be established between the gate and source of the kth power MOSFET.

  According to the fourth aspect of the present invention, the control means turns on the m-th ON switch, injects charges into the control terminal of the m-th power MOSFET through the m-th charge injection / discharge circuit, and the current of the m-th power MOSFET is previously set Before the predetermined time exceeding the settling current for the first time elapses, the kth off-switch is turned off and the kth impedance switching unit is controlled to be switched to the predetermined kth impedance state. The gate-source of the k-th power MOSFET can be set in a predetermined k-th impedance state in advance before the steep period begins, and the occurrence of self-turn-on can be prevented with high reliability.

  According to the element value determination method according to claim 5 or 6, the counter electromotive voltage generated in the parasitic inductance of the source of the k-th power MOSFET according to the recovery current generated in the parasitic diode of the k-th power MOSFET, and the k-th power MOSFET The generated voltage generated by the coupling of the parasitic capacitance is added, and the element value satisfying the condition that the added voltage is less than or substantially equal to the threshold voltage of the k-th power MOSFET is determined as the element value of the k-th impedance switching unit. doing. For this reason, the occurrence of self-turn-on can be prevented with high reliability. In addition, ringing can be suppressed. By determining an appropriate element value, switching loss can be suppressed and surge voltage can be suppressed.

  According to the seventh aspect of the invention, since the a-th energization switch circuit, the a-th charge injection / discharge circuit, the a-th impedance switching unit, and the b-th energization switch circuit are provided, substantially the same as the first aspect of the invention. Works. It should be noted that the power MOSFET of the present invention includes any semiconductor switching element as long as the recovery current changes abruptly.

FIG. 2 is an electrical configuration diagram of a driving circuit on a high side and a low side showing a first embodiment of the present invention. Circuit configuration diagram showing an aspect of the impedance switching unit (A) Electrical configuration diagram showing a specific example of a control circuit, (b) Electrical configuration diagram showing a specific example of a logic circuit Timing chart showing on / off period of each switch Table showing on / off status of switch in each section Timing chart showing the relationship between the ON / OFF state of each switch and the voltage / current waveform at each node Explanatory drawing showing the current change in section (4) Flow chart showing the flow of the element value determination method of the impedance switching unit The figure showing an example of the parameter value collected beforehand Equivalent circuit for determining the voltage generated in the parasitic inductance according to the recovery current Diagram showing the relationship between the recovery current flowing through parasitic inductance, resistance, and parasitic capacitance, the induced electromotive force generated in the parasitic inductance, and the voltage between the gate and source of the transistor Timing chart showing the relationship between current and voltage of each part before and after energizing the recovery current Flow chart showing the flow of how to obtain the voltage generated between the gate and source of the MOSFET according to the recovery current Equivalent circuit considering parasitic capacitance around MOSFET Timing chart showing relationship between recovery current and drain-source voltage response waveform FIG. 3B equivalent view showing the second embodiment of the present invention. Figure equivalent to FIG. 6 equivalent diagram FIG. 7 equivalent diagram showing a third embodiment of the present invention. 6 equivalent diagram Explanatory drawing showing the current change in the section (2) of FIG. Electrical configuration diagram of the drive circuit on the high side showing the fourth embodiment of the present invention Fig. 3 (b) equivalent 6 equivalent diagram FIG. 6 equivalent view showing the fifth embodiment of the present invention. The figure which shows an example of the switching speed adjustment circuit which shows 6th Example of this invention. FIG. 9 equivalent diagram showing a seventh embodiment of the present invention. Figure 13 equivalent Illustration of voltage domain definition 6 equivalent diagram Explanatory drawing showing the electric current change at the time of applying the element value which satisfy | filled the conditions which the addition voltage enters in voltage range VR2 Explanatory drawing showing the electric current change at the time of applying the element value which satisfy | filled the conditions in which addition voltage enters in voltage range VR1 FIG. 31 and FIG. 32 equivalent view showing a comparative example Evaluation circuit for verifying surge voltage characteristics Transient response waveform of drain-source voltage of power MOSFET (1) Transient response waveform of drain-source voltage of power MOSFET (Part 2) Transient response waveform of drain-source voltage of power MOSFET (Part 3) Transient response waveform of drain-source voltage of power MOSFET (Part 4) Characteristic diagram showing impedance dependence of switching loss and surge voltage

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. In this embodiment, an example applied to a half-bridge circuit is shown.

  A half-bridge circuit 1 shown in FIG. 1 is a basic circuit of a power conversion circuit, and converts a DC voltage into an AC voltage by operating switching elements of upper and lower arms in a complementary manner. The half-bridge circuit 1 includes two N-channel SJ (Super-Junction) -MOSFETs between a supply node (first power supply line) and a ground (second power supply line) of a DC power supply 2 (for example, 100 V). (Power MOSFET) 3H and 3L (corresponding to a first power MOSFET and a second power MOSFET) are connected in series. The power MOSFET drive circuits 6H and 6L can be applied to power conversion circuits (converters and inverters).

  For example, one end of a stator coil 4 of an AC motor is connected to the common node between these N-channel MOSFETs 3H and 3L as an inductive load. A parasitic diode 5H is built in between the drain and source of the high-side MOSFET 3H. A parasitic diode 5L is built in between the drain and source of the low-side MOSFET 3L. These parasitic diodes 5H and 5L operate as freewheeling diodes.

  In the drawing, a circuit for driving the MOSFET 3H on the high side (upper arm) side is shown as a drive circuit 6H, and a circuit for driving the MOSFET 3L on the low side (lower arm) side is shown as the drive circuit 6L, but the drive circuits 6H and 6L are shown. Since the circuit configurations are identical to each other, the electrical configuration of the high-side drive circuit 6H will be described below, and the electrical configuration of the low-side drive circuit 6L is denoted by “H” as a subscript to the components in the figure. An alternative “L” is attached and description thereof is omitted.

  The drive circuit 6H includes a drive voltage generation circuit (first energization switch circuit) 7H connected in series between the gate (control terminal) and the source of the MOSFET 3H, a switching speed adjustment circuit (first charge injection / release circuit) 8H, and an off hold circuit. (First impedance switching unit) 9H is provided. The drive voltage generating circuit 7H is configured by connecting a switch with control terminal (first on switch) S1H and a switch with control terminal (first off switch) S2H in series between the positive and negative terminals of the DC power supply 10H. It is possible to switch and output the power supply voltage of 10H and 0V, or to open the output. Here, the switches S1H and S2H are each composed of, for example, an NPN transistor.

  The switching speed control circuit 8H is configured by connecting in parallel a series connection circuit of a resistor RnH and a diode DnH, and a series connection circuit of a resistor RfH and a diode DfH. When the switch S2H is switched off after the switch S1H is switched on, the charge is injected into the gate of the MOSFET 3H through the resistor RnH and the diode DnH, so that the charge is accumulated in the gate input capacitance. The charge accumulation speed depends on the gate input capacitance of the MOSFET 3H and the resistance value of the resistor RnH. Further, when the switch S2H is turned on after the switch S1H is turned off, the accumulated charge of the gate input capacitance of the MOSFET 3H is extracted and released through the resistor RfH and the diode DfH. This discharge speed depends on the gate input capacitance of the MOSFET 3H and the resistance value of the resistor RfH.

  The off-holding circuit 9H is configured by connecting a predetermined impedance element ZH and a switch S3H with a control terminal in series between the gate and source of the MOSFET 3H. 2A to 2E show configuration examples of the off-holding circuit. The impedance element ZH of the off-holding circuit 9H is preferably an impedance having resistance or inductivity. If the resistance value or the inductance value is large, the effect of suppressing the rise of the gate-source voltage of the MOSFET 3H is increased. Therefore, a resistor Rgs may be applied as the impedance element ZH as shown in FIG. 2A, or it may be configured using the on-resistance of the MOSFET M1 as shown in FIG. good. When the configuration of FIG. 2B is applied, the functions of the configuration of FIG. 2A in which the resistor Rgs and the switch SW are connected in series can be integrated into one transistor. Further, as shown in FIG. 2C, an inductance Lgs may be used instead of the resistor Rgs. Further, as shown in FIG. 2 (d), the resistor Rgs and the inductance Lgs may be connected in series, or as shown in FIG. 2 (e), the inductance Lgs is connected in series with the MOSFET M1. May be. Such a drive circuit 6H is also configured as a drive circuit 6L on the low side.

  The control circuit (control means) 11 turns on and off each of the switches S1H, S2H, and S3H by giving on / off control signals Sg11, Sg12, and S1 to the control terminals of the switches S1H, S2H, and S3H, respectively. In addition, the control circuit 11 turns on and off the switches S1L, S2L, and S3L by giving on / off control signals Sg21, Sg22, and S2 to the control terminals of the switches S1L, S2L, and S3L, respectively.

  FIG. 3A shows the electrical configuration of the control circuit. The control circuit 11 includes a comparison circuit 12 and a logic circuit 13. The comparison circuit 12 compares the triangular wave signal with the output voltage command value (DC signal) and outputs PWM signals Ssd1 and Ssd2. The logic circuit 13 receives the PWM signals Ssd1 and Ssd2 from the comparison circuit 12 and outputs control signals Sg11, Sg12, S1, Sg21, Sg22, and S2.

  FIG. 3B shows the hardware configuration of the logic circuit. The logic circuit 13 includes a NOR gate 14. The logic circuit 13 is connected so as to output the PWM signal Ssd1 as on / off control signals Sg11 and S2 and to output the PWM signal Ssd2 as on / off control signals Sg21 and S1. The NOR gate 14 receives the PWM signals Ssd1 and Ssd2 and outputs the on / off control signals Sg12 and Sg22.

  FIG. 4 shows signal waveform examples of the PWM signals Ssd1 and Ssd2 output from the comparison circuit 12. The signals Ssd1 and Ssd2 repeat the states of the sections (1) to (4) shown below at a predetermined frequency and duty ratio.

(1) Ssd1 is “H” (on), Ssd2 is “L” (off)
(2) Ssd1 is “L” (off), Ssd2 is “L” (off)
(3) Ssd1 is “L” (off), Ssd2 is “H” (on)
(4) Ssd1 is “L” (off), Ssd2 is “L” (off)
By repeating the states of the sections (1) to (4), the logic circuit 13 outputs the on / off control signals Sg11, Sg12, S1, Sg21, Sg22, and S2 having a predetermined period. FIG. 5 shows the on / off states of the high-side and low-side power MOSFETs that change in response to the on / off control signal, and FIG. 6 shows this state in a timing chart. In each section (1) to (4), the output of the logic circuit 13 repeats the following state.

(1) Sg11 and S2 are “H” (on), others are “L” (off)
(2) Sg12 and Sg22 are “H” (on), others are “L” (off)
(3) S1 and Sg21 are “H” (on), and others are “L” (off).
(4) Sg12 and Sg22 are “H” (on), others are “L” (off)
If such switching is repeated, the switches S1H and S2H are turned on and off almost simultaneously between the sections (1) and (2), and between the sections (3) and (4). Although S1L and S2L are turned on and off almost simultaneously, the circuit may be configured to provide a predetermined dead time in order to prevent short circuit of the DC power supplies 10H and 10L.

  Hereinafter, the basic operation of the circuit when the on / off control signals Sg11, Sg12, S1, Sg21, Sg22, and S2 are input to the switches S1H to S3H and S1L to S3L, respectively, in each of the sections (1) to (4) are shown in FIG. This will be described with reference to FIGS. However, the load current flowing through the stator coil 4 is in the direction shown in FIG.

<(1) Basic operation of section>
In section (1), on the high side, the switch S1H is turned on and the other switches S2H and S3H are turned off. Therefore, the gate of the MOSFET 3H is supplied with electric charge from the DC power supply 10H, and the gate input capacitance of the MOSFET 3H Charged. In this section (1), as shown in FIG. 6 (i), the gate-source voltage Vgs1 of the MOSFET 3H exceeds the threshold voltage Vt between the gate and source of the MOSFET 3H, so that the MOSFET 3H is turned on.

  Meanwhile, on the other low side, the switch S3L is turned on and the switches S1L and S2L are turned off, so that the gate-source of the MOSFET 3L has a predetermined impedance (for example, several tens of Ω) by the off holding circuit 9H. Therefore, as shown in FIG. 6 (j), the gate-source voltage Vgs2 of the MOSFET 3L becomes substantially 0, and the MOSFET 3L maintains the off state.

<(2) Basic operation of section>
In the section (2), on the high side, the switch S2H is turned on after the switch S1H is turned off, so that the accumulated charge at the gate of the MOSFET 3H is discharged through the resistor RfH of the switching speed adjustment circuit 8H. Therefore, as shown in FIG. 6 (i), the MOSFET 3H is turned off when the gate-source voltage Vgs1 decreases and falls below the threshold voltage Vt.

  Meanwhile, on the low side, the switch S3L is turned off and the switch S2L is turned on, so that the gate-source between the MOSFET 3L is fixed to the impedance of the switching speed adjusting circuit 8H. Therefore, as shown in FIG. 6 (j), the gate-source voltage Vgs2 of the MOSFET 3L is maintained at substantially 0 V, and the MOSFET 3L maintains the off state. When MOSFETs 3H and 3L are both turned off, the load current flowing through stator coil 4 circulates in the forward direction of diode 5H.

<(3) Basic operation of section>
(3) In the section, on the high side, the switch S2H is turned off and the switch S3H is turned on, so that the impedance element ZH of the off holding circuit 9H is connected between the gate and source of the MOSFET 3H, and the off holding circuit 9H holds a predetermined impedance between the gate and the source of the MOSFET 3H by the impedance element ZH. As a result, as shown in FIG. 6I, the MOSFET 3H is held in the off state.

  During this time, on the low side, the switch S1L is turned on after the switch S2L is turned off, so that charge is accumulated in the gate input capacitance of the MOSFET 3L through the resistor RnL of the switching speed adjustment circuit 8L. As shown in FIG. 6J, the MOSFET 3L is turned on when the gate-source voltage Vgs2 rises and exceeds the threshold voltage Vt of the element.

<(4) Basic operation of section>
(4) In the section, since the switch S3H is turned off and the switch S2H is turned on on the high side, the gate and the source of the MOSFET 3H are connected to the impedance of the switching speed adjusting circuit 8H. Meanwhile, on the low side, the switch S1L is turned on and then the switch S2L is turned off, so that the accumulated charge at the gate of the MOSFET 3L is discharged through the resistor RfL of the switching speed adjustment circuit 8L. The gate of the MOSFET 3L is connected to the impedance of the switching speed adjustment circuit 8L.

  Such basic operations in the sections (1) to (4) are repeated. While repeating such a periodic basic operation, the load current circulates in the forward direction of the diode 5H in the section (2), and when the MOSFET 3L is turned on in the section (3), as shown in FIG. Rises sharply. This is because when the MOSFET 3L is turned on, a reverse recovery current (recovery current) due to the carrier accumulation effect flows to the diode 5H, and the currents I1 and I2 change rapidly.

  In particular, the currents I1 and I2 change rapidly when the reverse recovery current decays. The increase / decrease degree is large in the increasing section of current I1 shown in FIG. 6 (k) (second half of recovery: decreasing section of current I2 shown in FIG. 6 (l)).

  A parasitic inductance LH exists at the source of the MOSFET 3H, and a parasitic inductance LL exists at the source of the MOSFET 3L. For this reason, the induced electromotive forces -Ldi / dt corresponding to the time fluctuations of the currents I1 and I2 are generated in the parasitic inductances LH and LL, respectively.

  In the latter half of the recovery, when an induced electromotive force is generated in the parasitic inductance LH, a voltage is generated in the parasitic inductance LH from the source of the MOSFET 3H to the stator coil 4 side node. Therefore, the gate-source voltage Vgs1 of the MOSFET 3H increases.

  In the section (3), since the MOSFET 3H (high-side element) is in the off-holding period, the gate-source voltage Vgs1 of the MOSFET 3H needs to be suppressed to be less than the threshold voltage Vt of the MOSFET 3H.

  Therefore, in this embodiment, the off-hold circuit 9H is connected between the gate and source of the MOSFET 3H, and the switch S3H is always turned on before entering the second half of the recovery period in which the induced electromotive force of the parasitic inductance LH particularly increases. The impedance element ZH is connected between the gate and source of the MOSFET 3H by the off hold circuit 9H.

  Therefore, even if the parasitic inductance LH generates an induced electromotive force, the impedance element ZH of the off-holding circuit 9H acts, so that a charge corresponding to the induced electromotive voltage of the parasitic inductance LH is applied to the gate of the MOSFET 3H through the impedance element ZH. As a result, an increase in the gate-source voltage Vgs1 of the MOSFET 3H can be suppressed. Thereby, even when the SJ-MOSFETs 3H and 3L are driven at high speed, the self-turn-on phenomenon can be prevented.

  FIG. 7 schematically shows a current change in the section (4) of FIG. In the section (4) of FIG. 6, on the low side, the switch S2L is turned on after the switch S1L is turned off, so that the gate-source voltage Vgs2 of the MOSFET 3L decreases as shown in FIG. 6 (j). Meanwhile, on the high side, as shown in FIG. 6 (k), the current decrease is increased by flowing in the forward direction of the parasitic diode 5H.

In this case, the device may malfunction due to an unintended voltage increase. This is because of reduced current I2 by MOSFET3L is turned off, because the induced electromotive force _{V LL} is generated in the parasitic inductance LL in accordance with the current gradient. In order to suppress malfunction due to the induced electromotive force V _LL , the current gradient of the current I2 may be reduced, and the resistance value of the resistor RfL for adjusting the turn-off speed may be adjusted. Moreover, it can operate | move normally by repeating the operation | movement of these (1)-(4) area | regions of FIG.

  Therefore, by controlling as described above, the gate-sources of the MOSFETs 3H and 3L can be adjusted to a predetermined impedance at the time of turn-off, the switching speed can be reduced, and the rise of the gate-source voltage can be suppressed.

  In particular, in order to increase the reliability of preventing the self turn-on phenomenon, it is desirable to determine the circuit element values of the drive circuits 6H and 6L by a predetermined method. Hereinafter, a method for determining the element value will be described.

<About the impedance determination method of the off-holding circuits 9H and 9L>
In order to prevent the self-turn-on phenomenon, it is particularly preferable to position the impedance values of the impedance elements ZH and ZL of the off-holding circuits 9H and 9L as important elements. Therefore, it is assumed that the impedances of the impedance elements ZH and ZL are the same from the viewpoint of circuit symmetry, and a method for determining the impedance value when the off-holding circuits 9H and 9L are respectively set in series circuits of a resistor Rgs and an inductance Lgs. explain.

  The main causes of the rise in the gate-source voltage Vgs of the MOSFETs 3H and 3L are the induced electromotive force generated in the parasitic inductances LH and LL according to the recovery current and the coupling voltage of the parasitic capacitance. Therefore, when the voltage increase due to the cause of the increase is calculated separately for each case, and the impedance of the impedance elements ZH and ZL satisfying the condition that the added voltage obtained by superimposing these effects falls below a predetermined threshold voltage Vt is determined. good.

  FIG. 8 is a flowchart showing the flow of the impedance determination method for the impedance elements ZH and ZL. As shown in FIG. 8, parameter values necessary for determining the impedance of the circuit are collected (S1). These parameters are determined as design values by simulation, experiment, etc. based on the semiconductor MOSFET structures of the power MOSFETs 3H and 3L, parasitic elements, and circuit connection forms, and the parameters listed in FIG.

  For example, as shown in FIG. 9, the parameters include the values Ls of the parasitic inductances LL and LH, the recovery current gradient di / dt, the settling time tf from the second half of the recovery to the end, the parasitic capacitance value Cgs between the gate and the source, and the gate drain A parasitic capacitance value Cgd between them and a drain-source voltage Vds between them.

  As shown in FIG. 8, after collecting each parameter, the impedances of the off-holding circuits 9H and 9L are temporarily set (S2). As described above, the induced electromotive force of the parasitic inductances LH and LL is generated according to the recovery current, but the gate-source voltage Vgsa is calculated using the impedance temporarily set in step S2 (S3).

<Voltage Vgsa generated in parasitic inductance in response to recovery current>
FIG. 10 shows an equivalent circuit for obtaining the voltage Vgsa generated in the parasitic inductances LH and LL according to the recovery current.

  As shown in FIG. 10, a parasitic capacitance Cgs exists between the gate and source of the MOSFET 3H. Since the gate-source voltage Vgs of the MOSFET 3H is equal to the voltage applied to the parasitic capacitance Cgs, when an induced electromotive force −Ls × di / dt is generated in the parasitic inductance Ls as shown in the equivalent circuit of FIG. The capacitor Cgs is charged via the inductance Lgs and the resistor Rgs according to the induced electromotive force. As a result, the gate-source voltage Vgs of the MOSFET 3H increases.

  FIG. 11 shows the relationship between the recovery current i flowing through the parasitic inductance Ls, the resistance Rgs, and the parasitic capacitance Cgs, the induced electromotive force −Ls × di / dt generated in the parasitic inductance Ls, and the gate-source voltage Vgs of the transistor 3H. ing. FIG. 12 shows changes in current and voltage with time before and after energization of the recovery current.

  In the aforementioned section (2), the load current flows back to the diode 5H, and the current i flows in the reverse direction of the diode 5H. Thereafter, in the section (3), when the MOSFET 3L is turned on, a reverse recovery current corresponding to the carrier accumulation effect is supplied to the diode 5H, and the current i rapidly increases (section (A) in (3) of FIG. 12). In the first half of the recovery shown in (A) of (3), an induced electromotive force −Ls × di / dt corresponding to the current rising gradient is generated for the parasitic inductance Ls. In the first half section of recovery, compared to the second half section of recovery, the current rising gradient is low, and the induced electromotive force generated thereby is also small.

  Thereafter, in the second half of the recovery shown in (B) of (3), an induced electromotive force corresponding to the current descending gradient is generated and the current descending gradient is large. Therefore, the induced electromotive force generated according to the current descending gradient also increases. Here, if it is assumed that the recovery current i decreases linearly, it can be assumed that the step voltage Vs is generated in the parasitic inductance Ls for a predetermined settling time tf in the second half of the recovery period.

  Since the gate-source voltage Vgsa of the MOSFET 3H rises according to the step voltage Vs generated in the parasitic inductance Ls, each element value is determined so as to make the maximum value of the voltage Vgsa in the second half of the recovery as low as possible.

  FIG. 13 is a flowchart showing how to obtain the voltage Vgsa. When the step response formula of the RLC series circuit is applied, a second-order transfer function is obtained, which is expressed by the following Laplace transform formula (5).

ここで、ωｎは不減衰自然角周波数（固有周波数）、ζは減衰率（制動比）を示している。

Here, ωn represents an unattenuated natural angular frequency (natural frequency), and ζ represents an attenuation rate (braking ratio).

  When this equation (5) is subjected to inverse Laplace transform and divided into the following cases: ζ = 1 (equation (6)), ζ> 1 (equation (7)), 0 <ζ <1 (equation (8)).

と導出される。

Is derived.

As shown in FIG. 13, cases are classified according to the value of ζ, and a predetermined time tf is substituted into each equation (T1 to T6). Since the voltage Vgsa in the equation (8) has a value that oscillates with time, the time tm = π / ωn (√ (1-ζ ² )) at which the voltage Vgsa becomes the maximum value is a predetermined settling time tf. If it is within (step T5: NO), tm = π / ωn (√ (1-ζ ² )) is substituted into equation (8) to obtain the voltage Vgsa. Then, the maximum voltage Vgsa can be obtained in step S3 according to the parameter values collected in step S1 of FIG.

After obtaining the voltage Vgsa, the voltage Vgsb generated by coupling of the parasitic capacitance is obtained (step S4 in FIG. 8).
<How to obtain voltage Vgsb caused by parasitic capacitance coupling>
FIG. 14 shows an equivalent circuit in consideration of the parasitic capacitance around the MOSFET, and FIG. 15 shows the relationship between the response waveform of the recovery current and the drain-source voltage in a timing chart. After the MOSFET 3H is turned off, the drain-source voltage Vds of the MOSFET 3H increases. The maximum voltage Vgsb of the gate-source voltage Vgs at this time can be obtained by the following equation (9).

これは、ゲートドレイン間寄生容量Ｃｇｄ、ゲートソース間容量Ｃｇｓの分圧電圧となるためである。

This is because the gate-drain parasitic capacitance Cgd and the gate-source capacitance Cgs are divided voltages.

  Then, in step S5 of FIG. 8, an added voltage Vgs = voltage Vgsa + voltage Vgsb obtained by superimposing these effects is obtained, and the values of the resistance Rgs and the inductance Lgs satisfying the condition that the total value Vgs is lower than the threshold voltage Vt are determined. If the condition is not satisfied (step S5: NO), the process returns to step S2, and repeats from the point where the impedances of the off-holding circuits 9H and 9L are temporarily set. Desirably, the values of the resistance Rgs and the inductance Lgs are determined in consideration of a margin in the threshold voltage Vt. Verification may be made by substituting the values of the resistance Rgs and the inductance Lgs thus obtained.

  Therefore, since the element values of the off holding circuits 9H and 9L are determined according to the added voltage of the voltage Vgsa + the voltage Vgsb, an appropriate element value can be determined. Note that the same element value determination method can be applied to these contents in consideration of circuit symmetry in both the high-side MOSFET 3H and the low-side MOSFET 3L.

As described above, according to the first embodiment,
(1) In the section
On the high side, the switch S1H is turned on with the switch S2H turned off, and the switch S3H is turned off to turn off the off-holding circuit 9H, so that the DC power supply 10H is supplied from the drive voltage generation circuit 7H to the gate of the MOSFET 3H. Supply between sources and turn on
On the low side, the switch S1L is turned off, the switch S2L is turned off, and the switch S3L is turned on to set the off holding circuit 9L to a predetermined impedance, thereby fixing the gate-source of the MOSFET 3L to a predetermined impedance.

Next, in (2) section,
On the high side, the switch S1H is turned off and then turned on, the switch S2H is turned on, the switch S3H is held off, the off holding circuit 9H is held open, and the output voltage of the drive voltage generating circuit 7H is supplied to the source of the MOSFET 3H. By controlling to match the side voltage (the voltage at the low potential side reference terminal), the charge is discharged from the gate input capacitance of the MOSFET 3H through the switching speed adjustment circuit 8H,
On the low side, the switch S2L is turned on from off while holding the switch S1L off, and the switch S3L is turned off from on and the off hold circuit 9L is opened, so that the output voltage of the drive voltage generation circuit 7L is increased. Control is performed so as to match the source side voltage (voltage of the low potential side reference terminal) of the MOSFET 3L.

Next, in (3) section,
On the high side, the switch S2H is turned off from on while holding the switch S1H off, and at the same time the switch S3H is turned on from off to switch the off holding circuit 9H from the open state to a predetermined impedance, thereby connecting between the gate and source of the MOSFET 3H. Fixed to a predetermined impedance,
On the low side, after the switch S2L is turned off, the switch S1L is turned on, the switch S3L is kept off, and the off holding circuit 9L is held in an open state, whereby the output voltage of the drive voltage generating circuit 7L Is applied between the gate and the source of the MOSFET 3L.

Next, in (4) section,
On the high side, the switch S2H is turned on from off while holding the switch S1H off, and the switch S3H is turned off from on to open the off holding circuit 9H, and the output voltage of the drive voltage generating circuit 7H is set to the MOSFET 3H. Control to match the source side voltage (voltage of the low potential side reference terminal)
On the low side, the switch S1L is turned off and then turned on, the switch S2L is turned on, the switch S3L is held off, and the off holding circuit 9L is held open, so that the output voltage of the drive voltage generating circuit 7L is supplied to the MOSFET 3L. The voltage is controlled to the source side voltage (voltage at the low potential side reference terminal), and the charge is discharged from the gate input capacitance of the MOSFET 3L through the switching speed adjustment circuit 8L.

  The control circuit 11 drives and controls the switches by the drive circuits 6H and 6L, so that the switches S2H and S2L are turned on in the section (2) and the others are turned off, and the switches S1L and S3H are turned on in the section (3). Turn off the others. Then, over the period (2) to (3), the gate-source between the high-side MOSFETs can be switched to a predetermined impedance, and even if the second half of recovery is reached, the gate-source voltage Vgs1 of the high-side MOSFET is It can be suppressed below the threshold voltage Vt.

  In particular, before the start of the section (3), before a predetermined time when the current I2 exceeds the predetermined settling current for the first time, or before the second half of the recovery, the impedance between the gate and the source of the MOSFET 3H on the high side is set. It is fixed to.

  As a result, the gate-source voltage Vgs of the high-side MOSFET 3H and the low-side MOSFET 3L can be suppressed to less than the threshold voltage Vt. Therefore, even when the power MOSFET is driven at high speed, the occurrence of self-turn-on can be prevented.

Further, the induced electromotive force Vgsa generated in the parasitic inductance Ls due to the flow of the recovery current and the voltage Vgsb generated by the coupling of the parasitic capacitance are added to satisfy that the added voltage is less than the threshold voltage of the MOSFETs 3H and 3L. Since the element value is determined as the element value of the impedance element ZH of the off holding circuits 9H and 9L, the element values of the off holding circuits 9H and 9L can be appropriately determined according to the parasitic inductance Ls, the parasitic capacitance, and the like.
(Second embodiment)
FIGS. 16 to 18 show a second embodiment of the present invention. The difference from the above-described embodiment is that the switching timing of the switch of the off-holding circuit is changed. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below.

  FIG. 16 shows a hardware configuration of a logic circuit 15 that replaces the logic circuit 13 of FIG. The logic circuit 15 is configured by combining the NOR gate 16 and the NOT gates 17 and 18 in the illustrated form, inputs the PWM signals Ssd1 and Ssd2 of the comparison circuit 12, and outputs the control signals Sg11, Sg12, S1, Sg21, Sg22 and S2. To do.

  The logic circuit 15 outputs the PWM signal Ssd1 as the on / off control signal Sg11, and outputs the PWM signal Ssd2 as the on / off control signal Sg21. The NOR gate 16 receives these PWM signals Ssd1 and Ssd2 and outputs on / off control signals Sg12 and Sg22. The NOT gate 17 receives the PWM signal Ssd1 and outputs an on / off control signal S1. The NOT gate 18 receives the PWM signal Ssd2 and outputs an on / off control signal S2.

  When the logic circuit 15 is formed as shown in FIG. 16, the on / off state of each switch is switched as shown in FIG. In the present embodiment, the switches S2L and S3L indicated by reference numeral Y1 in the section (2) in FIG. 17 are both turned on. In the present embodiment, the switches S2H and S3H indicated by the symbol Y2 in the section (4) in FIG. 17 are both turned on. These switches denoted by Y1 and Y2 may be on or off. Therefore, both may be on or both may be off. In these cases, the logic circuit 15 may be appropriately changed.

  FIG. 18 shows a timing chart. In section (2) shown in FIG. 18, both the on / off control signal Sg12 of the switch S2H and the on / off control signal S1 of the switch S3H are output as the on control signal. Therefore, in the section (2) in FIG. 18, the off hold circuit 9H is set to a predetermined impedance, and the output voltage of the drive voltage generation circuit 7H is controlled to the voltage of the source side reference terminal of the MOSFET 3H.

  In this case, the on / off control signal can be output at the timing shown in FIGS. 18 (c) to 18 (h). In the section (2), the impedance between the gate and the source of the MOSFET 3H can be fixed to a low impedance by turning on the switches S2H and S3H. In the section (3), the switch S2H is turned off and the switch S3H is turned on, so that the impedance between the gate and the source of the MOSFET 3H can be fixed to a high impedance compared to the section (2). This is because the impedance between the gate and source of the MOSFET 3H is the combined impedance of the resistor RfH and the impedance element ZH in the section (2), but only the impedance of the impedance element ZH in the section (3). Further, when the resistance value of the resistor RhH is set lower than the impedance of the impedance element ZH, the combined impedance is also lowered.

  In this case, even if the gate-source voltage Vgs1 increases in the second half of the recovery in the section (3), the threshold voltage Vt does not become higher than the threshold voltage Vt, and the gate-source voltage Vgs1 of the MOSFET 3H is changed to the threshold voltage Vt of the MOSFET 3H as in the above embodiment. It can be suppressed to less than.

(Third embodiment)
19 to 21 show a third embodiment of the present invention. The difference from the above-described embodiment is that the load current is applied in the opposite direction to the above-described embodiment. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below.

  As shown in FIG. 19, a state is considered in which the load current of the stator coil 4 is energized in the right direction in the figure. In addition, the definitions of the source current I1 of the high-side MOSFET 3H and the drain current I2 of the MOSFET 3L are defined in the opposite direction to the above-described embodiment.

  Then, as shown in the timing chart of FIG. 20, the gate-source voltages Vgs1 and Vgs2 of the MOSFET 3H and MOSFET 3L change. In accordance with this, the source current I1 of the MOSFET 3H and the drain current I2 of the MOSFET 3L change.

  Since the voltage and current changes at this time only cause a time lag from the first embodiment, the description thereof will be omitted. However, in the same manner as the previous embodiment, in the section (1) in FIG. A recovery current is generated, and the gate-source voltage Vgs2 of the MOSFET 3L increases in the second half of the recovery. However, since the switch S2L is turned on in advance in the section (4) and then the switch S3L is turned on in the section (1), the gate-source between the MOSFETs 3L can be controlled to a predetermined impedance. Vgs2 can be suppressed, and the gate-source voltage Vgs2 of the MOSFET 3L can be suppressed below the threshold voltage Vt.

  FIG. 21 schematically shows a current change in the section (2) of FIG. In section (2) of FIG. 20, since the switch S2H is turned on after the switch S1H is turned off on the high side, the gate-source voltage Vgs1 of the MOSFET 3H decreases as shown in FIG. 20 (i). Meanwhile, on the low side, as shown in FIG. 20 (l), the current corresponding to the current decrease is increased by flowing in the forward direction of the parasitic diode 5L.

In this case, the device may malfunction due to an unintended voltage increase. This is because the current I1 decreases when the MOSFET 3H is turned off, and an induced electromotive force V _LH corresponding to the current gradient is generated in the parasitic inductance LH. In order to suppress the malfunction due to the induced electromotive force V _LH , the current gradient of the current I1 may be reduced, and the resistance value of the resistor RfH for adjusting the turn-off speed may be adjusted. A normal operation can be continued by repeating the operations in the sections (1) to (4) in FIG.

  In the present embodiment, when the load current is considered in the opposite direction to the previous embodiment, the gate-source voltage Vgs2 of the MOSFET 3L generated according to the recovery current can be suppressed to be lower than the threshold voltage Vt of the MOSFET 3L.

(Fourth embodiment)
22 to 24 show a fourth embodiment of the present invention. The difference from the above-described embodiment is that the switches S2H and S2L are turned on in the section in which the switches S2H and S2L are on in the above-described embodiment. Instead, the switches S3H and S3L are turned on to suppress the gate-source voltages Vgs1 and Vgs2 of the MOSFETs 3H and 3L below the threshold voltage Vt. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below. In the present embodiment, the description will be made assuming that the load current is in the same direction as the first or second example.

  FIG. 22 shows an example of the drive circuit on the high side. This drive circuit includes a switching speed adjustment circuit using a switch SWH and a resistor Rg instead of the switching speed adjustment circuit 8H, and is connected in series between the DC power supply 2 and the gate of the MOSFET 3H. Although not shown in FIG. 22, a switching speed adjustment circuit (not shown) using a switch SWL and a resistor Rg is configured on the low side instead of the switching speed adjustment circuit 8L. It is connected in series with the gate of the MOSFET 3L.

  FIG. 23 shows a hardware configuration of a logic circuit 19 that replaces the logic circuit 13. This logic circuit 19 is configured by combining NOT gates 20 and 21 in the illustrated form, receives PWM signals Ssd1 and Ssd2 of the comparison circuit 12, and outputs control signals Sg11, S1, Sg21 and S2.

  The logic circuit 19 outputs the PWM signal Ssd1 as the on / off control signal Sg11, and outputs the PWM signal Ssd2 as the on / off control signal Sg21. The NOT gate 20 receives the PWM signal Ssd1 and outputs the on / off control signal S1. Further, the NOT gate 21 receives the PWM signal Ssd2 and outputs the on / off control signal S2.

  When the logic circuit 19 is configured as shown in FIG. 23, the on / off states of the switches are switched as shown in the timing chart of FIG. Then, before the switch SWL is turned on in the section (3) of FIG. 24, the gate S of the MOSFET 3H can be maintained at a predetermined impedance by turning on the switch S3H in advance in the section (2) of FIG. Therefore, in the section (3) of FIG. 24, even if a voltage is applied between the low-side DC power supply 2 between the gate and source of the MOSFET 3H and the MOSFET 3H is turned on, an increase in the gate-source voltage Vgs1 of the MOSFET 3L is suppressed. Thus, the gate-source voltage Vgs1 of the MOSFET 3L can be suppressed to be lower than the threshold voltage Vt. This embodiment also has the same operational effects as the previous embodiment. Moreover, the circuit can be simplified.

(5th Example)
FIG. 25 shows a fifth embodiment of the present invention. The difference from the above-described embodiment is that the switches S2H and S2L in the section where the switches S2H and S2L of the above-described embodiment are turned on are replaced with the switches S3H and S3L are on. In this embodiment, the load current is in the same direction as that of the third embodiment, but the self-turn-on phenomenon can be prevented by suppressing the gate-source voltage Vgs2 of the MOSFET 3L to less than the threshold voltage Vt.

(Sixth embodiment)
26 (a) and 26 (b) show a sixth embodiment of the present invention. Instead of the switching speed adjustment circuits 8H and 8L in FIG. 1, a switching speed adjustment circuit shown in FIG. 26A or 26B may be applied.

  In the case of the circuit configuration shown in FIG. 26A, charges can be injected into the gate of the MOSFET 3H through the resistor RnH when turned on, and the gate charge can be discharged through the resistors RfH and RnH when turned off. Therefore, the circuit configuration is suitable when the switching speed at turn-on is higher than that at turn-off.

  In the circuit configuration shown in FIG. 26B, charges can be injected into the gate of the MOSFET 3H through the resistors RnH and RfH when turned on, and the gate charge can be discharged through the resistor RfH when turned off. Therefore, the circuit configuration is suitable when the switching speed at turn-off is higher than at turn-on.

(Seventh embodiment)
27 to 39 show a seventh embodiment of the present invention. The difference from the previous embodiment is that the method for determining the element value of the circuit is changed. Although there is no change in the flow of the main calculation method shown in FIG. 8, the difference is that the calculation method of the voltage Vgsa and the voltage Vgsb in step S3 during this process is changed. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted.

  FIG. 27 shows the equivalent of FIG. 9 described in the above embodiment, and the time tsr is applied in FIG. 27 instead of the predetermined time (settling time) tf of FIG. This time tsr indicates the time from the timing approaching the second half of the recovery to the channel current injection (increase) start timing due to the inversion layer formation of the power MOSFET.

  As described in the above embodiment, the parameter values are collected in step S1 of FIG. After that, after temporarily setting the impedance of the constant impedance holding circuit in step S2, the voltage Vgsa generated in the parasitic inductance in accordance with the recovery current is calculated in step S3.

  When the second-order transfer function based on the step response equation of the RLC series circuit is applied, Vgsa is ζ = 1 (Equation (6)), ζ> 1 (Equation (7)), 0 <ζ <1 (Equation (8) )).

As shown in FIG. 28, cases are classified according to the value of ζ, and the value of the time tsr is substituted into the equations (6) to (8). As described in the above embodiment, the voltage Vgsa in the equation (8) is a voltage that oscillates with time. The time tm at which the voltage Vgsa becomes the maximum value is represented by π / ωn (√ (1-ζ ² )). If this time tm is within the above-described time tsr (step U5: NO), (8 ) Is substituted for tm = π / ωn (√ (1-ζ ² )) to obtain the voltage Vgsa. Then, the maximum voltage Vgsa can be obtained in step S3 according to the parameter values collected in step S1 of FIG.

  Next, in step S4 of FIG. 8, the voltage Vgsb generated by coupling of the parasitic capacitance is calculated. When the equivalent circuit shown in FIG. 14 is applied and the parasitic capacitance between the gate and drain of the MOSFET 3H is Cgd and the parasitic capacitance between the gate and source is Cgs, and the step response of this divided voltage is obtained, the voltage Vgs is expressed by the following equation (10). Asking.

この（１０）式の電圧Ｖｇｓｂは時間ｔの経過に応じて減少する時間依存関数であるが、ｔが０となるタイミングで最大となる。このため、この最大値を電圧Ｖｇｓｂとして求めると、このときの電圧Ｖｇｓｂは前述実施形態で説明した（９）式の値と同一値となる。そして、図８のステップＳ５において、図２８のフローチャートを用いて得られた電圧Ｖｇｓａと前述の最大電圧Ｖｇｓｂの影響を重ね合わせた加算電圧Ｖｇｓとして求めると良い。

The voltage Vgsb in the equation (10) is a time-dependent function that decreases with the lapse of time t, and becomes the maximum when t becomes 0. For this reason, when the maximum value is obtained as the voltage Vgsb, the voltage Vgsb at this time is the same value as the value of the equation (9) described in the above embodiment. Then, in step S5 of FIG. 8, the added voltage Vgs obtained by superimposing the influence of the voltage Vgsa obtained using the flowchart of FIG. 28 and the aforementioned maximum voltage Vgsb may be obtained.

  On the other hand, in order to accurately obtain the voltage Vgsb depending on the time t, the voltage Vgsb can be obtained as in the following equation (11) by substituting the time tsr in the latter half of the recovery into the equation (10).

そして、図８のステップＳ５において、この時間ｔに依存した電圧Ｖｇｓｂと、図２８に示すフローチャートの流れに応じて算出した電圧Ｖｇｓａとを重ね合わせた加算電圧Ｖｇｓを求める。

Then, in step S5 of FIG. 8, an added voltage Vgs obtained by superimposing the voltage Vgsb depending on the time t and the voltage Vgsa calculated according to the flow of the flowchart shown in FIG.

  In this embodiment, instead of the determination process in step S5 of FIG. 8, the voltage region VR1 (Vtd ≦ Vt ≦ Vm) where the added voltage Vgs is substantially equal to the threshold voltage Vt, and the voltage region VR2 (less than the voltage Vtd) It is determined whether or not Vgs <Vtd). The definitions of these voltage regions VR1 and VR2 are shown in FIG. The voltage region VR2 is a voltage region of the gate-source voltage Vgs that can be almost regarded as the drain current Id≈0 of the power MOSFET. FIG. 29 shows the static characteristics of the drain current Id-gate-source voltage Vgs in the saturation region of a general MOSFET. In the circuit configuration of this embodiment, a current different from the drain current characteristics flows. There is also.

  When the gate-source voltage Vgs is in the voltage region VR2, a drain current hardly flows because a PN junction reverse bias is generated between the drain and source of the power MOSFET. According to the characteristics shown in FIG. 29, the drain current Id changes exponentially with respect to the gate-source voltage Vgs in the subthreshold region below the threshold voltage Vt.

  In the present embodiment, it is determined whether or not the added voltage Vgs is within a voltage region (VR2 + VR1) having an upper limit of a voltage value Vm obtained by adding a predetermined margin voltage to the threshold voltage Vt, and an element that satisfies this determination condition Determine the value.

  Here, the voltage value Vm obtained by adding the margin voltage to the threshold voltage Vt varies depending on device characteristics and operating conditions (for example, load current), and therefore may be adjusted as appropriate. Further, the value of the threshold voltage Vt may vary greatly depending on the technical level of the element manufacturer. For this reason, in consideration of the influence of the variation in the technical level, the threshold value of the upper limit of the variation may be applied as the threshold voltage Vt, and the voltage value Vm obtained by adding the margin voltage may be used as the upper limit value.

  When the element value satisfying the condition that the added voltage Vgs is within the voltage region VR1 is determined, a time-dependent waveform is obtained as shown in FIG. The waveforms to be noted here are those shown in FIGS. 30 (i), 30 (k), and 30 (l). The gate-source voltage Vgs1 of the power MOSFET 3H has an upper limit value that is substantially equal to the threshold voltage Vt (in the above-described definition, in the voltage region VR1) (see the portion indicated by symbol Y in FIG. 30 (i)).

  When the gate-source voltage Vgs1 of the MOSFET 3H is substantially equal to the threshold voltage Vt and reaches the voltage in the voltage region VR1, the channel current flowing through the MOSFET 3H increases, and the transient current change in the second half of recovery of the MOSFET 3H and MOSFET 3L becomes small. (Refer to the broken line → solid line part in FIG. 30 (k) and FIG. 30 (l)).

  The inventors verified the above-mentioned contents by performing simulations and experiments as follows. FIG. 31 shows a current change when an element value that satisfies the condition that the added voltage Vgs falls within the voltage region VR2 is applied. FIG. 32 shows an element value that satisfies the condition that the added voltage Vgs falls within the voltage region VR1. The current change when applying is shown. FIG. 33 shows a change in current when the circuit configuration of the conventional example (Patent Document 1) is applied.

  When the circuit configuration of Patent Document 1 is applied as a comparative example, a so-called self-turn-on phenomenon occurs as shown in FIG. 33. As a result, the drain current gradient di / dt in the latter half of the recovery increases and the drain current ringing is large. However, if an element value satisfying the condition that the added voltage Vgs falls within the voltage region VR2 is applied, the self-turn-on phenomenon is suppressed, and therefore the ringing of the drain current waveform can be reduced as shown in FIG.

  Further, even if an element value that satisfies the condition that the added voltage Vgs falls within the voltage region VR1 is applied, the self-turn-on phenomenon is suppressed. Therefore, as shown in FIG. 32, the ringing is reduced as compared with the current waveform of FIG. I understand that I can do it. Further, it can be seen that the current change gradient (dId / dt) in the latter half of the recovery can be made gentle (the absolute value is small) when compared with the current waveform of FIG.

  Further, the inventors connect an inductive load (corresponding to the stator coil 4 described above) to the supply node of the DC power source 2 as shown in FIG. 34 in order to confirm the surge voltage characteristics of the drain-source voltage Vds of the MOSFET 3H. An evaluation experiment is carried out using the above circuit. The test conditions were: power supply voltage of the DC power supply 2: 200 V, load current: 10 A, inductive load corresponding to reference numeral 4 in FIG. 34: 300 μH, impedance element ZL of the off-holding circuit 9 L as the resistance Rd, Is changed to 0Ω, 20Ω, 50Ω, and 100Ω.

  When these conditions were applied and the impedance element ZL (resistor Rd) connected between the gate and source of the power MOSFET 3H was changed, the drain-source voltage Vds of the power MOSFET 3H was observed. The transient response waveforms at this time are shown in FIG. 35 (Rd = 0Ω), FIG. 36 (Rd = 20Ω), FIG. 37 (Rd = 50Ω), and FIG. 38 (Rd = 100Ω). Moreover, the result of having measured and put together the switching loss W and the surge voltage V is shown by the relative level in FIG.

  As shown in the measurement result of the surge voltage in FIG. 39, if the resistance Rd is increased, the maximum value of the drain-source voltage Vds is decreased, so that the surge voltage [V] tends to decrease, but the switching loss W [μJ ] Becomes the lowest when the resistance value Rd = 20 [Ω] of the impedance element ZL or a value around it is adopted.

  This shows that when the resistance value Rd is lowered, the switching loss W tends to be lowered. However, when the resistance value Rd is too low, the ringing is increased and the loss is increased. For this reason, the element value may be determined by trade-off so as to satisfy the necessary surge voltage characteristics and switching loss in consideration of these situations.

  This evaluation result shows an example of resistance value dependency. For example, when taking into account that the value of the voltage Vgsb changes with the capacitance values Cds and Cgs, each size of the power MOSFETs 3H and 3L (gate width, Note that the resistance value Rd to be determined in a trade-off varies depending on the gate length.

  According to the present embodiment, an element value that satisfies that the added voltage Vgs becomes a voltage in the voltage region VR2 that is less than the threshold voltage Vt is applied. For this reason, ringing can be reduced as compared with the prior art. Further, the switching loss W can be reduced.

In addition, ringing can be reduced by applying an element value that satisfies that the added voltage Vgs becomes a voltage in the voltage region VR1 that is substantially equal to the threshold voltage Vt. In addition, the surge voltage can be reduced.
(Other examples)
The present invention is not limited to the above-described embodiments, and for example, the following modifications or expansions are possible.

  Further, as shown in the first embodiment, the energization resistance RnH when the switching speed adjustment circuit 8H is turned on and the energization resistance RfH when the switching speed adjustment circuit 8L is turned on, and the energization resistance RnL when the switching speed adjustment circuit 8L is turned on and the energization when turn-off is performed. When the resistor RfL is provided separately, the turn-on speed and the turn-off speed can be adjusted.

  When the current change in the second half of the turn-on recovery is considerably larger than the current change at the turn-off, the resistance values of the resistors RnH and RfH and the resistance values of the resistors RnL and RfL may be required to be different from each other. . In this case, by individually adjusting the resistance values of these resistors RnH, RnL, RfH, and RfL, it becomes easy to adjust the required turn-on time and turn-off time, respectively. Therefore, it becomes easy to complete switching in the required switching time, and switching loss can be suppressed.

  The circuit configuration shown in the above embodiment may be applied only to the drive circuit 6H for the high-side power MOSFET 3H, and the conventional circuit may be applied to the drive circuit 6L for the low-side power MOSFET 3L. In this case, a configuration for energizing the power MOSFET 6L through, for example, an on switch may be used as a conventional circuit instead of the drive circuit 6L. Even if such a circuit configuration is applied, the same effect as that of the above-described embodiment can be obtained.

  Conversely, the circuit configuration shown in the above embodiment may be applied only to the drive circuit 6L for the low-side power MOSFET 3L, and the conventional circuit may be applied to the drive circuit 6H for the high-side power MOSFET 3H. In this case, a configuration for energizing the power MOSFET 6H through, for example, an on switch may be used as a conventional circuit instead of the drive circuit 6H. Even if such a circuit configuration is applied, the same effect as that of the above-described embodiment can be obtained.

  In the drawing, 1 is a half-bridge circuit, 2 is a DC power supply, 3H is a high-side N-channel SJ-MOSFET (power MOSFET), and 3L is a low-side N-channel SJ-MOSFET (power MOSFET). Is a stator coil, 5H and 5L are freewheel diodes, 6H and 6L are drive circuits (power MOSFET drive circuits), 7H and 7L are drive voltage generation circuits (7H is a first energization switch circuit, and 7L is a second energization switch circuit). 8H and 8L are switching speed adjusting circuits (8H is a first charge injection / discharge circuit, 8L is a second charge injection / release circuit), 9H and 9L are off-hold circuits (9H is a first impedance switching unit, and 9L is a second circuit). Impedance switching unit), 10H and 10L are DC power supplies, 11 is a control circuit, 12 is a comparison circuit, 13 is a logic circuit, and 14 is OR gate 15 is a logic circuit, 16 is a NOR gate, 17 and 18 a NOT gate, the logic circuit 19, 20 is a NOT gate, 21 denotes a NOT gate.

Claims (10)

A drive target in which a voltage-driven first power MOSFET and a second power MOSFET are half-bridge connected between the first power supply line and the second power supply line, and an inductive load is connected between the first power MOSFET and the second power MOSFET. In the drive circuit that drives
A first energization switch circuit capable of energizing and deenergizing a power supply voltage using a potential of a low potential side reference terminal of the first power MOSFET as a reference potential, between a power supply voltage supply terminal and the low potential side reference terminal A first energization switch circuit configured by connecting a first on switch and a first off switch in series to each other;
A first charge injection / discharge circuit connected between the first energization switch circuit and the control terminal of the first power MOSFET for adjusting a rate at which charges are injected / discharged to the control terminal;
It is connected between the control terminal of the first power MOSFET and the low potential side reference terminal, and the impedance between the control terminal and the low potential side reference terminal is higher than the impedance of the first charge injection / discharge circuit. A first impedance switching unit that switches between a first impedance state (where the first impedance state includes at least one of resistive and inductive) and an open state in which the impedance is higher than the first impedance state;
A second energization switch circuit capable of energizing on and releasing a power supply voltage with a potential of a low potential side reference terminal of the second power MOSFET as a reference potential, and comprising a power supply voltage supply terminal and the low potential side reference terminal A second energizing switch circuit configured by connecting a second on switch and a second off switch in series between the second on switch and the second on switch;
A second charge injection / release circuit connected between the second energization switch circuit and a control terminal of the second power MOSFET for adjusting a rate at which charges are injected / discharged to the control terminal;
The second power MOSFET is connected between the control terminal of the second power MOSFET and the low potential side reference terminal, and the impedance between the control terminal and the low potential side reference terminal is higher than the impedance of the second charge injection / discharge circuit. A second impedance switching unit that switches between a second impedance state (wherein the second impedance state includes at least one of resistive and inductive) and an open state having a higher impedance than the second impedance state;
Control means for controlling the switch states of the first and second energization switch circuits and the switching states of the first and second impedance switching units;
The control means includes
(A) Turn on the kth on switch and turn off the kth off switch. (B) Turn off the kth on switch from on and then turn on the kth off switch. (C) Turn on the kth off switch from on and off at the same time. Switching control including (A) to (C) shown in the k impedance switching unit in the kth impedance state and the mth on switch on (where k is 1 or 2 and m is the other) is performed. A power MOSFET drive circuit. When the control means switches and controls the k-th on switch, the k-th off switch, the m-th on switch, and the m-th off switch,
In the section (B), after the k-th on switch is turned off, the k-th off switch is turned on, the k-th impedance switching unit is kept open, and the m-th off switch is turned on.
2. The power according to claim 1, wherein in the section (C), the k-th impedance switching unit is switched from an open state to a predetermined k-th impedance state at the same time when the k-th off switch is turned off. MOSFET drive circuit. When the control means switches and controls the k-th on switch, the k-th off switch, the m-th on switch, and the m-th off switch,
In the section (B), after the k-th on switch is turned off from on, the k-th off switch is turned on and the k-th impedance switching unit is switched from an open state to a predetermined k-th impedance state,
2. The power MOSFET drive circuit according to claim 1, wherein the k-th off switch is controlled to be switched from on to off in the section (C). 3. The control means includes
When the m-th ON switch is turned on and charges are injected into the control terminal of the m-th power MOSFET through the m-th charge injection / discharge circuit, a predetermined time elapses when the m-th power MOSFET current exceeds a predetermined settling current for the first time. 4. The power MOSFET according to claim 1, wherein the impedance of the k-th impedance switching unit is controlled to be switched to a predetermined k-th impedance state simultaneously with turning off the k-th off switch. Drive circuit. The power MOSFET drive circuit according to any one of claims 1 to 4, wherein the device value of the kth impedance switching unit (k is 1 or 2) is determined.
A counter electromotive voltage generated in the parasitic inductance of the source of the kth power MOSFET according to a recovery current generated in the parasitic diode of the kth power MOSFET, and a generated voltage generated by coupling of the parasitic capacitance of the kth power MOSFET. And determining an element value satisfying that the added voltage is less than a threshold voltage of the k-th power MOSFET as an element value of the k-th impedance switching unit. Method. The power MOSFET drive circuit according to any one of claims 1 to 4, wherein the device value of the kth impedance switching unit (k is 1 or 2) is determined.
A counter electromotive voltage generated in the parasitic inductance of the source of the kth power MOSFET according to a recovery current generated in the parasitic diode of the kth power MOSFET, and a generated voltage generated by coupling of the parasitic capacitance of the kth power MOSFET. The element value of the power MOSFET drive circuit is determined by adding and determining an element value satisfying that the added voltage is substantially equal to a threshold voltage of the k-th power MOSFET as an element value of the k-th impedance switching unit Decision method. Driving a drive target in which a voltage-driven a-th and b-th power MOSFETs are half-bridge connected between the first power line and the second power line and an inductive load is connected between the a-th and b-th power MOSFETs. A driving circuit for
An a-th energization switch circuit capable of turning on and off a power supply voltage using a potential of a low-potential side reference terminal of the a-th power MOSFET as a reference potential, between a power supply voltage supply terminal and the low-potential side reference terminal An a energization switch circuit configured by connecting the a-th on switch and the a-th off switch in series;
An a charge injection / release circuit connected between the a th energization switch circuit and the control terminal of the a th power MOSFET for adjusting the rate at which charges are injected / discharged to the control terminal;
It is connected between the control terminal of the a-th power MOSFET and the low-potential side reference terminal, and the impedance between the control terminal and the low-potential side reference terminal is higher than the impedance of the a-th charge injection / discharge circuit. A-th impedance switching unit that switches between the a-th impedance state (where the a-th impedance state includes at least one of resistive and inductive) and an open state in which the impedance is higher than that of the a-th impedance state;
A b-th energization switch circuit for energizing the b-th power MOSFET by energizing the control terminal of the b-th power MOSFET through the b-th on switch;
Control means for controlling the switch states of the a-th and b-th energization switch circuits and the switching state of the a-th impedance switching unit,
The control means includes
(A) The a-th on switch is turned on and the a-th off switch is turned off. (B) After the a-th on switch is turned off, the a-th off switch is turned on. (C) At the same time as the a-th off switch is turned off. The switching control including (A) to (C) shown in (a) is performed in the a impedance state and the b on switch is turned on (where a is 1 or 2 and b is the other). A power MOSFET drive circuit. When the control means switches and controls the a-th on switch, the a-th off switch, and the b-th on switch,
In the section (B), after the a-th on switch is turned off from on, the a-th off switch is turned on and the a-th impedance switching unit is switched from an open state to a predetermined a-th impedance state,
8. The power MOSFET drive circuit according to claim 7, wherein the a-th off switch is controlled to be switched from on to off in the section (C). The power MOSFET drive circuit according to claim 7 or 8, wherein the element value of the a-th impedance switching unit is determined.
A counter electromotive voltage generated in the parasitic inductance of the source of the a-th power MOSFET according to a recovery current generated in the parasitic diode of the a-th power MOSFET, and a generated voltage generated by coupling of the parasitic capacitance of the a-th power MOSFET. And determining an element value satisfying that the added voltage is less than a threshold voltage of the a-th power MOSFET as an element value of the a-th impedance switching unit. Method. The power MOSFET drive circuit according to claim 7 or 8, wherein the element value of the a-th impedance switching unit is determined.
A counter electromotive voltage generated in the parasitic inductance of the source of the a-th power MOSFET according to a recovery current generated in the parasitic diode of the a-th power MOSFET, and a generated voltage generated by coupling of the parasitic capacitance of the a-th power MOSFET. The element value of the drive circuit for the power MOSFET is determined by adding and determining an element value satisfying that the added voltage is substantially equal to the threshold voltage of the a-th power MOSFET as the element value of the a-th impedance switching unit Decision method.

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