JP5466432B2 - Frame synchronizer - Google Patents

Description

  The present invention relates to a frame synchronization apparatus that establishes frame synchronization under a predetermined frame configuration in a frame synchronization communication system.

  Currently, in many wired transmission systems and wireless transmission systems including an optical transmission system, a predetermined frame synchronization word (UW) (hereinafter referred to as “UW”) is used for each data field in which transmission information is divided and arranged. ) Is added as a sequence of frames, data of various word lengths and contents are transmitted.

In these transmission systems, in order to realize stable restoration of transmission information at the receiving end, frame synchronization is taken under the correlation between the reception sequence and the UW.
Such frame synchronization is realized, for example, as follows under the configuration shown in FIG.

The received wave that has arrived at the antenna 21 is subjected to processing such as demodulation, signal determination, and transmission path decoding by the receiving device 22 to be converted into a symbol string indicating the above-described frame (FIG. 5 (1)). The
The bit synchronization unit 23 reproduces a clock signal synchronized with each bit of transmission information constituting each symbol from such a symbol string.

The frame synchronization unit 24 performs the following processing.
(1) The above-described symbol sequence is serial-parallel converted in units of bits by the first-in first-out method in synchronization with the above clock signal, and a word with a predetermined number of bits (hereinafter “correlated”) Word ").
(2) Correlation between such a correlated word and a known UW is performed, and the time point at which the inter-code distance is minimum (without exceeding a predetermined upper limit value) is specified.
(3) The period of the data field (FIG. 5 (2)) on the time axis is specified based on this time point.

  On the other hand, the data extraction unit 25 captures a symbol sequence in bit units in synchronization with the clock signal, and among these bits, extracts a sequence of bits captured in the period specified by the frame synchronization unit 24 as described above. Output as transmission information.

  The UW is not limited to one type. For example, the transmission speed to be notified from the transmission end to the reception end, the type / word length of transmission information, the applied modulation scheme, the identification information of the receiving station, and the like. It may be set as a corresponding unique word.

  Further, the above-described upper limit value is not necessarily constant, and may be changed depending on, for example, the level of the received wave, the SN ratio, transmission quality, and the like.

Further, the transmission information arranged in the data field may include the identification information of the receiving station.
In addition, there exist the following patent documents 1 thru | or patent documents 3 as a prior art relevant to this invention.

(1) “In a frame synchronization detection circuit that detects a frame synchronization pattern by a multipoint monitoring method, the frame synchronization pattern is divided into a plurality of patterns and sequentially matched with a fixed pattern to perform synchronization detection. By storing the matching patterns in the memory in advance and sequentially reading them out and collating them with the frame synchronization pattern, it is possible to realize a logical path frame that is inexpensive and can realize space saving. Synchronization detection circuit (frame synchronization detection method) ... Patent Literature 1

(2) “A serial-to-parallel conversion circuit that sequentially multiplexes a multiplexed signal in which a signal of a plurality of channels is multiplexed and a frame synchronization pulse pattern is periodically inserted into n signal strings, and the divided n signals A detection circuit for detecting n types of frame synchronization pulse patterns from the column, a frame pulse output circuit for outputting a frame pulse at a frame synchronization pulse pattern insertion position, the frame pulse output timing, and n types of frame synchronization pulse patterns of the detection circuit In a frame synchronization circuit having a timing comparison circuit for comparing whether or not detection timings coincide with each other, n types corresponding to n types of patterns that can be generated when a synchronization word is converted by serial / n parallel conversion N synchronization protection circuits (4) for determining whether the pattern detection circuit and the timing comparison circuit are out of synchronization; When the timing comparison circuit detects a mismatch with respect to all the detection pulses of the n types of frame synchronization patterns and all the n synchronization protection circuits determine that the synchronization is lost, the frame pulse of the frame pulse output circuit A frame synchronization circuit characterized in that the same synchronization protection circuit as that of the multiplexed signal frame synchronization circuit before division is applied.

(3) “A serial-to-parallel conversion circuit that sequentially multiplexes a multiplexed signal in which a signal of a plurality of channels is multiplexed and a frame synchronization pulse pattern is periodically inserted into n signal sequences, and the divided n signals A detection circuit for detecting n types of frame synchronization pulse patterns from the column, a frame pulse output circuit for outputting a frame pulse at a frame synchronization pulse pattern insertion position, the frame pulse output timing, and n types of frame synchronization pulse patterns of the detection circuit In a frame synchronization circuit having a timing comparison circuit for comparing whether or not detection timings coincide with each other, n types corresponding to n types of patterns that can be generated when a synchronization word is converted by serial / n parallel conversion N synchronization protection circuits (4) for determining whether the pattern detection circuit and the timing comparison circuit are out of synchronization; When the timing comparison circuit detects a mismatch with respect to all the detection pulses of the n types of frame synchronization patterns and all the n synchronization protection circuits determine that the synchronization is lost, the frame pulse of the frame pulse output circuit Frame synchronization circuit characterized in that it can be synchronized with the same synchronization recovery time as before without changing the frame synchronization pattern by providing a timing control circuit (52) that controls the output timing '' ... Patent Document 3

JP-A-8-102733 Japanese Examined Patent Publication No. 6-38597 Japanese Examined Patent Publication No. 6-38597

  By the way, in the above-described conventional example, for example, the received wave arriving at the antenna 21 includes distortion caused by fading or multipath generated in the wireless transmission path. In particular, the distortion bursts during a period during which UW is transmitted. In such a case, there is a high possibility that smooth establishment of frame synchronization is hindered, or that erroneous synchronization of frame synchronization occurs or backward protection of frame synchronization cannot be maintained.

  Conventionally, for example, a plurality of UWs (in some cases, unique identification information may be included) are arranged in each frame, and a correlation between the plurality of UW strings at the receiving end is known. To some extent, frame synchronization based on the above is achieved.

  However, in such a frame, the word length is long, so that the transmission efficiency is lowered, or it is often not applicable because of restrictions on specifications and the like.

  An object of the present invention is to provide a frame synchronization apparatus capable of stably establishing and maintaining frame synchronization without causing any significant change in the frame configuration and a decrease in transmission efficiency.

  According to the first aspect of the present invention, the correlation means correlates in parallel the bit sequence received as a sequence of frames and a permutation of a plurality of subwords obtained by dividing frame synchronization words to be included in the frame. . The synchronization determination unit specifies an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applies the frame configuration of the frame to the bit string based on the arrangement, thereby The position of the frame at is determined.

  That is, the frame synchronization is realized based on the “result of correlation with the received bit string” performed for each of a plurality of subwords formed by dividing known frame synchronization words and the frame configuration.

  In the invention according to claim 2, the correlating means calculates the correlation between the bit sequence received as a sequence of frames and a frame synchronization word that is configured as a permutation of different sub-words and should be included in the frame. Take each subword in parallel. The synchronization determination unit specifies an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applies the frame configuration of the frame to the bit string based on the arrangement, thereby The position of the frame at is determined.

  In other words, frame synchronization is realized based on the “result of correlation with the received bit string” performed for each of a plurality of different subwords constituting the frame synchronization word and the suitability of the frame configuration.

  According to a third aspect of the present invention, the correlation means includes a plurality of words generated from a bit sequence received as a sequence of frames based on a rule that allows duplication in bit units and distributes without omission, and The frame synchronization word to be included is correlated in parallel with the permutation of a plurality of subwords divided under the rule. The synchronization determination unit specifies an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applies the frame configuration of the frame to the bit string based on the arrangement, thereby The position of the frame at is determined.

  That is, the “correlation with the received bit string” performed for each of the plurality of subwords is performed by referring to some bits of the frame synchronization word, and the desired rule on the time axis under the above rule. Obtained at the time.

  According to a fourth aspect of the present invention, in the frame synchronizer according to any one of the first to third aspects, the plurality of subwords are such that all bits included in the bit string are ordered with respect to the bit string. Arranged in a random manner.

  The accuracy of the result of correlation between such a plurality of subwords and the received bit string is that even if the quality of the bit string deteriorates in a burst state, bit errors due to the deterioration are dispersed on the time axis. Does not deteriorate rapidly.

  According to a fifth aspect of the present invention, in the frame synchronization device according to any one of the first to fourth aspects, the correlation means calculates the correlation result according to the transmission quality of the received bit string. Use with weight.

  That is, the result of “correlation with the received bit string” performed for each of a plurality of subwords is weighted larger or smaller as the transmission quality is lower, and is used for frame synchronization.

According to the present invention, compared with the conventional example in which frame synchronization is performed based on a simple correlation between a received bit string and a known frame synchronization word, the frame configuration is significantly changed and transmission efficiency is reduced. Thus, stable frame synchronization can be established and maintained.

  According to the present invention, even when a frame configuration different from the existing frame configuration is applied or the frame synchronization word is changed, the frame length is significantly increased as compared with the conventional example, and the transmission efficiency is reduced. It is possible to stably establish and maintain frame synchronization without occurring.

According to the present invention, even when the quality of the received frame synchronization word is deteriorated in a burst state, the configuration can be optimized and the restrictions on the configuration can be relaxed.
According to the present invention, the establishment of frame synchronization can be stabilized.

  Therefore, in the transmission system to which the present invention is applied, the performance and reliability are improved at a low cost, and the efficiency of maintenance and operation is improved.

It is a figure which shows one Embodiment of this invention. It is an operation | movement time chart of this embodiment. It is a figure which shows the flame | frame structure applied to this embodiment. It is a figure which shows the structural example of the receiver arrange | positioned at the receiving end of a frame synchronous communication system. It is a figure which shows the frame structure applied to the prior art example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention.
The difference between the present embodiment and the conventional example shown in FIG. 4 is that a frame synchronization unit 10 is provided instead of the frame synchronization unit 24, and the frame synchronization 10 is configured as follows.

(1) The shift register 11 having a clock terminal connected to the output of the bit synchronization unit 23 and a serial input to which the above-described symbol string is input is arranged in the first stage.
(2) The shift register 11 has parallel outputs individually corresponding to three sub-unique words SUW1, SUW2, and SUW3 described later.

(3) These parallel outputs are connected to one input of each of the correlators 12-1, 12-2 and 12-3.
(4) The other inputs of the correlators 12-1, 12-2 and 12-3 are given known words indicating the sub-unique words SUW1, SUW2 and SUW3, respectively.

(5) The outputs of these correlators 12-1, 12-2, 12-3 are connected to the first to third inputs of the synchronization verification unit 13, respectively, and the clock terminal of the synchronization verification unit 13 is bit-synchronized. The output of the unit 23 is connected.
(6) The output of the synchronization verification unit 13 is connected to the corresponding input of the data extraction unit 25.

FIG. 2 is an operation time chart of this embodiment.
The operation of this embodiment will be described below with reference to FIGS. The feature of the present embodiment is that the frame configuration shown in FIG. 3 is applied instead of the frame configuration shown in FIG. 5, and each unit of the frame synchronization unit 10 is linked as described later under such a frame configuration. In the point.
Therefore, in the following, detailed description of operations performed in the same manner as the conventional example shown in FIG. 4 is omitted.

  The UW arranged in the “frame synchronization word” field is the same as the UW shown in FIG. 5 as a bit string, but the UW is divided into three without being rearranged (FIG. 3 ( This corresponds to the permutation of 1)), SUW2 (FIG. 3 (2)), and SUW3 (FIG. 3 (3)).

In the following, it is assumed that the word lengths L1, L2, and L3 of the sub-unique words SUW1, SUW2, and SUW3 are all different.
Each unit of the frame synchronization unit 10 is linked as follows.

  The shift register 11 performs serial-parallel conversion of the above-described symbol sequence in bit units by a first-in first-out method in synchronization with the clock signal generated by the bit synchronization unit 23. A similar correlated word is generated.

  Correlators 12-1, 12-2, and 12-3 have three partial correlated words PCW1, PCW2, and PCW3 obtained by dividing the correlated words by the word lengths L1, L2, and L3, and the sub-states described above. By taking the correlation with the unique words SUW1, SUW2, and SUW3 in parallel (FIG. 2 (1)), the correlation result of binary (the level of correlation is indicated by the logical value “1” / “0”). RC1 (FIG. 2 (2), FIG. 3 (4)), RC2 (FIG. 2 (3), FIG. 3 (5)), RC3 (FIG. 2 (4), FIG. 3 (6)) are output.

  It should be noted that the criterion for determining whether the correlation is high or low is thresholds N1 (≦ L1), N2 (≦ L2), which are the minimum number of bits individually corresponding to the above-described partial correlated words PCW1, PCW2, and PCW3. It is given as N3 (≦ L3).

  The synchronization verification unit 13 specifies, for example, a time point when two or more logical values are detected as “1” among the logical values of the correlation results RC1, RC2, and RC3 described above, and uses this timing as a reference. By applying the frame configuration shown in FIG. 3 (FIG. 2 (5)), the period (FIG. 2 (6)) of the data field (FIG. 3 (7)) on the time axis is specified.

  The data extraction unit 25 outputs a bit string taken in synchronization with the clock signal during the period specified in this way as transmission information.

  In other words, according to the present embodiment, the establishment of frame synchronization based on UW is based on the correlation between the sub-unique words SUW1, SUW2, and SUW3 obtained by dividing the UW and the partial correlated words PCW1, PCW2, and PCW3. It is based on the point in time when it is determined that all or a part is high.

  Therefore, according to the present invention, frame synchronization is achieved based on the word lengths L1, L2, and L3 as well as the permutation of the sub-unique words SUW1, SUW2, and SUW3. Both the reduction in transmission efficiency and the delay in frame synchronization that occur when UWs are simply sent continuously can be avoided without significantly complicating or increasing the size of hardware.

  In the present embodiment, the sub-unique words SUW1, SUW2, and SUW3 may not be configured by simply dividing the UW applied to the conventional frame configuration.

  These sub-unique words SUW1, SUW2, and SUW3 are, for example, provided that frame synchronization based on a combination of intervals on the time axis at the time when the correlation is determined to be high is realized with desired accuracy and accuracy. Alternatively, it may be set as a permutation of desired different UWs (different in word length is irrelevant) or a permutation of the same UW.

  Further, the sub-unique words SUW1, SUW2, and SUW3 are set as three blocks into which the UW is divided without changing the permutation as the bit string of the UW described above. However, these sub-unique words SUW1, SUW2, and SUW3 are set as three words in which the bits included in the UW are allocated regardless of the order of the bit strings, for example, due to a burst error caused by the UW. Missynchronization and synchronization delay may be avoided.

  Also, for the sub-unique words SUW1, SUW2, and SUW3, it is determined that the correlation is high, for example, by setting the bits included in the UW as three words that are allowed to be duplicated and distributed without omission. The arrangement of the time point on the time axis may be optimized, or may be matched with the hardware configuration.

  Further, the minimum number of bits N1 (≦ L1), N2 (≦ L2), and N3 (≦ L3) individually corresponding to the partially correlated words PCW1, PCW2, and PCW3 are, for example, to obtain the above-described symbol string By varying based on the transmission quality evaluated in the process of signal determination and transmission path decoding performed, optimization of the frame synchronization reference according to the transmission quality may be achieved.

  Among the time points when the correlation is determined to be high, the number and combination of time points to be applied for frame synchronization can be changed based on transmission quality, for example, so that frame synchronization can be flexibly performed. It may be used to realize the determination.

Further, in the present embodiment, all or part of the frame synchronization unit 10 may be realized as an integrated circuit that realizes, for example, signal processing performed by a DSP or a function equivalent to the operation described above.
Further, the present invention is not limited to the above-described embodiments, and various configurations can be made within the scope of the present invention, and any improvement may be applied to all or some of the components.
Hereinafter, among the inventions disclosed as the above embodiments, the inventions that can be included in the claims of the present application are referred to as “Claims”, “Means for Solving the Problems”, and “Effects of the Invention”. It is added in the description format according to each column.

[Claim 6] In the frame synchronization apparatus according to any one of claims 1 to 4,
The synchronization determination means includes
The frame synchronization apparatus, wherein the combination or number of the correlation results to be specified as an arrangement on the bit string is varied among the correlation results according to the transmission quality of the received bit string.

  According to a sixth aspect of the present invention, in the frame synchronization device according to any one of the first to fourth aspects, the synchronization determination unit is configured to determine the correlation according to the transmission quality of the received bit string. Among the results, the combination or number of the correlation results to be specified as an arrangement on the bit string is varied.

That is, among the results of “correlation with received bit strings” performed for each of a plurality of subwords, the number of results used for frame synchronization is set to be larger or smaller as the transmission quality is lower.
Therefore, according to the present invention, flexible frame synchronization suitable for changes in transmission quality is possible.

10, 24 Frame synchronization unit 11 Shift register 12 Correlator 13 Synchronization verification unit 21 Antenna 22 Receiver 23 Bit synchronization unit 25 Data extraction unit

Claims (5)

Correlation means for taking a correlation between a bit sequence received as a sequence of frames and a permutation of a plurality of subwords obtained by dividing a frame synchronization word to be included in the frame;
The position of the frame on the bit string is determined by specifying an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applying the frame configuration of the frame to the bit string based on the arrangement A frame synchronization apparatus comprising: synchronization determination means for determining Correlation means configured as a permutation of a bit sequence received as a sequence of frames and a plurality of different subwords, and taking a correlation with a frame synchronization word to be included in the frame in parallel for each of the plurality of subwords;
The position of the frame on the bit string is determined by specifying an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applying the frame configuration of the frame to the bit string based on the arrangement A frame synchronization apparatus comprising: synchronization determination means for determining A plurality of words generated from a bit sequence received as a sequence of frames based on a rule that allows duplication in bit units and is distributed without omission and a frame synchronization word to be included in the frame are classified under the rule Correlation means for taking a correlation with a permutation of a plurality of subwords in parallel,
The position of the frame on the bit string is determined by specifying an arrangement on the bit string of the correlation result individually corresponding to the plurality of subwords, and applying the frame configuration of the frame to the bit string based on the arrangement A frame synchronization apparatus comprising: synchronization determination means for determining In the frame synchronizer according to any one of claims 1 to 3,
The plurality of subwords are:
A frame synchronization apparatus characterized in that all bits included in the bit string are arranged out of order with respect to the bit string. In the frame synchronizer according to any one of claims 1 to 4,
The correlation means includes
The frame synchronization apparatus, wherein the correlation result is weighted according to the transmission quality of the received bit string.