JP5465266B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit for relieving a defective memory cell.

  Conventionally, a shift redundancy system has been used to relieve defective memory cells. For example, the defective bit relief circuit disclosed in Patent Document 1 is arranged corresponding to a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, and the rows or columns of the memory cell array, Each has (n + 1) row or column lines to which memory cells corresponding to the corresponding row or column are connected, and n output signal lines, and an output signal of the n output signal lines according to an address signal Decoder means for driving the line to a selected state. When there are no defective memory cells in the row or column line, the n output lines of the decoder means are n adjacent rows or columns of the (n + 1) row or column lines. Associated with a line. The defective bit relief circuit is further provided between the n output signal lines and the (n + 1) row or column lines corresponding to each of the n output signal lines, and each of them is conductive. A switching transistor of a first conductivity type that electrically connects a corresponding output signal line to a corresponding row or column line, and a conductive signal complementary to the first conductivity type switching transistor, and corresponding to the output signal line when conducting A plurality of switching elements including a second conductivity type switching transistor connecting to a row or column line adjacent to a corresponding row or column line, and a first power supply potential supply node and a second power supply potential supply node One voltage supply path including a plurality of fusible fuse elements coupled to each other and provided corresponding to each of the n output signal lines and the switching elements and connected in series to each other is provided. The voltage at one side node of each fuse element is applied to the control electrodes of the first and second switching transistors of the corresponding switching element.

  Further, Patent Document 2 discloses a semiconductor memory device that can reduce standby current. That is, in Patent Document 2, a memory cell power supply line is disconnected from a power supply node during a test operation by a switch gate, and the voltage of the memory cell power supply line is detected by a detection circuit. Driving to the ground voltage level sets a memory cell having a defective standby current and operating normally to an operation unnecessary state. With such a configuration, a memory cell having a standby current failure and a normal operation is detected, and the standby current abnormality is relieved.

Japanese Patent No. 2837433 JP 2003-288799 A

  However, when repairing a plurality of columns as one column block in units of column blocks, in the shift redundancy system described in Patent Document 1, when any of two adjacent column blocks is defective, These column blocks cannot be relieved. In the conventional shift redundancy system, when a certain column block has a defect, the next adjacent column block is used instead of the column block. Because is impossible in practice.

  Further, in the circuit described in Patent Document 2, for example, it is necessary to include both a circuit for detecting a leak of a bit line and a circuit for detecting a leak of a memory cell power line, or a bit line load circuit and a power source. Since the switch gate circuit is inserted between the bit line load circuit and the switch gate circuit, the size of the MOS transistors included in the bit line load circuit and the switch gate circuit is increased.

  Therefore, a first object of the present invention is to provide a semiconductor memory device capable of relieving these column blocks even when any of two adjacent column blocks is defective.

  A second object of the present invention is to provide a semiconductor memory device capable of reducing standby current with a simple circuit configuration.

  In order to solve the above problems, a semiconductor memory device according to an aspect of the present invention includes a normal memory array unit in which normal memory cells are arranged in a matrix, and a normal memory array unit provided adjacent to the normal memory array unit. A memory cell array including a spare memory array unit in which spare memory cells are arranged in a matrix to relieve defective columns in the unit, and a plurality of internal units for transmitting data input to and output from the normal memory array unit Regular data lines, a plurality of internal spare data lines for transmitting / receiving data to / from the spare memory array section, a plurality of external data lines capable of transmitting / receiving data to / from the outside, an internal regular data line and an internal Spare data lines and data line shift circuits for connecting external data lines are provided, and the normal memory array section is arranged in the order of arrangement in the row direction of the memory cell array. , N spare blocks ordered from 0th to (N-1) th, and the spare memory array section has two spares ordered from 0th to 1st according to the arrangement order in the row direction. Each of the plurality of internal normal data lines corresponds to one of the N normal blocks, and the plurality of internal normal data lines correspond to the N normal blocks from the 0th to the ( The N-1) th order, each of the plurality of internal spare data lines corresponds to one of the two spare blocks, and the plurality of internal spare data lines correspond to the spare block from the 0th. Ordered up to the first, each of the plurality of external data lines corresponds to one of the N regular blocks, and the plurality of external data lines correspond to the regular block from the 0th to the (N−th). 1) Order by the first When the even-numbered regular block is defective, the data line shift circuit uses the shift redundancy method for the even-numbered regular block and the even-numbered spare block to perform even-numbered internal regular data lines and even-numbered blocks. The internal spare data line is connected to the even-numbered external data line, and the odd-numbered regular block is defective and the odd-numbered regular block and the odd-numbered spare block are used for the shift redundancy method. The odd-numbered internal normal data lines, the odd-numbered internal spare data lines, and the odd-numbered external data lines are connected.

  A semiconductor memory device according to another aspect of the present invention is coupled to a plurality of memory cells arranged in a matrix, a reference potential node, and a reference potential node, and is selectively turned on. A switch gate circuit for transmitting a potential, a first voltage transmission line for transmitting a voltage from the switch gate circuit to a plurality of memory cells, and activated in a specific operation mode, and the first voltage transmission line is connected A power control circuit for detecting whether or not the potential of the first node is at a predetermined potential level, and setting the potential of the first node to a potential according to the detection result, and a memory cell A plurality of bit line pairs arranged corresponding to each column and connected to the memory cells in the corresponding column and corresponding to the bit line pair, and charging the bit line in the corresponding column at least in the standby state Bi The switch gate circuit outputs a first control signal that is set to a predetermined level when the switch gate circuit is non-conductive, and the bit line load circuit has a first control signal that is set to a predetermined level. When set to level, stops charging the bit line.

  A semiconductor memory device according to another aspect of the present invention is coupled to a plurality of memory cells arranged in a matrix, a reference potential node, and a reference potential node, and is selectively turned on. A switch gate circuit for transmitting a potential, a first voltage transmission line for transmitting a voltage from the switch gate circuit to a plurality of memory cells, and activated in a specific operation mode, and the potential of the first node is a predetermined potential A power supply control circuit for detecting whether or not it is at a level and setting the potential of the first node to a potential according to the detection result according to the detection result, and arranged corresponding to the column of memory cells, And a plurality of bit line pairs to which the memory cells in the corresponding column are connected, and the bit line pair and the first voltage transmission line are connected to the first node.

  According to the semiconductor memory device according to an aspect of the present invention, even when any of two adjacent column blocks has a defect, these column blocks can be relieved.

  In addition, according to the semiconductor memory device according to another aspect of the present invention, standby current can be reduced with a simple circuit configuration.

It is a figure showing the structure of the semiconductor memory device of the 1st Embodiment of this invention. It is a diagram showing a program circuit 55a and a redundancy control circuit 56a for even blocks. It is a diagram showing a program circuit 55b and a redundancy control circuit 56b for odd blocks. It is a figure showing the data line shift circuit 58 when there is no defect in a regular block. It is a figure showing a data line shift circuit when there is an abnormality in two adjacent regular blocks. It is a figure showing the structure of the semiconductor memory device of the 2nd Embodiment of this invention. FIG. 7 is a diagram illustrating a configuration of a main part of the semiconductor memory device of FIG. 6 for one block (for four columns). FIG. 8 is a diagram illustrating an example of a configuration of a memory cell MC illustrated in FIG. 7. It is a flowchart which shows test operation | movement of the semiconductor memory device of embodiment of this invention. FIG. 5 is a timing chart showing an operation during a test of the semiconductor memory device according to the embodiment of the present invention. It is a figure showing the structure of the semiconductor memory device of the 3rd Embodiment of this invention. FIG. 12 is a diagram illustrating a configuration of a main part of the semiconductor memory device of FIG. 11 for one block (for four columns). It is a figure showing the structure of the semiconductor memory device of the 4th Embodiment of this invention. FIG. 14 is a diagram illustrating a configuration of a main part of the semiconductor memory device of FIG. 13 for one block (for four columns). It is a signal waveform diagram which shows the operation | movement at the time of reading and writing of the semiconductor memory device of the 4th Embodiment of this invention. It is a figure showing the structure of the semiconductor memory device of the 5th Embodiment of this invention. FIG. 17 is a diagram illustrating a configuration of a main part of the semiconductor memory device of FIG. 16 for one block (for four columns).

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram showing the configuration of the semiconductor memory device according to the first embodiment of the present invention.

  Referring to FIG. 1, the semiconductor memory device includes a memory cell array 51, a main control circuit 52, a row selection circuit 53, a column peripheral circuit 54, a program circuit 55, a redundancy control circuit 56, and a column decoder 57. A data line shift circuit 58, a data input / output circuit 59, and a test control circuit 110.

  The memory cell array 51 is provided adjacent to the normal memory array unit 91 in which normal memory cells are arranged in a matrix, and for repairing a defective column in the normal memory array unit 91. And spare memory array section 92 in which spare memory cells are arranged in a matrix. In the embodiment of the present invention, the number of regular memory cell columns is 128, and the number of spare memory cell columns is 8.

  The normal memory array unit 91 includes 128 normal blocks ordered from the 0th to the 127th according to the arrangement order of the memory cell array 51 in the row direction. Similarly, the spare memory array unit 92 includes two spare blocks that are ordered from the 0th to the first according to the arrangement order of the memory cell array 51 in the row direction. In the embodiment of the present invention, the number of columns included in the regular block and the spare block is four. Here, it is assumed that the 0th block of the normal memory array unit 91 and the 1st block of the spare memory array unit 92 are adjacent to each other.

  128 internal normal I / O lines NIO0 to NIO127 are arranged to transmit data input / output to / from normal memory array unit 91. The internal normal I / O line NIOX corresponds to the Xth normal block. However, X is 0-127.

  Two internal spare I / O lines are arranged to transmit data input / output to / from spare memory array unit 92. The internal spare I / O line SIOX corresponds to the Xth spare block. However, X is 0-1. Internal normal I / O lines NIO0 to NIO127 and internal spare I / O lines SIO0 and SIO1 are collectively referred to as internal I / O lines.

  In addition, 128 external I / O lines EIO0 to EIO127 are arranged for exchanging data with the outside. The external I / O line EIOX corresponds to the Xth regular block. However, X is 0-127.

  The main control circuit 52 generates an internal row address signal RA, an internal column address signal CA and control signals necessary for each operation in accordance with an external address signal AD, a write control signal WE, and a chip enable signal CE. For example, main control circuit 52 activates write control signal WE_N to L level during data writing.

  Test control circuit 110 sets test signal R_TEST to H level when testing a redundant column, and sets burn-in instruction signal BI_MODE to H level when performing a burn-in test.

  Row select circuit 53 drives word line WL corresponding to the addressed row to a selected state in accordance with internal row address signal RA. More specifically, row selection circuit 53 includes a row decoder 93 that decodes internal row address signal RA, and a word line drive circuit 94 that drives selected word line WL to a selected state according to the decoding result. In accordance with the word line activation timing signal, the word line WL corresponding to the selected row is driven to the selected state. In the standby state or not selected, word line WL is held at the ground voltage level.

  Column decoder 57 decodes internal column address signal CA to generate a column selection signal.

  The column selection circuit 19 is provided corresponding to each block, and one of the four bit lines BL and BLC in the block is determined by a column selection signal transmitted by the column selection line at the time of data reading and writing. Is selected and connected to the internal I / O line. Each of the four columns in the block is designated by a column selection signal Y_N [i] (i = 0 to 3).

  When reading data, reading unit 82 detects and amplifies data transmitted from bit line pairs BL and BLC corresponding to the column selected by column selection circuit 19 to internal I / O lines NIO0 to NIO127, SIO0 and SIO1. To generate read data.

  Write unit 81 transmits write data through internal I / O lines NIO0 to NIO127, SIO0, and SIO1 to bit line pairs BL and BLC corresponding to the column selected by column selection circuit 19 during data writing.

  Data line shift circuit 58 connects 128 of (128 + 2) internal I / O lines NIO0 to NIO127, SIO0, and SIO1 to 128 external I / O lines EIO0 to EIO127.

  The data input / output circuit 59 generates DQ data based on the read data on the external I / O lines EIO0 to EIO127 and outputs the DQ data to the outside. The data input / output circuit 59 generates write data based on the external DQ data and generates external data. / O lines are transmitted to EIO0 to EIO127.

  Program circuit 55 includes a program circuit 55a for even blocks and a program circuit 55b for odd blocks. The redundancy control circuit 56 includes a redundancy control circuit 56a for even blocks and a redundancy control circuit 56b for odd blocks.

  The redundancy control circuit 56a for the even block uses a shift control signal SHIFT [indicating whether or not there is a shift to the even-numbered external I / O line EIOX by a shift redundancy system for even-numbered regular blocks and even-numbered spare blocks. X]. However, X = 0, 2,..., 124, 126.

  The redundancy control circuit 56b for odd blocks uses a shift control signal SHIFT [indicating whether or not there is a shift with respect to the odd-numbered external I / O lines EIOX by a shift redundancy system for odd-numbered regular blocks and odd-numbered spare blocks. X]. However, X = 1, 3,..., 125, 127.

  FIG. 2 is a diagram showing program circuit 55a and redundancy control circuit 56a for even blocks.

  Program circuit 55a has a 7-bit configuration, and includes a 1-bit first fuse element that indicates whether a spare column is used and a 6-bit second fuse element that specifies one of 64 regular even-numbered blocks. including.

  The redundancy control circuit 56a includes an inverter IVS150 that inverts a signal from the first fuse element and outputs a control signal Column_Red_Enable_N, and an inverter IVS151 that inverts a signal from the second fuse element. Further, the redundancy control circuit 56a includes decoders DEC0, DEC2,..., DEC124, DEC126, NOR gates NRS0, NRS2,. ,..., IVS124, IVS126 are included. Decoder DECX, NOR gate NRSX, and inverter IVSX correspond to the regular Xth block. However, X is 0, 2,... 126.

  The decoder DECX receives the output signal from the second fuse, the output signal of the inverter IVS151, and the output signal of the inverter IVS150, and redundantly generates a defect identification signal CRED_N [X] indicating the presence or absence of a defect in the normal Xth block. Output to outside of the control circuit 56a. The defect identification signal CRED_N [X] is set to the L level when indicating normality, and is set to the H level when indicating defect.

  The NOR gate NRSX receives the output signal of the decoder XDEC of the normal Xth block and the shift control signal SHIFT [X + 2] corresponding to the normal (X + 2) th block.

  The inverter IVSX inverts the output signal of the NOR gate NRSX of the normal X-th block, generates the shift control signal SHIFT [X], outputs it to the outside of the redundancy control circuit 56a, and outputs the normal (X -2) Output to the NOR gate NRS (X-2) corresponding to the second block. However, when X = 0, the shift control signal SHIFT [0] is output to the NOR gate NRS 128 corresponding to the spare 0th block. Shift control signal SHIFT [X] is set to H level when it indicates that there is a shift, and is set to L level when it indicates that there is no shift.

  FIG. 3 is a diagram showing program circuit 55b and redundancy control circuit 56b for odd blocks.

  Program circuit 55b has a 7-bit configuration, and includes a 1-bit first fuse element that indicates whether a spare column is used and a 6-bit second fuse element that specifies one of 64 regular odd-numbered blocks. including.

  The redundancy control circuit 56b includes an inverter IVS152 that inverts a signal from the first fuse element and outputs a control signal Column_Red_Enable_N, and an inverter IVS153 that inverts a signal from the second fuse element. In addition, the redundancy control circuit 56b includes decoders DEC1, DEC3,..., DEC125, DEC127, NOR gates NRS1, NRS3,. , ..., IVS125, IVS127 are included. Decoder DECX, NOR gate NRSX, and inverter IVSX correspond to the regular Xth block. However, X is 1, 3, ... 127.

  The decoder DECX receives the output signal from the second fuse, the output signal from the inverter IVS152, and the output signal from the inverter IVS153, and redundantly generates a defect identification signal CRED_N [X] that indicates the presence or absence of a defect in the normal Xth block. Output to outside of the control circuit 56b. The defect identification signal CRED_N [X] is set to the L level when indicating normality, and is set to the H level when indicating defect.

  The NOR gate NRSX receives the output signal of the decoder XDEC of the normal Xth block and the shift control signal SHIFT [X + 2] corresponding to the normal (X + 2) th block.

  The inverter IVSX inverts the output signal of the NOR gate NRSX of the normal X-th block, generates the shift control signal SHIFT [X], outputs it to the outside of the redundancy control circuit 56a, and outputs the normal (X -2) Output to the NOR gate NRS (X-2) corresponding to the second block. However, when X = 1, the shift control signal SHIFT [1] is output to the NOR gate NRS 129 corresponding to the spare first block. Shift control signal SHIFT [X] is set to H level when it indicates that there is a shift, and is set to L level when it indicates that there is no shift.

Next, operation examples of the program circuit 55 and the redundancy control circuit 56 will be described.
In the initial setting, the program circuit 55a and the program circuit 55b are not programmed, and all the defect identification signals CRED_N [0] to CRED_ [127], R_CRED_N [0], and R_CRED_N [1] are at the L level indicating no defect. All shift control signals SHIFT [0] to SHIFT [127] are set to L level indicating no shift.

  When the redundant column test is performed, since the test signal R_TEST is set to the H level, all the shift control signals SHIFT [0] to SHIFT [127] are set to the L level indicating no shift.

  Burn-in instruction signal BI_MODE is activated to H level in a burn-in mode in which potential defects are made obvious by accelerating voltage and temperature. Thereby, the shift control signals R_CRED_N [0] and R_CRED_N [1] are set to the H level.

  Further, for example, it is assumed that defects are found in the regular 124th block and 125th block. In such a case, the program circuit 55a is programmed so that the regular 124th block is defective. Thereby, the decoder DEC124 sets the defect identification signal CRED_N [124] to the H level indicating that there is a defect. The defect identification signal CRED_N [i] (even when i ≠ 124) and the defect identification signal R_CRED_N [0] maintain the L level. When the defect identification signal CRED_N [124] becomes H level, the shift control signals SHIFT [124],... Are generated by the NOR gates NRS124,..., NRS2, NRS0 and the inverters IVS124,. , SHIFT [2] and SHIFT [0] are set to the H level indicating that there is a shift. Shift control signal SHIFT [126] maintains the L level.

  Further, the program circuit 55b is programmed so that the regular 125th block is defective. Thereby, the decoder DEC125 sets the defect identification signal CRED_N [125] to the H level indicating that there is a defect. The defect identification signal CRED_N [i] (i ≠ 125 and odd number) and the defect identification signal R_CRED_N [1] maintain the L level. When the defect identification signal CRED_N [125] becomes H level, the shift control signals SHIFT [125],... Are driven by the NOR gates NRS125,..., NRS3, NRS1 and the inverters IVS125,. , SHIFT [3] and SHIFT [1] are set to the H level indicating that there is a shift. Shift control signal SHIFT [127] maintains the L level.

FIG. 4 is a diagram showing the data line shift circuit 58 when the normal block has no defect.
Referring to FIG. 4, data line shift circuit 58 includes shift switches SWX (X = 0 to 127) corresponding to external IO lines EIOX (X = 0 to 127). The shift switch SWX is controlled by a shift control signal SHIFT [X].

  When there is no defect in the regular block, the redundancy control circuit 56 sets all shift control signals SHIFT [X] (X = 0 to 127) to the L level. In response, shift switch SWX connects external I / O line EIOX to internal normal I / O line NIOX.

  FIG. 5 is a diagram showing a data line shift circuit when there are abnormalities in two adjacent regular blocks.

  Referring to FIG. 5, when there is a defect in the regular third block and the fourth block, shift control signals SHIFT [0] to SHIFT [4] are set to the H level by redundancy control circuit 56, and the rest Shift control signals SHIFT [5] to SHIFT [127] maintain the L level. Shift switch SWX (X = 5 to 127) connects external I / O line EIOX to internal normal I / O line NIOX because shift control signal SHIFT [X] is at L level.

  Shift switch SW4 connects external I / O line EIO4 to internal normal I / O line NIO2 because shift control signal SHIFT [4] is at the H level. Shift switch SW3 connects external I / O line EIO3 to internal normal I / O line NIO1 because shift control signal SHIFT [3] is at the H level. Shift switch SW2 connects external I / O line EIO2 to internal normal I / O line NIO0 because shift control signal SHIFT [2] is at the H level.

  The shift switch SW1 connects the external I / O line EIO1 to the internal spare I / O line SIO1 because the shift control signal SHIFT [1] is at the H level. Shift switch SW0 connects external I / O line EIO0 to internal spare I / O line SIO0 because shift control signal SHIFT [0] is at the H level.

  As described above, according to the semiconductor memory device of the first embodiment of the present invention, relief is performed by the shift redundancy method by dividing into even-numbered blocks and odd-numbered blocks. Even if any of them has a defect, these column blocks can be relieved.

[Second Embodiment]
(Constitution)
FIG. 6 is a diagram showing the configuration of the semiconductor memory device according to the second embodiment of the present invention.

  Referring to FIG. 6, the semiconductor memory device of the second embodiment is similar to the semiconductor memory device of the first embodiment shown in FIG. 1, and further includes a bit line load circuit 13, a potential drop detection holding circuit 16, and a switch. A gate circuit 15 and a latch circuit 17 are added. The semiconductor memory device of the second embodiment includes a test control circuit 10 instead of the test control circuit 110 shown in FIG.

  In addition to the control of the levels of the test signal R_TEST and the burn-in instruction signal BI_MODE described in the first embodiment, the test control circuit 10 further includes a first test mode signal RED_LEAK1, a second test mode signal RED_LEAK2, and a third test mode signal RED_LEAK2. The level of the test mode signal RED_LEAK3 is controlled.

  Bit line load circuit 13 is arranged corresponding to each bit line pair of the memory cell array, and holds the corresponding bit line pair at the ground voltage level at least in the standby state.

  The potential drop detection holding circuit 16 is arranged corresponding to each block of the memory cell array, activated in the specific operation mode (when the second test mode signal RED_LEAK2 is at H level), and connected to the memory cell power supply line. It is detected whether the potential of the determination node is equal to or lower than the threshold voltage level. When the potential is lower than the threshold voltage level, the potential of the determination node is set to the ground voltage level.

  Switch gate circuit 15 is arranged corresponding to each block of the memory cell array, is coupled to a reference potential node, is selectively rendered conductive, and transmits the reference potential to the determination node when rendered conductive.

  The latch circuit 17 is arranged corresponding to each block of the memory cell array, and the voltage of the determination node set by the potential drop detection holding circuit 16 in the specific operation mode (when the second test mode signal RED_LEAK2 is at the H level). And the conduction state of the switch gate circuit 15 is set by the latch signal.

  FIG. 7 is a diagram showing the configuration of the main part of the semiconductor memory device of FIG. 6 for one block (for four columns). Although FIG. 7 shows the regular Kth block, the same applies to other regular blocks and spare blocks. However, in the spare block, the defect identification signal R_CRED_N [0] or R_CRED_N [1] is input instead of the defect identification signal CRED_N [K].

  Referring to FIG. 7, bit line pairs BL [0], BLC [0] to BL [3], BLC [3] are arranged corresponding to the memory cell columns. Further, memory cell power supply lines arvdd [0] to arvdd [3] are arranged corresponding to the memory cell columns.

FIG. 8 shows an example of the configuration of memory cell MC shown in FIG.
Referring to FIG. 8, memory cell MC has a configuration of a full CMOS single port SRAM cell. Memory cell MC includes a P channel MOS transistor PQ1, a P channel MOS transistor PQ2, an N channel MOS transistor NQ1, an N channel MOS transistor NQ2, an N channel MOS transistor NQ3, and an N channel MOS transistor NQ4.

  A memory cell power supply line arvdd [K] (K is any one of 0 to 3) is connected to the connection node NOD3. P-channel MOS transistor PQ1 is connected between connection node NOD3 and storage node NOD1, and has its gate connected to storage node NOD2. P-channel MOS transistor PQ2 is connected between connection node NOD3 and storage node NOD2, and has its gate connected to storage node NOD1. N channel MOS transistor NQ1 is connected between ground power supply and storage node NOD1, and has its gate connected to storage node NOD2. N channel MOS transistor NQ2 is connected between ground power supply and storage node NOD2, and has its gate connected to storage node NOD1. N-channel MOS transistor NQ3 couples storage node NOD1 to bit line BL [K] according to the voltage on word line WL. N-channel MOS transistor NQ4 couples storage node NOD2 to bit line BLC [K] according to the voltage on word line WL.

  Again referring to FIG. 7, bit line load circuits 13a-13d are provided corresponding to the respective columns of memory cells. Bit line load circuit 13a includes an inverter IV13, a P channel MOS transistor P13a, a P channel MOS transistor P13b, and a P channel MOS transistor P13c.

  The inverter IV13 inverts the column selection signal Y_N [0]. Inverter IV13 outputs a signal at L level when column selection signal Y_N [0] is at H level (the 0th column 0 in the block is not selected).

  P-channel MOS transistor P13a is conductive when the output of inverter IV13 is at L level, connects bit line BL [0] and power supply node PV2 when conductive, and charges bit line BL [0] with power supply voltage VDD. . P-channel MOS transistor P13b conducts when the output of inverter IV13 is at L level, connects bit line BLC [0] and power supply node PV2 when conducting, and charges bit line BLC [0] with power supply voltage VDD. . P channel MOS transistor P13c conducts when the output of inverter IV13 is at L level, and electrically short-circuits bit lines BL [0] and BLC [0] when conducting.

  The other bit line load circuits 13b to 13d have the same configuration and operation as the bit line load circuit 13a.

  A switch gate circuit 15 is provided for each block. Switch gate circuit 15 includes a three-input NOR gate NR15, an inverter IV15, and a P-channel MOS transistor P15.

  The 3-input NOR gate NR15 receives the defect identification signal CRED_N [K] of the normal Kth block from the redundancy control circuit 56, receives the output signal from the NOR gate NR17 included in the latch circuit 17, and receives the first signal from the test control circuit 10. Test mode signal RED_LEAK1 is received. In the redundancy control circuit 56, the defect identification signal CRED_N [K] is set to L level when the normal Kth block is not defective, and is set to H level when the normal Kth block is defective. The 3-input NOR gate NR15 outputs H level only when the defect identification signal CRED_N [K] is L level, the output signal of the NOR gate NR17 is L level, and the first test mode signal RED_LEAK1 is L level. Otherwise, L level is output. Inverter IV15 inverts the output of 3-input NOR gate NR15. P channel MOS transistor P15 conducts when the output signal of inverter IV15 is at L level, connects power supply node PV1 and decision node ND1 when conducting, and supplies power supply voltage VDD to memory cell power supply line arvdd via decision node ND1. [0] to arvdd [3].

  A latch circuit 17 is provided for each block. Latch circuit 17 includes an N channel MOS transistor N17 and a latch gate RG17.

  N-channel MOS transistor N17 is a transfer gate, and is conductive when second test mode signal RED_LEAK2 is at H level, and electrically couples determination node ND1 and node ND2 when conductive.

  The latch gate RG17 is initialized when the third test mode signal RED_LEAK3 is set to the H level, and is activated (enabled) when the third test mode signal RED_LEAK3 is set to the L level. The latch gate RG17 latches the potential of the node ND2 when activated (enabled). Latch gate RG17 includes a NOR gate NR17, an inverter IV17, and a tristate circuit TR17. The NOR gate NR17 receives the third test mode signal RED_LEAK3 and the signal (voltage) of the node ND2. The inverter IV17 inverts the second test mode signal RED_LEAK2. The tristate circuit TR17 has a gate controlled by the second test mode signal RED_LEAK2 and the output signal of the inverter IV17 (inverted signal of RED_LEAK2). When the gate is on, the output signal of the NOR gate NR17 is inverted and the node is inverted. Transmit to ND2.

  A potential drop detection holding circuit 16 is provided corresponding to each block. Potential drop detection holding circuit 16 includes an inverter IV16a, a NOR gate NR16, an inverter IV16b, an inverter IV16c, and an N-channel MOS transistor N16.

  The inverter IV16a inverts the second test mode signal RED_LEAK2. NOR gate NR16 receives the output of inverter IV16a and the voltage of determination node ND1. Two-stage cascade-connected inverters IV16b and IV16c shape the waveform of the output signal of NOR gate NR16 to reliably generate a binary signal at power supply voltage VDD or ground voltage level. Therefore, even when the amount of voltage drop at decision node ND1 is small and the output signal of NOR gate NR16 is at an intermediate voltage level, decision node ND1 is reliably connected to ground voltage according to inverters IV16b and IV16c in the next stage when the standby current is abnormal. The memory cells that can be driven to the level and that are normally in standby current abnormality / normal operation can be reliably set to a normal operation failure state.

  N channel MOS transistor N16 is selectively turned on according to the output signal of inverter IV16c, and transmits the ground voltage to determination node ND1 when turned on.

(Operation)
FIG. 9 is a flowchart showing a test operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 10 is a timing chart showing an operation during a test of the semiconductor memory device according to the embodiment of the present invention. Hereinafter, a method for testing a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

  Here, how the circuit related to the regular Kth block operates during the test will be described, but related circuits also operate in the same manner for other blocks.

  First, in step S1, a standby state before entering the test operation mode is set. The test control circuit 10 sets the first test mode signal RED_LEAK1 to L level, sets the second test mode signal RED_LEAK2 to L level, and sets the third test mode signal RED_LEAK3 to H level. In this standby state, the fuse program has not yet been performed, and the normal Kth block defect identification signal CRED_N [K] is at the L level. Further, the column selection signals Y_N [0] to Y_N [3] are at the H level.

  By setting the third test mode signal RED_LEAK3 to the H level, the latch gate RG17 of the latch circuit 17 is initialized, and the voltage of the node ND2 is set to the power supply voltage level VDD.

  Further, the power supply voltage VDD is set to a voltage level higher than the voltage level VDDn used during normal operation. This is done by adjusting the power supply voltage level applied to the power supply terminal under the control of an external tester. As a result, the standby current failure / normal operation state of the memory cell MC becomes apparent.

  In the switch gate circuit 15, since the defect identification signal CRED_N [K] is at the L level, the first test mode signal RED_LEAK1 is at the L level, and the output of the latch gate RG17 is at the L level, the P channel MOS transistor P15 becomes conductive, and power supply node PV1 and determination node ND1 are connected. As a result, the power supply voltage VDD is supplied from the power supply node PV1 to the four memory cell power supply lines arvdd [0] to arvdd [3] via the determination node ND1. P channel MOS transistor P15 has a current supply capability that is large enough to supply a sufficiently stable operating power supply voltage to memory cells connected to memory cell power supply lines arvdd [0] to arvdd [3] ( Channel width to channel length).

  In this state, in memory cell MC, power supply voltage VDD applied via memory cell power supply lines arvdd [0] to arvdd [3] is higher than voltage level VDDn applied during normal operation. When there is a resistance component due to a foreign substance or the like, the on-resistance of the MOS transistor in the memory cell MC is made sufficiently small, and the influence of the resistance component due to the foreign substance or the like becomes obvious. Thereby, the memory cell MC that may cause the standby current failure is surely set to the standby current failure state.

  In the bit line load circuits 13a to 13d, since the column selection signals Y_N [0] to Y_N [3] are at the H level, the P channel MOS transistors P13a, P13b, and P13c are turned on, and the bit line BL [0] is turned on. , BLC [0] to BL [3], BLC [3] are charged with the power supply voltage VDD transmitted from the power supply node PV2.

  Next, in step S2, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the H level and sets the third test mode signal RED_LEAK3 to the L level for the time Ta. The test control circuit 10 maintains the second test mode signal RED_LEAK2 at the L level.

  By setting the first test mode signal RED_LEAK1 to the H level, in the switch gate circuit 15, the P-channel MOS transistor P15 is turned off, and the power supply node PV1 and the determination node ND1 are separated. As a result, the four memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV1. During the period Ta in which the memory cell power supply lines arvdd [0] to arvdd [3] are disconnected from the power supply node PV1, a large voltage drop does not occur in the standby leakage current allowed by the normal specification value, and abnormal in standby. The period is set such that a large voltage drop occurs in the memory cell power supply lines arvdd [0] to arvdd [3] only with current.

  As a result, the memory cell power supply lines arvdd [0] to arvdd [3] are in a floating state and connected to the determination node ND1.

  When there is a short circuit failure related to the memory cell power supply lines arvdd [0] to arvdd [3], a standby abnormal current flows through the memory cell power supply lines arvdd [0] to arvdd [3]. When the standby abnormal current flows, the potential of the determination node ND1 drops. On the other hand, when there is no short circuit failure as described above, the voltage levels of the memory cell power supply lines arvdd [0] to arvdd [3] are substantially maintained at the charge voltage level (VDD), and the potential of the determination node ND1 is Do not descend.

In the latch circuit 17, the third test mode signal RED_LEAK3 becomes L level, thereby enabling the latch gate RG17. However, since the second test mode signal RED_LEAK2 is at L level, the N-channel MOS transistor N17 is non-conductive, and the potential of the determination node ND1 is not input to the latch circuit 17.

  Next, in step S3, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the H level for the time Tb. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the H level, the potential drop detection holding circuit 16 is enabled, the voltage level of the determination node ND1 is detected, and the voltage level of the determination node ND1 is set according to the detection result. .

  When the standby abnormal current flows through any of the memory cell power supply lines arvdd [0] to arvdd [3] and the voltage level of the determination node ND1 falls below the threshold value, the N-channel NOS transistor N16 becomes conductive, The voltage level of decision node ND1 is driven to the ground voltage level.

  On the other hand, when the standby abnormal current does not flow through any of memory cell power supply lines arvdd [0] to arvdd [3], N-channel NOS transistor N16 is non-conductive, and determination node ND1 is driven to the ground level. Not done.

  The time Tb is a time required for reliably driving the memory cell power supply lines arvdd [0] to arvdd [3] in the standby current defective state to the ground voltage level.

  At this time, in the latch circuit 17, the N-channel MOS transistor N17 is turned on in accordance with the second test mode signal RED_LEAK2, and the voltage level of the determination node ND1 is latched by the latch gate RG17.

  Next, in step S4, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the L level for the time Tc. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the L level, the potential drop detection holding circuit 16 is deactivated, and in the latch circuit 17, the N channel MOS transistor N17 is turned off. The time Tc is provided to ensure the hold time of the latch circuit 17.

  Next, in step S5, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the L level. In the test control circuit 10, the second test mode signal RED_LEAK2 maintains the L level, and the third test mode signal RED_LEAK3 maintains the L level.

  By setting the first test mode signal RED_LEAK1 to the L level, the switch gate circuit 15 controls the connection between the determination node ND1 and the power supply node PV1 according to the latch information of the latch circuit 17.

  When the ground voltage level is latched in latch circuit 17, P channel MOS transistor P15 is maintained in a non-conductive state, and power supply node PV1 and determination node ND1 are separated.

  On the other hand, when power supply voltage level VDD is latched in latch circuit 17, P channel MOS transistor P15 is turned on to connect power supply node PV1 and determination node ND1. As a result, the power supply voltage VDD is supplied from the power supply node PV1 to the four memory cell power supply lines arvdd [0] to arvdd [3] via the determination node ND1.

  Next, in step S6 and step S7, data writing and reading are executed using various data patterns. The selected column i to be written or read is designated by activating the column selection signal Y_N [i] to L level.

  When there is a standby current failure in the regular Kth block, the power supply voltage VDD is not supplied from the power supply node PV1 to the memory cell power supply lines arvdd [0] to arvdd [3], and therefore the bit line BL [ 0], BLC [0] to BL [3], BLC [3], no accurate data is stored in the memory cell MC. Therefore, the data written in the memory cell MC and the data read from the memory cell MC do not match, and it is determined that the normal Kth block is defective.

  On the other hand, when there is no standby current failure in the regular Kth block, the power supply voltage VDD is supplied from the power supply node PV1 to the memory cell power supply lines arvdd [0] to arvdd [3], and the bit line BL [0 ], Accurate data is stored in memory cells MC connected to BLC [0] to BL [3], BLC [3]. Therefore, the data written in the memory cell MC matches the data read from the memory cell MC, and it is determined that the normal Kth block is normal.

  In step S8, the address of the defective block is programmed and the program circuit 55 is blown. When it is determined that the regular Kth block is abnormal, the defect identification signal CRED_N [K] is set to the H level by the program circuit 55 and the redundancy control circuit 56.

  When the defect identification signal CRED_N [K] is set to H level, the switch gate circuit 15 causes the memory cell power supply lines arvdd [0] to arvdd [3] to be fixedly separated from the power supply node PV1. Thereby, in the normal operation mode, the memory cell power supply lines arvdd [0] to arvdd [3] are in a floating state, and an abnormal standby leak current is prevented from flowing in the regular Kth block.

  Similarly to the first embodiment, the data line shift circuit 58 uses the external I / O line based on the shift control signal SHIFT [X] (X = 0 to 127) set by the redundancy control circuit 56. The connection between the EIOX and the internal I / O lines NIOX, SIO0, SIO1 is switched to repair the defective regular Kth block.

  As described above, according to the semiconductor memory device of the second embodiment, the memory cell power supply line extending in the column direction is separated from the power supply node during the test, and the voltage level of the memory cell power supply line is detected. If there is a short circuit associated with the memory cell power line and the voltage level of the memory cell power line is lowered, the memory cell power line is driven to the ground voltage level, and the standby current defective memory cell is It is possible to reliably set the malfunction state. Thereby, the standby current failure / normal operation memory cell can be set to an operation failure state, and this column address can be easily specified. In addition, during normal operation, the standby current failure can be reliably remedied by fixing the memory cell power supply line with the standby current failure fixedly away from the power supply node.

[Third Embodiment]
FIG. 11 is a diagram showing the configuration of the semiconductor memory device according to the third embodiment of the present invention.

  Referring to FIG. 11, the semiconductor memory device of the third embodiment is different from the semiconductor memory device of the second embodiment shown in FIG. 6 in the following points. That is, in the semiconductor memory device of the third embodiment, the bit line / determination node switch circuit 14 is added to the semiconductor memory device of the second embodiment shown in FIG. The bit line load circuit 23 and the switch gate circuit 75 of the semiconductor memory device of the third embodiment are the same as the bit line load circuit 13 and the switch gate circuit 15 included in the semiconductor memory device of the second embodiment shown in FIG. And different.

  The switch gate circuit 75 is basically the same as the switch gate circuit 15, but further outputs a control signal CRED_W_N [K] to the bit line load circuit 23. The control signal CRED_W_N [K] is set to H level when the power supply node PV1 and the determination node ND1 are separated, and is set to L level when the power supply node PV1 and the determination node ND1 are connected.

  The bit line / determination node switch circuit 14 switches connection and separation of the bit line pair BL and BLC to the determination node ND1. The bit line / determination node switch circuit 14 becomes conductive when in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level), and connects the bit lines BL and BLC to the determination node ND1. As a result, the potential drop detection holding circuit 16 detects the potential, and not only the memory cell power supply line arvdd but also the bit line pair BL and BLC are connected to the determination node ND1 to be set, so that the memory cell power supply line arvdd is connected. Not only the standby abnormal current that flows, but also the standby abnormal current that flows through the bit line pair BL and BLC can be detected.

  Further, the bit line / determination node switch circuit 14 is a bit connected to the bit line / determination node switch circuit 14 at times other than in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level). When data is read from or written to the memory cells to the line pair BL, BLC, it becomes non-conductive, and the bit lines BL, BLC are separated from the determination node ND1. Thus, at the time of data reading and writing, the bit line pair BL, BLC is disconnected from the determination node ND1, and the bit line BL, BLC of the selected column is disconnected from the bit line BL, BLC of the non-selected column, the memory cell power supply line arvdd, and the power supply Since it is separated from the node PV1, data is read and written normally.

  The bit line load circuit 23 is basically the same as the bit line load circuit 13, but when the control signal CRED_W_N [K] output from the switch gate circuit 75 is set to H level, the bit line BL, BLC Stop charging.

  FIG. 12 is a diagram showing the configuration of the main part of the semiconductor memory device of FIG. 11 for one block (for four columns). In FIG. 12, differences from the main part of the semiconductor memory device according to the second embodiment shown in FIG. 7 will be described.

  Referring to FIG. 12, a switch gate circuit 75 is provided corresponding to each block of memory cells. The switch gate circuit 75 is basically the same as the switch gate circuit 15 of the second embodiment, but the output of the inverter IV15 is not only output to the P-channel MOS transistor P15 but also the control signal CRED_W_N [K ] Is output to the bit line load circuits 23a to 23d via the inverter IV23. Control signal CRED_W_N [K] is set to L level when P channel MOS transistor P15 is turned on, that is, when power supply node PV1 and determination node ND1 are connected, and P channel MOS transistor P15 is turned off. When the power supply node PV1 and the determination node ND1 are separated, the H level is set.

  In addition, bit line determination node switch circuits 14a to 14d are provided corresponding to each column of memory cells, and an inverter IV14 is provided corresponding to each block.

The inverter IV14 inverts the first test mode signal RED_LEAK1.
Bit line / determination node switch circuit 14a includes a transmission gate TG14a and a transmission gate TG14b.

  The gate of the transmission gate TG14a is controlled by the first test mode signal RED_LEAK1 and the inverted signal of the first test mode signal RED_LEAK1. The transmission gate TG14a is turned on when the first test mode signal RED_LEAK1 is at the H level, and connects the determination node ND1 and the bit line BL [0] when the gate is turned on.

  The gate of the transmission gate TG14b is controlled by the first test mode signal RED_LEAK1 and the inverted signal of the first test mode signal RED_LEAK1. The transmission gate TG14b is turned on when the first test mode signal RED_LEAK1 is at the H level, and connects the determination node ND1 and the bit line BLC [0] when the gate is turned on.

  The other bit line / determination node switch circuits 14b to 14d have the same configuration and operation as the bit line / determination node switch circuit 14a.

  Bit line load circuits 23a to 23d are provided corresponding to each column of memory cells, and inverter IV23 is provided corresponding to each block.

The inverter IV23 inverts the control signal CRED_W_N [K].
Bit line load circuit 23a includes a NAND gate NA13, a P channel MOS transistor P13a, a P channel MOS transistor P13b, and a P channel MOS transistor P13c.

  The NAND gate NA13 receives an inverted signal of the control signal CRED_W_N [K] and a column selection signal Y_N [0]. The NAND gate NA13 outputs an L level signal only when the control signal CRED_W_N [K] is at an L level and the column selection signal Y_N [0] is at an H level, and otherwise outputs an H level signal.

  P-channel MOS transistor P13a conducts when the output of NAND gate NA13 is at L level, connects bit line BL [0] and power supply node PV2 when conducting, and charges bit line BL [0] with power supply voltage VDD. To do. P-channel MOS transistor P13b conducts when the output of NAND gate NA13 is at L level, connects bit line BLC [0] and power supply node PV2 when conducting, and charges bit line BLC [0] with power supply voltage VDD. To do. P-channel MOS transistor P13c conducts when the output of NAND gate NA13 is at L level, and electrically shorts bit lines BL [0] and BLC [0] when conducting.

  The other bit line load circuits 23b to 23d have the same configuration and operation as the bit line load circuit 23a.

  By the way, in the circuit described in Patent Document 2 (for example, the circuit of FIG. 24), a switch gate circuit is inserted between the bit line load circuit and the power source, and the MOS transistor of the bit line load circuit and the MOS of the switch gate circuit Transistors are connected in series, and the charging of the bit line is controlled by the two-stage MOS transistor. Since the bit line is connected to these two-stage MOS transistors, the size of the MOS transistors of the bit line load circuit and the switch gate circuit has to be increased in order to charge the bit line.

  On the other hand, in the embodiment of the present invention, the charging of the bit line is controlled by the control signal CRED_W_N [K] generated by the switch gate circuit 75. Since the bit line is only connected to the one-stage MOS transistor in the bit line load circuits 23a to 23d, the bit line load circuits 23a to 23d and the MOS transistor P15 of the switch gate circuit 75 in order to charge the bit line, There is no need to increase the sizes of P13a, P13b, and P13c.

(Operation)
Hereinafter, a test method for a semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS. 9 and 10 used for explaining the operation of the second embodiment.

  Here, how the circuit related to the regular Kth block operates during the test will be described, but related circuits also operate in the same manner for other blocks.

  First, in step S1, a standby state before entering the test operation mode is set. The test control circuit 10 sets the first test mode signal RED_LEAK1 to L level, sets the second test mode signal RED_LEAK2 to L level, and sets the third test mode signal RED_LEAK3 to H level. In this standby state, the fuse program has not yet been performed, and the normal Kth block defect identification signal CRED_N [K] is at the L level. Further, the column selection signals Y_N [0] to Y_N [3] are at the H level.

  By setting the third test mode signal RED_LEAK3 to the H level, the latch gate RG17 of the latch circuit 17 is initialized, and the voltage of the node ND2 is set to the power supply voltage level VDD.

  In the bit line / determination node switch circuits 14a to 14d, since the first test mode signal RED_LEAK1 is at the L level, the transmission gate TG14a and the transmission gate TG14b are turned off, and the determination node ND1 and the bit line BL [ 0], BLC [0] to BL [3], BLC [3] are separated.

  Further, the power supply voltage VDD is set to a voltage level higher than the voltage level VDDn used during normal operation. This is done by adjusting the power supply voltage level applied to the power supply terminal under the control of an external tester. As a result, the standby current failure / normal operation state of the memory cell MC becomes apparent.

  In the switch gate circuit 75, since the defect identification signal CRED_N [K] is at the L level, the first test mode signal RED_LEAK1 is at the L level, and the output of the latch gate RG17 is at the L level, the control signal CRED_W_N [ K] becomes L level, P-channel MOS transistor P15 becomes conductive, and power supply node PV1 and determination node ND1 are connected. As a result, the power supply voltage VDD is supplied from the power supply node PV1 to the four memory cell power supply lines arvdd [0] to arvdd [3] via the determination node ND1. P channel MOS transistor P15 has a current supply capability that is large enough to supply a sufficiently stable operating power supply voltage to memory cells connected to memory cell power supply lines arvdd [0] to arvdd [3] ( Channel width to channel length).

  In this state, in memory cell MC, power supply voltage VDD applied via memory cell power supply lines arvdd [0] to arvdd [3] is higher than voltage level VDDn applied during normal operation. When there is a resistance component due to a foreign substance or the like, the on-resistance of the MOS transistor in the memory cell MC is made sufficiently small, and the influence of the resistance component due to the foreign substance or the like becomes obvious. Thereby, the memory cell MC that may cause the standby current failure is surely set to the standby current failure state.

  In the bit line load circuits 23a to 23d, since the control signal CRED_W_N [K] is L level and the column selection signals Y_N [0] to Y_N [3] are H level, P channel MOS transistors P13a, P13b, P13c Becomes conductive, and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are charged with the power supply voltage VDD transmitted from the power supply node PV2.

  Next, in step S2, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the H level and sets the third test mode signal RED_LEAK3 to the L level for the time Ta. The test control circuit 10 maintains the second test mode signal RED_LEAK2 at the L level.

  By setting first test mode signal RED_LEAK1 to H level, control signal CRED_W_N [K] is set to H level in switch gate circuit 75, P channel MOS transistor P15 is turned off, and power supply node PV1 is connected to power supply node PV1. The decision node ND1 is separated. As a result, the four memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV1. During the period Ta in which the memory cell power supply lines arvdd [0] to arvdd [3] are disconnected from the power supply node PV1, a large voltage drop does not occur in the standby leakage current allowed by the normal specification value, and abnormal in standby. The period is set such that a large voltage drop occurs in the memory cell power supply lines arvdd [0] to arvdd [3] only with current.

  Further, when the control signal CRED_W_N [K] is set to the H level, in the bit line load circuit 23a, the P channel MOS transistors P13a, P13b, P13c are turned off, and the bit line pair BL [0], BLC [ 0] to BL [3] and BLC [3] are separated from the power supply node PV2.

  Further, by setting the first test mode signal RED_LEAK1 to the H level, in the bit line / determination node switch circuits 14a to 14d, the transmission gate TG14a and the transmission gate TG14b become conductive, and the determination node ND1 and the bit line BL [0], BLC [0] to BL [3], BLC [3] are connected.

  Thus, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are in a floating state and connected to the determination node ND1. Is done.

  When there is a short circuit failure related to the memory cell power supply lines arvdd [0] to arvdd [3], a standby abnormal current flows through the memory cell power supply lines arvdd [0] to arvdd [3]. In addition, when there is a short circuit failure related to the bit lines BL [0], BLC [0] to BL [3], BLC [3], the bit lines BL [0], BLC [0] to BL [3], A standby abnormal current flows through BLC [3]. When the standby abnormal current as described above flows, the potential of the determination node ND1 drops. On the other hand, when there is no short circuit failure as described above, the memory cell power supply lines arvdd [0] to arvdd [3] and bit lines BL [0], BLC [0] to BL [3], BLC [3] The voltage level substantially maintains the charge voltage level (VDD), and the potential of the determination node ND1 does not drop.

In the latch circuit 17, the third test mode signal RED_LEAK3 becomes L level, thereby enabling the latch gate RG17. However, since the second test mode signal RED_LEAK2 is at L level, the N-channel MOS transistor N17 is non-conductive, and the potential of the determination node ND1 is not input to the latch circuit 17.

  Next, in step S3, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the H level for the time Tb. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the H level, the potential drop detection holding circuit 16 is enabled, the voltage level of the determination node ND1 is detected, and the voltage level of the determination node ND1 is set according to the detection result. .

  Standby abnormal current is present in any of memory cell power supply lines arvdd [0] to arvdd [3] and / or any of bit lines BL [0], BLC [0] to BL [3], BLC [3] When the voltage level of determination node ND1 falls below the threshold value, N-channel NOS transistor N16 becomes conductive, and the voltage level of determination node ND1 is driven to the ground voltage level.

  On the other hand, when the standby abnormal current does not flow in any of the memory cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3]. N channel NOS transistor N16 is non-conductive, and determination node ND1 is not driven to the ground level.

  During the time Tb, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit line pairs BL [0], BLC [0] to BL [3], BLC [3] in the standby current failure state are reliably grounded. This is the time required to drive to the level.

  At this time, in the latch circuit 17, the N-channel MOS transistor N17 is turned on in accordance with the second test mode signal RED_LEAK2, and the voltage level of the determination node ND1 is latched by the latch gate RG17.

  Next, in step S4, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the L level for the time Tc. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the L level, the potential drop detection holding circuit 16 is deactivated, and in the latch circuit 17, the N channel MOS transistor N17 is turned off. The time Tc is provided to ensure the hold time of the latch circuit 17.

  Next, in step S5, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the L level. In the test control circuit 10, the second test mode signal RED_LEAK2 maintains the L level, and the third test mode signal RED_LEAK3 maintains the L level.

  By setting the first test mode signal RED_LEAK1 to the L level, in the bit line / determination node switch circuits 14a to 14d, the transmission gate TG14a and the transmission gate TG14b become non-conductive, and the determination node ND1 and the bit line BL [ 0], BLC [0] to BL [3], BLC [3] are separated.

  Further, by setting the first test mode signal RED_LEAK1 to the L level, the switch gate circuit 75 controls the connection between the determination node ND1 and the power supply node PV1 according to the latch information of the latch circuit 17.

  When the ground voltage level is latched in latch circuit 17, control signal CRED_W_N [K] is maintained at the H level, P channel MOS transistor P15 is maintained in the non-conductive state, and power supply node PV1 and determination node ND1 Are kept separated. Further, when control signal CRED_W_N [K] is maintained at the H level, P channel MOS transistors P13a, P13b, and P13c are turned off in bit line load circuits 23a to 23d, and bit line pairs BL [0], The state where BLC [0] to BL [3] and BLC [3] are separated from the power supply node PV2 is maintained.

  On the other hand, when the power supply voltage level VDD is latched in the latch circuit 17, the control signal CRED_W_N [K] is set to the L level, the P-channel MOS transistor P15 becomes conductive, and the power supply node PV1 and the determination node ND1 are connected. Connecting. As a result, the power supply voltage VDD is supplied from the power supply node PV1 to the four memory cell power supply lines arvdd [0] to arvdd [3] via the determination node ND1. Further, the control signal CRED_W_N [K] is set to L level, so that the column selection signals Y_N [0] to Y_N [3] are set to H level (non-selected) in the bit line load circuits 23a to 23d. At times, P channel MOS transistors P13a, P13b, P13c are rendered conductive, and bit line pairs BL [0], BLC [0] to BL [3], BLC [3] are supplied with power supply voltage VDD transmitted from power supply node PV2. Charged.

  Next, in step S6 and step S7, data writing and reading are executed using various data patterns. The selected column i to be written or read is designated by activating the column selection signal Y_N [i] to L level.

  When there is a standby current failure in the regular Kth block, the power supply voltage VDD is not supplied from the power supply node PV1 to the memory cell power supply lines arvdd [0] to arvdd [3], and therefore the bit line BL [ 0], BLC [0] to BL [3], BLC [3], no accurate data is stored in the memory cell MC. Therefore, the data written in the memory cell MC and the data read from the memory cell MC do not match, and it is determined that the normal Kth block is defective.

  On the other hand, when there is no standby current failure in the regular Kth block, the power supply voltage VDD is supplied from the power supply node PV1 to the memory cell power supply lines arvdd [0] to arvdd [3], and the bit line BL [0 ], Accurate data is stored in memory cells MC connected to BLC [0] to BL [3], BLC [3]. Therefore, the data written in the memory cell MC matches the data read from the memory cell MC, and it is determined that the normal Kth block is normal.

  In step S8, the address of the defective block is programmed and the program circuit 55 is blown. When it is determined that the regular Kth block is abnormal, the defect identification signal CRED_N [K] is set to the H level by the program circuit 55 and the redundancy control circuit 56.

  When the defect identification signal CRED_N [K] is set to the H level, the switch gate circuit 75 fixedly separates the memory cell power supply lines arvdd [0] to arvdd [3] from the power supply node PV1, and the bit line load In the circuits 23a to 23d, the bit line pairs BL [0], BLC [0] to BL [3], and BLC [3] are fixedly separated from the power supply node PV2. Accordingly, in the normal operation mode, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit line pairs BL [0], BLC [0] to BL [3], BLC [3] are in a floating state. An abnormal standby leak current is prevented from flowing in the regular Kth block.

  Similarly to the first embodiment, the data line shift circuit 58 uses the external I / O line based on the shift control signal SHIFT [X] (X = 0 to 127) set by the redundancy control circuit 56. The connection between the EIOX and the internal I / O lines NIOX, SIO0, SIO1 is switched to repair the defective normal Kth block.

  As described above, according to the semiconductor memory device of the third embodiment, when testing, a voltage drop is detected by disconnecting a bit line as well as a memory cell power supply line from the power supply node, and a case where a voltage drop occurs is dealt with. The memory cell power supply line is driven to the ground potential level, and the memory cells in the corresponding column are set to the operation failure state. Therefore, not only a short circuit of the memory cell power supply line but also a memory cell having a standby current failure / normal operation due to a short circuit of the bit line pair is surely set to an operation defective state, and a memory cell having an abnormal standby current is detected. The standby current abnormality can be detected and repaired by replacing the redundant memory cell.

  In the semiconductor memory device of the third embodiment, the node for detecting the leak of the memory cell power supply line and the node for detecting the leak of the bit line pair are shared, and the potential drop detection holding circuit is used for the bit line pair. Since the memory cell power supply line is shared, the number of circuits can be reduced as compared with the circuit described in Patent Document 2 (for example, the circuit of FIG. 24) in which these are not shared.

[Fourth Embodiment]
(Constitution)
FIG. 13 is a diagram showing the configuration of the semiconductor memory device according to the fourth embodiment of the present invention.

  Referring to FIG. 13, in this semiconductor memory device, a write assist power supply circuit 18 and a memory cell power supply line / determination node switch circuit 24 are added to the semiconductor memory device of the second embodiment shown in FIG. Yes. Further, the switch gate circuit 75 of the semiconductor memory device of the fourth embodiment is different from the switch gate circuit 15 included in the semiconductor memory device of the second embodiment shown in FIG.

The switch gate circuit 75 is the same as that described in the third embodiment.
Write assist power supply circuit 18 lowers the voltage level of memory cell power supply line arvdd arranged corresponding to the memory cell in the selected column during data writing.

  The memory cell power supply line / determination node switch circuit 24 switches connection and separation of the memory cell power supply line arvdd to the determination node ND1. The memory cell power supply line / determination node switch circuit 24 becomes conductive when in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level), and connects the memory cell power supply line arvdd to the determination node ND1. As a result, the potential drop detection holding circuit 16 detects the potential, and the determination node ND1 to be set is connected to the memory cell power supply line arvdd. Therefore, the standby abnormal current flowing through the memory cell power supply line arvdd can be detected.

  The memory cell power supply line / determination node switch circuit 24 is connected to the memory cell power supply line / determination node switch circuit 24 at a time other than in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level). The memory cell power supply line arvdd is turned off when data is read from and written to the memory cell connected to the memory cell power supply line arvdd, and the memory cell power supply line arvdd is separated from the determination node ND1. As a result, at the time of data reading and writing, the memory cell power supply line arvdd is disconnected from the determination node ND1, and the memory cell power supply line arvdd of the selected column is separated from the memory cell power supply line arvdd of the non-selected column and the power supply node PV1. Data can be read and written normally.

  FIG. 14 is a diagram showing the configuration of the main part of the semiconductor memory device of FIG. 13 for one block (for four columns). In FIG. 14, differences from the main part of the semiconductor memory device according to the second embodiment shown in FIG. 7 will be described.

  Referring to FIG. 14, a switch gate circuit 75 is provided corresponding to each block of memory cells. The switch gate circuit 75 is basically the same as the switch gate circuit 15 of the second embodiment, but the output of the inverter IV15 is not only output to the P-channel MOS transistor P15 but also the control signal CRED_W_N [K ] Is output to the bit line load circuits 23a to 23d via the inverter IV23. Control signal CRED_W_N [K] is set to L level when P channel MOS transistor P15 is turned on, that is, when power supply node PV1 and determination node ND1 are connected, and P channel MOS transistor P15 is turned off. When the power supply node PV1 and the determination node ND1 are separated, the H level is set.

  Memory cell power line / determination node switch circuits 24a-24d are provided corresponding to each column of memory cells, and inverter IV24 is provided corresponding to each block.

The inverter IV24 inverts the first test mode signal RED_LEAK1.
Memory cell power supply line / determination node switch circuit 24a includes a transmission gate TG24a.

Transmission gate TG 24 a includes a first test mode signal RED_LEAK1, gate controlled by the inverted signal of the first test mode signal RED_LEAK1. Transmission gate TG 24 a, the first test mode signal RED_LEAK1 gate when H level is turned on, the gate is connected to the determination node ND1 and the memory cell power supply line arvdd [0] when on.

  Other memory cell power supply line / determination node switch circuits 24b to 24d have the same configuration and operation as memory cell power supply line / determination node switch circuit 24a.

  A down power supply line downvdd is arranged corresponding to each block. Each of the memory cell power supply lines arvdd [0] to arvdd [3] has a parasitic capacitance C0 due to its wiring capacitance, and the down power supply line downvdd has a parasitic capacitance CP1 due to its wiring capacitance.

  An inverter IV23 is provided corresponding to each block. The inverter IV23 inverts the control signal CRED_W_N [K]. Write assist power supply circuits 18a to 18d are provided corresponding to the respective columns of memory cells.

  Write assist power supply circuit 18a includes a NOR gate NR18, a NAND gate NA18, an inverter IV18, a P-channel MOS transistor P18, and an N-channel MOS transistor N18.

  The NOR gate NR18 receives the write control signal WE_N and the column selection signal Y_N [0]. The NOR gate NR18 outputs an H level signal only when the write control signal WE_N is at L level and the column selection signal Y_N [0] is at L level, and outputs an L level signal otherwise. N channel MOS transistor N18 conducts when the output signal of NOR gate NR18 is at H level, and couples memory cell power supply line arvdd [0] to down power supply line downvdd.

  Inverter IV18 inverts the output signal of NOR gate NR18. NAND gate NA18 receives an inverted signal of control signal CRED_W_N [K] output from inverter IV23 and an inverted signal of the output signal of NOR gate NR18 output from inverter IV18. The NAND gate NR18 outputs an L level signal only when the control signal CRED_W_N [K] is at the L level and at least one of the write control signal WE_N and the column selection signal Y_N [0] is at the H level. An H level signal is output. P-channel MOS transistor P18 conducts when the output signal of NAND gate NA18 is at L level, and connects memory cell power supply line arvdd [0] to power supply node PC3.

  An N channel MOS transistor NQ18 is provided corresponding to each block. N-channel MOS transistor NQ18 connects down power supply line downvdd to the ground power supply when write control signal WE_N is at the H level.

  In the standby state and data reading, write control signal WE_N is set to the H level. Accordingly, in channel assist power supply circuit 18a, N channel MOS transistor N18 is turned off, and memory cell power supply line arvdd [0] is not connected to down power supply line downvdd. Further, when there is no abnormality in the regular Kth block, the control signal CRED_W_N [K] becomes L level, so that the P-channel MOS transistor P18 becomes conductive, and the memory cell power supply line arvdd [0] is connected to the power supply node PV3. Then, the power supply voltage VDD is supplied to the memory cell power supply line arvdd [0]. On the other hand, when there is an abnormality in the regular Kth block, the control signal CRED_W_N [K] becomes H level, so that the P-channel MOS transistor P18 becomes non-conductive and the memory cell power supply line arvdd [0] is connected to the power supply node PV3. Do not connect.

  At the time of data writing, write control signal WE_N is set to L level. In response, the down power supply line downvdd is in a floating state at the ground voltage level.

  Further, when there is no abnormality in the regular Kth block, the control signal CRED_W_N [K] becomes L level. In this state, when writing to the 0th column, the column selection signal Y_N [0] becomes L level. In such a case, the write control signal WE_N is set to the L level, the control signal CRED_W_N [K] is set to the L level, and the column selection signal Y_N [0] is set to the L level. P channel MOS transistor P18 is turned off, and N channel MOS transistor N18 is turned on. Therefore, the memory cell power supply line arvdd [0] is separated from the power supply node PV3 and is electrically connected to the down power supply line downvdd in the floating state. On the other hand, when writing is not performed on the 0th column, the column selection signal Y_N [0] becomes H level. In such a case, the write control signal WE_N is set to the L level, the control signal CRED_W_N [K] is set to the L level, and the column selection signal Y_N [0] is set to the H level. P channel MOS transistor P18 is turned on, and N channel MOS transistor N18 is turned off. Accordingly, the memory cell power supply line arvdd [0] is connected to the power supply node PV3 and is not connected to the down power supply line downvdd in the floating state.

When there is an abnormality in the regular Kth block, the control signal CRED_W_N [K] becomes H level. In this state, when writing to the 0th column, the column selection signal Y_N [0] becomes L level. In such a case, the write control signal WE_N is set to the L level, the control signal CRED_W_N [K] is set to the H level, and the column selection signal Y_N [0] is set to the L level. P channel MOS transistor P18 is turned off, and N channel MOS transistor N18 is turned on. Therefore, the memory cell power supply line arvdd [0] is separated from the power supply node PV3 and is electrically connected to the down power supply line downvdd in the floating state. On the other hand, when writing is not performed on the 0th column, the column selection signal Y_N [0] becomes H level. In such a case, the write control signal WE_N is set to the L level, the control signal CRED_W_N [K] is set to the H level, and the column selection signal Y_N [0] is set to the H level. P channel MOS transistor P18 is turned off, and N channel MOS transistor N18 is turned off. Therefore, the memory cell power supply line arvdd [0] is not connected to the power supply node PV3 and is not connected to the down power supply line downvdd in the floating state.

  When writing to the 0th column, the charge accumulated in the parasitic capacitance CP0 of the memory cell power supply line arvdd [0] at the time of non-writing is distributed to the parasitic capacitance CP1 of the down power supply line downvdd. The voltage level of the memory cell power supply line arvdd [0] decreases in proportion to the capacitance ratio of the capacitors CP0 and CP1. As a result, the latching capability of the memory cell MC is reduced, a write margin is secured, and data writing is performed stably and at high speed.

  FIG. 15 is a signal waveform diagram showing operations during reading and writing of the semiconductor memory device according to the fourth embodiment of the present invention.

  Referring to FIG. 15, a state where the voltage levels of memory cell power supply line arvdd and down power supply line downvdd are maintained at different voltage levels at the time of writing is shown. This is because a voltage distribution due to the on-resistance of the switching MOS transistor N18 occurs. The parasitic capacitance CP0 of the memory cell power supply line arvdd is sufficiently larger than the parasitic capacitance CP1 of the down power supply line downvdd. Even if the voltage levels of the memory cell power supply line arvdd and the down power supply line downvdd are the same voltage level, the memory cell The amount of potential drop in the power supply line is sufficiently small, and the data held in the non-selected memory cell is not destroyed.

  When the on-resistance of the switching MOS transistor N18 is made relatively large so that the voltage levels of the memory cell power supply line and the down power supply line are intentionally different, the decrease in the voltage level of the memory cell power supply line is surely suppressed. It is possible to suppress the occurrence of a state in which the static data margin of the non-selected memory cell is lowered and the retained data is inverted.

  The drop voltage level of the memory cell power supply line arvdd can compensate for a decrease in write margin due to a decrease in driving capability of the access transistor due to a decrease in voltage level of the selected word line WL, and a static noise margin of unselected memory cells can be reduced. Any voltage level that is sufficiently maintained may be used.

  The power supply voltage of the memory cell power supply line arvdd is connected to the high-side power supply node NOD3 of the memory cell. Therefore, the current drivability of load MOS transistors PQ1 and PQ2 is reduced (since the source voltage is lowered, the gate-gate voltage of the load transistor receiving L data at the gate is reduced). Access transistor ATr (NQ3, NQ4) has the same current driving capability as that at the time of data reading and does not change. Therefore, the write margin of the memory cell in the selected column is increased, and the storage node storing H data is discharged to L level at high speed according to the write data. Thereby, data can be written to the selected memory cell at high speed according to the data transmitted to bit lines BL and BLC.

  When data writing is completed, bit lines BL and BLC are restored to power supply voltage level VDD by bit line load circuits 13a to 13d, and word line WL is driven to a non-selected state. Thereafter, write control signal WE_N is also deselected, N channel MOS transistor N18 is non-conductive, and P channel MOS transistor P18 is conductive. In response, down power supply line downvdd is again driven to the ground voltage level, while memory cell power supply line arvdd returns to power supply voltage level VDD.

  Further, only the movement of charges using the parasitic capacitance of the down power supply line downvdd and the memory cell power supply line arvdd, the voltage of the memory cell power supply line arvdd is set at the time of writing and reading using another power supply line. There is no need to switch, and the configuration of the power supply circuit is simplified. Further, it is merely the movement of charges between the capacitive elements, and during this write cycle, a path through which a through current flows between the memory cell power supply line arvdd and the ground node does not occur, and power consumption is reduced.

  The voltage level during writing of the memory cell power supply line arvdd can be adjusted by setting the capacitance ratio of the parasitic capacitance CP0 of the memory cell power supply line arvdd to the parasitic capacitance CP1 of the down power supply line downvdd to an appropriate value.

  By using the write assist power supply circuit as described above, the voltage level of the memory cell power supply line arvdd provided in each column is electrically coupled to the down power supply line downvdd, and the voltage level is changed between the parasitic capacitances. Therefore, even when the voltage level of the selected word line WL is lowered, the high-side power supply voltage level of the selected memory cell is lowered at a high speed during data writing. The margin can be enlarged. Thus, a semiconductor memory device capable of stably writing and reading data at high speed even under a low power supply voltage can be realized.

(Operation)
Hereinafter, a test method for a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 9 and 10 used in describing the operation of the second embodiment.

  Here, how the circuit related to the regular Kth block operates during the test will be described, but related circuits also operate in the same manner for other blocks.

  First, in step S1, a standby state before entering the test operation mode is set. The test control circuit 10 sets the first test mode signal RED_LEAK1 to L level, sets the second test mode signal RED_LEAK2 to L level, and sets the third test mode signal RED_LEAK3 to H level. In this standby state, the fuse program has not yet been performed, and the normal Kth block defect identification signal CRED_N [K] is at the L level. Further, the column selection signals Y_N [0] to Y_N [3] are at the H level. Further, the main control circuit 52 sets the write control signal WE_N to the H level.

  By setting the third test mode signal RED_LEAK3 to the H level, the latch gate RG17 of the latch circuit 17 is initialized, and the voltage of the node ND2 is set to the power supply voltage level VDD.

  In the memory cell power supply line / determination node switch circuits 24a to 24d, since the first test mode signal RED_LEAK1 is at the L level, the transmission gate TG24a is turned off, and the determination node ND1 and the memory cell power supply line arvdd [ 0] to arvdd [3] are separated.

  Further, the power supply voltage VDD is set to a voltage level higher than the voltage level VDDn used during normal operation. This is done by adjusting the power supply voltage level applied to the power supply terminal under the control of an external tester. As a result, the standby current failure / normal operation state of the memory cell MC becomes apparent.

  In the switch gate circuit 75, since the defect identification signal CRED_N [K] is at the L level, the first test mode signal RED_LEAK1 is at the L level, and the output of the latch gate RG17 is at the L level, the control signal CRED_W_N [K ] Becomes L level, P-channel MOS transistor P15 becomes conductive, and power supply node PV1 and determination node ND1 are connected.

  In write assist power supply circuits 18a-18d, since control signal CRED_W_N [K] is at L level and write control signal WE_N is at H level, P channel MOS transistor P18 becomes conductive, and N channel MOS transistor N18. Becomes non-conductive. As a result, the memory cell power supply lines arvdd [0] to arvdd [3] are charged with the power supply voltage VDD transmitted from the power supply node PV3.

  In this state, in memory cell MC, power supply voltage VDD applied via memory cell power supply lines arvdd [0] to arvdd [3] is higher than voltage level VDDn applied during normal operation. When there is a resistance component due to a foreign substance or the like, the on-resistance of the MOS transistor in the memory cell MC is made sufficiently small, and the influence of the resistance component due to the foreign substance or the like becomes obvious. Thereby, the memory cell MC that may cause the standby current failure is surely set to the standby current failure state.

  In the bit line load circuits 13a to 13d, since the column selection signals Y_N [0] to Y_N [3] are at the H level, the P channel MOS transistors P13a, P13b, and P13c are turned on, and the bit line BL [0] is turned on. , BLC [0] to BL [3], BLC [3] are charged with the power supply voltage VDD transmitted from the power supply node PV2.

  Next, in step S2, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the H level and sets the third test mode signal RED_LEAK3 to the L level for the time Ta. The test control circuit 10 maintains the second test mode signal RED_LEAK2 at the L level.

  Further, by setting the first test mode signal RED_LEAK1 to the H level, the control signal CRED_W_N [K] is set to the H level in the switch gate circuit 75, the P-channel MOS transistor P15 is turned off, and the power supply node PV1 and decision node ND1 are separated.

  In write assist power supply circuits 18a-18d, since control signal CRED_W_N [K] is at H level and write control signal WE_N is at H level, P channel MOS transistor P18 is turned off. As a result, the memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV3. During the period Ta in which the memory cell power supply lines arvdd [0] to arvdd [3] are disconnected from the power supply node PV3, a large voltage drop does not occur in the standby leakage current allowed by the normal specification value, and abnormal in standby The period is set such that a large voltage drop occurs in the memory cell power supply lines arvdd [0] to arvdd [3] only with current.

  In the memory cell power supply line / determination node switch circuits 24a to 24d, since the first test mode signal RED_LEAK1 is at the H level, the transmission gate TG24a becomes conductive, and the determination node ND1 and the memory cell power supply line arvdd [0 ] To arvdd [3].

  As described above, the memory cell power supply lines arvdd [0] to arvdd [3] are in a floating state and are connected to the determination node ND1.

  When there is a short circuit failure related to the memory cell power supply lines arvdd [0] to arvdd [3], a standby abnormal current flows through the memory cell power supply lines arvdd [0] to arvdd [3]. When the standby abnormal current as described above flows, the potential of the determination node ND1 drops. On the other hand, when there is no short circuit failure as described above, the voltage levels of the memory cell power supply lines arvdd [0] to arvdd [3] are substantially maintained at the charge voltage level (VDD), and the potential of the determination node ND1 is Do not descend.

  In the latch circuit 17, the latch gate RG17 is enabled when the third test mode signal RED_LEAK3 becomes H level. However, since the second test mode signal RED_LEAK2 is at L level, the N-channel MOS transistor N17 is non-conductive, and the potential of the determination node ND1 is not input to the latch circuit 17.

  Next, in step S3, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the H level for the time Tb. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the H level, the potential drop detection holding circuit 16 is enabled, the voltage level of the determination node ND1 is detected, and the voltage level of the determination node ND1 is set according to the detection result. .

  When the standby abnormal current flows through any of the memory cell power supply lines arvdd [0] to arvdd [3] and the voltage level of the determination node ND1 falls below the threshold value, the N-channel NOS transistor N16 becomes conductive, The voltage level of decision node ND1 is driven to the ground voltage level.

  On the other hand, when the standby abnormal current does not flow through any of memory cell power supply lines arvdd [0] to arvdd [3], N-channel NOS transistor N16 is non-conductive, and determination node ND1 is driven to the ground level. Not done.

  The time Tb is a time required for reliably driving the memory cell power supply lines arvdd [0] to arvdd [3] in the standby current defective state to the ground voltage level.

  At this time, in the latch circuit 17, the N-channel MOS transistor N17 is turned on in accordance with the second test mode signal RED_LEAK2, and the voltage level of the determination node ND1 is latched by the latch gate RG17.

  Next, in step S4, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the L level for the time Tc. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the L level, the potential drop detection holding circuit 16 is deactivated, and in the latch circuit 17, the N channel MOS transistor N17 is turned off. The time Tc is provided to ensure the hold time of the latch circuit 17.

  Next, in step S5, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the L level. In the test control circuit 10, the second test mode signal RED_LEAK2 maintains the L level, and the third test mode signal RED_LEAK3 maintains the L level.

  In the memory cell power supply line / determination node switch circuits 24a to 24d, since the first test mode signal RED_LEAK1 is at L level, the transmission gate TG24a becomes non-conductive, and the determination node ND1 and the memory cell power supply line arvdd [0] ~ Arvdd [3] are separated.

  By setting the first test mode signal RED_LEAK1 to the L level, the switch gate circuit 15 controls the connection between the determination node ND1 and the power supply node PV1 according to the latch information of the latch circuit 17.

  When the ground voltage level is latched in latch circuit 17, control signal CRED_W_N [K] is maintained at the H level, P channel MOS transistor P15 is maintained in the non-conductive state, and power supply node PV1 and determination node ND1 Are kept separated.

  In write assist power supply circuits 18a to 18d, since control signal CRED_W_N [K] is at the H level, P channel MOS transistor P18 maintains a non-conductive state. Thus, the state where the memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV3 is maintained.

  On the other hand, when power supply voltage level VDD is latched in latch circuit 17, control signal CRED_W_N [K] is set to L level, P channel MOS transistor P15 is turned on, and power supply node PV1 and determination node ND1 are connected. Connecting.

  In write assist power supply circuits 18a-18d, since control signal CRED_W_N [K] is at L level, when at least one of write control signal WE_N and column selection signal Y_N [i] is set at H level. P channel MOS transistor P18 becomes conductive. Thus, at the time of non-writing, memory cell power supply lines arvdd [0] to arvdd [3] are charged with power supply voltage VDD transmitted from power supply node PV3. At the time of writing, memory cell power supply lines arvdd [j] (j ≠ i) in columns other than selected column i are charged with power supply voltage VDD transmitted from power supply node PV3.

  Next, in step S6 and step S7, data writing and reading are executed using various data patterns. When writing is performed, write control signal WE_N is set to L level, and selected column i to be written or read is designated by activating column selection signal Y_N [i] to L level.

  When there is a standby current failure in the regular Kth block, the ground voltage is latched in the latch circuit 17, so that the power supply to the memory cell power supply lines arvdd [0] to arvdd [3] is as described above. The power supply voltage VDD is not supplied from the node PV3, and sufficient charges are not accumulated. Therefore, when the selected column i is written, even when the memory cell power line arvdd [i] of the selected column i is connected to the down power line downvdd, the voltage level of the memory cell power line arvdd [i] is necessary for writing The minimum voltage level is not exceeded. That is, the voltage level is lower than the voltage level that is decreased to increase the write margin. Therefore, accurate data is not stored in the memory cell MC connected to the memory cell power supply line arvdd [i], and the data written to the memory cell MC and the data read from the memory cell MC do not match. The regular Kth block including the selected column i is determined to be defective.

  On the other hand, when there is no standby current failure in the regular Kth block, the power supply voltage VDD level is latched in the latch circuit 17, so that the memory cell power supply lines arvdd [0] to arvdd [3] are connected to the power supply node PV3. It is charged with the power supply voltage VDD transmitted from. When the selected column i is written, when the memory cell power supply line arvdd [i] of the selected column i is connected to the down power supply line downvdd, the voltage level of the memory cell power supply line arvdd [i] decreases, and the write operation is performed. The margin is increased, and data can be stored at high speed and accurately in the memory cell MC connected to the memory cell power supply line arvdd [i]. Therefore, the data written in the memory cell MC matches the data read from the memory cell MC, and it is determined that the normal Kth block is normal.

  In step S8, the address of the defective block is programmed and the program circuit 55 is blown. When it is determined that the regular Kth block is abnormal, the defect identification signal CRED_N [K] is set to the H level by the program circuit 55 and the redundancy control circuit 56.

  By setting defect identification signal CRED_N [K] to the H level, memory cell power supply lines arvdd [0] to arvdd [3] are fixedly separated from power supply node PV1 and power supply node PV3. Thereby, in the normal operation mode, the memory cell power supply lines arvdd [0] to arvdd [3] are in a floating state, and an abnormal standby leak current is prevented from flowing in the Kth block.

  Similarly to the first embodiment, the data line shift circuit 58 uses the external I / O line based on the shift control signal SHIFT [X] (X = 0 to 127) set by the redundancy control circuit 56. The connection between the EIOX and the internal I / O lines NIOX, SIO0, SIO1 is switched to repair the defective regular Kth block.

  As described above, according to the semiconductor memory device of the fourth embodiment, the write power supply circuit is used to electrically couple the cell power supply line of the selected column to the down power supply line at the time of data writing. Although the driving power of the load transistor of the memory cell is reduced by lowering the level, the driving power of the access transistor is the same as that at the time of reading and does not change. Therefore, the writing margin can be increased without impairing the reading margin. And high speed writing is realized. Further, the memory cell power supply line and the down power supply line are electrically connected, and the voltage level of the cell power supply line changes at a high speed due to the movement of charges. Further, the voltage level of the memory cell power supply line is set to an intermediate voltage level by capacity division, and the write margin can be optimized. Further, when there is a short circuit related to the memory cell power supply line and the voltage level of the memory cell power supply line is lowered, the memory cell power supply line is driven to the ground voltage level, and the standby current defective memory cell is It is possible to reliably set the malfunction state. Thereby, the standby current failure / normal operation memory cell can be set to an operation failure state, and this column address can be easily specified. In addition, during normal operation, the standby current failure can be reliably remedied by fixing the memory cell power supply line with the standby current failure fixedly away from the power supply node.

[Fifth Embodiment]
FIG. 16 is a diagram showing the configuration of the semiconductor memory device according to the fifth embodiment of the present invention.

  Referring to FIG. 16, the semiconductor memory device of the fifth embodiment is different from the fourth semiconductor memory device shown in FIG. 13 in the following points. That is, the bit line load circuit 23 of the semiconductor memory device of the fifth embodiment is different from the bit line load circuit 13 included in the semiconductor memory device of the fourth embodiment shown in FIG. Further, the semiconductor memory device of the fifth embodiment has a bit line and a memory cell power line instead of the memory cell power line / determination node switch circuit 24 included in the semiconductor memory device of the fourth embodiment shown in FIG. / Judgment node switch circuit 34 is included.

The bit line load circuit 23 is the same as that described in the third embodiment.
Bit line and memory cell power supply line / determination node switch circuit 34 switches connection and separation to bit line pair BL, BLC and memory cell power supply line arvdd determination node ND1. The bit line and memory cell power supply line / determination node switch circuit 34 becomes conductive when in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level), and the bit lines BL and BLC and the memory cell power supply line arvdd. Is connected to the decision node ND1. As a result, the potential drop detection holding circuit 16 detects the potential, and the determination node ND1 to be set is connected to the memory cell power supply line arvdd and the bit line pair BL, BLC. The current and the standby abnormal current flowing through the bit line pair BL and BLC can be detected.

  Further, the bit line and memory cell power supply line / decision node switch circuit 34 is not in the specific operation mode (when the first test mode signal RED_LEAK1 is at the H level), that is, at least the bit line and memory cell power supply line / The bit line pair BL, BLC connected to the determination node switch circuit 34 and the memory cell power supply line arvdd are turned off when data is read from and written to the memory cell, and the bit lines BL, BLC and the memory cell power supply line arvdd are turned off. And the determination node ND1 are separated. Thereby, at the time of data reading and writing, the bit line pair BL, BLC and the memory cell power supply line arvdd are disconnected from the determination node ND1, and the bit line BL, BLC of the selected column is disconnected from the bit line pair BL, BLC, The memory cell power supply line arvdd and the power supply node PV1 can be separated from each other, and the memory cell power supply line arvdd in the selected column is separated from the memory cell power supply line arvdd, the bit line pair BL, BLC and the power supply node PV1 in the non-selected column. Data can be read and written normally.

  FIG. 17 is a diagram showing the configuration of the main part of the semiconductor memory device of FIG. 16 for one block (for four columns). In FIG. 17, differences from the main part of the semiconductor memory device according to the fourth embodiment shown in FIG. 14 will be described.

  Referring to FIG. 17, bit lines and memory cell power supply line / determination node switch circuits 34a-34d are provided corresponding to the respective columns of memory cells, and inverter IV13 is provided corresponding to each block.

The inverter IV34 inverts the first test mode signal RED_LEAK1.
Bit line and memory cell power supply line / determination node switching circuit 34a includes a transmission gate TG14a, a transmission gate TG14b, and a transmission gate TG24a.

  The gate of the transmission gate TG14a is controlled by the first test mode signal RED_LEAK1 and the inverted signal of the first test mode signal RED_LEAK1. The transmission gate TG14a is turned on when the first test mode signal RED_LEAK1 is at the H level, and connects the determination node ND1 and the bit line BL [0] when the gate is turned on.

  The gate of the transmission gate TG14b is controlled by the first test mode signal RED_LEAK1 and the inverted signal of the first test mode signal RED_LEAK1. The transmission gate TG14b is turned on when the first test mode signal RED_LEAK1 is at the H level, and connects the determination node ND1 and the bit line BLC [0] when the gate is turned on.

Transmission gate TG 24 a includes a first test mode signal RED_LEAK1, gate controlled by the inverted signal of the first test mode signal RED_LEAK1. Transmission gate TG 24 a, the first test mode signal RED_LEAK1 gate when H level is turned on, the gate is connected to the determination node ND1 and the memory cell power supply line arvdd [0] when on.

  The other bit line and memory cell power supply line / determination node switch circuits 34b to 34d have the same configuration and operation as the bit line and memory cell power supply line / determination node switch circuit 34a.

  Bit line load circuits 23a to 23d are provided corresponding to each column of memory cells, and inverter IV23 is provided corresponding to each block.

The inverter IV23 inverts the control signal CRED_W_N [K].
Bit line load circuit 23a includes a NAND gate NA13, a P channel MOS transistor P13a, a P channel MOS transistor P13b, and a P channel MOS transistor P13c.

  The NAND gate NA13 receives an inverted signal of the control signal CRED_W_N [K] and a column selection signal Y_N [0]. The NAND gate NA13 outputs an L level signal only when the control signal CRED_W_N [K] is at an L level and the column selection signal Y_N [0] is at an H level, and otherwise outputs an H level signal.

  P-channel MOS transistor P13a conducts when the output of NAND gate NA13 is at L level, connects bit line BL [0] and power supply node PV2 when conducting, and charges bit line BL [0] with power supply voltage VDD. To do. P-channel MOS transistor P13b conducts when the output of NAND gate NA13 is at L level, connects bit line BLC [0] and power supply node PV2 when conducting, and charges bit line BLC [0] with power supply voltage VDD. To do. P-channel MOS transistor P13c conducts when the output of NAND gate NA13 is at L level, and electrically shorts bit lines BL [0] and BLC [0] when conducting.

  The other bit line load circuits 23b to 23d have the same configuration and operation as the bit line load circuit 23a.

(Operation)
Hereinafter, a test method for the semiconductor memory device according to the embodiment of the present invention will be described with reference to FIGS. 9 and 10 used for explaining the operation of the second embodiment.

  Here, how the circuit related to the regular Kth block operates during the test will be described, but related circuits also operate in the same manner for other blocks.

  First, in step S1, a standby state before entering the test operation mode is set. The test control circuit 10 sets the first test mode signal RED_LEAK1 to L level, sets the second test mode signal RED_LEAK2 to L level, and sets the third test mode signal RED_LEAK3 to H level. In this standby state, the fuse program has not yet been performed, and the normal Kth block defect identification signal CRED_N [K] is at the L level. Further, the column selection signals Y_N [0] to Y_N [3] are at the H level. Further, the main control circuit 52 sets the write control signal WE_N to the H level.

  By setting the third test mode signal RED_LEAK3 to the H level, the latch gate RG17 of the latch circuit 17 is initialized, and the voltage of the node ND2 is set to the power supply voltage level VDD.

  In the bit line and memory cell power supply line / determination node switch circuits 34a to 34d, since first test mode signal RED_LEAK1 is at L level, transmission gates TG14a, TG14b and TG24a are rendered non-conductive, and decision node ND1 And the memory cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are separated.

  Further, the power supply voltage VDD is set to a voltage level higher than the voltage level VDDn used during normal operation. This is done by adjusting the power supply voltage level applied to the power supply terminal under the control of an external tester. As a result, the standby current failure / normal operation state of the memory cell MC becomes apparent.

  In the switch gate circuit 75, since the defect identification signal CRED_N [K] is at the L level, the first test mode signal RED_LEAK1 is at the L level, and the output of the latch gate RG17 is at the L level, the control signal CRED_W_N [K ] Becomes L level, P-channel MOS transistor P15 becomes conductive, and power supply node PV1 and determination node ND1 are connected.

  In write assist power supply circuits 18a-18d, since control signal CRED_W_N [K] is at L level and write control signal WE_N is at H level, P channel MOS transistor P18 becomes conductive, and N channel MOS transistor N18. Becomes non-conductive. As a result, the memory cell power supply lines arvdd [0] to arvdd [3] are charged with the power supply voltage VDD transmitted from the power supply node PV3.

  In this state, in memory cell MC, power supply voltage VDD applied via memory cell power supply lines arvdd [0] to arvdd [3] is higher than voltage level VDDn applied during normal operation. When there is a resistance component due to a foreign substance or the like, the on-resistance of the MOS transistor in the memory cell MC is made sufficiently small, and the influence of the resistance component due to the foreign substance or the like becomes obvious. Thereby, the memory cell MC that may cause the standby current failure is surely set to the standby current failure state.

  In the bit line load circuits 23a to 23d, since the control signal CRED_W_N [K] is L level and the column selection signals Y_N [0] to Y_N [3] are H level, P channel MOS transistors P13a, P13b, P13c Becomes conductive, and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are charged with the power supply voltage VDD transmitted from the power supply node PV2.

  Next, in step S2, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the H level and sets the third test mode signal RED_LEAK3 to the L level for the time Ta. The test control circuit 10 maintains the second test mode signal RED_LEAK2 at the L level.

  By setting first test mode signal RED_LEAK1 to H level, control signal CRED_W_N [K] is set to H level in switch gate circuit 75, P channel MOS transistor P15 is turned off, and power supply node PV1 is connected to power supply node PV1. The decision node ND1 is separated.

  In write assist control circuits 18a-18d, since control signal CRED_W_N [K] is at H level and write control signal WE_N is at H level, P channel MOS transistor P18 is turned off. As a result, the four memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV3. During the period Ta in which the memory cell power supply lines arvdd [0] to arvdd [3] are disconnected from the power supply node PV3, a large voltage drop does not occur in the standby leakage current allowed by the normal specification value, and abnormal in standby The period is set such that a large voltage drop occurs in the memory cell power supply lines arvdd [0] to arvdd [3] only with current.

  By setting the control signal CRED_W_N [K] to the H level, the P-channel MOS transistors P13a, P13b, and P13c are turned off in the bit line load circuit 23a, and the bit line pair BL [0] and BLC [0]. ... BL [3] and BLC [3] are separated from the power supply node PV2.

  In the bit line and memory cell power supply line / determination node switch circuits 34a to 34d, since the first test mode signal RED_LEAK1 is at the L level, the transmission gates TG14a, TG14b, and TG24a are turned on, and the determination node ND1 Memory cell power supply lines arvdd [0] to arvdd [3] and bit lines BL [0], BLC [0] to BL [3], BLC [3] are connected.

  As described above, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are in a floating state and are set to the determination node ND1. Connected.

  When there is a short circuit failure related to the memory cell power supply lines arvdd [0] to arvdd [3], a standby abnormal current flows through the memory cell power supply lines arvdd [0] to arvdd [3]. In addition, when there is a short circuit failure related to the bit lines BL [0], BLC [0] to BL [3], BLC [3], the bit lines BL [0], BLC [0] to BL [3], A standby abnormal current flows through BLC [3]. When the standby abnormal current as described above flows, the potential of the determination node ND1 drops. On the other hand, when there is no short circuit failure as described above, the memory cell power supply lines arvdd [0] to arvdd [3] and bit lines BL [0], BLC [0] to BL [3], BLC [3] The voltage level substantially maintains the charge voltage level (VDD), and the potential of the determination node ND1 does not drop.

  In the latch circuit 17, the latch gate RG17 is enabled when the third test mode signal RED_LEAK3 becomes H level. However, since the second test mode signal RED_LEAK2 is at L level, the N-channel MOS transistor N17 is non-conductive, and the potential of the determination node ND1 is not input to the latch circuit 17.

  Next, in step S3, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the H level for the time Tb. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the H level, the potential drop detection holding circuit 16 is enabled, the voltage level of the determination node ND1 is detected, and the voltage level of the determination node ND1 is set according to the detection result. .

  Standby abnormal current is present in any of memory cell power supply lines arvdd [0] to arvdd [3] and / or any of bit lines BL [0], BLC [0] to BL [3], BLC [3] When the voltage level of determination node ND1 falls below the threshold value, N-channel NOS transistor N16 becomes conductive, and the voltage level of determination node ND1 is driven to the ground voltage level.

  On the other hand, when the standby abnormal current does not flow in any of the memory cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3]. N channel NOS transistor N16 is non-conductive, and determination node ND1 is not driven to the ground level.

  During the time Tb, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit line pairs BL [0], BLC [0] to BL [3], BLC [3] in the standby current failure state are reliably grounded. This is the time required to drive to the level.

  At this time, in the latch circuit 17, the N-channel MOS transistor N17 is turned on in accordance with the second test mode signal RED_LEAK2, and the voltage level of the determination node ND1 is latched by the latch gate RG17.

  Next, in step S4, the test control circuit 10 sets the second test mode signal RED_LEAK2 to the L level for the time Tc. The test control circuit 10 maintains the first test mode signal RED_LEAK1 at the H level and the third test mode signal RED_LEAK3 at the L level.

  By setting the second test mode signal RED_LEAK2 to the L level, the potential drop detection holding circuit 16 is deactivated, and in the latch circuit 17, the N channel MOS transistor N17 is turned off. The time Tc is provided to ensure the hold time of the latch circuit 17.

  Next, in step S5, the test control circuit 10 sets the first test mode signal RED_LEAK1 to the L level. In the test control circuit 10, the second test mode signal RED_LEAK2 maintains the L level, and the third test mode signal RED_LEAK3 maintains the L level.

  In bit line and memory cell power supply line / determination node switch circuits 34a-34d, since first test mode signal RED_LEAK1 is at L level, transmission gates TG14a, TG14b, and TG24a are rendered non-conductive, and determination node ND1 and memory The cell power supply lines arvdd [0] to arvdd [3] and the bit lines BL [0], BLC [0] to BL [3], BLC [3] are separated.

  By setting the first test mode signal RED_LEAK1 to the L level, the switch gate circuit 75 controls the connection between the determination node ND1 and the power supply node PV1 according to the latch information of the latch circuit 17.

  When the ground voltage level is latched in latch circuit 17, control signal CRED_W_N [K] is maintained at the H level, P channel MOS transistor P15 is maintained in the non-conductive state, and power supply node PV1 and determination node ND1 Are kept separated.

  In write assist power supply circuits 18a to 18d, since control signal CRED_W_N [K] is at the H level, P channel MOS transistor P18 maintains a non-conductive state. Thus, the state where the memory cell power supply lines arvdd [0] to arvdd [3] are separated from the power supply node PV3 is maintained.

  Further, when control signal CRED_W_N [K] is maintained at the H level, P channel MOS transistors P13a, P13b, and P13c are turned off in bit line load circuits 23a to 23d, and bit line pairs BL [0], The state where BLC [0] to BL [3] and BLC [3] are separated from the power supply node PV2 is maintained.

  On the other hand, when power supply voltage level VDD is latched in latch circuit 17, control signal CRED_W_N [K] is set to L level, P channel MOS transistor P15 is turned on, and power supply node PV1 and determination node ND1 are connected. Connecting.

  In write assist power supply circuits 18a-18d, since control signal CRED_W_N [K] is at L level, when at least one of write control signal WE_N and column selection signal Y_N [i] is set at H level. P channel MOS transistor P18 becomes conductive. Thus, at the time of non-writing, memory cell power supply lines arvdd [0] to arvdd [3] are charged with power supply voltage VDD transmitted from power supply node PV3. At the time of writing, memory cell power supply lines arvdd [j] (j ≠ i) in columns other than selected column i are charged with power supply voltage VDD transmitted from power supply node PV3.

  Further, when the control signal CRED_W_N [K] is set to the L level, the column selection signals Y_N [0] to Y_N [3] are set to the H level in the bit line load circuits 23a to 23d. Channel MOS transistors P13a, P13b, and P13c are rendered conductive, and bit line pairs BL [0], BLC [0] to BL [3], BLC [3] are charged with power supply voltage VDD transmitted from power supply node PV2. .

  Next, in step S6 and step S7, data writing and reading are executed using various data patterns. When writing is performed, write control signal WE_N is set to L level, and selected column i to be written or read is designated by activating column selection signal Y_N [i] to L level.

  When there is a standby current failure in the regular Kth block, the ground voltage is latched in the latch circuit 17, so that the power supply to the memory cell power supply lines arvdd [0] to arvdd [3] is as described above. The power supply voltage VDD is not supplied from the node PV3, and sufficient charges are not accumulated. Therefore, when the selected column i is written, even when the memory cell power line arvdd [i] of the selected column i is connected to the down power line downvdd, the voltage level of the memory cell power line arvdd [i] is necessary for writing The minimum voltage level is not exceeded. In other words, the voltage level is lower than the voltage level to be lowered in order to increase the write margin. Therefore, accurate data is not stored in the memory cell MC connected to the memory cell power supply line arvdd [i], and the data written to the memory cell MC and the data read from the memory cell MC do not match. The regular Kth block including the selected column i is determined to be defective.

  On the other hand, when there is no standby current failure in the regular Kth block, the power supply voltage VDD level is latched in the latch circuit 17, so that the memory cell power supply lines arvdd [0] to arvdd [3] are connected to the power supply node PV3. It is charged with the power supply voltage VDD transmitted from. When the selected column i is written, when the memory cell power supply line arvdd [i] of the selected column i is connected to the down power supply line downvdd, the voltage level of the memory cell power supply line arvdd [i] decreases, and the write operation is performed. The margin is increased, and data can be stored at high speed and accurately in the memory cell MC connected to the memory cell power supply line arvdd [i]. Therefore, the data written in the memory cell MC matches the data read from the memory cell MC, and it is determined that the normal Kth block is normal.

  In step S8, the address of the defective block is programmed and the program circuit 55 is blown. When it is determined that the regular Kth block is abnormal, the defect identification signal CRED_N [K] is set to the H level by the program circuit 55 and the redundancy control circuit 56.

  By setting defect identification signal CRED_N [K] to H level, memory cell power supply lines arvdd [0] to arvdd [3] are fixedly separated from power supply nodes PV1 and PV3. In bit line load circuits 23a-23d, bit line pairs BL [0], BLC [0] -BL [3], BLC [3] are fixedly separated from power supply node PV2. Accordingly, in the normal operation mode, the memory cell power supply lines arvdd [0] to arvdd [3] and the bit line pairs BL [0], BLC [0] to BL [3], BLC [3] are in a floating state. An abnormal standby leak current is prevented from flowing in the Kth block.

  Similarly to the first embodiment, the data line shift circuit 58 uses the external I / O line based on the shift control signal SHIFT [X] (X = 0 to 127) set by the redundancy control circuit 56. The connection between the EIOX and the internal I / O lines NIOX, SIO0, SIO1 is switched to repair the defective regular Kth block.

  As described above, according to the semiconductor memory device of the fifth embodiment, the write margin can be expanded at the time of data writing as in the fourth embodiment, and the memory cell power supply line and / or the bit line can be expanded. When the memory cell power supply line and / or the bit line voltage level is lowered, the memory cell power supply line is driven to the ground voltage level to ensure that the standby current defective memory cell is It is possible to set a malfunction state. Thereby, the standby current failure / normal operation memory cell can be set to an operation failure state, and this column address can be easily specified. In addition, the standby current failure can be reliably remedied by fixing the memory cell power supply line and / or the bit line having the standby current failure fixedly from the power supply node during normal operation.

(Modification)
The present invention is not limited to the above-described embodiment, and includes, for example, the following modifications.

(1) Relief Unit In the embodiment of the present invention, the relief unit has four columns, and the switch gate circuit 15 (75), the potential drop detection holding circuit 16, and the latch circuit 17 are provided for each relief unit to search for leaks. Made possible. However, the rescue unit is not limited to 4 columns, and may be 2, 8 or 16 columns, for example.

(2) Down power supply line In the embodiment of the present invention, the down power supply line is provided for each block (4 columns). However, the present invention is not limited to this, and any column such as every 1 column or every 2 columns may be used. A down power supply line may be provided for each.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  13, 13a to 13d, 23, 23a to 23d Bit line load circuit, 14, 14a to 14d Bit line / determination node switch circuit, 15, 75 Switch gate circuit, 16 Potential drop detection holding circuit, 17 Latch circuit, 18, 18a -18d, write assist power supply circuit, 19 column selection circuit, 24, 24a-24d, memory cell power supply line / determination node switch circuit, 34, 34a-34d bit line and memory cell power supply line / determination node switch circuit, 51 memory cell array, 52 main control circuit, 53 row selection circuit, 54 column peripheral circuit, 55 program circuit, 55a program circuit for even block, 55b program circuit for odd block, 56 redundancy control circuit, 56a redundancy control circuit for even block, 56b for odd block Redundant control circuit, 57 columns Decoder, 58 data line shift circuit, 59 data input / output circuit, 81 writing unit, 82 reading unit, 91 normal memory array unit, 92 spare memory array unit, 93 row decoder, 94 word line driving circuit, 10, 110 test control Circuit, DEC0 to DEC3, DEC124 to DEC127 decoder, NRS0 to NRS3, NRS124 to NRS129, NR15, NR16, NR17, NR18 NOR gate, NA13, NA18 NAND gate, IVS0 to IVS3, IVS124 to IVS127, IVS150 to IVS153, IV13, IV14 , IV16a, IV16b, IV16c, IV15, IV17, IV18, IV23 Inverter, SW0 to SW7, SW126, SW127 Shift switch, SIO01, SIO02 Spare I / O line, TR17 tristate circuit, TG14a, TG14b, TG24a transfer gate, NIO0 to NIO7, NIO126, NIO127 Internal normal I / O lines, EIO0 to EIO7, EIO126, EIO127 Internal spare I / O lines, MC memory Cell, P13a, P13b, P13c, P15, PQ1, PQ2, P18 P channel MOS transistor, N16, N17, NQ1 to NQ4, N18, NQ18 N channel MOS transistor, RG17 latch gate, PV1, PV2, PV3, ND1, ND2, NOD1, NOD2 node, BL, BLC bit line, arvdd memory cell power line, downvdd down power line, WL word line.

Claims (6)

A plurality of memory cells arranged in a matrix;
A reference potential node;
A switch gate circuit coupled to the reference potential node, selectively turned on and transmitting the reference potential when turned on;
A first voltage transmission line for transmitting a voltage from the switch gate circuit to the plurality of memory cells;
It is activated in a specific operation mode and detects whether or not the potential of the first node to which the first voltage transmission line is connected is at a predetermined potential level, and the potential of the first node is set according to the detection result. A power supply control circuit for setting the potential according to the detection result;
A plurality of bit line pairs arranged corresponding to the columns of the memory cells, each connected to a memory cell in the corresponding column;
A bit line load circuit arranged corresponding to the bit line pair and charging a bit line of a corresponding column at least in a standby state;
The switch gate circuit outputs a first control signal that is set to a predetermined level when the switch gate circuit is non-conductive,
The bit line load circuit is a semiconductor memory device that stops charging the bit line when the first control signal is set to the predetermined level. A plurality of memory cells arranged in a matrix;
A reference potential node;
A switch gate circuit coupled to the reference potential node, selectively turned on and transmitting the reference potential when turned on;
A first voltage transmission line for transmitting a voltage from the switch gate circuit to the plurality of memory cells;
Activated in the specific operation mode to detect whether or not the potential of the first node is at a predetermined potential level, and to set the potential of the first node to a potential corresponding to the detection result according to the detection result Power supply control circuit,
A plurality of bit line pairs arranged corresponding to the columns of the memory cells and connected to the memory cells in the corresponding columns,
The bit line pair and the first voltage transmission line are connected to the first node, the semiconductor memory device. The semiconductor memory device further includes:
A connection switch for connecting the bit line pair to the first node;
The connection switch is in a conductive state at least when the power supply control circuit is activated, and is in a non-conductive state at the time of reading and writing data to a memory cell connected to a bit line pair connected to the connection switch. The semiconductor memory device according to claim 2. A plurality of static memory cells arranged in a matrix;
A reference potential node;
A plurality of array power supply lines arranged corresponding to each memory cell column, each coupled to a cell power supply node of a memory cell in the corresponding column;
Activated in the specific operation mode to detect whether or not the potential of the first node is at a predetermined potential level, and to set the potential of the first node to a potential corresponding to the detection result according to the detection result Power supply control circuit,
A write assist circuit for lowering the voltage level of the array power supply line arranged corresponding to the memory cell of the selected column at the time of data writing;
A first connection switch for connecting the array power supply line to the first node;
The write assist circuit transmits a voltage from the reference potential node to the array power supply line at least in a standby state,
The first connection switch is turned on at least when the power supply control circuit is activated, and at least when data is read from the memory cell connected to the array power supply line connected to the first connection switch; A semiconductor memory device which becomes non-conductive at the time of writing. The semiconductor memory device further includes:
A plurality of bit line pairs arranged corresponding to the columns of the memory cells, each connected to a memory cell in the corresponding column;
A bit line load circuit arranged corresponding to the bit line pair and charging a bit line of a corresponding column at least in a standby state ;
A second connection switch for connecting said bit line pair to said first node,
A switch gate circuit coupled to the reference potential node, selectively turned on, and transmitting the reference potential to the first node when turned on;
The switch gate circuit outputs a first control signal that is activated when the switch gate circuit is non-conductive,
The bit line load circuit stops charging the bit line in response to the activation of the first control signal;
The second connection switch is rendered conductive at least when the power supply control circuit is activated, and at least when data is read to a memory cell connected to the bit line pair connected to the second connection switch; The semiconductor memory device according to claim 4, wherein the semiconductor memory device is rendered non-conductive at the time of writing. The semiconductor memory device further includes:
Including a plurality of down power supply lines arranged corresponding to each memory cell column or a plurality of memory cell columns, maintained at a ground voltage level during data reading, and brought into a floating state during data writing;
The write assist circuit stops supplying the power supply voltage to the array power supply line of the selected column during data writing, and arranges the array power supply line of the selected column corresponding to the selected column 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is connected to a down power supply line.

Images