JP5442754B2 - Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, television receiver - Google Patents

Description

  The present invention relates to a pixel division type active matrix substrate and a liquid crystal panel.

  As a technique for improving the viewing angle characteristics of a liquid crystal display device, a pixel division method is known in which two pixel electrodes (a bright pixel electrode corresponding to a bright subpixel and a dark pixel electrode corresponding to a dark subpixel) are provided in one pixel. ing. FIG. 36 shows an example of a pixel division type liquid crystal panel. This liquid crystal panel has two data signal lines corresponding to one pixel, and is an individual writing type in which different data signals are written to the bright and dark pixel electrodes during halftone display. In this individual writing type, two pixel electrodes capacitively coupled to one pixel are provided, and there is no pixel electrode that is electrically floating as compared with the capacitive coupling type in which a data signal is written to only one of them. There is an advantage that the brightness of the bright and dark sub-pixels can be accurately controlled.

Japanese Patent Publication “Japanese Patent Laid-Open No. 2006-209135 (Publication Date: May 13, 2006)”

  However, in the configuration of FIG. 36, since writing is performed for each pixel row, the pixel charging time when applied to, for example, a large-sized high-definition liquid crystal display device or a high-speed drive (for example, double speed / triple speed drive) liquid crystal display device. However, there was a problem that display quality deteriorated.

  An object of the present invention is to extend the pixel charging time of an individual writing type liquid crystal display device.

  The active matrix substrate includes a plurality of data signal lines and a plurality of scanning signal lines, each pixel region is provided with a plurality of pixel electrodes, and the extending direction of each data signal line is defined as a column direction. Corresponding to the two data signal lines, and one pixel electrode of the pixel region included in the pixel region column is connected to one of the two data signal lines through a transistor connected to the scanning signal line. And another pixel electrode of the pixel region is connected to the other of the two data signal lines via a transistor connected to another scanning signal line, and adjacent two pixels of the pixel region column One of the pixel electrodes included in one of the regions and one of the pixel electrodes included in the other region are connected to the same scanning signal line through transistors, respectively.

  In the liquid crystal display device provided with the active matrix substrate, individual writing can be performed on a plurality of pixel electrodes provided in one pixel region while selecting two scanning signal lines at a time. The pixel charging time can be extended.

  According to the present invention, the pixel charging time of an individual writing type liquid crystal display device can be extended.

1 is a circuit diagram showing a configuration of a liquid crystal panel according to Embodiment 1. FIG. 3 is a timing chart showing a method for driving the liquid crystal panel of FIG. 1. It is a schematic diagram explaining the state of the horizontal scanning period H1. It is a schematic diagram explaining the state of the horizontal scanning period H2. It is a schematic diagram explaining the state of the horizontal scanning period H3. FIG. 2 is a plan view showing a specific configuration of the liquid crystal panel of FIG. 1. FIG. 7 is a cross-sectional view taken along the arrow in FIG. 6 . 6 is a timing chart showing another driving method of the liquid crystal panel shown in FIG. It is a schematic diagram explaining the state of H1 of FIG. It is a schematic diagram explaining the state of H2 of FIG. It is a schematic diagram explaining the state of H3 of FIG. It is a top view which shows the other specific structure of the liquid crystal panel shown in FIG. 6 is a timing chart showing still another driving method of the liquid crystal panel shown in FIG. It is a schematic diagram explaining the state of h1 of FIG. It is a schematic diagram explaining the state of h2 of FIG. It is a schematic diagram explaining the state of h3 of FIG. FIG. 6 is a circuit diagram illustrating a configuration of a liquid crystal panel according to a second embodiment. It is a timing chart which shows the drive method of the liquid crystal panel of FIG. It is a schematic diagram explaining the state of the horizontal scanning period H1. It is a schematic diagram explaining the state of the horizontal scanning period H2. It is a schematic diagram explaining the state of the horizontal scanning period H3. FIG. 18 is a plan view showing a specific configuration of the liquid crystal panel of FIG. 17. FIG. 10 is a circuit diagram showing another configuration of the liquid crystal panel according to the second exemplary embodiment. 24 is a timing chart showing a method for driving the liquid crystal panel shown in FIG. It is a schematic diagram explaining the state of the horizontal scanning period H1. It is a schematic diagram explaining the state of the horizontal scanning period H2. It is a schematic diagram explaining the state of the horizontal scanning period H3. It is a schematic diagram which shows the structural example of the gate driver of a liquid crystal display device. (A) is a schematic diagram which shows the structure of this liquid crystal display unit, (b) is a schematic diagram which shows the structure of this liquid crystal display device. It is a block diagram explaining the whole structure of this liquid crystal display device. It is a block diagram explaining the function of this liquid crystal display device. FIG. 26 is a block diagram illustrating functions of the present television receiver. It is a disassembled perspective view which shows the structure of this television receiver. It is a top view which shows the modification of FIG. It is a schematic diagram which shows the structure of the gate driver of this liquid crystal display device. It is a schematic diagram which shows the structure of the conventional liquid crystal panel.

  An example of an embodiment according to the present invention will be described below with reference to FIGS. For convenience of explanation, hereinafter, the extending direction of the data signal lines is referred to as a column direction, and the extending direction of the scanning signal lines is referred to as a row direction. However, in the use (viewing) state of the present liquid crystal display device (or the liquid crystal panel or active matrix substrate used therein), the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say. One pixel area of the active matrix substrate corresponds to one pixel of a liquid crystal panel or a liquid crystal display device.

[Embodiment 1]
FIG. 1 is an equivalent circuit diagram showing a part of the liquid crystal panel 5a. In the liquid crystal panel 5a, a plurality of pixel electrodes are provided for each pixel, and two data signal lines are provided corresponding to one pixel column with the extending direction of each data signal line as a column direction. One pixel electrode of the included pixel is connected to one of the two data signal lines through a transistor connected to the scanning signal line, and another pixel electrode of the pixel is connected to another scanning signal line One of the pixel electrodes included in one of the two adjacent pixel pixels of the pixel column and one of the pixel electrodes included in the other are connected to the other of the two data signal lines via the connected transistor. Are connected to the same scanning signal line through transistors. In addition, in each pixel, two pixel electrodes are arranged in the row direction and belong to the same pixel column, and each of the two pixel electrodes connected to the same scanning signal line via a transistor is diagonally opposite to each other. It is arranged in.

  For example, two data signal lines Sx and Sy are provided corresponding to a pixel column including the pixels 101 to 104 arranged in the column direction, and a pixel row including the pixels 101 and 105 arranged in the row direction and scanning thereof. A scanning signal line G (n−1) is provided corresponding to a gap with a pixel row on the upstream side in the direction, and a pixel row including pixels 102 and 106 and a pixel row including pixels 101 and 105 arranged in the row direction The scanning signal line Gn is provided corresponding to the gap between the pixel rows including the pixels 103 and 107 and the pixel rows including the pixels 102 and 106 arranged in the row direction. ) And a scanning signal line G (n + 2) is provided corresponding to the gap between the pixel row including the pixels 104 and 108 and the pixel row including the pixels 103 and 107 arranged in the row direction. Pixel row containing and its scan direction The scanning signal line G (n + 3) is provided corresponding to the gap with the pixel row on the flow side, and the two data signal lines SX and SY are corresponding to the pixel column including the pixels 105 to 108 arranged in the column direction. Is provided. Further, the storage capacitor wiring Cs (n−) corresponds to the pixel row including the pixels 101 and 105, the pixel row including the pixels 102 and 106, the pixel row including the pixels 103 and 107, and the pixel row including the pixels 104 and 108, respectively. 1) A storage capacitor line Csn, a storage capacitor line Cs (n + 1), and a storage capacitor line Cs (n + 2) are provided.

Here, in the pixel 101, two pixel electrodes 17a and 17b are arranged in this order along the row direction, the drain electrode of the transistor 12a connected to the scanning signal line Gn is connected to the pixel electrode 17a, and the scanning signal The drain electrode of the transistor 12b connected to the line G (n-1) is connected to the pixel electrode 17b, the source electrode of the transistor 12a is connected to the data signal line Sx, and the source electrode of the transistor 12b is connected to the data signal line Sy. Has been. A liquid crystal capacitor Cla is formed between the pixel electrode 17a and the common electrode (counter electrode) com, and a liquid crystal capacitor Clb is formed between the pixel electrode 17b and the common electrode (counter electrode) com. together with the holding capacitor csa is formed between the 17a and the retention capacitor line Cs (n-1), the holding capacitor csb is formed between the pixel electrode 17 b and the storage capacitor wire Cs (n-1).

  In the pixel 102 adjacent to the pixel 101 in the column direction, two pixel electrodes 17c and 17d are arranged in this order along the row direction, and the drain electrode of the transistor 12c connected to the scanning signal line G (n + 1) is the pixel. The drain electrode of the transistor 12d connected to the scanning signal line Gn is connected to the pixel electrode 17d, the source electrode of the transistor 12c is connected to the data signal line Sx, and the source electrode of the transistor 12d is connected to the data signal line Sx. It is connected to the signal line Sy. A liquid crystal capacitor Clc is formed between the pixel electrode 17c and the common electrode (counter electrode) com, and a liquid crystal capacitor Cld is formed between the pixel electrode 17d and the common electrode (counter electrode) com. A storage capacitor csc is formed between 17c and the storage capacitor line Csn, and a storage capacitor csd is formed between the pixel electrode 17d and the storage capacitor line Csn.

  In the pixel 103 adjacent to the pixel 102 in the column direction, two pixel electrodes 17e and 17f are arranged in this order along the row direction, and the drain electrode of the transistor 12e connected to the scanning signal line G (n + 2) is the pixel. The drain electrode of the transistor 12f connected to the electrode 17e, connected to the scanning signal line G (n + 1), is connected to the pixel electrode 17f, the source electrode of the transistor 12e is connected to the data signal line Sx, and the source of the transistor 12f The electrode is connected to the data signal line Sy. A liquid crystal capacitor Cle is formed between the pixel electrode 17e and the common electrode (counter electrode) com, and a liquid crystal capacitor Clf is formed between the pixel electrode 17f and the common electrode (counter electrode) com. A storage capacitor cse is formed between 17e and the storage capacitor line Cs (n + 1), and a storage capacitor csf is formed between the pixel electrode 17f and the storage capacitor line Cs (n + 1).

  Further, in the pixel 104 adjacent to the pixel 103 in the column direction, two pixel electrodes 17g and 17h are arranged in this order along the row direction, and the drain electrode of the transistor 12g connected to the scanning signal line G (n + 3) is the pixel. The drain electrode of the transistor 12h connected to the electrode 17g and connected to the scanning signal line G (n + 2) is connected to the pixel electrode 17h, and the source electrode of the transistor 12g is connected to the data signal line Sx, and the source of the transistor 12h The electrode is connected to the data signal line Sy. A liquid crystal capacitor Clg is formed between the pixel electrode 17g and the common electrode (counter electrode) com, and a liquid crystal capacitor Clh is formed between the pixel electrode 17h and the common electrode (counter electrode) com. A storage capacitor csg is formed between 17g and the storage capacitor line Cs (n + 2), and a storage capacitor csh is formed between the pixel electrode 17h and the storage capacitor line Cs (n + 2).

In the pixel 105 adjacent to the pixel 101 in the row direction, two pixel electrodes 17A and 17B are arranged in this order along the row direction, and the drain electrode of the transistor 12A connected to the scanning signal line Gn is connected to the pixel electrode 17A. The drain electrode of the transistor 12B connected to the scanning signal line G (n−1) is connected to the pixel electrode 17B, the source electrode of the transistor 12A is connected to the data signal line SX, and the source electrode of the transistor 12B is connected. Is connected to the data signal line SY. A liquid crystal capacitor ClA is formed between the pixel electrode 17A and the common electrode (counter electrode) com, and a liquid crystal capacitor ClB is formed between the pixel electrode 17B and the common electrode (counter electrode) com. together with the holding capacitor CsA is formed between the 17A and the retention capacitor line Cs (n-1), the holding capacitor CsB is formed between the pixel electrode 17 B and the storage capacitor wire Cs (n-1).

  In the pixel 106 adjacent to the pixel 102 in the row direction, two pixel electrodes 17C and 17D are arranged in this order along the row direction, and the drain electrode of the transistor 12C connected to the scanning signal line G (n + 1) is the pixel. The drain electrode of the transistor 12D connected to the electrode 17C is connected to the pixel electrode 17D, the source electrode of the transistor 12C is connected to the data signal line SX, and the source electrode of the transistor 12D is connected to the data signal line SX. It is connected to the signal line SY. A liquid crystal capacitor ClC is formed between the pixel electrode 17C and the common electrode (counter electrode) com, and a liquid crystal capacitor ClD is formed between the pixel electrode 17D and the common electrode (counter electrode) Com. A storage capacitor csC is formed between 17C and the storage capacitor line Csn, and a storage capacitor csD is formed between the pixel electrode 17D and the storage capacitor line Csn.

  In the pixel 107 adjacent to the pixel 103 in the row direction, two pixel electrodes 17E and 17F are arranged in this order along the row direction, and the drain electrode of the transistor 12E connected to the scanning signal line G (n + 2) is the pixel. The drain electrode of the transistor 12F connected to the electrode 17E and the scan signal line G (n + 1) is connected to the pixel electrode 17F, the source electrode of the transistor 12E is connected to the data signal line SX, and the source of the transistor 12F The electrode is connected to the data signal line SY. A liquid crystal capacitor ClE is formed between the pixel electrode 17E and the common electrode (counter electrode) com, and a liquid crystal capacitor ClF is formed between the pixel electrode 17F and the common electrode (counter electrode) com. A storage capacitor csE is formed between 17E and the storage capacitor line Cs (n + 1), and a storage capacitor csF is formed between the pixel electrode 17F and the storage capacitor line Cs (n + 1).

  In the pixel 108 adjacent to the pixel 104 in the row direction, two pixel electrodes 17G and 17H are arranged in this order along the row direction, and the drain electrode of the transistor 12G connected to the scanning signal line G (n + 3) is the pixel. The drain electrode of the transistor 12H connected to the electrode 17G, connected to the scanning signal line G (n + 2), is connected to the pixel electrode 17H, the source electrode of the transistor 12G is connected to the data signal line SX, and the source of the transistor 12H The electrode is connected to the data signal line SY. A liquid crystal capacitor ClG is formed between the pixel electrode 17G and the common electrode (counter electrode) com, and a liquid crystal capacitor ClH is formed between the pixel electrode 17H and the common electrode (counter electrode) com. A storage capacitor csG is formed between 17G and the storage capacitor line Cs (n + 2), and a storage capacitor csH is formed between the pixel electrode 17H and the storage capacitor line Cs (n + 2).

3 to 5 show a driving method when halftone display is performed on a part of the liquid crystal panel 5a (seven pixel rows including the four pixel rows in FIG. 1) in three horizontal scanning periods that are continuous every one horizontal scanning period. It is a schematic diagram which shows a minute (H1-H3). 3 shows two selection periods and one selection period for H1, FIG. 4 shows two selection periods and one selection period for H2, and FIG. 5 shows two selection periods and one selection period for H3 . Is shown. 2 is a timing chart (for two frames) showing a driving method when halftone display is performed on a part of the liquid crystal panel 5a . Sx, Sy, SX, and SY in FIG. 2 shows data signals supplied to the data signal lines Sx, Sy, SX, SY, and Gn to G (n + 5) in FIG. 2 are scanning signals supplied to the scanning signal lines Gn to G (n + 5) in FIGS. (Active High), and 17a to 17f in FIG. 2 indicate potentials of the pixel electrodes 17a to 17f in FIG.

  In the driving method shown in FIGS. 2 to 5, the scanning signal lines are sequentially selected two by two. In one horizontal scanning period, two scanning signal lines are selected at the same time, and the two scanning signal lines are selected. Following the selection period, one selection period in which one of the two scanning signal lines is not selected is included. Further, at the time of halftone display, a low gradation data signal is supplied to each data signal line during two selection periods, and a high gradation data signal is supplied to each data signal line during one selection period. In addition, data signals having opposite polarities are supplied to two data signal lines corresponding to one pixel column. In addition, data signals having the same polarity are supplied to two adjacent data signal lines (for example, Sy · SX) corresponding to different pixel columns. The polarity of the data signal supplied to each data signal line is inverted every horizontal scanning period (1H).

For example, in three consecutive horizontal scanning periods H1 to H3, two scanning signal lines Gn · G (n + 1) are selected (made active) in the two selection period H1. As a result, as shown in FIGS. 1, 2, and 3 , a positive precharge signal (low gradation) is written to the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx through the transistor, and the transistor A negative precharge signal (low gradation) is written to the pixel electrode 17d connected to the scanning signal line Gn and the data signal line Sy through the transistor, and the scanning signal line G (n + 1) and the data signal line Sx are transmitted through the transistor. A positive low gradation data signal is written to the pixel electrode 17c connected to the pixel electrode 17 and a negative low gradation data signal is applied to the pixel electrode 17f connected to the scanning signal line G (n + 1) and the data signal line Sy via the transistor. Is written. In addition, a negative precharge signal (low gradation) is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX through the transistor, and the scanning signal line Gn and the data signal line SY through the transistor. A positive precharge signal (low gradation) is written to the pixel electrode 17D connected to the pixel electrode 17D, and a negative lower order is applied to the pixel electrode 17C connected to the scanning signal line G (n + 1) and the data signal line SX via the transistor. A tone data signal is written, and a positive low gradation data signal is written to the pixel electrode 17F connected to the scanning signal line G (n + 1) and the data signal line SY via a transistor.

Next, in the single selection period of H1, it is assumed that the scanning signal line G (n + 1) is not selected and only the scanning signal line Gn is selected. As a result, as shown in FIGS. 1, 2, and 3 , a positive high gradation data signal is written to the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx via the transistor, and scanning is performed via the transistor. A negative high gradation data signal is written to the pixel electrode 17d connected to the signal line Gn and the data signal line Sy. Further, a negative high gradation data signal is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX via the transistor, and the pixel connected to the scanning signal line Gn and the data signal line SY via the transistor. A positive high gradation data signal is written to the electrode 17D.

  From the above, the subpixels corresponding to the pixel electrodes 17a, 17c, 17d, 17f, 17A, 17C, 17D, and 17F are the bright subpixel (+), the dark subpixel (+), the bright subpixel (−), and the dark subpixel. Sub-pixel (-), bright sub-pixel (-), dark sub-pixel (-), bright sub-pixel (+), and dark sub-pixel (+).

Further, in the two selection period H2, two scanning signal lines G (n + 2) · G (n + 3) are selected (made active). As a result, as shown in FIGS. 1, 2, and 4 , a negative precharge signal (low gradation) is written to the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor. Then, a positive precharge signal (low gradation) is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy via the transistor, and the scanning signal line G (n + 3) is passed via the transistor. ) And a negative low gradation data signal is written to the pixel electrode 17g connected to the data signal line Sx, and a positive value is applied to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line Sy via the transistor. A low gradation data signal is written. Further, a positive precharge signal (low gradation) is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX via the transistor, and the scanning signal line G (n + 2) is passed via the transistor. ) And the pixel electrode 17H connected to the data signal line SY is written with a negative precharge signal (low gradation), and the pixel electrode 17G connected to the scanning signal line G (n + 3) and the data signal line SX through the transistor. A positive low gradation data signal is written to the pixel electrode, and a negative low gradation data signal is written to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line SY through the transistor.

Next, in the single selection period of H2, the scanning signal line G (n + 3) is not selected and only the scanning signal line G (n + 2) is selected. As a result, as shown in FIGS. 1, 2, and 4 , a negative high gradation data signal is written into the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor, A positive high gradation data signal is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy. Further, a positive high gradation data signal is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX through the transistor, and the scanning signal line G (n + 2) and the data signal are written through the transistor. A negative high gradation data signal is written to the pixel electrode 17H connected to the line SY.

  From the above, the subpixels corresponding to the pixel electrodes 17e, 17g, 17h, 17E, 17G, and 17H are the bright subpixel (−), the dark subpixel (−), the bright subpixel (+), and the bright subpixel (+ ), Dark subpixel (+), and bright subpixel (-).

Further, in the two selection period of H3, two scanning signal lines G (n + 4) · G (n + 5) are selected, and in the next selection period of H3, the scanning signal line G (n + 5) is not selected, Only the scanning signal line G (n + 4) is selected. The state of H3 is as shown in FIG.

  Since the liquid crystal display device including the liquid crystal panel 5a is an individual writing type pixel division method, the viewing angle characteristics are good, and there is no pixel electrode that is electrically floating as compared with the capacitive coupling type. There are advantages that the reliability is high and that the brightness of the bright and dark sub-pixels can be accurately controlled.

  Then, the scanning signal lines are selected two by two, and the bright sub-pixel connected to the even-numbered scanning signal line (Gn · G (n + 2). Since the data signal can be written in the selection period, the charging time of the bright sub-pixel can be substantially doubled with normal driving. Further, the two selection period in which the data signal is written to the dark sub-pixel connected to the odd-numbered scanning signal lines (G (n + 1) · G (n + 3)...) Is set longer than the one selection period. For this reason, during normal driving, the charging time of the dark sub-pixel can be extended. Accordingly, it is suitable for a large-sized high-definition liquid crystal display device and a liquid crystal display device driven at a high speed (driving at 60 Hz or more).

  Furthermore, when displaying halftones, bright subpixels and dark subpixels are alternately arranged in the row direction and the column direction (bright and dark subpixels are arranged in a checkered pattern), so that line-shaped unevenness is less visible. There is also an effect.

  In addition, since the polarity of the data signal written on the screen is inverted in units of two subpixels in each of the row direction and the column direction, flickering of the screen can be suppressed.

  FIG. 6 is a plan view showing a configuration example of a part of the liquid crystal panel 5a shown in FIG. As shown in FIG. 6, on the liquid crystal panel 5a, scanning signal lines G (n-1), scanning signal lines Gn, and scanning signal lines G (n + 1) extending in the row direction are arranged in this order along the scanning direction. In addition, the data signal lines Sx, Sy, SX, and SY extending in the column direction are arranged in this order, and when viewed in plan, the scanning signal line G (n−1), the scanning signal line Gn, and the data signal line The pixel electrodes 17a and 17b are arranged in this order along the row direction in the region defined by Sx and Sy, and are defined by the scanning signal line G (n-1), the scanning signal line Gn, and the data signal line SX and SY. The pixel electrodes 17A and 17B are arranged in this order along the row direction in the region in which the pixel electrodes 17c and 17d are arranged in the region defined by the scanning signal line Gn, the scanning signal line G (n + 1), and the data signal lines Sx and Sy. Along the line Converting mechanism are arranged in this order, the scanning signal line Gn and the scanning signal line G (n + 1) as well as areas in the pixel electrode 17C · 17D that bounded by the data signal line SX · SY are arranged in this order along the row direction. In addition, a storage capacitor line Cs (n−1) is arranged between the scanning signal line G (n−1) and the scanning signal line Gn, and a storage capacitor line is connected between the scanning signal line Gn and the scanning signal line G (n + 1). Csn is arranged.

  The scanning signal line G (n−1) is the gate electrode of the transistors 12b and 12B, the scanning signal line Gn is the gate electrode of the transistors 12a and 12A, and the scanning signal line G (n + 1) is the gate electrode of the transistors 12c and 12C. Function as. The source electrodes of the transistors 12a and 12c are connected to the data signal line Sx, the source electrodes of the transistors 12b and 12d are connected to the data signal line Sy, and the source electrodes of the transistors 12A and 12C are connected to the data signal line SX. In addition, the source electrodes of the transistors 12B and 12D are connected to the data signal line SY.

  Further, the drain electrode of the transistor 12a is connected to the pixel electrode 17a through the contact hole 11a, and the drain electrode of the transistor 12b is connected to the pixel electrode 17b through the contact hole 11b, and is connected to the storage capacitor wiring Cs (n−1). The overlapping capacitor electrode 67a and the pixel electrode 17a are connected via a contact hole 91a, and the capacitor electrode 67b and the pixel electrode 17b overlapping the storage capacitor wiring Cs (n-1) are connected via a contact hole 91b. Similarly, the drain electrode of the transistor 12A is connected to the pixel electrode 17A through the contact hole 11A, the drain electrode of the transistor 12B is connected to the pixel electrode 17B through the contact hole 11B, and the storage capacitor line Cs (n−1). The capacitor electrode 67A and the pixel electrode 17A that overlap each other are connected via the contact hole 91A, and the capacitor electrode 67B and the pixel electrode 17B that overlap the storage capacitor wiring Cs (n-1) are connected via the contact hole 91B. .

  Here, the overlapping portion of the storage capacitor wiring Cs (n−1) and the capacitor electrode 67a, the overlapping portion of the storage capacitor wiring Cs (n−1) and the capacitor electrode 67b, the storage capacitor wiring Cs (n−1) and the capacitor electrode 67A. Most of the storage capacitors csa, csb, csA, and csB (see FIG. 1) are formed in the overlapping portion of the storage capacitor line Cs (n-1) and the overlapping portion of the capacitor electrode 67B, respectively.

  Further, the drain electrode of the transistor 12c is connected to the pixel electrode 17c through the contact hole 11c, the drain electrode of the transistor 12d is connected to the pixel electrode 17d through the contact hole 11d, and the capacitor electrode 67c overlapping the storage capacitor wiring Csn. The pixel electrode 17c is connected through the contact hole 91c, and the capacitor electrode 67d and the pixel electrode 17d overlapping the storage capacitor wiring Csn are connected through the contact hole 91d. Similarly, the drain electrode of the transistor 12C is connected to the pixel electrode 17C through the contact hole 11C, the drain electrode of the transistor 12D is connected to the pixel electrode 17D through the contact hole 11D, and the capacitor electrode 67C that overlaps the storage capacitor wiring Csn. And the pixel electrode 17C are connected via a contact hole 91C, and the capacitor electrode 67D and the pixel electrode 17D overlapping the storage capacitor line Csn are connected via a contact hole 91D.

Here, the overlapping portion of the retention capacitor line Csn and the capacitor electrode 67 c, overlapping part of the retention capacitor line Csn and the capacitor electrode 67 d, overlapping part of the retention capacitor line Csn and the capacitor electrode 67C, and the storage capacitor wire Csn and the capacitor electrodes 67D Most of the storage capacitors csc, csd, csC, and csD (see FIG. 1) are formed in the overlapping portions.

  In FIG. 6, the channel sizes (W / L) of the transistors 12a, 12d, 12A, and 12D are made equal to the channel sizes (W / L) of the transistors 12b, 12c, 12B, and 12C, but the present invention is not limited to this. . The channel sizes of the transistors 12a, 12d, 12A, and 12D connected to the bright pixel electrodes that can take a long charge time can be made smaller than those of the transistors 12b, 12c, 12B, and 12C connected to the dark pixel electrodes. In this way, the aperture ratio can be increased.

  7 is a cross-sectional view taken along the arrow in FIG. As shown in the figure, the liquid crystal panel 5a includes an active matrix substrate 3, a color filter substrate 30 facing the active matrix substrate 3, and a liquid crystal layer 40 disposed between the substrates (3, 30).

  In the active matrix substrate 3, the scanning signal line Gn and the storage capacitor wiring Cs (n−1) are formed on the glass substrate 31, and the gate insulating film 22 is formed so as to cover them. On the gate insulating film 22, a semiconductor layer (i layer and n + layer), a source electrode in contact with the n + layer, a drain electrode (not included in the cross section), and a capacitor electrode 67a are formed, and an inorganic layer is formed so as to cover them. An interlayer insulating film 25 is formed. A thicker organic interlayer insulating film 26 is formed on the inorganic interlayer insulating film 25, and a pixel electrode 17 a is formed on the organic interlayer insulating film 26. Although not shown, an alignment film is formed so as to cover the surface of the active matrix substrate 3. Here, in the contact hole 91a, the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 are penetrated, whereby the pixel electrode 17a and the capacitor electrode 67a are connected. The capacitor electrode 67a overlaps the storage capacitor line Cs (n−1) via the gate insulating film 22, and most of the storage capacitor csa (see FIG. 1) is formed in this overlapping portion.

  On the other hand, in the color filter substrate 30, the black matrix 13 and the colored layer 14 are formed on the glass substrate 32, the common electrode (com) 28 is formed thereon, and an alignment film is formed so as to cover the surface of the color filter substrate 30. Is formed (not shown).

  Below, the manufacturing method of this liquid crystal panel is demonstrated. The method for manufacturing a liquid crystal panel includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembly process in which both substrates are bonded to each other and filled with liquid crystal.

  First, a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a laminated film thereof (thickness: 1000 mm to 3000 mm) is sputtered on a substrate such as glass or plastic. Then, patterning is performed by photolithography technology (Photo Engraving Process, hereinafter referred to as “PEP technology”, which includes an etching process), and scanning is performed by removing the photoresist. A signal line (a gate electrode of each transistor) and a storage capacitor line are formed.

  Next, an inorganic insulating film (thickness of about 3000 to 5000 mm) such as silicon nitride or silicon oxide is formed on the entire substrate on which the scanning signal lines are formed by a CVD (Chemical Vapor Deposition) method to form a gate insulating film. .

  Subsequently, an intrinsic amorphous silicon film (thickness 1000 to 3000 mm) and an n + amorphous silicon film (thickness 400 to 700 mm) doped with phosphorus are continuously formed on the gate insulating film (whole substrate) by CVD. After film formation, patterning is performed by the PEP technique, and the photoresist is removed, thereby forming an island-shaped silicon laminate including an intrinsic amorphous silicon layer and an n + amorphous silicon layer on the gate electrode.

  Subsequently, a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a stacked film thereof (thickness: 1000 mm to 3000 mm) is formed on the entire substrate on which the silicon stacked body is formed. Then, patterning is performed by the PEP technique to form data signal lines, transistor source / drain electrodes, and capacitor electrodes (formation of a metal layer). Here, the resist is removed as necessary.

  Further, the n + amorphous silicon layer constituting the silicon stacked body is removed by etching using the photoresist at the time of forming the metal wiring or the source electrode and the drain electrode as a mask, and the photoresist is removed to form a transistor channel. . Here, the semiconductor layer may be formed of an amorphous silicon film as described above. Alternatively, a polysilicon film may be formed, or the amorphous silicon film and the polysilicon film are subjected to laser annealing to be crystallized. May be improved. Thereby, the moving speed of the electrons in the semiconductor layer is increased, and the characteristics of the transistor (TFT) can be improved.

Next, an interlayer insulating film is formed over the entire substrate on which the data signal lines and the like are formed. Specifically, using a mixed gas of SiH ₄ gas, NH ₃ gas and N ₂ gas, an inorganic interlayer insulating film 25 (passivation film) made of SiNx having a thickness of about 3000 mm is formed by CVD so as to cover the entire surface of the substrate. Form. Thereafter, an organic interlayer insulating film 26 made of a positive photosensitive acrylic resin having a thickness of about 3 μm is formed by spin coating or die coating.

Subsequently, a contact pattern is formed on the organic interlayer insulating film 26 by the PEP technique. Further, using the patterned organic interlayer insulating film 26 as a mask, a mixed gas of CF ₄ gas and O ₂ gas is used. The insulating film 25 is dry etched. The organic interlayer insulating film 26 may be an insulating film made of, for example, an SOG (spin-on-glass) material. The organic interlayer insulating film 26 may be an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, or a novolac resin. , And at least one of siloxane resins may be included.

  Subsequently, a transparent conductive film (thickness 1000 to 2000 mm) made of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), zinc oxide, tin oxide or the like is formed on the entire substrate on the interlayer insulating film in which the contact holes are formed. Is formed by sputtering, followed by patterning by PEP technique, and the resist is removed to form each pixel electrode.

  Finally, polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then baked and rubbed in one direction with a rotating cloth to form an alignment film. The active matrix substrate is manufactured as described above.

  Hereinafter, the color filter substrate manufacturing process will be described.

  First, after forming a chromium thin film or a resin containing a black pigment on a substrate such as glass or plastic (entire substrate), patterning is performed by the PEP technique to form a black matrix. Next, red, green and blue color filter layers (thickness of about 2 μm) are formed in a pattern in the gap of the black matrix by using a pigment dispersion method or the like.

  Subsequently, a transparent conductive film (thickness of about 1000 mm) made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).

  Finally, polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film. A color filter substrate can be manufactured as described above.

  Below, an assembly process is demonstrated.

  First, a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate and the color filter substrate by screen printing in a frame-like pattern lacking the liquid crystal inlet portion, and the liquid crystal layer is applied to the other substrate. A spherical spacer having a diameter corresponding to the thickness and made of plastic or silica is dispersed. Instead of spraying the spacer, the spacer may be formed on the BM of the CF substrate or the metal wiring of the active matrix substrate by the PEP technique.

  Next, the active matrix substrate and the color filter substrate are bonded together, and the sealing material is cured.

  Finally, after injecting the liquid crystal material into the space surrounded by the active matrix substrate, the color filter substrate, and the sealing material by the decompression method, applying a UV curable resin to the liquid crystal injection port, and sealing the liquid crystal material by UV irradiation To form a liquid crystal layer. As described above, the liquid crystal panel is manufactured.

  In an MVA (multi-domain vertical alignment) liquid crystal panel, for example, each pixel electrode of an active matrix substrate is provided with an alignment regulating slit, and an alignment regulating rib (linear protrusion) is provided on the color filter substrate. Provided. Note that, instead of the ribs, a slit for regulating the orientation can be provided in the common electrode of the color filter substrate. In addition, photo-alignment liquid crystal that determines the alignment of liquid crystal by irradiation with ultraviolet rays or the like can also be used. In this case, a high viewing angle can be realized without providing a rib or slit structure, and the aperture ratio can be greatly improved.

  6 and 7, the gap between two data signal lines adjacent to each other and corresponding to different pixel columns (same layer as the data signal line) or above the gap (pixels). An interstitial wiring to which a signal different from the data signal is supplied may be provided in the same layer as the electrode). For example, an interstitial wiring is provided in the gap between the data signal lines Sy and SX. In this way, for example, the crosstalk between the data signal line SX and the pixel electrode 17a and the crosstalk between the data signal line Sy and the pixel electrode 17A can be reduced. Further, in FIGS. 6 and 7, each storage capacitor wiring is formed in the same layer as the scanning signal line and extends in the row direction (lateral direction in the figure), but is not limited thereto. Each storage capacitor wiring may be formed in the same layer (metal layer) as the data signal line and extended in the column direction (vertical direction in the figure).

  For example, in FIG. 34, the storage capacitor line Csz extending in the column direction is provided in the metal layer so as to overlap the gap between the pixel electrodes 17a and 17b and the gap between the pixel electrodes 17c and 17d, and the storage capacitor line Csz and the pixel electrode 17a. A storage capacitor is formed in an overlapping portion with each of 17b, 17c, and 17d, and the storage capacitor wiring CsZ extending in the column direction is overlapped with the gap between the pixel electrodes 17A and 17B and the gap between the pixel electrodes 17C and 17D. A storage capacitor is formed in an overlapping portion of the storage capacitor wiring CsZ and the pixel electrodes 17A, 17B, 17C, and 17D. By adopting such a configuration, it is possible to efficiently hide the liquid crystal alignment disorder and light leakage between the pixel electrodes. Then, the black matrix provided on the color filter substrate side corresponding to the space between the pixel electrodes can be reduced or omitted, so that the aperture ratio can be increased. Note that in the structure shown in FIG. 34, the channel protective film (interlayer insulating film) can be formed using only an inorganic insulating film in order to secure a storage capacitor.

In the driving method of the liquid crystal panel 5a shown in FIG. 2 , a low gradation data signal is supplied to each data signal line during two selection periods, and a high gradation data signal is supplied to each data signal line during one selection period. It is not limited to this. As shown in FIG. 8, a high gradation data signal may be supplied to each data signal line during two selection periods, and a low gradation data signal may be supplied to each data signal line during one selection period.

  In this case, as shown in FIG. 9, in two consecutive horizontal scanning periods H1 to H3, two scanning signal lines Gn · G (n + 1) are selected (made active) in the two selection periods H1. . As a result, as shown in FIGS. 1, 8, and 9, a positive precharge signal (high gradation) is written to the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx via the transistor, and the transistor is turned on. A negative precharge signal (high gradation) is written to the pixel electrode 17d connected to the scanning signal line Gn and the data signal line Sy via the transistor, and connected to the scanning signal line G (n + 1) and the data signal line Sx via a transistor. A positive high gradation data signal is written to the pixel electrode 17c to be written, and a negative high gradation data signal is written to the pixel electrode 17f connected to the scanning signal line G (n + 1) and the data signal line Sy through the transistor. In addition, a negative precharge signal (high gradation) is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX through the transistor, and is applied to the scanning signal line Gn and the data signal line SY through the transistor. A positive precharge signal (high gradation) is written to the connected pixel electrode 17D, and a negative high gradation data signal is applied to the pixel electrode 17C connected to the scanning signal line G (n + 1) and the data signal line SX via the transistor. Is written, and a positive high gradation data signal is written to the pixel electrode 17F connected to the scanning signal line G (n + 1) and the data signal line SY through the transistor.

  Next, in the single selection period of H1, it is assumed that the scanning signal line G (n + 1) is not selected and only the scanning signal line Gn is selected. As a result, as shown in FIGS. 1, 8, and 9, a positive low gradation data signal is written to the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx through the transistor, A negative low gradation data signal is written to the pixel electrode 17d connected to the scanning signal line Gn and the data signal line Sy. Further, a negative low gradation data signal is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX through the transistor, and is connected to the scanning signal line Gn and the data signal line SY through the transistor. A positive low gradation data signal is written to the pixel electrode 17D.

  From the above, the subpixels corresponding to the pixel electrodes 17a, 17c, 17d, 17f, 17A, 17C, 17D, and 17F are the dark subpixel (+), the bright subpixel (+), the dark subpixel (−), and the bright subpixel. Sub-pixel (−), dark sub-pixel (−), bright sub-pixel (−), dark sub-pixel (+), and bright sub-pixel (+).

  Further, in the two selection period H2, two scanning signal lines G (n + 2) · G (n + 3) are selected (made active). As a result, as shown in FIGS. 1, 8, and 10, a negative precharge signal (high gradation) is written to the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor. A positive precharge signal (high gradation) is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy via the transistor, and the scanning signal line G (n + 3) and the pixel signal 17h are connected via the transistor. A negative high gradation data signal is written to the pixel electrode 17g connected to the data signal line Sx, and positive high gradation data is applied to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line Sy via the transistor. A signal is written. Further, a positive precharge signal (high gradation) is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX through the transistor, and the scanning signal line G (n + 2) is passed through the transistor. A negative precharge signal (high gradation) is written to the pixel electrode 17H connected to the data signal line SY, and the pixel electrode 17G connected to the scanning signal line G (n + 3) and the data signal line SX via the transistor is written. A positive high gradation data signal is written, and a negative high gradation data signal is written to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line SY through the transistor.

  Next, in the single selection period of H2, the scanning signal line G (n + 3) is not selected and only the scanning signal line G (n + 2) is selected. As a result, as shown in FIGS. 1, 8, and 10, a negative low gradation data signal is written to the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor, and the transistor A positive low gradation data signal is written into the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy via the. Further, a positive low gradation data signal is written into the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX through the transistor, and the scanning signal line G (n + 2) and the data are transmitted through the transistor. A negative low gradation data signal is written to the pixel electrode 17H connected to the signal line SY.

  From the above, the subpixels corresponding to the pixel electrodes 17e, 17g, 17h, 17E, 17G, and 17H are the dark subpixel (−), the bright subpixel (−), the dark subpixel (+), and the dark subpixel (+ ), Bright subpixel (+), and dark subpixel (-).

  Further, in the two selection period of H3, two scanning signal lines G (n + 4) · G (n + 5) are selected, and in the next selection period of H3, the scanning signal line G (n + 5) is not selected, Only the scanning signal line G (n + 4) is selected. The state of H3 is as shown in FIG.

  In the driving method of FIG. 8, the scanning signal lines are selected two by two, and the dark sub-pixels connected to the even-numbered scanning signal lines (Gn · G (n + 2). Since the data signal can be written in one selection period after charging, the charging time of the dark sub-pixel can be substantially doubled during normal driving. Further, the two selection period for writing the data signal to the bright sub-pixel connected to the odd-numbered scanning signal lines (G (n + 1) · G (n + 3)...) Is set longer than the one selection period. Therefore, during normal driving, the charging time of the bright subpixel can be extended. Accordingly, it is suitable for a large-sized high-definition liquid crystal display device and a liquid crystal display device driven at a high speed (driving at 60 Hz or more). In the driving method of FIG. 8, pixel electrodes 17a, 17d, 17A, and 17D (dark pixel electrodes) connected to even-numbered scanning signal lines (Gn · G (n + 2)...) As shown in FIG. This is suitable when the area is larger than the pixel electrodes 17b, 17c, 17B, and 17C (bright pixel electrodes) connected to the odd-numbered scanning signal lines (G (n + 1) · G (n + 3)...). This is because the charging time of a dark pixel electrode having a large area (which is difficult to charge) is doubled (during normal driving), and an overshoot effect is obtained by writing a low gradation data signal after precharging with a high gradation data signal. It is also possible to expect. The area of the dark pixel electrode is preferably 1 to 4, where the area of the bright pixel electrode is 1.

In the driving method of the liquid crystal panel 5a shown in FIG. 2 , data signals having the same polarity are supplied to two adjacent data signal lines (for example, Sy and SX) corresponding to different pixel columns, respectively. Although the polarity of the data signal supplied to is inverted every horizontal scanning period (1H), the present invention is not limited to this. As shown in FIG. 13, data signals having opposite polarities are supplied to two adjacent data signal lines (for example, Sy and SX) corresponding to different pixel columns, and the data supplied to each data signal line. The polarity of the signal may be inverted every one vertical scanning period (one frame period). Note that data signals having opposite polarities are supplied to two data signal lines corresponding to one pixel column.

  For example, in three consecutive horizontal scanning periods h1 to h3, two scanning signal lines Gn · G (n + 1) are selected in the two selection periods h1 (see FIGS. 13 and 14). As a result, as shown in FIGS. 1, 13, and 14, a positive precharge signal (low gradation) is written into the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx through the transistor, and the transistor A negative precharge signal (low gradation) is written to the pixel electrode 17d connected to the scanning signal line Gn and the data signal line Sy through the transistor, and the scanning signal line G (n + 1) and the data signal line Sx are transmitted through the transistor. A positive low gradation data signal is written to the pixel electrode 17c connected to the pixel electrode 17 and a negative low gradation data signal is applied to the pixel electrode 17f connected to the scanning signal line G (n + 1) and the data signal line Sy via the transistor. Is written. In addition, a negative precharge signal (low gradation) is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX through the transistor, and the scanning signal line Gn and the data signal line SY through the transistor. A positive precharge signal (low gradation) is written to the pixel electrode 17D connected to the pixel electrode 17D, and a negative lower order is applied to the pixel electrode 17C connected to the scanning signal line G (n + 1) and the data signal line SX via the transistor. A tone data signal is written, and a positive low gradation data signal is written to the pixel electrode 17F connected to the scanning signal line G (n + 1) and the data signal line SY via a transistor.

  Next, in the single selection period h1, it is assumed that the scanning signal line G (n + 1) is not selected and only the scanning signal line Gn is selected. As a result, as shown in FIGS. 1, 13, and 14, a positive high gradation data signal is written to the pixel electrode 17a connected to the scanning signal line Gn and the data signal line Sx via the transistor, and scanning is performed via the transistor. A negative high gradation data signal is written to the pixel electrode 17d connected to the signal line Gn and the data signal line Sy. Further, a negative high gradation data signal is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX via the transistor, and the pixel connected to the scanning signal line Gn and the data signal line SY via the transistor. A positive high gradation data signal is written to the electrode 17D.

  From the above, the subpixels corresponding to the pixel electrodes 17a, 17c, 17d, 17f, 17A, 17C, 17D, and 17F are the bright subpixel (+), the dark subpixel (+), the bright subpixel (−), and the dark subpixel. Sub-pixel (-), bright sub-pixel (-), dark sub-pixel (-), bright sub-pixel (+), and dark sub-pixel (+).

  In addition, in the two selection period h2, two scanning signal lines G (n + 2) · G (n + 3) are selected (see FIGS. 13 and 15). Thereby, as shown in FIGS. 1, 13, and 15, a positive precharge signal (low gradation) is written to the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor. Then, a negative precharge signal (low gradation) is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy via the transistor, and the scanning signal line G (n + 3) is passed via the transistor. ) And the pixel electrode 17g connected to the data signal line Sx is written with a positive low gradation data signal, and the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line Sy via the transistor is negative. A low gradation data signal is written. Further, a positive precharge signal (low gradation) is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX via the transistor, and the scanning signal line G (n + 2) is passed via the transistor. ) And the pixel electrode 17H connected to the data signal line SY is written with a negative precharge signal (low gradation), and the pixel electrode 17G connected to the scanning signal line G (n + 3) and the data signal line SX through the transistor. A positive low gradation data signal is written to the pixel electrode, and a negative low gradation data signal is written to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line SY through the transistor.

  Next, in the single selection period h2, it is assumed that the scanning signal line G (n + 3) is not selected and only the scanning signal line G (n + 2) is selected. As a result, as shown in FIGS. 1, 13, and 15, a positive high gradation data signal is written to the pixel electrode 17e connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor, and the transistor is turned on. A negative high gradation data signal is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy. Further, a positive high gradation data signal is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX through the transistor, and the scanning signal line G (n + 2) and the data signal are written through the transistor. A negative high gradation data signal is written to the pixel electrode 17H connected to the line SY.

  From the above, the subpixels corresponding to the pixel electrodes 17e, 17g, 17h, 17E, 17G, and 17H are the bright subpixel (+), the dark subpixel (+), the bright subpixel (−), and the bright subpixel (+ ), Dark subpixel (+), and bright subpixel (-).

  Further, in the two selection period h3, two scanning signal lines G (n + 4) · G (n + 5) are selected, and then in the one selection period h3, the scanning signal line G (n + 5) is not selected. Only the scanning signal line G (n + 4) is selected. The state of h3 is as shown in FIG.

  In the driving methods shown in FIGS. 13 to 16, since the polarity of the data signal supplied to the same data signal line does not change during one vertical scanning period, it is compared with the case where the polarity of the data signal is inverted in one horizontal scanning period. Thus, the power consumption of the source driver can be suppressed. In addition, when displaying halftones, bright sub-pixels and dark sub-pixels are alternately arranged in the row direction and the column direction (bright and dark sub-pixels are arranged in a checkered pattern), and line-like unevenness is difficult to be visually recognized. There is also an effect of becoming.

[Embodiment 2]
FIG. 17 is an equivalent circuit diagram showing a part of the liquid crystal panel 5b. In the liquid crystal panel 5b, two pixel electrodes are arranged along the column direction in each pixel, and belong to the same pixel column, and two pixel electrodes that are connected to the same scanning signal line through transistors are adjacent to each other. ing. The rest is the same as FIG.

  For example, in the pixel 101, two pixel electrodes 17a and 17b are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12a connected to the scanning signal line G (n−1) is the pixel electrode 17a. The drain electrode of the transistor 12b connected to the scanning signal line Gn is connected to the pixel electrode 17b, the source electrode of the transistor 12a is connected to the data signal line Sy, and the source electrode of the transistor 12b is connected to the data signal line Connected to Sx.

  In the pixel 102 adjacent to the pixel 101 in the column direction, two pixel electrodes 17c and 17d are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12c connected to the scanning signal line Gn is provided. The drain electrode of the transistor 12d connected to the pixel electrode 17c, connected to the scanning signal line G (n + 1), is connected to the pixel electrode 17d, and the source electrode of the transistor 12c is connected to the data signal line Sy. The source electrode is connected to the data signal line Sx.

  Further, in the pixel 103 adjacent to the pixel 102 in the column direction, two pixel electrodes 17e and 17f are arranged in this order along the column direction (scanning direction), and the transistor 12e connected to the scanning signal line G (n + 1) The drain electrode is connected to the pixel electrode 17e, the drain electrode of the transistor 12f connected to the scanning signal line G (n + 2) is connected to the pixel electrode 17f, and the source electrode of the transistor 12e is connected to the data signal line Sy. The source electrode of the transistor 12f is connected to the data signal line Sx.

  Further, in the pixel 104 adjacent to the pixel 103 in the column direction, two pixel electrodes 17g and 17h are arranged in this order along the column direction (scanning direction), and the transistor 12g connected to the scanning signal line G (n + 2) The drain electrode is connected to the pixel electrode 17g, the drain electrode of the transistor 12h connected to the scanning signal line G (n + 3) is connected to the pixel electrode 17h, and the source electrode of the transistor 12g is connected to the data signal line Sy. The source electrode of the transistor 12h is connected to the data signal line Sx.

  In the pixel 105 adjacent to the pixel 101 in the row direction, two pixel electrodes 17A and 17B are arranged in this order along the column direction (scanning direction) and connected to the scanning signal line G (n−1). The drain electrode of 12A is connected to the pixel electrode 17A, the drain electrode of the transistor 12B connected to the scanning signal line Gn is connected to the pixel electrode 17B, and the source electrode of the transistor 12A is connected to the data signal line SY. The 12B source electrode is connected to the data signal line SX.

  In the pixel 106 adjacent to the pixel 102 in the row direction, two pixel electrodes 17C and 17D are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12C connected to the scanning signal line Gn is provided. The drain electrode of the transistor 12D connected to the pixel electrode 17C, connected to the scanning signal line G (n + 1), is connected to the pixel electrode 17D, and the source electrode of the transistor 12C is connected to the data signal line SY. The source electrode is connected to the data signal line SX.

  Further, in the pixel 107 adjacent to the pixel 103 in the row direction, two pixel electrodes 17E and 17F are arranged in this order along the column direction (scanning direction), and the transistor 12E connected to the scanning signal line G (n + 1) The drain electrode is connected to the pixel electrode 17E, the drain electrode of the transistor 12F connected to the scanning signal line G (n + 2) is connected to the pixel electrode 17F, and the source electrode of the transistor 12E is connected to the data signal line SY. A source electrode of the transistor 12F is connected to the data signal line SX.

  Further, in the pixel 108 adjacent to the pixel 104 in the row direction, two pixel electrodes 17G and 17H are arranged in this order along the column direction (scanning direction), and the transistor 12G connected to the scanning signal line G (n + 2) The drain electrode is connected to the pixel electrode 17G, the drain electrode of the transistor 12H connected to the scanning signal line G (n + 3) is connected to the pixel electrode 17H, and the source electrode of the transistor 12G is connected to the data signal line SY. The source electrode of the transistor 12H is connected to the data signal line SX.

19 to 21 show a driving method in the case where halftone display is performed on a part of the liquid crystal panel 5b (7 pixel rows including the 4 pixel row in FIG. 17) in three horizontal scanning periods that are continuous every horizontal scanning period. It is a schematic diagram which shows a minute (H1-H3). FIG. 18 is a timing chart (for two frames) showing a driving method when halftone display is performed on a part of the liquid crystal panel 5b.

  In the driving method shown in FIGS. 18 to 21, the scanning signal lines are sequentially selected two by two. In one horizontal scanning period, two scanning signal lines are selected at the same time, and the two scanning signal lines are selected. Following the selection period, one selection period in which one of the two scanning signal lines is not selected is included. Further, at the time of halftone display, a low gradation data signal is supplied to each data signal line during two selection periods, and a high gradation data signal is supplied to each data signal line during one selection period. In addition, data signals having opposite polarities are supplied to two data signal lines corresponding to one pixel column. In addition, data signals having the same polarity are supplied to two adjacent data signal lines (for example, Sy · SX) corresponding to different pixel columns. Note that the polarity of the data signal supplied to each data signal line is inverted every vertical scanning period (one frame).

For example, in three consecutive horizontal scanning periods H1 to H3, two scanning signal lines Gn · G (n + 1) are selected in the two selection periods H1 (see FIGS. 18 and 19 ). As a result, as shown in FIGS. 17, 18, and 19 , a positive precharge signal (low gradation) is written to the pixel electrode 17b connected to the scanning signal line Gn and the data signal line Sx via the transistor. A negative precharge signal (low gradation) is written into the pixel electrode 17c connected to the scanning signal line Gn and the data signal line Sy through the transistor, and the scanning signal line G (n + 1) and the data signal line Sx are transmitted through the transistor. A positive low gradation data signal is written to the pixel electrode 17d connected to the pixel electrode 17 and a negative low gradation data signal is applied to the pixel electrode 17e connected to the scanning signal line G (n + 1) and the data signal line Sy via the transistor. Is written. Further, a negative precharge signal (low gradation) is written to the pixel electrode 17B connected to the scanning signal line Gn and the data signal line SX via the transistor, and the scanning signal line Gn and the data signal line SY are passed via the transistor. A positive precharge signal (low gradation) is written to the pixel electrode 17C connected to the pixel electrode 17C, and a negative lower order is applied to the pixel electrode 17D connected to the scanning signal line G (n + 1) and the data signal line SX via the transistor. A tone data signal is written, and a positive low gradation data signal is written to the pixel electrode 17E connected to the scanning signal line G (n + 1) and the data signal line SY through a transistor.

Next, in the single selection period of H1, it is assumed that the scanning signal line G (n + 1) is not selected and only the scanning signal line Gn is selected. As a result, as shown in FIGS. 17, 18, and 19 , a positive high gradation data signal is written to the pixel electrode 17b connected to the scanning signal line Gn and the data signal line Sx via the transistor, and scanning is performed via the transistor. A negative high gradation data signal is written into the pixel electrode 17c connected to the signal line Gn and the data signal line Sy. Further, a negative high gradation data signal is written into the pixel electrode 17B connected to the scanning signal line Gn and the data signal line SX through the transistor, and the pixel connected to the scanning signal line Gn and the data signal line SY through the transistor. A positive high gradation data signal is written to the electrode 17C.

  From the above, the subpixels corresponding to the pixel electrodes 17b, 17c, 17d, 17e, 17B, 17C, 17D, and 17E are the bright subpixel (+), the bright subpixel (−), the dark subpixel (+), and the dark subpixel. Sub-pixel (−), bright sub-pixel (−), bright sub-pixel (+), dark sub-pixel (−), and dark sub-pixel (+).

In the two selection period H2, two scanning signal lines G (n + 2) · G (n + 3) are selected (see FIGS. 18 and 20 ). As a result, as shown in FIGS. 17, 18, and 20 , a positive precharge signal (low gradation) is written to the pixel electrode 17f connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor. Then, a negative precharge signal (low gradation) is written to the pixel electrode 17g connected to the scanning signal line G (n + 2) and the data signal line Sy through the transistor, and the scanning signal line G (n + 3) is passed through the transistor. ) And the pixel electrode 17h connected to the data signal line Sx is written with a positive low gradation data signal, and the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line Sy via the transistor is negative. A low gradation data signal is written. Further, a negative precharge signal (low gradation) is written to the pixel electrode 17F connected to the scanning signal line G (n + 2) and the data signal line SX via the transistor, and the scanning signal line G (n + 2) is passed via the transistor. ) And the pixel electrode 17G connected to the data signal line SY is written with a positive precharge signal (low gradation), and the pixel electrode 17H connected to the scanning signal line G (n + 3) and the data signal line SX through the transistor. A negative low gradation data signal is written to the pixel electrode, and a positive low gradation data signal is written to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line SY through the transistor.

Next, in the single selection period of H2, the scanning signal line G (n + 3) is not selected and only the scanning signal line G (n + 2) is selected. As a result, as shown in FIGS. 17, 18, and 20 , a positive high gradation data signal is written to the pixel electrode 17f connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor, A negative high gradation data signal is written to the pixel electrode 17g connected to the scanning signal line G (n + 2) and the data signal line Sy. Further, a negative high gradation data signal is written to the pixel electrode 17F connected to the scanning signal line G (n + 2) and the data signal line SX via the transistor, and the scanning signal line G (n + 2) and the data signal are written via the transistor. A positive high gradation data signal is written to the pixel electrode 17G connected to the line SY.

  From the above, the subpixels corresponding to the pixel electrodes 17f, 17g, 17h, 17F, 17G, and 17H are the bright subpixel (+), the bright subpixel (−), the dark subpixel (+), and the bright subpixel (− ), Bright subpixel (+), and dark subpixel (-).

Further, in the two selection period of H3, two scanning signal lines G (n + 4) · G (n + 5) are selected, and in the next selection period of H3, the scanning signal line G (n + 5) is not selected, Only the scanning signal line G (n + 4) is selected. The state of H3 is as shown in FIG.

  Since the liquid crystal display device including the liquid crystal panel 5b is an individual writing type pixel division method, the viewing angle characteristics are good, and there is no pixel electrode that is electrically floating as compared with the capacitive coupling type. There are advantages that the reliability is high and that the brightness of the bright and dark sub-pixels can be accurately controlled.

  Then, the scanning signal lines are selected two by two, and the bright sub-pixel connected to the even-numbered scanning signal line (Gn · G (n + 2). Since the data signal can be written in the selection period, the charging time of the bright sub-pixel can be substantially doubled with normal driving. Further, the two selection period in which the data signal is written to the dark sub-pixel connected to the odd-numbered scanning signal lines (G (n + 1) · G (n + 3)...) Is set longer than the one selection period. For this reason, during normal driving, the charging time of the dark sub-pixel can be extended. Accordingly, it is suitable for a large-sized high-definition liquid crystal display device and a liquid crystal display device driven at a high speed (driving at 60 Hz or more).

  In addition, since the polarity of the data signal written on the screen is inverted in units of one subpixel in each of the row direction and the column direction, flickering of the screen can be suppressed.

  FIG. 22 is a plan view showing a configuration example of a part of the liquid crystal panel 5b shown in FIG. As shown in FIG. 22, the liquid crystal panel 5 b has a pixel electrode 17 a... In a region defined by the scanning signal line G (n−1), the scanning signal line Gn, and the data signal lines Sx / Sy in a plan view. 17b are arranged in this order along the column direction (scanning direction), and pixel electrodes 17A and 17B are formed in regions defined by the scanning signal line G (n-1), the scanning signal line Gn, and the data signal lines SX and SY. The pixel electrodes 17c and 17d are arranged in this order along the column direction (scanning direction), and the pixel electrodes 17c and 17d are arranged in the column direction (scanning) in a region defined by the scanning signal line Gn, the scanning signal line G (n + 1), and the data signal lines Sx and Sy. The pixel electrodes 17C and 17D are arranged in the column direction (scanning direction) in the region defined by the scanning signal line Gn, the scanning signal line G (n + 1), and the data signal lines SX and SY. Along the are arranged in this order. In addition, a storage capacitor line Cs (n−1) is arranged between the scanning signal line G (n−1) and the scanning signal line Gn, and a storage capacitor line is connected between the scanning signal line Gn and the scanning signal line G (n + 1). Csn is arranged.

  The scanning signal line G (n−1) is the gate electrode of the transistors 12b and 12B, the scanning signal line Gn is the gate electrode of the transistors 12a and 12A, and the scanning signal line G (n + 1) is the gate electrode of the transistors 12c and 12C. Function as. The source electrodes of the transistors 12a and 12c are connected to the data signal line Sx, the source electrodes of the transistors 12b and 12d are connected to the data signal line Sy, and the source electrodes of the transistors 12A and 12C are connected to the data signal line SX. In addition, the source electrodes of the transistors 12B and 12D are connected to the data signal line SY.

  Further, the drain electrode of the transistor 12a is connected to the pixel electrode 17a through the contact hole 11a, and the drain electrode of the transistor 12b is connected to the pixel electrode 17b through the contact hole 11b, and is connected to the storage capacitor wiring Cs (n−1). The overlapping capacitor electrode 67a and the pixel electrode 17a are connected via a contact hole 91a, and the capacitor electrode 67b and the pixel electrode 17b overlapping the storage capacitor wiring Cs (n-1) are connected via a contact hole 91b. Similarly, the drain electrode of the transistor 12A is connected to the pixel electrode 17A through the contact hole 11A, the drain electrode of the transistor 12B is connected to the pixel electrode 17B through the contact hole 11B, and the storage capacitor line Cs (n−1). The capacitor electrode 67A and the pixel electrode 17A that overlap each other are connected via the contact hole 91A, and the capacitor electrode 67B and the pixel electrode 17B that overlap the storage capacitor wiring Cs (n-1) are connected via the contact hole 91B. .

  Further, the drain electrode of the transistor 12c is connected to the pixel electrode 17c through the contact hole 11c, the drain electrode of the transistor 12d is connected to the pixel electrode 17d through the contact hole 11d, and the capacitor electrode 67c overlapping the storage capacitor wiring Csn. The pixel electrode 17c is connected through the contact hole 91c, and the capacitor electrode 67d and the pixel electrode 17d overlapping the storage capacitor wiring Csn are connected through the contact hole 91d. Similarly, the drain electrode of the transistor 12C is connected to the pixel electrode 17C through the contact hole 11C, the drain electrode of the transistor 12D is connected to the pixel electrode 17D through the contact hole 11D, and the capacitor electrode 67C that overlaps the storage capacitor wiring Csn. And the pixel electrode 17C are connected via a contact hole 91C, and the capacitor electrode 67D and the pixel electrode 17D overlapping the storage capacitor line Csn are connected via a contact hole 91D.

  The liquid crystal panel 5b of FIG. 17 can be modified as shown in FIG. In the liquid crystal panel 5c of FIG. 23, two pixel electrodes that belong to the same pixel region column and are connected to the same scanning signal line via transistors are arranged so as to sandwich another pixel electrode therebetween. . Further, two pixel electrodes belonging to the same pixel region row and connected to the same scanning signal line via the transistors are arranged diagonally opposite to each other.

  For example, in the pixel 101, two pixel electrodes 17a and 17b are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12a connected to the scanning signal line G (n−1) is the pixel electrode 17a. The drain electrode of the transistor 12b connected to the scanning signal line Gn is connected to the pixel electrode 17b, the source electrode of the transistor 12a is connected to the data signal line Sy, and the source electrode of the transistor 12b is connected to the data signal line Connected to Sx.

  In the pixel 102 adjacent to the pixel 101 in the column direction, two pixel electrodes 17c and 17d are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12c connected to the scanning signal line Gn is provided. Connected to the pixel electrode 17d, the drain electrode of the transistor 12d connected to the scanning signal line G (n + 1) is connected to the pixel electrode 17c, and the source electrode of the transistor 12c is connected to the data signal line Sy. The source electrode is connected to the data signal line Sx.

  Further, in the pixel 103 adjacent to the pixel 102 in the column direction, two pixel electrodes 17e and 17f are arranged in this order along the column direction (scanning direction), and the transistor 12e connected to the scanning signal line G (n + 1) The drain electrode is connected to the pixel electrode 17e, the drain electrode of the transistor 12f connected to the scanning signal line G (n + 2) is connected to the pixel electrode 17f, and the source electrode of the transistor 12e is connected to the data signal line Sy. The source electrode of the transistor 12f is connected to the data signal line Sx.

  Further, in the pixel 104 adjacent to the pixel 103 in the column direction, two pixel electrodes 17g and 17h are arranged in this order along the column direction (scanning direction), and the transistor 12g connected to the scanning signal line G (n + 2) The drain electrode is connected to the pixel electrode 17h, the drain electrode of the transistor 12h connected to the scanning signal line G (n + 3) is connected to the pixel electrode 17g, and the source electrode of the transistor 12g is connected to the data signal line Sy. The source electrode of the transistor 12h is connected to the data signal line Sx.

  In the pixel 105 adjacent to the pixel 101 in the row direction, two pixel electrodes 17A and 17B are arranged in this order along the column direction (scanning direction) and connected to the scanning signal line G (n−1). The drain electrode of 12A is connected to the pixel electrode 17B, the drain electrode of the transistor 12B connected to the scanning signal line Gn is connected to the pixel electrode 17A, and the source electrode of the transistor 12A is connected to the data signal line SY. The 12B source electrode is connected to the data signal line SX.

  In the pixel 106 adjacent to the pixel 102 in the row direction, two pixel electrodes 17C and 17D are arranged in this order along the column direction (scanning direction), and the drain electrode of the transistor 12C connected to the scanning signal line Gn is provided. The drain electrode of the transistor 12D connected to the pixel electrode 17C, connected to the scanning signal line G (n + 1), is connected to the pixel electrode 17D, and the source electrode of the transistor 12C is connected to the data signal line SY. The source electrode is connected to the data signal line SX.

  Further, in the pixel 107 adjacent to the pixel 103 in the row direction, two pixel electrodes 17E and 17F are arranged in this order along the column direction (scanning direction), and the transistor 12E connected to the scanning signal line G (n + 1) The drain electrode is connected to the pixel electrode 17F, the drain electrode of the transistor 12F connected to the scanning signal line G (n + 2) is connected to the pixel electrode 17E, and the source electrode of the transistor 12E is connected to the data signal line SY. A source electrode of the transistor 12F is connected to the data signal line SX.

  Further, in the pixel 108 adjacent to the pixel 104 in the row direction, two pixel electrodes 17G and 17H are arranged in this order along the column direction (scanning direction), and the transistor 12G connected to the scanning signal line G (n + 2) The drain electrode is connected to the pixel electrode 17G, the drain electrode of the transistor 12H connected to the scanning signal line G (n + 3) is connected to the pixel electrode 17H, and the source electrode of the transistor 12G is connected to the data signal line SY. The source electrode of the transistor 12H is connected to the data signal line SX.

25 to 27 show a driving method in the case where halftone display is performed on a part of the liquid crystal panel 5c (7 pixel rows including the 4 pixel rows in FIG. 23) in three horizontal scanning periods that are continuous every one horizontal scanning period. It is a schematic diagram which shows a minute (H1-H3). FIG. 24 is a timing chart (for two frames) showing a driving method when halftone display is performed on a part of the liquid crystal panel 5c.

  In the driving method shown in FIGS. 24 to 27, two scanning signal lines are sequentially selected. In one horizontal scanning period, two scanning signal lines are simultaneously selected and the two scanning signal lines are selected. Following the selection period, one selection period in which one of the two scanning signal lines is not selected is included. Further, at the time of halftone display, a low gradation data signal is supplied to each data signal line during two selection periods, and a high gradation data signal is supplied to each data signal line during one selection period. In addition, data signals having opposite polarities are supplied to two data signal lines corresponding to one pixel column. In addition, data signals having opposite polarities are supplied to two adjacent data signal lines (for example, Sy and SX) corresponding to different pixel columns. Note that the polarity of the data signal supplied to each data signal line is inverted every vertical scanning period (one frame).

For example, in three consecutive horizontal scanning periods H1 to H3, two scanning signal lines Gn · G (n + 1) are selected in the two selection periods H1 (see FIGS. 24 and 25 ). As a result, as shown in FIGS. 23, 24, and 25 , a positive precharge signal (low gradation) is written to the pixel electrode 17b connected to the scanning signal line Gn and the data signal line Sx via the transistor. A negative precharge signal (low gradation) is written to the pixel electrode 17d connected to the scanning signal line Gn and the data signal line Sy through the transistor, and the scanning signal line G (n + 1) and the data signal line Sx are transmitted through the transistor. A positive low gradation data signal is written to the pixel electrode 17c connected to the pixel electrode 17 and a negative low gradation data signal is applied to the pixel electrode 17e connected to the scanning signal line G (n + 1) and the data signal line Sy via the transistor. Is written. Further, a positive precharge signal (low gradation) is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX via the transistor, and the scanning signal line Gn and the data signal line SY are passed via the transistor. A negative precharge signal (low gradation) is written in the pixel electrode 17C connected to the pixel electrode 17C, and a positive lower floor is applied to the pixel electrode 17D connected to the scanning signal line G (n + 1) and the data signal line SX via the transistor. The tone data signal is written, and a negative low gradation data signal is written to the pixel electrode 17F connected to the scanning signal line G (n + 1) and the data signal line SY through the transistor.

Next, in the single selection period of H1, it is assumed that the scanning signal line G (n + 1) is not selected and only the scanning signal line Gn is selected. As a result, as shown in FIGS. 23, 24, and 25 , a positive high gradation data signal is written to the pixel electrode 17b connected to the scanning signal line Gn and the data signal line Sx via the transistor, and scanning is performed via the transistor. A negative high gradation data signal is written to the pixel electrode 17d connected to the signal line Gn and the data signal line Sy. Further, a positive high gradation data signal is written to the pixel electrode 17A connected to the scanning signal line Gn and the data signal line SX via the transistor, and the pixel connected to the scanning signal line Gn and the data signal line SY via the transistor. A negative high gradation data signal is written to the electrode 17C.

  From the above, the subpixels corresponding to the pixel electrodes 17b, 17c, 17d, 17e, 17A, 17C, 17D, and 17F are the bright subpixel (+), the dark subpixel (+), the bright subpixel (−), and the dark subpixel. Sub-pixel (-), bright sub-pixel (+), bright sub-pixel (-), dark sub-pixel (+), dark sub-pixel (-).

In the two selection period H2, two scanning signal lines G (n + 2) · G (n + 3) are selected (see FIGS. 24 and 26 ). As a result, as shown in FIGS. 23, 24, and 26 , a positive precharge signal (low gradation) is written to the pixel electrode 17f connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor. Then, a negative precharge signal (low gradation) is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy via the transistor, and the scanning signal line G (n + 3) is passed via the transistor. ) And the pixel electrode 17g connected to the data signal line Sx is written with a positive low gradation data signal, and the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line Sy via the transistor is negative. A low gradation data signal is written. Further, a positive precharge signal (low gradation) is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX via the transistor, and the scanning signal line G (n + 2) is passed via the transistor. ) And the pixel electrode 17G connected to the data signal line SY is written with a negative precharge signal (low gradation), and the pixel electrode 17H connected to the scanning signal line G (n + 3) and the data signal line SX through the transistor. A positive low gradation data signal is written to the pixel electrode, and a positive low gradation data signal is written to the pixel electrode connected to the scanning signal line G (n + 3) and the data signal line SY through the transistor.

Next, in the single selection period of H2, the scanning signal line G (n + 3) is not selected and only the scanning signal line G (n + 2) is selected. As a result, as shown in FIGS. 23, 24, and 26 , a positive high gradation data signal is written to the pixel electrode 17f connected to the scanning signal line G (n + 2) and the data signal line Sx through the transistor, and the transistor is turned on. A negative high gradation data signal is written to the pixel electrode 17h connected to the scanning signal line G (n + 2) and the data signal line Sy. Further, a positive high gradation data signal is written to the pixel electrode 17E connected to the scanning signal line G (n + 2) and the data signal line SX through the transistor, and the scanning signal line G (n + 2) and the data signal are written through the transistor. A negative high gradation data signal is written to the pixel electrode 17G connected to the line SY.

  From the above, the subpixels corresponding to the pixel electrodes 17f, 17g, 17h, 17E, 17G, and 17H are the bright subpixel (+), the dark subpixel (+), the bright subpixel (−), and the bright subpixel (+ ), Bright subpixel (-), and dark subpixel (+).

Further, in the two selection period of H3, two scanning signal lines G (n + 4) · G (n + 5) are selected, and in the next selection period of H3, the scanning signal line G (n + 5) is not selected, Only the scanning signal line G (n + 4) is selected. The state of H3 is as shown in FIG.

  In the liquid crystal panel 5c, when displaying the halftone, the bright sub-pixels and the dark sub-pixels are alternately arranged in the row direction and the column direction (the bright / dark sub-pixels are arranged in a checkered pattern), and the line-shaped unevenness is visually recognized. There is an effect that it becomes difficult to be done.

  Further, since the polarity of the data signal supplied to the same data signal line does not change during one vertical scanning period, the power consumption of the source driver is suppressed compared to the case where the polarity of the data signal is inverted in one horizontal scanning period. be able to.

  In addition, since the polarity of the data signal written on the screen is inverted in units of two subpixels in each of the row direction and the column direction, flickering of the screen can be suppressed.

  FIG. 28 is a circuit diagram showing a configuration of a gate driver of the present liquid crystal display device, and FIG. 35 is a timing chart showing a driving method of the gate driver. As shown in FIG. 28, the gate driver GD includes a shift register 45, a plurality of AND circuits (66x to 66z) arranged in the column direction, and an output circuit 46. The shift register 45 receives a gate star, a pulse signal GSP, and a gate clock signal GCK. Each AND circuit (66x to 66z) receives an inverted signal of the GOE signal (see FIG. 35) that becomes “H” during one selection period of each horizontal scanning period. The output of each stage of the shift register 45 is divided into two systems, one of which becomes a scanning signal through the output circuit 46, the other is inputted to one AND circuit, and the output of this AND circuit scans through the output circuit 46. Signal.

  For example, the output from a stage of the shift register 45 is divided into two systems (Q0 and Q1), Q0 becomes a scanning signal supplied to the scanning signal line Gn via the output circuit 46, and Q1 is input to the AND circuit 66x. Then, the output of the AND circuit 66x becomes a scanning signal supplied to the scanning signal line G (n + 1) via the output circuit 46. The output from the other stage of the shift register 45 is divided into two systems (Q2 and Q3), Q2 becomes a scanning signal supplied to the scanning signal line G (n + 2) through the output circuit 46, and Q3 is AND. The signal is input to the circuit 66y, and the output of the AND circuit 66y becomes a scanning signal supplied to the scanning signal line G (n + 3) via the output circuit 46.

  As shown in FIG. 28 and FIG. 35, this gate driver can generate a scanning signal to be supplied to each of two scanning signal lines to be simultaneously selected using an output from the same stage of one shift register. There is an advantage that the gate driver configuration can be simplified.

  In the present embodiment, the present liquid crystal display unit and the liquid crystal display device are configured as follows. That is, the two polarizing plates A and B are attached to both surfaces of the liquid crystal panels (5a to 5f) so that the polarizing axes of the polarizing plates A and B are orthogonal to each other. In addition, you may laminate | stack an optical compensation sheet etc. on a polarizing plate as needed. Next, as shown in FIG. 29A, drivers (gate driver 202, source driver 201) are connected. Here, as an example, connection of a driver using a TCP (Tape Career Package) method will be described. First, an ACF (Anisotropic Conductive Film) is temporarily bonded to the terminal portion of the liquid crystal panel. Next, the TCP on which the driver is placed is punched out of the carrier tape, aligned with the panel terminal electrode, and heated and pressed. Thereafter, a circuit board 203 (PWB: Printed wiring board) for connecting the driver TCPs to the TCP input terminal is connected by an ACF. Thereby, the liquid crystal display unit 200 is completed. After that, as shown in FIG. 29B, a display control circuit 209 is connected to each driver (201, 202) of the liquid crystal display unit via the circuit board 203, and integrated with the lighting device (backlight unit) 204. As a result, the liquid crystal display device 210 is obtained.

  The “polarity of potential” as used in the present application means a potential that is greater than or equal to a reference potential (plus) or less than or equal to a reference potential (minus). Here, the reference potential may be Vcom (common potential) which is the potential of the common electrode (counter electrode) or any other potential.

  FIG. 30 is a block diagram showing a configuration of the present liquid crystal display device. As shown in the figure, the liquid crystal display device includes a display unit (liquid crystal panel), a source driver (SD), a gate driver (GD), and a display control circuit. The source driver drives the data signal line, the gate driver drives the scanning signal line, and the display control circuit controls the source driver and the gate driver.

  The display control circuit controls a display operation from a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv from an external signal source (for example, a tuner). For receiving the control signal Dc. Further, the display control circuit, based on the received signals Dv, HSY, VSY, and Dc, uses a data start pulse signal SSP and a data clock as signals for displaying an image represented by the digital video signal Dv on the display unit. A signal SCK, a charge share signal sh, a digital image signal DA representing the image to be displayed (a signal corresponding to the video signal Dv), a gate start pulse signal GSP, a gate clock signal GCK, and a gate driver output control signal ( A scanning signal output control signal (GOE) is generated and output.

  More specifically, after adjusting the timing of the video signal Dv in the internal memory as necessary, the video signal Dv is output as a digital image signal DA from the display control circuit, and a pulse corresponding to each pixel of the image represented by the digital image signal DA. A data clock signal SCK is generated as a signal consisting of the above, a data start pulse signal SSP is generated as a signal that becomes high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY, and the vertical synchronization signal VSY The gate start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every one frame period (one vertical scanning period), and the gate clock signal GCK is generated based on the horizontal synchronization signal HSY, and the horizontal synchronization signal HSY and Charge share signal sh based on control signal Dc, and gate driver It generates a force control signal GOE.

  Of the signals generated in the display control circuit as described above, the digital image signal DA, the charge share signal sh, the signal POL for controlling the polarity of the signal potential (data signal potential), the data start pulse signal SSP, and the data clock The signal SCK is input to the source driver, and the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver.

  The source driver corresponds to the pixel value in each scanning signal line of the image represented by the digital image signal DA based on the digital image signal DA, the data clock signal SCK, the charge share signal sh, the data start pulse signal SSP, and the polarity inversion signal POL. The analog potential (signal potential) to be generated is sequentially generated for each horizontal scanning period, and these data signals are output to the data signal lines (for example, Sx · Sy).

  The gate driver generates a gate-on pulse signal based on the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE, and outputs these signals to the scanning signal line. Select one by one sequentially.

  Next, a configuration example when the present liquid crystal display device is applied to a television receiver will be described. FIG. 31 is a block diagram showing a configuration of a liquid crystal display device 800 for a television receiver. The liquid crystal display device 800 includes a liquid crystal display unit 84, a Y / C separation circuit 80, a video chroma circuit 81, an A / D converter 82, a liquid crystal controller 83, a backlight drive circuit 85, a backlight 86, A microcomputer 87 and a gradation circuit 88 are provided. The liquid crystal display unit 84 includes a liquid crystal panel and a source driver and a gate driver for driving the liquid crystal panel.

  In the liquid crystal display device 800 having the above configuration, first, a composite color video signal Scv as a television signal is inputted from the outside to the Y / C separation circuit 80, where it is separated into a luminance signal and a color signal. These luminance signals and color signals are converted into analog RGB signals corresponding to the three primary colors of light by the video chroma circuit 81, and further, the analog RGB signals are converted into digital RGB signals by the A / D converter 82. . This digital RGB signal is input to the liquid crystal controller 83. The Y / C separation circuit 80 also extracts horizontal and vertical synchronization signals from the composite color video signal Scv input from the outside, and these synchronization signals are also input to the liquid crystal controller 83 via the microcomputer 87.

  A digital RGB signal is input from the liquid crystal controller 83 to the liquid crystal display unit 84 at a predetermined timing together with a timing signal based on the synchronization signal. The gradation circuit 88 generates gradation potentials for the three primary colors R, G, and B for color display, and these gradation potentials are also supplied to the liquid crystal display unit 84. In the liquid crystal display unit 84, a driving signal (data signal = signal potential, scanning signal, etc.) is generated by an internal source driver, gate driver, or the like based on the RGB signal, timing signal, and gradation potential, and these driving signals are used. Based on the signal, a color image is displayed on the internal liquid crystal panel. In order to display an image by the liquid crystal display unit 84, it is necessary to irradiate light from behind the liquid crystal panel in the liquid crystal display unit. In the liquid crystal display device 800, the backlight drive is performed under the control of the microcomputer 87. The circuit 85 drives the backlight 86, so that light is irradiated to the back surface of the liquid crystal panel. The microcomputer 87 controls the entire system including the above processing. The video signal (composite color video signal) input from the outside includes not only a video signal based on television broadcasting but also a video signal captured by a camera, a video signal supplied via an Internet line, and the like. The liquid crystal display device 800 can display images based on various video signals.

  When an image based on television broadcasting is displayed on the liquid crystal display device 800, as shown in FIG. 32, a tuner unit 90 is connected to the liquid crystal display device 800, thereby configuring the television receiver 601. The tuner unit 90 extracts a signal of a channel to be received from a received wave (high frequency signal) received by an antenna (not shown), converts the signal to an intermediate frequency signal, and detects the intermediate frequency signal, thereby detecting the television. A composite color video signal Scv as a signal is taken out. The composite color video signal Scv is input to the liquid crystal display device 800 as described above, and an image based on the composite color video signal Scv is displayed by the liquid crystal display device 800.

  FIG. 33 is an exploded perspective view showing a configuration example of the present television receiver. As shown in the figure, the present television receiver 601 includes a first casing 801 and a second casing 806 in addition to the liquid crystal display device 800 as its constituent elements. It is configured to be sandwiched between one housing 801 and a second housing 806. The first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 800 is transmitted. The second housing 806 covers the back side of the liquid crystal display device 800, is provided with an operation circuit 805 for operating the display device 800, and a support member 808 is attached below. Yes.

  The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.

  As described above, the present active matrix substrate includes a plurality of data signal lines and a plurality of scanning signal lines, a plurality of pixel electrodes are provided in each pixel region, and the extending direction of each data signal line is a column direction. Two data signal lines are provided corresponding to one pixel area column, and one pixel electrode of the pixel area included in the pixel area column is connected to the two data lines via a transistor connected to the scanning signal line. Another pixel electrode of the pixel region connected to one of the data signal lines is connected to the other of the two data signal lines via a transistor connected to another scanning signal line, and the pixel region column Regarding two adjacent pixel regions, one of the pixel electrodes included in one and one of the pixel electrodes included in the other are each connected to the same scanning signal line through a transistor.

  In the liquid crystal display device provided with the active matrix substrate, individual writing can be performed on a plurality of pixel electrodes provided in one pixel region while selecting two scanning signal lines at a time. The pixel charging time can be extended.

  In this liquid crystal display device, two pixel electrodes may be arranged in the row direction in each pixel region.

  In this active matrix substrate, two pixel electrodes that belong to the same pixel region column and are connected to the same scanning signal line through transistors can be arranged obliquely opposite each other.

  In the present active matrix substrate, two pixel electrodes may be arranged in the column direction in each pixel region.

  In the present active matrix substrate, two pixel electrodes belonging to the same pixel region column and connected to the same scanning signal line through transistors are arranged so as to sandwich another pixel electrode therebetween. You can also

  In the present active matrix substrate, two pixel electrodes belonging to the same pixel region row and connected to the same scanning signal line through transistors may be arranged obliquely opposite each other.

  The liquid crystal panel includes the active matrix substrate.

  The liquid crystal display device includes the active matrix substrate.

  This liquid crystal display device can be configured to sequentially select two scanning signal lines.

  In the present liquid crystal display device, in one horizontal scanning period, two scanning signal lines are selected simultaneously, and one scanning signal line is selected following the two selection period. A period may be included.

  In the present liquid crystal display device, at the time of halftone display, a relatively low gradation data signal is supplied to each data signal line in the two selection period, and a relatively high gradation data signal is supplied to each data in the one selection period. It can also be configured to be supplied to the signal line.

  In the present liquid crystal display device, during halftone display, a relatively high gradation data signal is supplied to each data signal line during two selection periods, and a relatively low gradation data signal is supplied to each data signal during one selection period. It can also be configured to be supplied to the signal line.

  In the present liquid crystal display device, the pixel electrode connected to the scanning signal line selected in the single selection period via the transistor is more than the pixel electrode connected to the scanning signal line not selected in the single selection period via the transistor. Also, the area can be large.

  In the present liquid crystal display device, a data signal having a reverse polarity may be supplied to two data signal lines corresponding to one pixel region column.

  In the present liquid crystal display device, a data signal whose polarity is inverted every horizontal scanning period may be supplied to each data signal line.

  In the present liquid crystal display device, a data signal whose polarity is inverted every vertical scanning period can be supplied to each data signal line.

  In the present liquid crystal display device, data signals having opposite polarities may be supplied to data signal lines adjacent to each other corresponding to different pixel region columns.

  The present liquid crystal display device may be configured such that data signals having the same polarity are supplied to adjacent data signal lines corresponding to different pixel region columns.

  The present liquid crystal display device includes a scanning signal line driving circuit including a shift register, and a scanning signal supplied to each scanning signal line selected at the same time is generated using an output of the same stage of the shift register. It can also be.

  The present liquid crystal display unit includes the liquid crystal panel and a driver. The television receiver includes the liquid crystal display device and a tuner unit that receives a television broadcast.

  The driving method of the present liquid crystal panel includes a plurality of data signal lines and a plurality of scanning signal lines, a plurality of pixel electrodes are provided in each pixel region, and a direction in which each data signal line extends is a column direction. Two data signal lines are provided corresponding to the region columns, and one pixel electrode of the pixel region included in the pixel region column is connected to the two data signal lines via a transistor connected to the scanning signal line. And another pixel electrode of the pixel region is connected to the other of the two data signal lines through a transistor connected to another scanning signal line, and adjacent to the pixel region column. With respect to a liquid crystal panel in which one of the pixel electrodes included in one of the pixel regions and one of the pixel electrodes included in the other are connected to the same scanning signal line via transistors, 2 bottles Wherein the sequentially selected One.

  The active matrix substrate and the liquid crystal panel of the present invention are suitable for a liquid crystal television, for example.

5a to 5c Liquid crystal panel 12a to 12h / 12A to 12H Transistors 17a to 17h / 17A to 17H Pixel electrode Sx / Sy / SX / SY Data signal line Gn to G (n + 6) Scanning signal line Csn to Cs (n + 2) Retention capacitance wiring DESCRIPTION OF SYMBOLS 22 Gate insulating film 24 Semiconductor layer 25 Inorganic interlayer insulating film 26 Organic interlayer insulating film 84 Liquid crystal display unit 101-108 Pixel 601 Television receiver 800 Liquid crystal display device

Claims (20)

A plurality of data signal lines and a plurality of scanning signal lines;
A plurality of pixel electrodes are provided in each pixel region, and two data signal lines are provided corresponding to one pixel region column, with the extending direction of each data signal line as a column direction,
One pixel electrode of a pixel region included in the pixel region column is connected to one of the two data signal lines through a transistor connected to a scanning signal line, and another pixel electrode of the pixel region is Connected to the other of the two data signal lines through a transistor connected to another scanning signal line;
For two adjacent pixel regions in the pixel region column, one of the pixel electrodes included in one of the pixel regions and one of the pixel electrodes included in the other are connected to the same scanning signal line through transistors,
In each pixel region, two pixel electrodes are arranged along the row direction,
An active matrix substrate characterized in that two pixel electrodes belonging to the same pixel region column and connected to the same scanning signal line through transistors are arranged obliquely opposite each other. A plurality of data signal lines and a plurality of scanning signal lines;
A plurality of pixel electrodes are provided in each pixel region, and two data signal lines are provided corresponding to one pixel region column, with the extending direction of each data signal line as a column direction,
One pixel electrode of a pixel region included in the pixel region column is connected to one of the two data signal lines through a transistor connected to a scanning signal line, and another pixel electrode of the pixel region is Connected to the other of the two data signal lines through a transistor connected to another scanning signal line;
For two adjacent pixel regions in the pixel region column, one of the pixel electrodes included in one of the pixel regions and one of the pixel electrodes included in the other are connected to the same scanning signal line through transistors,
In each pixel region, two pixel electrodes are arranged along the column direction,
An active matrix substrate characterized in that two pixel electrodes belonging to the same pixel region column and connected to the same scanning signal line via transistors are arranged so as to sandwich another pixel electrode therebetween .   3. The active matrix substrate according to claim 2, wherein two pixel electrodes belonging to the same pixel region row and respectively connected to the same scanning signal line via a transistor are arranged obliquely opposite each other.   2. The active matrix substrate according to claim 1, wherein the storage capacitor wiring extending in the column direction so as to overlap the gap between the two pixel electrodes is formed in the same layer as each data signal line.   A liquid crystal panel comprising the active matrix substrate according to claim 1.   A liquid crystal display device comprising the active matrix substrate according to claim 1.   7. The liquid crystal display device according to claim 6, wherein two scanning signal lines are sequentially selected.   One horizontal scanning period includes two selection periods in which two scanning signal lines are simultaneously selected and one selection period in which only one scanning signal line is selected following the two selection periods. The liquid crystal display device according to claim 7.   During halftone display, a relatively low gradation data signal is supplied to each data signal line during two selection periods, and a relatively high gradation data signal is supplied to each data signal line during one selection period. The liquid crystal display device according to claim 8.   During halftone display, a relatively high gradation data signal is supplied to each data signal line during two selection periods, and a relatively low gradation data signal is supplied to each data signal line during one selection period. The liquid crystal display device according to claim 8.   The pixel electrode connected to the scanning signal line selected in the single selection period via the transistor has a larger area than the pixel electrode connected to the scanning signal line not selected in the single selection period via the transistor. The liquid crystal display device according to claim 10.   7. The liquid crystal display device according to claim 6, wherein data signals having opposite polarities are supplied to two data signal lines corresponding to one pixel region column.   7. The liquid crystal display device according to claim 6, wherein a data signal whose polarity is inverted every horizontal scanning period is supplied to each data signal line.   7. The liquid crystal display device according to claim 6, wherein each data signal line is supplied with a data signal whose polarity is inverted every vertical scanning period.   7. The liquid crystal display device according to claim 6, wherein data signals having opposite polarities are supplied to adjacent data signal lines corresponding to different pixel area columns.   7. The liquid crystal display device according to claim 6, wherein data signals having the same polarity are supplied to adjacent data signal lines corresponding to different pixel region columns. A scanning signal line driving circuit including a shift register;
9. The liquid crystal display device according to claim 8, wherein the scanning signals supplied to the scanning signal lines selected at the same time are generated by using the output of the same stage of the shift register.   9. The liquid crystal according to claim 8, wherein a channel size of a transistor connected to a scanning signal line selected in one selection period is smaller than that of a transistor connected to a scanning signal line not selected in one selection period. Display device.   A liquid crystal display unit comprising the liquid crystal panel according to claim 5 and a driver. A television receiver comprising the liquid crystal display device according to any one of claims 6 to 18 and a tuner unit for receiving a television broadcast.

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