JP5441474B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device such as an organic EL display device.

  Conventionally, an image display device using an organic EL (Electro Luminescence) element that emits light by recombination of holes and electrons injected into a light emitting layer has been proposed. As an image display device, for example, a pixel circuit having a thin film transistor (hereinafter referred to as “TFT”) formed of amorphous silicon, polycrystalline silicon, or the like, an organic light emitting diode, or the like is arranged in a matrix. There is something arranged.

  Conventionally, an image display apparatus having a configuration in which light emitting means divided into a plurality of planes is connected in series has been proposed (see Patent Document 1).

JP 2006-10986 A

  However, in the technique of Patent Document 1, although the current value per unit pixel can be reduced, compensation for the threshold voltage of the thin film transistor that drives the organic EL element is not taken into consideration. May occur.

  The present invention has been made in view of the above, and an object of the present invention is to provide an image display device capable of reducing a current value per unit pixel and compensating a threshold voltage.

In order to solve the above-described problems and achieve the object, an image display device according to a first aspect of the present invention includes a first light emitting element, a second light emitting element, the first light emitting element, and the second light emitting element. A driver element that adjusts a current flowing from the first light emitting element to the second light emitting element, a first capacitor element that holds a charge according to a threshold voltage of the driver element, and A switching element that switches connection to both ends of the two light emitting elements according to an on state or an off state, and when the switching element is in the off state, a current that flows out of the first light emitting element is supplied to the second light emitting element. When the switching element is turned on, the charge held in the first capacitor element flows into the switching element through the driver element.
In the image display device according to the second aspect of the present invention, the driver element includes a first electrode corresponding to a gate connected to the first capacitor element, one corresponding to a drain, and the other corresponding to a source. The second electrode is connected to the cathode of the first light emitting element, the third electrode is connected to the anode of the second light emitting element, A current flowing between the second terminal and the third terminal is adjusted according to a potential difference between the first terminal and the second terminal.
The image display apparatus according to a third aspect of the present invention further includes a threshold voltage detection element that detects the threshold voltage, and the threshold voltage detection element utilizes charges accumulated in the first capacitor element. The threshold voltage is detected.
In the image display device according to the fourth aspect of the present invention, the switching element is turned off when the first light emitting element and the second light emitting element emit light, and the first light emitting element and the second light emitting element are turned off. The element is connected via the driver element during the light emission.
The image display device according to a fifth aspect of the present invention further includes a second capacitor element that holds an image signal voltage corresponding to light emission luminance of the first light emitting element and the second light emitting element, and The capacitive element and the second capacitive element are connected in series to the driver element during the light emission.

  According to the present invention, it is possible to provide an image display device capable of reducing a current value per unit pixel and compensating for a variation in threshold voltage.

FIG. 1 is a diagram schematically showing the configuration of the image display apparatus according to the present embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of the pixel circuit shown in FIG. FIG. 3 is a timing chart for explaining a driving method of the pixel circuit shown in FIG. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the light emission stop period. FIG. 5 is a diagram illustrating an operation state of the pixel circuit during the V _th detection preparation period. FIG. 6 is a diagram illustrating an operation state of the pixel circuit during the V _th detection preparation period. FIG. 7 is a diagram illustrating an operation state of the pixel circuit during the V _th detection period. FIG. 8 is a diagram illustrating an operation state of the pixel circuit during the reset period. FIG. 9 is a diagram illustrating an operation state of the pixel circuit during the writing period. FIG. 10 is a diagram illustrating an operation state of the pixel circuit during the light emission period. FIG. 11 is a plan view of the pixel circuit shown in FIG. 12 is a cross-sectional view taken along the line AA of the pixel circuit shown in FIG. 13 is a cross-sectional view of the pixel circuit shown in FIG. 11 taken along the line BB. FIG. 14 is a plan view of an insulator provided in the pixel circuit. FIG. 15 is a plan view when the pixel circuits are arranged in a matrix. FIG. 16 is a diagram showing a current flow during the light emission period in the AA cross section of the pixel circuit shown in FIG. FIG. 17 is a diagram showing a current flow during the light emission period in the BB cross section of the pixel circuit shown in FIG.

  Hereinafter, an image display apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited to the following embodiment.

<Configuration of image display device>
FIG. 1 is a diagram schematically showing the configuration of the image display apparatus according to the present embodiment. As shown in the figure, the image display device includes a display panel 1 in which a plurality of pixel circuits 10 are arranged in a matrix, a control circuit 2, a power supply line control circuit 3, a control line drive circuit 4, and an image. And a signal line driving circuit 5.

In the horizontal direction of the screen of the display panel 1, a V _SS line 11, a V _DD line 12, a sense line 13, a reset line 15 and a select line 14 are provided. An image signal line 16 is disposed in the vertical direction of the display panel 1. Here, the V _SS line 11 and the V _DD line 12 are electrically connected to the power supply line control circuit 3. In addition, the sense line 13, the select line 14, and the reset line 15 are electrically connected to the control line drive circuit 4. The image signal line 16 is electrically connected to the image signal line driving circuit 5.

  The control circuit 2 can be configured using, for example, a control device such as an IC or counter that includes an arithmetic circuit, a logic circuit, and the like. The control circuit 2 controls the timing at which power for displaying image data to be displayed on the display panel 1 is supplied from the power line control circuit 3, the control line drive circuit 4, and the image signal line drive circuit 5.

The power supply line control circuit 3 can be configured using, for example, an IC that includes a semiconductor element or the like therein. The power supply line control circuit 3 applies the potential generated inside itself to each of the V _SS line 11 and the V _DD line 12 based on an instruction signal (such as a clock signal) input from the control circuit 2.

  The control line drive circuit 4 can be configured using, for example, an IC that includes a semiconductor element or the like. The control line drive circuit 4 applies a potential generated inside itself to each of the sense line 13, the select line 14, and the reset line 15 based on an instruction signal (such as a clock signal) input from the control circuit 2.

  The image signal line driving circuit 5 can be configured using, for example, an IC or the like that includes an arithmetic circuit or the like. The image signal line drive circuit 5 generates a voltage corresponding to the image signal (hereinafter referred to as an image data potential) from the image signal input from the control circuit 2, and an instruction signal (clock) input from the control circuit 2. The signal is supplied to the image signal line 16 based on the signal or the like.

1, the V _SS line 11, the V _DD line 12, the sense line 13, the reset line 15, the select line 14 and the image signal line 16, the control circuit 2, the power line control circuit 3, and the control line drive circuit. The layout relating to 4 and the image signal line drive circuit 5 shows an example, and is not limited to this. For example, in FIG. 1, the control circuit 2, the power line control circuit 3, the control line drive circuit 4, and the image signal line drive circuit 5 are arranged outside the display panel 1, but any or all of these circuits are displayed. It is good also as a form incorporated in the panel 1. FIG.

<Configuration of image circuit>
Next, the pixel circuit 10 constituting the display panel 1 shown in FIG. 1 will be described. FIG. 2 is a diagram showing an example of the configuration of the pixel circuit 10 (one pixel) shown in FIG. As shown in the figure, the pixel circuit 10 includes a first organic EL element OLED1 that is a first light emitting element, a second organic EL element OLED2 that is a second light emitting element, a first organic EL element OLED1, and a second organic EL element OLED1. A drive transistor _Td that is a driver element for driving the organic EL element OLED2, a threshold voltage detection transistor _Tth that is a threshold voltage detection element used when detecting a threshold voltage of the drive transistor _Td , and an image signal A first switching transistor T _sel that controls the application of voltage, a first holding capacitor C _th that holds a threshold voltage as a first capacitor, and a second holding capacitor C _data that holds an image signal voltage as a second capacitor. And a second switching transistor T _rst as a switching element connected in parallel with the second organic EL element OLED2. Since the first organic EL element OLED1 and the second organic EL element OLED2 function as capacitors when a reverse voltage is applied, they are equivalently represented as a first element capacitance C _oled1 and a second element capacitance C _oled2 in FIG. ing.

  The first organic EL element OLED1 and the second organic EL element OLED2 are organic EL elements that emit light with a luminance corresponding to the amount of current. Specifically, in the first organic EL element OLED1 and the second organic EL element OLED2, an organic light emitting layer between the anode electrode and the cathode electrode is generated by generating a potential difference equal to or higher than the conduction voltage between the anode electrode and the cathode electrode. Current flows, and light is generated by recombination of holes and electrons injected into the organic light emitting layer.

  Here, as the anode electrode, for example, a light-transmitting conductive material such as indium tin oxide film (ITO) or tin oxide can be used. Moreover, when an anode electrode consists of materials, such as magnesium, silver, aluminum, or calcium, for example, it can be set as a light-transmitting electrode by making the thickness into 100 nm or less. Moreover, as a cathode electrode, metals, such as aluminum, rhodium, neodymium, silver, copper, or gold, or these alloys can be used, for example.

  Moreover, as an organic light emitting layer, it is comprised with luminescent materials, such as Alq3 (Tris (8-quinolinolato) aluminum complex), for example. In order to increase luminous efficiency, a host material having a hole transporting property or an electron transporting property is doped with an organic metal compound such as tris [pyridinyl-kN-phenyl-kC] iridium or a dye such as coumarin as a dopant material. Layers may be configured. The density | concentration of the dopant material which comprises a light emitting layer shall be 0.5 mass% or more and 20 mass% or less, for example. Examples of the host material having a hole transporting property include α-NPD and TPD. Examples of a host material having an electron transporting property include bis (2-methyl-8-quinolinolato) -4- (phenylphenolato) aluminum, 1,4-phenylenebis (triphenylsilane), 1,3-bis ( Triphenylsilyl) benzene, 1,3,5-tri (9H-carbazol-9-yl) benzene, CBP, Alq3, or SDPVBi. Note that, as a material constituting each layer of the light emitting layer, an appropriate material is selected according to the color of emitted light. Examples of a dopant material that emits red light include tris (1-phenylisoquinolinato-C2, N) iridium or DCJTB. Examples of dopant materials that emit green light include tris [pyridinyl-kN-phenyl-kC] iridium or bis [2- (2-benzoxazolyl) phenolato] zinc (II). Examples of the dopant material that emits blue light include a distyrylarylene derivative, a perylene derivative, or an azomethine zinc complex.

Of the two electrodes of the first organic EL element OLED1, the anode electrode is electrically connected to the V _DD line 12, and the cathode electrode is electrically connected to the second _Td electrode t12 of the drive transistor _Td . . Of the two electrodes of the second organic EL element OLED2, the anode electrode is electrically connected to the third _Td electrode t13 of the drive transistor _Td , and the cathode electrode is electrically connected to the V _SS line 11. ing.

The drive transistor T _d , the threshold voltage detection transistor T _th , the first switching transistor T _sel, and the second switching transistor T _rst are, for example, thin film transistors (TFTs) formed of amorphous silicon or the like. Each TFT channel may be either n-type or p-type, but in this embodiment, n-type is used.

The drive transistor _Td has a first _Td electrode t11, a second _Td electrode t12, and a third _Td electrode t13. The 1T _d electrode t11 is the 2C _th electrode t52 electrically connected to the first storage capacitor C _th. The second _Td electrode t12 is electrically connected to the cathode electrode of the first organic EL element OLED1, and the third _Td electrode t13 is electrically connected to the anode electrode of the second organic EL element OLED2. Yes.

Here, the first _Td electrode t11 corresponds to a gate electrode (gate), and one of the second _Td electrode t12 and the third _Td electrode t13 is a drain electrode (drain), and the other is a source electrode (source). Correspond. In the n-type transistor used in the present embodiment, of the second _Td electrode t12 and the third _Td electrode t13, the high potential side electrode is the “drain” and the low potential side electrode is the “source”. Become. Therefore, the drain and the source are defined by a relative potential relationship applied to the second T _d electrode t12 and the third T _d electrode t13.

The drive transistor _Td is connected between the source and the drain according to the potential applied to the first _Td electrode t11, more specifically, the voltage value applied to the gate with respect to the source (gate-source voltage). The amount of flowing current is adjusted to selectively set a state where current can flow (on state) and a state where current cannot flow (off state).

The threshold voltage detection transistor T _th includes a first T _th electrode t21, a second T _th electrode t22, and a third T _th electrode t23. The first _Tth electrode t21 is electrically connected to the sense line 13. The second T _th electrode t22 is conductively connected to a wiring that electrically connects the second T _d electrode t12 of the drive transistor T _d and the cathode electrode of the first organic EL element OLED1. The third T _th electrode t23 is electrically connected to a wiring that electrically connects the first T _d electrode t11 of the drive transistor T _d and the second C _th electrode t52 of the first storage capacitor C _th . Yes.

Here, the first T _th electrode t21 corresponds to the gate, one of the second T _th electrode t22 and the third T _th electrode t23 corresponds to the source, and the other corresponds to the drain. Note that in the n-type transistor used in this embodiment, the high-potential side electrode is the “drain” and the low-potential side electrode is the “source”. Therefore, the drain and the source are defined by the relative potential relationship applied to the second T _th electrode t22 and the third T _th electrode t23.

The threshold voltage detection transistor T _th has a source and drain corresponding to a potential applied to the first T _th electrode t21, more specifically, a voltage value applied to the gate with respect to the source (gate-source voltage). Is adjusted to selectively set a state in which current can flow (ON state) and a state in which current cannot flow (OFF state).

The first switching transistor T _sel includes a first T _sel electrode t31, a second T _sel electrode t32, and a third T _sel electrode t33. Here, the first _Tsel electrode t31 is electrically connected to the select line. In addition, the 2T _sel electrode t32 is the image signal line 16 and electrically connected. Furthermore, the 3T _sel electrode t33 is electrically connected to the second 1C _th electrode t51 of the first holding capacitor C _th. In the present embodiment, the first T _sel electrode t31 corresponds to the gate, the second T _sel electrode t32 corresponds to the drain, and the third T _sel electrode t33 corresponds to the source.

The second switching transistor T _rst includes a first T _rst electrode t41, a second T _rst electrode t42, and a third T _rst electrode t43. Here, the first _Trst electrode t41 is electrically connected to the reset line 15. The second _Trst electrode t42 is electrically connected to the V _SS line 11. Furthermore, the 3T _rst electrode t43 is the anode electrode electrically connected to the second organic EL element OLED2.

Here, the first _Trst electrode t41 corresponds to the gate, and one of the second _Trst electrode t42 and the third _Trst electrode t43 corresponds to the drain and the other corresponds to the source. In the n-type transistor used in the present embodiment, of the second _Td electrode t12 and the third _Td electrode t13, the high potential side electrode is the “drain” and the low potential side electrode is the “source”. Become. Therefore, the drain and the source are defined by a relative potential relationship applied to the second T _d electrode t12 and the third T _d electrode t13.

The first storage capacitor C _th is a capacitive element for holding the threshold voltage V _th of the driving transistor T _d, holding an amount of charge corresponding to the threshold voltage V _th of the driving transistor T _d at Vth detection period to be described later It has a function to do. The first storage capacitor C _th has a first 1C _th electrode t51 and the 2C _th electrode t52. Here, the 1C _th electrode t51 is the 3T _sel electrode t33 and are electrically connected to the first switching transistor T _sel, the 2C _th electrode t52 is a 1T _d electrode t11 and the electric driving transistor T _d Connected.

The second holding capacitor C _data is a capacitive element for holding a charge amount according to the image signal voltage, and has a function of holding the charge amount according to the image signal voltage during a writing period to be described later. . The second storage capacitor C _data has a first C _data electrode t61 and a second C _data electrode t62. Here, the 1C _data electrode t61 includes a first 3T _sel electrode t33 of the first switching transistor T _sel, conductive capable of and the 1C _th electrode t51 of the first holding capacitor C _th respect wiring electrically connected to It is connected. Further, the 2C _data electrode t62 includes a first 3T _d electrode t13 of the driving transistor T _d, are connected to be conductive with respect to electrically connected to wiring the anode electrode of the second organic EL element OLED2.

<Operation of pixel circuit>
Next, the operation of the above-described pixel circuit 10 will be described with reference to FIGS. The operation of the pixel circuit 10 described below is realized by the control of the control means (the control circuit 2, the power supply line control circuit 3, the control line drive circuit 4, and the image signal line drive circuit 5) shown in FIG. Is. Also, the pixel circuit 10 shown in FIGS. 4 to 10, a portion where no current flows is indicated by a broken line.

  FIG. 3 is a timing chart for explaining a driving method of the pixel circuit 10, and shows signal waveforms (driving waveforms) when the first organic EL element OLED1 and the second organic EL element OLED2 emit light sequentially by the light emission method. Show. Here, the sequential light emission method refers to writing control of an image signal voltage for each pixel circuit for each frame and light emission control of each pixel circuit for each group of pixel circuits commonly connected to the same control line or power supply line ( (For example, every row, every column, etc.)

In FIG. 3, the vertical axis indicates the potential applied to each control line. From the top, the V _SS line 11, the V _DD line 12, the sense line 13, the reset line 15, the select line 14, and the image signal line 16. It has become. In addition, the horizontal axis indicates the passage of time. In the sequence described below, the six control periods of the light emission stop period, the V _th detection preparation period, the V _th detection period, the reset period, the writing period, and the light emission period are defined as one cycle. The EL element OLED1 and the second organic EL element OLED2 emit light once.

In the sequential light emission method, control is performed in a state in which the cycle for each group serving as a unit of control is shifted in time, but the operation of each pixel circuit group during one cycle is the same for each group. Therefore, in the following description, the operation will be described focusing on a specific group of pixel circuits. The V _DD line 12 is always set to zero potential (0 V) during one cycle, and the description thereof is omitted.

(Flash off period)
FIG. 4 is a diagram illustrating an operation state of the pixel circuit 10 during the light emission stop period. In the light emission stop period, as shown in FIG. 3, the sense line 13 has a low potential (V _gL ), the reset line 15 has a low potential (V _gL ), the select line 14 has a low potential (V _gL ), and the image signal line 16. Is set to zero potential (0 V), while the V _SS line 11 is changed from low potential (−V _p ) during the light emission period described later to zero potential (0 V).

By this control, the V _SS line 11 and the V _DD line 12 become the same potential, and the current flowing through the first organic EL element OLED1 and the second organic EL element OLED2 is stopped. Therefore, the first organic EL element OLED1 and the second organic EL The element OLED2 is turned off.

Note that at the end of the light emission stop period, the potential between the drive transistor T _d and the first storage capacitor C _th , that is, the gate potential of the drive transistor T _d is βV _g ′. Here, βV _g ′ is equal to the second C _th electrode t52 of the first storage capacitor C _{th and} the first T of the drive transistor T _d at the end of the light emission period of the previous frame (at the start of the light emission stop period of the main frame). _This is the potential remaining between the _d electrode t11 (the gate potential of the drive transistor _Td ). The potential between the driving transistor T _d and the first organic EL element OLED1 (first element capacitance C _OLED1), a voltage drop occurs due to the first organic EL element OLED1 in accordance with the value of V _data, a negative potential “ _−Voled ”.

(V _th detection preparation period)
5 and 6 are diagrams showing the operation state of the pixel circuit 10 during the V _th detection preparation period. In the V _th detection preparation period, as shown in FIG. 3, the reset line 15 is first set to the high potential while the low potential (V _gL ) of the select line 14 and the zero potential (0 V) of the image signal line 16 are maintained. (V _gH ), and the V _SS line 11 is set to a high potential (V _p ) after a predetermined time has elapsed.

By this control, a current flows through a path from the V _SS line 11 to the second storage capacitor C _data . As a result, the potential on the second C _data electrode t62 side of the second storage capacitor C _data becomes V _p . In addition, when the first holding capacitor C _th is pushed up by capacitive coupling corresponding to this potential, the potential between the second C _th electrode t52 and the first T _d electrode t11 of the drive transistor T _d increases, and as a result As a result, the driving transistor _Td is turned on. Therefore, from the 3T _d electrode t13 (source) current flows into the first 2T _d electrode t12 (drain), also it becomes V _p and the 2T _d electrode t12 potential of the first element capacitor C _OLED1.

At this time, the potential between the first storage capacitor _Cth and the driving transistor _Td , that is, the gate potential of the driving transistor _Td is derived as follows.

The potential between the second C _th electrode t52 of the first storage capacitor C _th and the first T _d electrode t11 of the drive transistor T _d , that is, the drive transistor gate potential is the same as that of the second C _data electrode t62 of the second storage capacitor C _data and the drive. the 3T _d electrode t13 of the transistor T _d is held between changes from 0V to -V _p. Therefore, the law of charge conservation is established, and when the drive transistor gate potential V _g in the 0V state and the −V _p state is βV _g ′ and V _{g_p} respectively, the following equation (1) is obtained.

_{(ΒV g '-0) × {} C gsTdoff + C th × C data / (C data + C th)}
_{+ (ΒV g '-0) ×} C oled1 × C gdTdoff / (C oled1 + C gdTdoff)
+ (ΒV _g '−V _gL ) × C _gsTthoff
= (V _{g — p} −V _p ) × {C _gsTdoff + C _th × C _data / (C _data + C _th )}
+ (V _{g_p} −0) × C _oled1 × C _gdTdoff / (C _oled1 + C _gdTdoff )
+ (ΒV _g ′ −V _gL ) × C _gsTthoff (1)

From this, the drive transistor gate potential after being pushed up by capacitive coupling is expressed by the following formula (2). The first term on the right side of the following formula (2) is a push-up voltage generated by capacitive coupling that occurs when the V _SS line 11 changes from 0 V to V _p .

_{V g_p = [- {C gsTdoff} + C th × C data / (C data + C th)} / [{C gsTdoff + C th × C data / (C data + C th)} + C oled1 × C gdTdoff / (C oled1 + C gdTdoff )]] × V _p + βV _g ′ (2)

In the above formulas (1) and (2), “C _gsTdoff ” is a parasitic capacitance between the first T _d electrode t11 (gate) and the third T _d electrode t13 (source) when the drive transistor T _d is off. It is. “C _gdTdoff ” is a parasitic capacitance between the first T _d electrode t11 (gate) and the second T _d electrode t12 (drain) when the driving transistor T _d is off. “C _gsTthoff ” is a parasitic capacitance between the first T _th electrode t21 (gate) and the third T _th electrode t23 (source) of the threshold voltage detection transistor T _th .

In the above formulas (1) and (2), “C _th ” means the electric capacity of the first holding capacitor C _th , “C _data ” means the electric capacity of the second holding capacitor C _data , C _oled1 ″ means the electric capacity of the first element capacitance C _oled1 .

Returning to FIG. 3, in the V _th detection preparation period, after the V _SS line 11 is set to the high potential (V _p ), the sense line 13 is further set to the high potential (V _gH ). By this control, the threshold voltage detection transistor T _th is turned on, and, as shown in FIG. 6, the path V _SS line 11 → second switching transistor T _rst → drive transistor T _d → threshold voltage detection transistor T _th Current flows. Thus, the potential between the first storage capacitor C _th and the driving transistor T _d becomes V _p.

(V _th detection period)
FIG. 7 is a diagram illustrating an operation state of the pixel circuit 10 during the V _th detection period. In the V _th detection period, as shown in FIG. 3, the V _SS line 11 is set to zero potential (0 V), while the sense line 13, the reset line 15, the select line 14, and the image signal line 16 are set to the previous potential. Maintained at.

By this control, as shown in FIG. 7, the charge accumulated in the first storage capacitor C _th is discharged, the threshold voltage detecting transistor T _th → driving transistor T _d → second switching transistor T _rst → V _SS line 11 Current flows through the path. Then, the 1T _d electrode t11- the potential difference between the 2T _d electrode t12 of the driving transistor T _d reaches the threshold voltage V _th of the driving transistor T _d, and the 2T _d electrode t12 and the 3T _d electrode t13 is connected It is held in the state. In this way, in the V _th detection period, charges corresponding to the threshold voltage V _th of the drive transistor T _d are accumulated in the first holding capacitor C _th , thereby compensating for variations in the threshold voltage V _{th that} are different for each pixel circuit. can do.

(Reset period)
FIG. 8 is a diagram illustrating an operation state of the pixel circuit 10 during the reset period. In the reset period, as shown in FIG. 3, the sense line 13 is set to a low potential (V _gL ), while the V _SS line 11, the reset line 15, the select line 14, and the image signal line 16 are at the previous potential. Maintained.

By this control, the threshold voltage detecting transistor T _th is turned off as shown in FIG. As a result, the charge corresponding to the threshold voltage V _th accumulated in the first element capacitance C _oled1 is discharged, and a current flows through the path of the drive transistor T _d → second switching transistor T _rst → V _SS line 11, and the first element The charge remaining in the capacitor _Coled1 is discharged. Thereby, the influence on the light emission by the residual charge of the first organic EL element OLED1 itself is avoided.

(Writing period)
FIG. 9 is a diagram illustrating an operation state of the pixel circuit 10 during the writing period. In the write period, as shown in FIG. 3, the zero potential (0 V) of the V _SS line 11, the low potential (V _gL ) of the sense line 13, the high potential (V _gH ) of the reset line 15, and the low potential of the select line 14. While the potential (V _gL ) is maintained, an image signal voltage (V _data ) of a predetermined level corresponding to the image signal is supplied to the image signal line 16 for a predetermined period. The select line 14 is set to a high potential (V _gH ) for a predetermined period while the image signal voltage is supplied.

By this control, as shown in FIG. 9, the first switching transistor T _sel is turned on, and the image signal line 16 → the first switching transistor T _sel → the second holding capacitor C _data → the second switching transistor T _rst → the V _SS line. A current flows through the path 11. As a result, charges corresponding to the image signal voltage are held in the second holding capacitor C _data . Further, the push-up of the image signal voltage second holding capacitor C _data is held (V _data), the potential between the first storage capacitor C _th and the driving transistor T _d rises to .beta.v _g.

Here, the potential βV _g is expressed by the following formula (3).
βV _g = {(C _th + C _gsTdoff + C _gsTthoff ) / (C _th + C _gsTdon + C _gdTdon + C _gsTthoff )} × V _th + {C _th / (C _th + C _gsTdon + C _gdTdon + C _gsTthoff )} × V _data

In the above formula (3), “C _gsTdon ” is a parasitic capacitance between the first T _d electrode t11 (gate) and the third T _d electrode t13 (source) when the drive transistor T _d is on. “C _gdTdon ” is a parasitic capacitance between the first T _d electrode t11 (gate) and the second T _d electrode t12 (drain) when the drive transistor T _d is on.

(Light emission period)
FIG. 10 is a diagram illustrating an operation state of the pixel circuit 10 during the light emission period. In the light emission period, as shown in FIG. 3, the V _SS line 11 is set to a low potential (−V _p ) and the reset line 15 is set to a low potential (V _gL ), while the sense line 13 and the select line 14 are set low. The potential (V _gL ) and the zero potential (0 V) of the image signal line 16 are maintained.

By this control, the first organic EL element OLED1 and the second organic EL element OLED2 are connected in series via the drive transistor _Td . Further, the first holding capacitor C _th and the second holding capacitor C _data are connected in series, and the sum of the voltages of both is applied to the first T _d electrode t11 (gate) of the driving transistor T _d , as shown in FIG. Thus, the drive transistor _Td is turned on. Thus, current flows through a path of the V _DD line 12 → the first organic EL element OLED1 → driving transistor T _d → second organic EL element OLED2 → V _SS line 11, the first organic EL element OLED1 and second organic EL devices The OLED 2 emits light.

At this time, the potential of the third _Td electrode t13 (source) of the drive transistor _Td becomes the same value as the anode potential of the second organic EL element OLED2, and thus varies from the potential of the writing period. However, the gate of the driving transistor T _d is because it is connected to the anode electrode of the second organic EL element OLED2 through the first storage capacitor C _th and the second storage capacitor C _data, the gate potential of the driving transistor T _d is Then, it fluctuates following the fluctuation of the potential of the anode electrode of the second organic EL element OLED2. Therefore, the gate potential of the driving transistor T _d maintains the value at the writing time, that is, βV _g .

<Characteristics of pixel circuit>
As described above, in the pixel circuit 10 according to the present embodiment, the first organic EL element OLED1 and the second organic EL element OLED2 connected in series emit light at the same time during the light emission period. Compared with a configuration in which only the EL element emits light, the luminous intensity with respect to the current can be approximately doubled.

  Further, it has been found that the lifetime of the organic EL element itself is dependent on the current density flowing through the organic EL element. Specifically, the larger the current density flowing through the organic EL element, the faster the deterioration of the organic light emitting layer. Therefore, it is possible to extend the life by reducing the current density supplied to the organic EL element. . In this regard, in the pixel circuit 10 of the present embodiment, it is possible to realize a predetermined luminance (hereinafter, referred to as target luminance) that is a target during the light emission period by using two organic EL elements connected in series. Therefore, the target predetermined luminous intensity can be realized by supplying about half the current density as compared with the configuration in which the target luminance is realized with only one organic EL element. That is, since the amount of current per unit pixel can be reduced, the lifetime of the organic EL element can be extended. In this case, the power supply voltage needs to be twice that of the configuration in which only one organic EL element emits light. However, since the voltage drop due to the resistance of the power supply line is halved, as a result, the luminance is reduced. The influence can be reduced.

<Configuration of pixel circuit>
Hereinafter, a specific configuration example of the pixel circuit 10 described above will be described. 11 is a plan view of the pixel circuit 10 shown in FIG. 2, FIG. 12 is a cross-sectional view taken along the line AA of the pixel circuit shown in FIG. 11, and FIG. 13 is a cross-sectional view of the pixel circuit shown in FIG. It is B sectional drawing. FIG. 14 is a plan view of insulators (insulating layers and partitions) provided in the pixel circuit, and FIG. 15 is a plan view when the pixel circuits 10 are arranged in a matrix.

In FIG. 11, a second insulating layer 132, which will be described later, a V _SS line 11, a V _DD line 12, the first organic EL element OLED1, and the second organic EL element OLED2 existing above the second insulating layer 132 are illustrated. Is omitted. Further, the pixel circuit 10 described below adopts a top emission type structure in which light is extracted from the upper surface side (organic EL element side), not a structure in which light is extracted from the substrate side.

11, 12, and 13, the pixel circuit 10 includes a driving transistor T _d , a threshold voltage detection transistor T _th , a first switching transistor T _sel , and a second switching transistor T _{rst on the} substrate 100. The first storage capacitor _Cth and the second storage capacitor _Cdata are provided. Here, the substrate 100 is made of a material such as glass or plastic.

The drive transistor _Td is formed in an overlapping portion of the first gate layer 101, the first amorphous silicon layer 111, and the first signal line 121 and the second signal line 122. Here, the first gate layer 101 portion corresponds to the first T _d electrode t11, the first signal line 121 portion corresponds to the second T _d electrode t12, and the second signal line 122 portion corresponds to the third T _d electrode t13. .

The threshold voltage detection transistor T _th is formed in an overlapping portion of the second gate layer 102, the second amorphous silicon layer 112, the first signal line 121, and the third signal line 123 provided in common with the sense line 13. Has been. Here, the second gate layer 102 portion corresponds to the first T _th electrode t21, the first signal line 121 portion corresponds to the second T _th electrode t22, and the third signal line 123 portion corresponds to the third T _th electrode t23. ing. The third signal line 123 and the first gate layer 101 are connected via a hole H1 provided in the first insulating layer 131 described later.

The first switching transistor T _sel is a fifth gate provided in common with the third gate layer 103 provided in common with the select line 14, the third amorphous silicon layer 113, the fourth signal line 124 and the image signal line 16. It is formed in a portion overlapping with the signal line 125. Here, the third gate layer 103 portion corresponds to the first T _sel electrode t31, the fourth signal line 124 portion corresponds to the third T _sel electrode t33, and the fifth signal line 125 portion corresponds to the second T _sel electrode t32. ing.

The second switching transistor T _rst is formed in an overlapping portion of the fourth gate layer 104, the fourth amorphous silicon layer 114, the second signal line 122, and the sixth signal line 126 provided in common with the reset line 15. ing. Here, the fourth gate layer 104 portion corresponds to the first _Trst electrode t41, the sixth signal line 126 portion corresponds to the second _Trst electrode t42, and the second signal line 122 portion corresponds to the third _Trst electrode t43. ing.

The first storage capacitor C _th is formed in the overlapping portion of the first gate layer 101 and the fourth signal line 124. Here, the fourth signal line 124 portion corresponds to the 1C _th electrode t51, the first gate layer 101 portion corresponds to the 2C _th electrode t52.

The second storage capacitor C _data is formed in an overlapping portion between the fifth gate layer 105 and the second signal line 122. Here, the second signal line 122 portion corresponds to the second C _data electrode t62, and the fifth gate layer 105 portion corresponds to the first C _data electrode t61. The fifth gate layer 105 and the fourth signal line 124 are connected via a hole H2 provided in the first insulating layer 131 described later.

  The first gate layer 101, the second gate layer 102, the third gate layer 103, the fourth gate layer 104, the fifth gate layer 105, the first signal line 121, the second signal line 122, the third signal line 123 described above, As a material for forming the fourth signal line 124, the fifth signal line 125, and the sixth signal line 126, for example, an aluminum alloy or a molybdenum alloy is used.

  In addition, as shown in FIGS. 12 and 13, the pixel circuit 10 further includes a first insulating layer 131, a second insulating layer 132, a planarizing layer 133, a first electrode layer 134, an interlayer insulating layer 135, and the like. , A partition layer 136, an organic light emitting layer 137, and a second electrode layer 138.

  The first insulating layer 131 is formed on the substrate 100 or the gate layer (the first gate layer 101, the second gate layer 102, the third gate layer 103, the fourth gate layer 104, and the fifth gate layer 105). Here, the first insulating layer 131 has a hole H1 for connecting the first gate layer 101 and the third signal line 123, and a connection for connecting the fifth gate layer 105 and the fourth signal line 124. A hole H2 (see FIG. 11) is formed.

  In addition, a second insulating layer 132 is formed on each of the transistors and the storage capacitor described above. The second insulating layer 132 has a hole H3 for connecting the first signal line 121 and the first electrode layer 134 (first connection layer 1342), the second signal line 122, and the first electrode layer 134. A hole H4 for connecting the (second organic EL element anode layer 1343) and a hole H5 for connecting the sixth signal line 126 and the first electrode layer 134 (second connection layer 1344). Is formed. Note that the first insulating layer 131 and the second insulating layer 132 are formed using an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

  A planarizing layer 133 is formed on the second insulating layer 132 to reduce surface irregularities caused by the transistors and the capacitive elements. For the planarizing layer 133, for example, an insulating organic material such as a novolac resin, an acrylic resin, an epoxy resin, or a silicon resin can be used. Note that the above-described holes H <b> 3 to H <b> 5 are formed in the planarization layer 133 as well as the second insulating layer 132.

  The first electrode layer 134 is formed on the planarization layer 133, and the first organic EL element anode layer 1341, the first connection layer 1342, and the second organic EL element anode are formed by the interlayer insulating layer 135 shown in FIG. It is divided into four parts: a layer 1343 (including a connection layer formed by the hole H4) and a second connection layer 1344 (connected to the hole H5 and the second organic EL element cathode layer 1382). A partition layer 136 is formed on the interlayer insulating layer 135.

  As shown in FIG. 14, the interlayer insulating layer 135 is formed to hold the rectangular holes H6 and H7. Further, the partition layer 136 is formed so as to surround the hole H6. The holes H6 and H7 are regions where the first organic EL element OLED1 and the second organic EL element OLED2 are formed, and correspond to openings of the first organic EL element OLED1 and the second organic EL element OLED2. Moreover, H3-H5 shown with a wavy line respectively respond | corresponds to the position of hole part H3-H5 mentioned above.

The first organic EL element anode layer 1341 corresponds to the anode layer of the first organic EL element OLED1, and forms a common electrode V _DD line layer in the pixel circuit 10. The V _DD line layer corresponds to the V _DD line 12. The first connection layer 1342 electrically connects the first signal line 121 and a first organic EL element cathode layer 1381 described later through the hole H3. The second organic EL element anode layer 1343 corresponds to the anode layer of the second organic EL element OLED2, and is electrically connected to the second signal line 122 through the hole H4. The second connection layer 1344 electrically connects the sixth signal line 126 and a second organic EL element cathode layer 1382 described later through the hole H5.

  The first electrode layer 134 is formed using, for example, a metal such as aluminum, rhodium, neodymium, silver, copper, or gold, or an alloy thereof. The interlayer insulating layer 135 is formed using a light-transmitting organic insulating material such as phenol resin, acrylic resin, or polyimide resin, or a light-transmitting inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. ing. In addition, the partition layer 136 is formed using an organic material having optical transparency such as an acrylic resin, a polyimide resin, or a novolac resin.

  The organic light emitting layer 137 is formed in the hole portions H6 and H7. Specifically, a first organic light emitting layer 1371 that becomes a light emitting layer of the first organic EL element OLED1 is formed in the hole H6 of the interlayer insulating layer 135 above the first organic EL element anode layer 1341. In addition, a second organic light emitting layer 1372 serving as a light emitting layer of the second organic EL element OLED2 is formed above the second organic EL element anode layer 1343 and in the hole H7 of the interlayer insulating layer 135.

In the uppermost layer, a second electrode layer 138 that becomes the V _SS line 11 is formed. Here, the second electrode layer 138 is divided into two parts, a first organic EL element cathode layer 1381 and a second organic EL element cathode layer 1382, by the partition layer 136. Here, the first organic EL element cathode layer 1381 corresponds to the cathode layer of the first organic EL element OLED1. The second organic EL element cathode layer 1382 corresponds to a cathode layer of the second organic EL element OLED2, to form a common electrode V _SS line layer in the pixel circuit 10. The V _SS line layer corresponds to the V _SS line 11. The second organic EL element cathode layer 1382 corresponds to the second T _rst electrode t42 of the second switching transistor T _rst . Note that the second electrode layer 138 is formed of a light-transmitting conductive material such as an indium tin oxide film (ITO) or tin oxide. In addition, when the second electrode layer 138 is made of a material such as magnesium, silver, aluminum, or calcium, for example, the second electrode layer 138 can be made a light transmissive electrode by setting the thickness to 100 nm or less.

  As shown in FIG. 15, the pixel circuit 10 having the above configuration is arranged in a matrix to form the display panel 1. In FIG. 15, the range occupied by one pixel circuit 10 is indicated by a broken line.

  Next, the flow of current during the light emission period described above will be described with reference to FIGS. Here, FIG. 16 is a diagram illustrating a current flow during the light emission period in the AA cross section of the pixel circuit 10 illustrated in FIG. 11. FIG. 17 is a diagram showing a current flow during the light emission period in the BB cross section of the pixel circuit 10 shown in FIG.

As described above, since the V _DD line 12 is controlled to zero potential (0 V) and the V _SS line 11 is controlled to a low potential (−Vp) during the light emission period, a current flows from the V _DD line 12 toward the V _SS line 11. Flows (see D1 and D2 in FIG. 16). At this time, a current flows from the first organic EL element anode layer 1341 to the first organic EL element cathode layer 1381 via the first organic light emitting layer 1371, whereby the first organic EL element OLED1 emits light and moves upward in the drawing. Light is irradiated.

In addition, a current flows from the first organic EL element cathode layer 1381 to the first signal line 121 (see D3 in FIG. 16), and the second signal passes through the drive transistor _Td and the first signal line 121 of the first holding capacitor _Cth . The line 122 is reached (see D4 in FIG. 16 and D5 in FIG. 17). Next, a current flows from the second signal line 122 to the second organic EL element anode layer 1343 through the hole H4 (see D6 in FIG. 17), and the second organic EL element cathode passes through the second organic light emitting layer 1372. When a current flows through the layer 1382 (see D7 in FIG. 17), the second organic EL element OLED2 emits light, and light is irradiated upward in the drawing.

  The embodiment according to the present invention has been described above, but the present invention is not limited to this, and various modifications, substitutions, additions, and the like are possible without departing from the spirit of the present invention. In the above-described embodiment, the top emission image display device has been described. However, a bottom emission image display device may be used as long as the effects of the present invention are achieved.

  As described above, the image display device according to the present invention is useful for an image display device such as an organic EL display device, and particularly useful when each pixel circuit constituting the display panel includes two organic EL elements. is there.

DESCRIPTION OF SYMBOLS 1 Display panel 2 Control circuit 3 Power supply line control circuit 4 Control line drive circuit 5 Image signal line drive circuit 10 Pixel circuit 11 V _SS line 12 V _DD line 13 Sense line 14 Select line 15 Reset line 16 Image signal line 100 Substrate 101 1st 1st gate layer 102 2nd gate layer 103 3rd gate layer 104 4th gate layer 105 5th gate layer 111 1st amorphous silicon layer 112 2nd amorphous silicon layer 113 3rd amorphous silicon layer 114 4th amorphous silicon layer 121 1st Signal line 122 Second signal line 123 Third signal line 124 Fourth signal line 125 Fifth signal line 126 Sixth signal line 131 First insulating layer 132 Second insulating layer 133 Planarizing layer 134 First electrode layer 1341 First organic EL element anode layer 1342 first connection layer 1343 second organic EL element Anode layer 1344 Second connection layer 135 Interlayer insulating layer 136 Partition layer 137 Organic light emitting layer 1371 First organic light emitting layer 1372 Second organic light emitting layer 138 Second electrode layer 1381 First organic EL element cathode layer 1382 Second organic EL element cathode Layer C _oled1 first element capacity C _oled2 second element capacity C _th first retention capacity C _data second retention capacity OLED1 first organic EL element OLED2 second organic EL element T _d drive transistor T _th threshold voltage detection transistor T _sel First switching transistor T _rst second switching transistor

Claims (4)

An image display device comprising a plurality of pixel circuits arranged in a matrix, wherein the pixel circuits are
A first light emitting device comprising a first terminal and a second terminal, wherein the first terminal is connected to a first potential ;
A second light emitting device comprising a first terminal and a second terminal, wherein the second terminal is connected to a second potential ;
A first electrode corresponding to the gate; a second electrode and a third electrode, one of which corresponds to the drain and the other corresponds to the source; and the second electrode serves as a second terminal of the first light emitting element . connected, and the third electrode connected to the first terminal of the second light emitting element, a driver element for adjusting the first light emitting element and the second current Ru is flow to the light emitting element,
An image signal voltage is applied to one end, the other end is connected to the first electrode of the driver element, and holds a charge according to a threshold voltage of the driver element;
A switching element that switches connection to the first terminal and the second terminal of the second light emitting element according to an on state or an off state;
A threshold detection element that switches a connection between the first electrode and the second electrode of the driver element according to an on state or an off state;
With
When the switching element is in an off state and the threshold detection element is in an off state , a current that flows out from the first light emitting element flows into the second light emitting element, the switching element is in an on state , and the threshold detection An image display device, wherein the charge held in the first capacitor element flows into the switching element through the threshold detection element and the driver element when the element is in an on state . The image display device according to claim 1,
The first terminal of the first light emitting element and the second light emitting element is an anode, the second terminal is a cathode,
The second electrode of the driver element is a drain and the third electrode is a source, and a current flowing between the second electrode and the third electrode is adjusted according to a potential difference between the first electrode and the third electrode. An image display device. In the image display device according to any one of claims 1 and 2 ,
The switching element is turned off when the first light emitting element and the second light emitting element emit light,
The image display device, wherein the first light emitting element and the second light emitting element are connected via the driver element during the light emission. In the image display device according to any one of claims 1 to 3 ,
A second capacitive element that holds an image signal voltage corresponding to the light emission luminance of the first light emitting element and the second light emitting element between the one end of the first capacitive element and the third electrode of the driver element; an image display device comprising <br/> by comprising further.

Images