JP5338042B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly, to a field effect transistor having a complementary metal oxide film structure having a low electrical resistance at a junction between an electrode and a source / drain region (Complementary-Metal Oxide Semiconductor-Field). Effect Transistor: CMOSFET) and a manufacturing method thereof.

At present, CMOSFETs using silicon (Si) as a channel material are widely used. In recent years, there has been a demand for higher performance and miniaturization. In these higher performance and miniaturization, the channel length is shortened, the gate oxide film thickness is reduced, and the source / drain layers are further reduced. It is important to reduce the resistance.
Currently, in a semiconductor device having a CMOSFET or the like, a silicide electrode made of a refractory metal silicide is being studied as a wiring having high heat resistance and low resistance. As one of the techniques for forming such a silicide electrode, a silicon material such as a diffusion layer formed on a silicon substrate or a gate electrode made of polycrystalline silicon is used with a high melting point such as titanium (Ti) or tungsten (W). Silicide is formed by reacting with a metal, and an unreacted refractory metal is selectively removed by etching to form a silicide electrode.

Further, recently, an impurity is ion-implanted into the surface of the silicide electrode / silicon substrate, interfacial contact resistance reducing technology using impurity segregation phenomenon occurring by heat treatment are proposed. In this interface contact resistance reduction technology, impurities implanted before silicide formation are segregated at the silicide electrode / silicon single crystal interface during silicide formation, thereby forming a shallow and high-concentration impurity layer at the silicide / silicon interface. Is. This high-concentration impurity layer is intended to reduce the interface contact resistance.
As a result, the interface contact resistance between the source / drain electrodes and the diffusion region of the source / drain is reduced, thereby contributing to high performance and miniaturization of the COMSFET.

Kunihiro Suzuki et al, IEEE Trans.on Electron Devices, Vol.50 No.8, August 2003, pp.1753-1757 Kunihiro Suzuki et al, IEEE Trans. On Electron Devices, Vol.51 No.5, May 2004, pp.663-668

  The present invention has a high-concentration impurity layer having an impurity concentration increased beyond the impurity concentration to be ion-implanted, and has a source / drain with reduced contact electrical resistance between the high-concentration impurity device and a silicide electrode. And a method of manufacturing the same.

The features of the present invention, which is a means for solving the above problems, are listed below.
In the present invention, forms a steep high-concentration impurity layer in the source-drain in the emissions, moreover, provided two layers of high concentration impurity layer, further, the silicided electrodes provided to reduce therebetween electrical resistance, This achieves thinning of the source / drain. Therefore, in a field effect transistor including an n-type MOS field effect transistor and a p-type MOS field effect transistor, an electric field having two high-concentration impurity layers having different impurity concentrations under the silicide electrode at the source and drain. An effect transistor is provided.
In the present invention, in order to form a steep impurity layer described above, a so-called impurity segregation effect not only to amorphous by injecting ions in the solid phase, of the substrate of the Si single crystal Amo le Fuss layer A diffusion layer having two high-concentration impurity layers is formed by utilizing both the effects of diffusing impurities at the interface, solidifying beyond the solid solubility limit in the equilibrium state, and using the effect of activation (non-patent) References 1, 2). Furthermore, it is possible to provide a manufacturing method of the heat treatment, the field effect transistor obtained by simplifying the manufacturing process by forming a sheet Risaido electrodes simultaneously when forming these impurities.

As described above, the present invention provides a field effect transistor that has a source / drain with reduced contact resistance, speeds up, consumes less power, and is miniaturized by using a thin diffusion layer. I was able to.
Furthermore, in the present invention, an impurity diffusion layer having an abrupt concentration change can be formed by segregating impurities exceeding a solid solubility limit to an intended interface to form an impurity layer. Thus, it was possible to provide a method of manufacturing a field effect transistor with a simplified manufacturing process.

  The best mode for carrying out the present invention will be described below with reference to the drawings. It should be noted that it is easy for those skilled in the art to make other embodiments by changing or modifying the present invention within the scope of the claims, and the following description is an example of the best mode of the present invention. It is not intended to limit the scope of the claims.

FIG. 1 is a schematic view showing the structure of the field effect transistor of the present invention.
The field effect transistor (CMOSFET) 1 includes two elements separated by an element isolation oxide film (STI: Shallow Trench Isolation) 30 between the nMOSFET 10 and the pMOSFET 20.
As shown in FIG. 1, a p-type element region (p-well) 11 in which an nMOSFET 10 is formed by an element isolation region 30 and an n-type element region (n-well) in which a pMOSFET 20 is formed on an Si substrate 2. 21 and a gate 12 is formed on the p-well 11. The gate 12 includes a gate electrode 121 with a gate insulating film 123 interposed therebetween, and sidewall insulating films ( sidewalls ) 123 formed on both sides of the gate electrode 121. In addition, a channel region 124 is provided immediately below. Although illustration is omitted, generally, a silicide layer is formed on the gate electrodes 121 and 221 made of polysilicon, and the electric resistance of the gate 12 is reduced.

In the p-well 11 of the element region, n− high concentration impurity regions 131 and 141 are formed in the source / drains 13 and 14 on both sides of the gate 12. Further, source / drain electrodes 132 and 142 are provided on the n − high-concentration impurity regions 131 and 141.
Similarly, the source / drain regions 23 and 24 of the pMOSFET 20 are formed on the n-well 21 in the element region outside the sidewall insulating film of the gate 22. (Hereinafter, the pMOS 20 is the same as the nMOS 10 unless otherwise specified, and is omitted.)
In the CMOSFET 1 of the present invention, silicide electrodes 132 and 142 are used as source / drain electrodes 132 and 142 as metal electrodes. Examples of the metal that becomes silicide include Ni, Co, W, Mo, Ti, V, and Nb. Silicide has a lower electrical resistance than metal Si, and can further reduce power consumption. Among these, Ni, Co, and electric resistance are small, and it is preferable because silicidation can be performed at a low temperature and diffusion of impurities can be prevented.

Further, in the present invention, an impurity region having a steep concentration of impurities is not provided immediately below the source / drain electrodes 132 and 142 by ion-implanting impurities such as As so as to provide a conventional ion-implanted impurity region. Two high-concentration impurity layers 133, 134, 143, and 144 having a thin layer thickness are provided. These two high-concentration impurity layers 133, 134, 143, and 144 contain high-concentration impurities, and are formed into thin layers to be brought into contact with the silicide electrodes 132 and 142 to reduce the contact electric resistance. Yes.
In order to reduce the electric resistance of the source / drain 12, 13, a large amount of impurities are included in the interface between the diffusion region of the electrode 132, 142 of the source / drain 13, 14 and the p-well 11. I found out that I can do it. Therefore, in the present invention, two high-concentration impurity layers 133, 134, 143, and 144 are provided immediately below the silicide layers 132 and 142. These high-concentration impurity layers 133, 134, 143, 144 all exceed the solid solubility limit of impurities in the Si substrate 2. Alternatively, the ion-implanted impurity concentration is increased and concentrated to be in the range of 10 ²⁰ to 10 ²¹ cm ⁻³ . By setting it within this range, the contact resistance at the interface between the silicide electrodes 132 and 142 serving as the Schottky interface and the diffusion region of the p-well 11 could be reduced. Further, by providing high-concentration impurity regions 131 and 141 under the silicide electrodes 132 and 142, respectively, the layer thickness of the entire high-concentration impurity layer is controlled, and the silicide electrodes 132 and 142 and the p-well 11 are controlled. Is prevented from occurring.

The two high-concentration impurity layers 133, 134, 143, and 144 are formed of the same kind of impurities. In order to form the high concentration impurity layers 133 and 134 of the nMOSFET 10, V group P, As, and Sb are used. In order to form the high-concentration impurity layers 143 and 144 of the pMOSFET 20, group III B, Al, Ga, and In are used. At this time, the two high-concentration impurity layers 133, 134, 143, and 144 can use the same impurity element.
The two high-concentration impurity layers 133, 134, 143, and 144 can use different impurity elements. This is because the high-concentration impurity layers 133, 134, 143, and 144 contain impurities exceeding the solid solubility limit, but when the impurity concentration is further increased, different elements are contained respectively. It can be contained in a larger amount than the same kind of impurities. In addition, even if the charges are the same, the atomic weight is different, so that a large atomic weight impurity can reduce the distribution width when ions are implanted. Further, since the diffusion rate in the Si single crystal varies depending on each atom, it can be selected from the viewpoint of reducing the diffusion by heat treatment or the like. Therefore, in the nMOSFET 10, for example, when V group P and As are used, P is preferable for the second high-concentration impurity layer 134 and As is preferable for the first high-concentration impurity layer 133.
In the pMOSFET 20, B is preferable as the same type impurity, and B and In are preferable as the different type impurities. In particular, In is used for the second high-concentration impurity layer 143, and B is preferred.
These two high-concentration impurity layers 133, 134, 143, and 144 may have a clear interface, but the interfaces between the two high-concentration impurity layers 133, 134, 143, and 144 are unclear. It may be in a state of almost one layer. This is because the second high-concentration impurity layers 134 and 144 are moved by the impurity segregation effect in the heat treatment to be described later, so that it is integrated with the first high-concentration impurity layers 133 and 143 formed earlier. It may be.

The principle of the method for manufacturing a CMOS field effect transistor according to the present invention will be described.
FIG. 2 is a schematic diagram showing the principle of a semiconductor manufacturing method using an impurity segregation effect. In the method of manufacturing the CMOS field effect transistor 1 according to the present invention, the high concentration impurity layers 133, 134, 143, and 144 which are high concentration and are very thin layers are formed.
In (1), the bonding position is defined on the Si substrate, but here, the target position is not particularly present . In an actual semiconductor device, this may be regarded as an interface between the source and drain diffusion regions.
In (2), first, Ge is ion-implanted into the Si substrate. By injecting with appropriate energy , the single crystal of the Si substrate is broken to form an amorphous layer. The A / C interface indicates the interface between the single crystal and the amorphous layer. The depth of this A / C interface can also be adjusted by the energy for ion implantation. For this amorphization, Si, Ge, Ar, Xe, or the like can be used.
In (3), As is doped into the Si substrate as an impurity. The depth of As can also be controlled by the implantation energy for doping. (3) The vertical axis of the figure indicates the concentration with an arbitrary scale for the impurity As.
In (4), this Si substrate is heated by LSA ( laser annealing ) or the like. By this heating, when the previously amorphized part is recovered by heating and crystallized, As of impurities is poured into the A / C interface. At this time, since it flows into the A / C interface, the distribution of As becomes steep, and a thin first high-concentration impurity layer is formed.
(5) Next, As is again ion-implanted as an impurity into the Si substrate and added. Furthermore, Ni is vapor-deposited thereon by sputtering .
In (6), this Si substrate is heated. By this heating, silicide is formed by diffusion of Ni and Si, and at the same time, As doped in the second time is segregated at the interface between the silicide and the Si substrate. The second impurity layer does not absorb or flow into the first high-concentration impurity layer, but forms a sharp high-concentration impurity layer at the interface between the silicide and the Si substrate. As a result, two layers can be formed by forming layers of impurities such as As. At this time, the second high-concentration impurity layer and the first high-concentration impurity layer may be integrated.

A method for manufacturing the CMOS field effect transistor 1 of the present invention will be specifically described. In the method of manufacturing a CMOS field effect transistor according to the present invention, when the CMOSFET 1 including the nMOSFET 10 and the pMOSFET 20 is manufactured, the source / drain of the CMOS field effect transistor 1 includes the step of forming the source / drain 13 and 14. In the step of forming 13 and 14, Ge or the like is ion-implanted into the source / drain regions to form an A / C interface 4, and then an impurity is implanted and a first heat treatment is performed to form the first layer. A first high-concentration impurity layer forming step for forming high-concentration impurity layers 133 and 143 for the eyes, and impurities are implanted, and a refractory metal containing Co and Ni is formed thereon. Next, the second high-concentration impurity layer forming step of forming the second high-concentration impurity layers 134 and 144 and the silicide electrodes 132 and 142 at the same time by performing the second heat treatment is characterized.
The CMOS field effect transistor 1 of the present invention is shown in FIG. 1, and the manufacturing process until this final structure is achieved will be described below.

FIG. 3 is a schematic view showing ion implantation for forming a high concentration impurity region in the source / drain region in order to form an nMOSFET on the Si substrate.
First, as shown in FIG. 3, according to a conventional method, the nMOSFET 10 is provided with a gate 12 on a Si substrate 2 on which a p-well 11 is formed. The gate 12 has a gate electrode 121 formed through a gate insulating film 122, and a sidewall insulating film 123 is formed on the side walls of the gate insulating film 122 and the gate electrode 121. Further, source / drains 13 and 14 are provided on both sides of the gate 12 on which the sidewall insulating film 123 is formed. Similarly, the pMOSFET 20 is provided with a gate 22 on the Si substrate 2 on which the n-well 21 is formed. Source / drains 23 and 24 are provided on both sides of the gate 22.
The gate insulating film 121 includes a silicon oxide (SiO ₂ ) film formed by acid treatment of the surface of the Si substrate 2, a silicon oxynitride (SiON) film, a high dielectric constant (High-k) insulating film, and the like. Can be used. High-k insulating films include zirconium oxide (ZrO ₂ ) film, zirconium oxynitride (ZrON) film, zirconium silicate (ZrSiO) film, hafnium oxide (HfO ₂ ) film, hafnium oxynitride (HfON) film, silicon oxynitride A hafnium (HfSiON) film or the like can be used.

Next, in order to form the nMOSFET 10, P, As, Sb, etc. are ion-implanted as n-type impurities in order to provide the high concentration impurity region 131 in the p-well 11. At the same time, the resist film 3 is provided on the side where the pMOSFET 20 is to be formed because the impurities to be ion-implanted are different. In this process, impurities are ion-implanted using the gate 12 as a mask to form a high-concentration impurity region 131 in which the source / drain region of the MOSFET having the LDD structure has a high-concentration source / drain structure. The ion implantation for forming the high-concentration impurity region 131 on the nMOSFET 10 side uses, for example, acceleration voltage of about 5 to 15 keV and a dose of about 2 × 10 ¹⁴ cm ⁻² to about 2 × when using P, As, Sb or the like. The condition is 1 × 10 ¹⁶ cm ⁻² . Hereinafter, the Si substrate 2 in the drawings is omitted.
The CMOS field effect transistor 1 of this embodiment has a high concentration source / drain structure, but does not include the high concentration impurity regions 131 and 141, and the channel region 124 immediately below the gate 12 directly forms the high concentration impurity region 133, 134, 143, 144 may be connected.

FIG. 4 is a schematic view showing ion implantation for forming a high concentration impurity region in the source / drain region in order to form a pMOSFET on the Si substrate.
In order to form the pMOSFET 20, a p-type impurity is ion-implanted in order to form a high concentration impurity region in the n-well 21. At the same time, the resist film 3 is provided in the region where the nMOSFET 10 is to be formed because the impurities to be ion-implanted are different.
When B, Ga, In, or the like is used as the p-type impurity in order to form the high-concentration impurity regions 231 and 241 on the pMOSFET 10 side, for example, an acceleration voltage of about 5 to 15 keV and a dose amount of about 2 × 10 ^{14 are used.} The condition is cm ⁻² to about 1 × 10 ¹⁶ cm ⁻² .

FIG. 5 is a schematic view of forming an A / C interface at the source / drain.
Elements for amorphizing the source / drains 13 and 14 of the Si substrate 2 are ion-implanted, and a part thereof is amorphized to form the A / C interface 4. After the last silicide electrodes 132 and 142 are formed, the A / C interface 4 is positioned slightly deeper than the region to be the silicide / silicon interface and shallower than the junction, for example, the film thickness of the silicide electrodes 132 and 142. If it is 15 nm, the silicon single crystal of the Si substrate 2 of the source / drain 13 and 14 is made amorphous by Ge ion implantation up to about 18 nm. As an element for amorphization, a metal such as Si or Ge, or an inert gas such as Ar or Xe is used. Si ions may be used. By doping the same atoms as the substrate, fluctuations in characteristics can be suppressed.
Further, Ge is ion-implanted to make it amorphous from the crystalline state. At this time, the Ge doping is performed under conditions of, for example, an acceleration voltage of about 1 to 10 keV and a dose of about 1 × 10 ¹⁴ cm ⁻² to about 1 × 10 ¹⁶ cm ⁻² . In addition, an inert gas having a large atomic weight such as Ar or Xe can be used. Because it is an inert gas, it hardly affects the characteristics of the Si substrate, and if the atomic weight is increased, the impact on the crystal lattice of the Si substrate can be increased and it is easy to make it amorphous. .

FIG. 6 is a schematic diagram showing doping for forming the first high-concentration impurity layer in the nMOSFET.
Next, in order to form the nMOSFET 10, n-type impurities are ion-implanted near the surfaces of the source / drain 13 and 14. Positions ion implantation, from the position Amo Le Fass reduction, adding implanting impurities under conditions such that the peak to the presence of impurities in the shallower position. At the same time, a resist film 3 is provided on the side where the pMOSFET 20 is to be formed. Here, examples of the n-type impurity include P, As, and Sb.
At this time, the doping of As is performed under the conditions of an acceleration voltage of about 1 keV and a dose of about 1 × 10 ¹⁴ cm ⁻² to about 1 × 10 ¹⁶ cm ⁻² , for example.

FIG. 7 is a schematic diagram showing the doping for forming the first high-concentration impurity layer in the pMOSFET.
Next, in order to form the pMOSFET 20, a p-type impurity is doped in the vicinity of the surface of the source / drain region. At the same time, a resist film 3 is provided on the side where the pMOSFET is to be formed because the impurities to be doped are different. Here, examples of impurities include B, Al, Ga, and In.

FIG. 8 is a diagram illustrating a state in which the first heat treatment is performed.
At this time, by this heating, the amorphous portion can be recovered and crystallized. Further, by heating, impurities such as P, As, and B doped in the vicinity of the Si substrate surface diffuse and flow into the A / C interface. It is important that the A / C interface 4 formed by Ge ion implantation is narrower than the distribution of impurities such as As and B. The state at that time is shown in FIG. Therefore, by collecting As or the like activated beyond the solid solubility limit at the A / C interface 4 formed by doping with Ge, the first high-concentration impurity layers 133 and 143 having a steep concentration distribution are formed. It is formed. Heating may be performed by any annealing apparatus such as laser annealing, electron beam, infrared ray, halogen lamp, and flash lamp annealing. In particular, the laser annealing method is a method of irradiating a laser beam to heat-treat the surface of a Si substrate or a thin film existing on the surface in a short time locally, and includes a pulse laser annealing method, a CW laser annealing method, and the like. . The flash lamp annealing method is a method in which a xenon lamp is used and light is irradiated with high power density to perform heat treatment in a short time. Any of them can be processed in a short time, so that it can be locally annealed in a very short time of m seconds, and impurities such as ion-implanted As and B, and diffusion of Ge and the like can be performed. Can be suppressed, which is preferable. At this time, as the first heat treatment condition, the surface of the Si substrate is heated in a temperature range of 800 to 1300 ° C. in an inert gas atmosphere such as N 2 for a heat treatment time of several milliseconds.

FIG. 9 is a schematic diagram showing ion implantation of an impurity for forming a second high-concentration impurity layer into an nMOSFET.
As in the case of the first high-concentration impurity layers 133 and 134, n-type impurities are ion-implanted near the surfaces of the source / drain 13 and 14. At the same time, the resist film 3 is provided on the side where the pMOSFET 20 is to be formed because the impurities to be ion-implanted are different. Here, examples of impurities include P, As, and Sb. At this time, the doping of P is performed under the conditions of, for example, an acceleration voltage of about 1 keV and a dose of about 1 × 10 ¹⁴ cm ⁻² to about 1 × 10 ¹⁶ cm ⁻² .

FIG. 10 is a schematic diagram showing ion implantation of impurities for forming the second high-concentration impurity layer into the pMOSFET.
In order to form the pMOSFET 20, p-type impurities are ion-implanted in the vicinity of the surfaces of the source / drain 23 and 24. At the same time, a resist film 3 is provided on the side where the nMOSFET 10 is to be formed. Here, B, Ga, In, etc. can be mentioned as an impurity. At this time, the ion implantation of B is performed under the conditions of an acceleration voltage of about 1 keV and a dose of about 1 × 10 ¹⁴ cm ⁻² to about 1 × 10 ¹⁶ cm ⁻² , for example.

FIG. 11 is a diagram showing that a metal for silicidation is deposited on the surface of each source / drain of the n / pMOSFET of the CMOSFET.
Using the STI 30 and the gate 12 as a mask, a metal to be silicided is deposited on the source / drain 13 and 14. For deposition, EB vapor deposition, boat vapor deposition, sputtering, or the like can be used. Considering the mass productivity, film quality, etc. of CMOSFET 1, it is preferable to use a sputtering method that has been widely used in other conventional processes, and it is particularly preferable to use an ultra-high vacuum sputtering method.
Examples of the metal to be deposited include Ni, Co, W, Mo, Ti, V, and Nb. Of these, Ni and Co are preferable. These can be silicided at a low temperature, and diffusion of impurities can be prevented.
FIG. 12 is a schematic view showing the heat treatment of the metal deposited on the surface of the source / drain region. It is a figure which shows the state which is heat-processing.
At this time, when Ni or the like, such as impurities such as As and B doped in the vicinity of the Si substrate 2 are precipitated by heating due to the impurity segregation effect by heating, is converted to silicide by heating. The interface moves into the Si substrate 2. At the same time, the high-concentration impurity layers 134 and 144 located immediately below are also pushed out and spread to the surface of the silicide interface, and further, the second high-concentration impurity layers 134 and 144 having a thin and steep concentration gradient are formed. . According to this embodiment, a steep impurity diffusion layer having a concentration equal to or higher than the solid solution limit in an equilibrium state and having a width in the depth direction of 5 nm or less can be formed. As the second heat treatment condition for silicidation, the heating method may be any annealing apparatus such as laser annealing, electron beam, infrared ray, halogen lamp, flash lamp annealing. At this time, as the second heat treatment condition, a halogen lamp RTA treatment is performed on the surface of the Si substrate in a N ₂ atmosphere at 200 to 500 ° C. for a treatment time of about 1 minute. As a result, it is possible to prevent the second high-concentration impurity layers 134 and 144 from becoming thick due to excessive diffusion of impurities, thereby forming a silicide electrode.

  The structure of the CMOS field effect transistor 1 manufactured by the method for manufacturing the CMOS field effect transistor 1 of the present invention is shown in FIG. 1, but the silicide electrode 132, 142 and the Si substrate 2 are formed by the above manufacturing method. In this case, impurities in the Si region silicidated due to the impurity segregation phenomenon at the time of silicide formation segregate at the interface, and the second high-concentration impurity layers 134 and 144 are formed. By the above manufacturing method, the first high-concentration impurity layers 133 and 143 formed by additional impurity implantation and laser annealing at the silicide / silicon interface and the second layer formed by utilizing the impurity segregation phenomenon at the time of silicide formation. A CMOSFET 1 is formed in which two steep high-concentration impurity layers 133, 143, 134, and 144 are formed so as to overlap the silicide portions of the high-concentration impurity layers 134 and 144 of the eyes. At this time, the ion species of the impurity implanted for the first time may be the same or different.

It is the schematic which shows the structure of the CMOS field effect transistor of this invention. It is a schematic diagram which shows the principle of the semiconductor manufacturing method using the impurity segregation effect. It is the schematic which shows the ion implantation which forms a high concentration impurity region in a source / drain region in order to form nMOSFET on a Si substrate. It is the schematic which shows the ion implantation which forms a high concentration impurity region in a source / drain region, in order to form pMOSFET on a Si substrate. It is the schematic which forms an A / C interface in a source / drain. It is the schematic which shows doping which forms the high concentration impurity layer of the 1st layer in nMOSFET. It is the schematic which shows doping which forms the high concentration impurity layer of the 1st layer in pMOSFET. It is a figure which shows the state which is performing the 1st heat processing. It is the schematic which shows ion-implanting the impurity for forming the high concentration impurity layer of the 2nd layer in nMOSFET. It is the schematic which shows ion-implanting the impurity for forming the high concentration impurity layer of the 2nd layer into pMOSFET. It is a figure which shows depositing the metal for silicidation on the surface of each source / drain of n / pMOSFET of CMOSFET. It is the schematic which shows heat-treating the metal deposited on the surface of a source / drain region.

Explanation of symbols

1 CMOSFET
2 Silicon substrate 3 Resist film 4 A / C interface 10 nMOSFET
11 p-well 12 gate 121 gate electrode 122 oxide film 123 side wall insulating film (side wall)
124 channel region 13 source 131 high concentration impurity region 132 silicide electrode 132 ′ deposited metal 133 high concentration impurity region of the first layer 134 high concentration impurity region of the second layer 14 drain 141 high concentration impurity region 142 silicide electrode 143 first High concentration impurity region 144 of the second layer 144 High concentration impurity region 20 of the second layer pMOSFET
21 n-well 22 gate 23 source 24 drain 30 inter-element isolation oxide film (STI)

Claims (3)

In a method of manufacturing a field effect transistor having a step of forming source / drain regions in a semiconductor substrate,
  The step of forming the source / drain region includes:
  Forming an amorphous layer on the surface of the semiconductor substrate by performing ion implantation on the semiconductor substrate;
  Injecting a first impurity into the amorphous layer;
  Forming a first impurity layer by segregating the first impurity layer to a bottom of the amorphous layer by a first heat treatment;
  After the first heat treatment, injecting a second impurity into the amorphous layer surface;
  Depositing a refractory metal on the amorphous layer after implanting the second impurity;
  A step of reacting the refractory metal with the semiconductor substrate by a second heat treatment to form a silicide electrode and moving the second impurity into the first impurity layer.
  A method of manufacturing a field effect transistor. The first heat treatment is performed by a laser annealing method or a flash lamp annealing method.
  The method of manufacturing a field effect transistor according to claim 1. The step of forming the amorphous layer on the surface of the semiconductor substrate is performed by ion implantation of Ge.
  The method of manufacturing a field effect transistor according to claim 1 or 2, wherein