JP5336070B2 - Improved method of selective epitaxial growth process. - Google Patents

Description

  The present invention relates to the field of manufacturing semiconductor devices and methods for selectively forming epitaxial semiconductor layers.

  Furthermore, the present invention relates to an improved manufacturing method of a semiconductor device using selective epitaxial growth (SEG).

  Epitaxial growth is a process of depositing a thin layer (typically 0.5 to 20 μm) of a single crystal material on a single crystal substrate, and chemical vapor deposition (CVD) is usually used. Epitaxial growth is defined by the degree of matching between the crystal structure of the layer being grown / deposited and the crystal structure of the substrate.

  In semiconductor manufacturing, CVD is widely used to deposit materials in various forms. For example, in the semiconductor industry, CVD is a chemical process used to form thin films of high purity and high performance solid materials. In a typical CVD process, the substrate is exposed to one or more volatile precursors (semiconductor source gases) that react and / or decompose on the surface of the substrate to form the desired thin film of the required material. It is.

  Low temperature epitaxial growth is very attractive in device fabrication to improve the electrical properties of advanced complementary metal oxide semiconductors (CMOS) and bipolar complementary metal oxide semiconductors (BiCMOS). CMOS is a major class of integrated circuits that can cover both digital logic and analog circuits.

  In particular, silicon, silicon-germanium, pure germanium, and III / V group selective epitaxial growth (SEG) such as GaAs and InGaAs are three-dimensional bipolar, metal oxide semiconductor (MOS), bipolar complementary metal oxide semiconductor. (BiCMOS), and plays an important role in the manufacture of super integrated circuits (VLSI) and ultra super integrated circuits (ULSI) used in silicon-on-insulator (SOI) devices. In the case of a semiconductor substrate having a patterning structure formed in an insulator / dielectric mask material, SEG is a process in which epitaxial growth of the semiconductor material occurs only in exposed (uncovered) regions of the semiconductor substrate. This process is called “selective” if no deposition / growth occurs in the area covered by the insulator / dielectric mask. This technology has a lot of attractive interest due to the possibility of very advanced device self-alignment processing. Some important applications of SEG are: (i) base layer stack of heterojunction bipolar transistors in BiCMOS technology, (ii) elevated source / drain on bulk Si as well as on silicon on insulator (SOI) wafers (Iii) growth of Ge on Si or shallow trench isolation (STI) of patterned Si wafer, (iv) growth of III / V on Ge or STI patterned wafer. STI is an integrated circuit structure that prevents current leakage between adjacent semiconductor device elements.

  SEG is used for a variety of deposition chemistries that can be separated into two classes, namely those with and without chlorine. In general, unlimited SEG in a chlorine-free atmosphere is possible only at temperatures above 1100 ° C. Below this temperature, certain Si nucleation occurs on the insulating surface and deposition of polycrystalline silicon occurs. Polycrystalline silicon deposition is a process of depositing a polycrystalline silicon layer on a substrate.

The selectivity of the SEG process at low temperatures (means that during SEG, the material grows / deposits on the bare substrate but does not grow / deposit on the insulator / dielectric material), for example Shown for chlorine mixtures containing SiH ₄ and HCl, or SiH ₂ Cl ₂ (DCS) with or without HCl. Such chlorine components can remove nuclei from the insulator surface before the size of the nuclei reaches criticality. In the absence of Si nucleation on the insulator surface, selectivity increases.

  However, as Caymax et al. Stated in the “Proceedings of the 206th Meeting of the Electrochemical Society (Abs 1363, 2004)”, even when using chlorine-based chemicals, full selectivity is not always guaranteed. Absent. In order to suppress Si nucleation, an etching gas (eg HCl) is added to the semiconductor source gas / precursor.

  Etching is used in microfabrication to chemically remove layers from the wafer surface during manufacturing.

  Changes in pre-treatment (e.g. changes in concentration of chemicals used during the wet cleaning process, changes in composition / stoichiometry of deposited nitride material, typical of wet chemicals or carrier and process gases) Contamination (humidity, organic matter, metal)) is known to lead to a decrease in selectivity as well as changes in the composition of the insulator. Defects, contamination, or non-uniformity of the insulator surface promotes Si nucleation. In order to compensate for expanded Si nucleation, a higher flow of etching gas is required. This negatively affects the growth rate and controls the process for other unwanted effects (eg faceting). This causes important problems, especially in manufacturing.

  Thus, the selectivity of the SEG process is influenced by the choice of insulator material, the method of deposition, and the steps prior to SEG, so that a stronger SEG process against process changes and contamination prior to SEG. It is desirable to provide.

  An object of the present invention is to provide an improved method for manufacturing a semiconductor device using selective epitaxial growth, which does not have the disadvantages of the prior art.

  In particular, the present invention aims at processing that strongly limits the amount of heat in the SEG process for deep submicron CMOS.

  A preferred object of the present invention is to provide a method for surface treatment of a semiconductor substrate, to provide a less reactive surface and to maintain a wider process window for selective epitaxial processes.

  It is another object of the present invention to provide an improved method which provides room for adjusting different growth rates in faceted or n-type and p-type implanted substrates.

  The present invention seeks to provide a method for improving the characteristics of a selective epitaxial growth process, such as increased selectivity.

Another object of the present invention is to provide a method for manufacturing a semiconductor device using a selective epitaxial growth (SEG) process as described below.
Such a manufacturing method is at least
Supplying a semiconductor substrate;
Forming a pattern of insulating material on a semiconductor substrate, thereby forming a covered and uncovered surface;
Cleaning a covered and uncovered surface of a semiconductor substrate having a pattern of formed insulating material;
Placing a substrate having a pattern of insulating material into a reaction chamber of an epitaxial reactor;
Initiating selective epitaxial growth including introducing at least one semiconductor source gas into the reaction chamber of the epitaxial reactor together with at least one first carrier gas if possible.

  In accordance with the present invention, such a process involves introducing a halogen-containing etching gas with a second carrier gas, if possible, in the reaction chamber prior to the step of initiating selective epitaxial growth, possibly in-situ on the surface of the substrate. Processing is performed.

  Furthermore, according to the present invention, a cleaning process is performed on the substrate prior to introducing the substrate into the epitaxial reactor.

  Further, the cleaning step includes wet cleaning and / or wet etching.

  Preferably, the semiconductor substrate is selected from the group consisting of a single crystal silicon substrate, a single crystal germanium substrate, a single crystal silicon germanium substrate, a single crystal silicon germanium carbide substrate, a single crystal silicon carbide substrate, and a silicon on insulator (SOI) substrate. Is done.

Suitably, the insulating material is a dielectric material, preferably silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  Preferably, the main semiconductor source gas is a source gas selected from the group consisting of a silicon source gas, a germanium source gas, a silicon germanium source gas, a III / V source gas, a carbon source gas, and a germanylsilane gas and a mixed gas thereof. , Are selected from the group consisting of

Preferably, the halogen-containing etching gas is a gas containing F or Cl, and more preferably Cl-containing, such as HCl gas, Cl ₂ gas, diluted HCl gas, and diluted Cl ₂ gas. Gas, or other fluorine-containing gas, or a mixed gas thereof.

Suitably, the difference 1 and / or the second carrier gas is H ₂ gas or an inert gas.

  In a preferred embodiment, the introduction of the halogen-containing etching gas is performed at least once prior to the introduction of the at least one semiconductor source gas, and the introduction of the halogen-containing etching gas is performed during the introduction of the at least one semiconductor source gas. Continue without interruption.

  In another preferred embodiment, the introduction of the halogen-containing etching gas is performed at least once prior to the introduction of the at least one semiconductor source gas, and the introduction of the halogen-containing etching gas is performed while the at least one semiconductor source gas is being introduced. Is stopped and restarted.

  In another preferred embodiment, introduction of at least one semiconductor source gas and introduction of a halogen-containing etching gas are repeated.

Preferably, the in-situ pretreatment using a halogen-containing etching gas that is performed prior to the selective epitaxial growth step is performed by in-situ H ₂ thermal annealing.

More preferably, the temperature of the in situ H ₂ thermal annealing is higher than the temperature of the in situ pretreatment using a halogen-containing etching gas.

More preferably, the in situ H ₂ thermal anneal is performed at a temperature between 700 ° C. and 900 ° C., more preferably between 700 ° C. and 850 ° C.

  In a preferred embodiment, the temperature of the in-situ pretreatment using the halogen-containing etching gas is higher than the temperature of the selective epitaxial growth process.

  In another preferred embodiment, the temperature of the in-situ pretreatment using the halogen-containing etching gas is performed at a temperature lower than the temperature of the selective epitaxial growth process.

  Preferably, selective epitaxial growth is performed at a temperature between 500 ° C and 900 ° C.

  Preferably, selective epitaxial growth is performed at reduced pressure (LPCVD) or atmospheric pressure.

  More preferably, the in situ pretreatment with a halogen-containing etching gas is performed at a temperature between 500 ° C. and 900 ° C., preferably between 550 ° C. and 750 ° C.

  More preferably, the temperature of the in situ pretreatment using a halogen-containing etching gas is lower than 900 ° C.

  More preferably, the minimum duration of the in-situ pretreatment using a halogen-containing etching gas is at least 1 second, preferably at least 1 minute.

  Suitably, the in situ pretreatment with a halogen-containing etching gas is performed for at least 30 seconds, more preferably 1 to 10 minutes, more preferably 1 to 8 minutes, more preferably 2 to 4 minutes.

  Advantageously, the temperature and time of the process so that the amount of etching required during the in-situ pretreatment using the halogen-containing etching gas is less than or equal to the etching of the semiconductor material of 0.5 to 10 mm. Should be decided.

  Preferably, during pre-treatment, less than 10 mm, more preferably less than 5 mm of semiconductor material is removed from the uncovered surface.

  As used herein, the term “in situ” means inside the reaction chamber of an epitaxial reactor.

  “Insulating” as used in the present invention refers to the property of obstructing the current path by surrounding it with a non-conductive material.

  As used herein, the term “insulator” refers to an insulating or non-electrically conductive material.

  As used herein, “dielectric” means non-electrically conductive.

  In the present invention, it is understood that the terms “insulator” and “dielectric” are equivalent.

  The term “injection” as used in the present invention means the action of starting the introduction of gas and continuing this introduction for a predetermined period of time.

  It will be understood that a period is defined by a start time and an end time.

  The objects of the present invention will be explained in more detail using non-limiting examples and drawings.

  In one aspect, the present invention relates to a method for manufacturing a semiconductor device such as a CMOS device. A non-single crystal pattern is formed on the single crystal semiconductor substrate. In the case of CMOS, insulator spacers are formed on the sidewalls of the non-single crystal pattern.

  The surface of the substrate having an insulating spacer may be cleaned before being introduced into the reaction chamber and may be subjected to a wet etching process for removing the natural oxide film. This process, which is a cleaning and / or wet etching process, is necessary just prior to epitaxial growth, as natural oxide grows on the (bare) substrate when exposed to the surrounding environment.

  For example, a wet etch process such as a diluted HF process amplifies the reactivity of the insulating material and leads to a decrease in selectivity during selective epitaxial growth. After the cleaning process (wet etching), a substrate having an insulating spacer is placed in the reaction chamber of the epitaxial apparatus.

  A first annealing step is then selectively applied to the substrate. The annealing process is performed by introducing a carrier gas into the reaction chamber. Hydrogen is used as the carrier gas and the annealing step is preferably performed at a temperature between 700 ° C. and 900 ° C.

  Next, after the annealing process is completed, in-situ pretreatment using an etching gas is performed. Prior to the introduction of the semiconductor source gas, an etching gas is introduced into the reaction chamber. This corrects the amplified reactivity of the insulating material. Selective epitaxial growth begins when at least one semiconductor source gas is introduced into the reaction chamber. The etching gas may be continuously supplied without interruption during in-situ pretreatment or selective epitaxial growth, but the flow rate used varies depending on the process.

  In one embodiment, the spacer typically comprises a silicon-based dielectric material such as silicon oxide or silicon nitride.

  In some embodiments, the single crystal semiconductor substrate may be one of the following substrates: Si, Ge, SiGe, SiGeC, and SiC of different composition, or a silicon on insulator (SOI) substrate. .

  In other embodiments, the non-single crystal semiconductor dielectric pattern is formed from an amorphous semiconductor layer or a polycrystalline semiconductor layer. The amorphous semiconductor layer or the polycrystalline semiconductor layer may be a silicon layer, a gallium layer, a silicon gallium layer, or a metal gate material.

In another preferred embodiment, the etching gas preferably includes a halogen component that reacts with the epitaxial semiconductor layer and does not etch the bulk insulator material. Thus, the in-situ treatment only affects the thin surface layer of insulating material. The halogen-containing etching gas may be HCl gas, Cl ₂ gas, diluted HCl, or diluted Cl ₂ gas. The diluted HCl gas may be a mixed gas of HCl and H ₂ or a mixed gas of HCl and an inert gas (for example, Ar or He). The diluted Cl ₂ gas may be a mixed gas of Cl ₂ and H ₂ , or a mixed gas of Cl ₂ and an inert gas (eg, Ar or He).

In other embodiments, the semiconductor source gas may be one of a silicon source gas, a germanium source gas, and a silicon germanium source gas, or III / V or a mixture thereof. The silicon source gas may be one of silane (SiH ₄ ) gas, disilane (Si ₂ H ₆ ) gas, dichlorosilane (SiH ₂ Cl ₂ ) gas, SiHCl ₃ gas, and SiCl ₄ gas, The germanium source gas may be GeH ₄ gas. The semiconductor source gas is also a more advanced gas of the family of germylsilanes such as H ₃ GeSiH ₃ , (H ₃ Ge) ₂ SiH ₂ , (H ₃ Ge) ₃ SiH, (H ₃ Ge) ₄ Si The carbon source gas, which may be one or may contain a carbon source gas for the growth of SiC and SiGeC, may be C ₂ H ₆ gas or CH ₃ SiH ₃ gas. The semiconductor source gas preferably includes a doping gas such as phosphine (PH ₃ ) for n-type doping and a doping gas such as diborane (B ₂ H ₆ ) for p-type doping.

In addition to the choice of insulating material (eg, SiO ₂ , Si ₃ H ₄ , SiC, or polymer material) and the manner in which it is deposited, processes prior to SEG such as cleaning and immersion in diluted HF It should also be noted that the process has an important impact on the selectivity of the SEG process.

  Due to the strong limitations on the amount of heat of selective epitaxial growth in deep sub-micron CMOS processes, it is necessary to perform HF dip prior to growth to remove most of the native oxide. As a negative side effect, HF dip makes the surface of the insulating material more reactive, which narrows the process window in which growth is selected. Extended reactivity is observed with insulating materials such as silicon nitride and silicon oxide.

In particular, in the case of silicon nitride, a cleaning step, which is performed prior to epitaxial growth and is followed by a diluted HF step to remove native oxide, makes the Si ₃ N ₄ surface more reactive and increases the selectivity in SEG. It should be noted that this leads to a decline. Furthermore, it has been observed that more nucleation occurs on the Si ₃ N ₄ surface treated with diluted HF than on the uncleaned surface. The increase in the number of nuclei formed is a direct measure of surface reactivity.

  The increased reactivity of the nitride surface after HF is observed by the following experiment. Short deposition using dichlorosilane (DCS) on the nitride surface. Since DCS contains Cl, it is a Si precursor gas having almost selectivity without adding extra HCl. Due to the very short deposition time, only separated nuclei are formed on the nitride surface instead of the clogged layer. The number of nuclei formed at a given deposition time can be counted, which is a direct measurement of surface reactivity, reactive gas and reaction tube conditions.

  By using this method, an increase in the number of nuclei, at least on the order of orders, is observed when the nitride surface is HF-impregnated prior to DCS deposition.

The extended nitride reactivity is shown by the following experiment. That is, 20 nm of PECVD nitride is first deposited on three silicon wafers, followed by ammonium peroxide mixture (H ₄ OH / H ₂ O ₂ / H ₂ O = 1: 1: 5). A standard SC1 wash followed by a DI rinse and drying.

  All wafers are placed in an epitaxial (epi) reactor for deposition using a short time DCS. Prior to the epitaxial growth process, the wafers 2 and 3 are subjected to an extra HF immersion treatment in 2% HF for 30 seconds. Prior to DCS deposition, the wafer 3 is subjected to in situ HCl pretreatment in an epireactor. Table 1 summarizes the results of particle measurements before and after epi deposition in all these cases.

  Prior to deposition, all wafers show similar light point defects (LPD). As can be seen from Table 1, the distribution for different bins (bins refer to a specific range of particle size variation based on particle diameter) is equal and the haze (background measurement provided by the particle measurement tool) Scattering information, measuring small surface dimensional changes such as the presence of small particles with a diameter of 50 nm or less, for example, shows similar values. For all three wafers, approximately 250 counts for bin 1 were measured, corresponding to LPDs with diameters greater than 0.1 microns, and haze values below 0.15 ppm.

  After deposition, the number of LPDs in bin 1 is much higher on wafers 2 and 3, which were diluted HF dip prior to deposition. For wafer 2, both bins 1 and 2 are saturated and the average haze is about 8.089 ppm, indicating that there are many small nuclei on the nitride surface.

  The wafer 3 that was subjected to the first diluted HF dip prior to DCS deposition followed by in situ HCl pretreatment in the epireactor has a sufficiently reduced number of LPDs after deposition. The haze is about 30% lower and the bin 2 value (LPD with a diameter greater than 0.150 microns) is reduced from 20802 to 530, which is actually similar to that of wafer 1. In this case, the increased reactivity of the nitride surface was reduced by in situ HCl pretreatment.

  Therefore, in situ HCl pretreatment prior to the SEG process restores the top layer stoichiometry of the nitride, which was affected by the initially diluted HF treatment.

  In addition, the SEG process is more robust because in situ HCl treatment can compensate for other variations in process parameters.

  For example, a lower than critical value is used for the (HCl) etch gas flow added during the SEG process. The critical value refers to the minimum etch gas flow rate required to have sufficient selectivity for nitride without in situ HCl pretreatment. Another feature of in-situ HCl pretreatment is that there is room to adjust the process for faceting and the difference in growth lag on the n-type and p-type implanted substrates by lowering the flow rate of the etching gas (HCl). It will be bigger.

  At the same time, by introducing in-situ HCl pretreatment, the SEG process changes the changes introduced by cleaning, stoichiometry of the deposited nitride layer, carrier gas / process gas, or metal or moisture from the cleaning bath Be more robust against contamination.

  Furthermore, by etching the highly doped layer on the surface, a reduction in the difference in growth rate on the n-type and p-type semiconductor substrates is achieved.

  Prior to HF immersion, there is likely a thin oxide layer on the nitride layer on the as-deposited layer, which has actually been confirmed by XPS measurements. The thin oxide layer is almost completely removed by HP immersion, potentially leading to selectivity degradation during SEG. This is because it is known that the selectivity to oxide is better than the selectivity to nitride.

In a preferred embodiment, the process flow includes at least the following steps.
(I) Wet cleaning step, SC1 cleaning (well known as the first step of standard RCA cleaning) may be used.
(II) Diluted HF treatment (immersion), typically 30% at 2% HF.
(III) Thermal annealing for 1 to 10 minutes in an H ₂ atmosphere at 700 to 900 ° C.
(IV) In situ HCl pretreatment at a temperature between 500-900 ° C. with a 50-100 sccm HCl stream diluted in 20-40 slm hydrogen, each time preferably between 2-4 minutes .
(V) Selective epitaxial growth by simultaneously supplying an etching gas (for example, HCl) and at least one source gas (for example, SiH ₄ , SiCl ₂ H ₂ ).

  These processes are preferably continuous processes.

In situ HCl pretreatment (above procedure and step IV in FIG. 1) is performed prior to selective epitaxial growth (V), and optionally in situ H ₂ anneal (III) is performed before. Steps (I) and (II) are preferably wet treatment operations outside the epireactor. Steps (III) to (V) are performed in situ in the epireactor.

  FIG. 2 shows the case where the in situ HCl pretreatment is performed immediately before the introduction of at least one semiconductor source gas. According to the present invention, the introduction of the etching gas (HCl) is started at a time interval δ0 before the introduction (t0) of at least one semiconductor source gas.

  According to the preferred embodiment shown in FIG. 2A, the introduction of the etching gas (HCl) is continued without interruption after the introduction of at least one semiconductor source gas.

  According to another embodiment shown in FIG. 2B, the introduction of the etching gas (HCl) is started at a time interval δ0 before the introduction of at least one semiconductor source gas (t0), but is subsequently interrupted. And resumed with the introduction of at least one semiconductor source gas.

  In the case of FIG. 2B, the deposition temperature in the epitaxial process is lower than the in-situ pretreatment temperature, preventing the desorption of halogen species and maintaining the protective effect.

  FIG. 2C shows the deposition of a plurality of steps (n), and the introduction of the etching gas (HCl) is performed every time interval δi before the introduction of at least one semiconductor source gas (ti, i = 0 to n). You can get started. In the case of FIG. 2C, the deposition step (i) can be started immediately after the deposition step (i-1) is completed.

  Halogen content in step (1), (1) ′ or (1) ″ as compared to the introduction temperature of any semiconductor source gas in step (2), (2) ′ or (2) ″ The introduction temperature of the etching gas may be the same or different and may be higher or lower.

  The halogen-containing etching gas in steps (1), (1) ′ and (1) ″ is the same or different as the semiconductor source gas in steps (2), (2) ′ and (2) ″. Higher or lower.

  During the introduction of any of the semiconductor source gases in steps (2), (2) ′ and (2) ″, the gas in steps (1), (1) ′ and (1) ″ is the main etch. Supplied as a gas.

  In a preferred embodiment, the in situ (HCl) pretreatment described in steps (1), (1) ′ and (1) ″ corresponding to step VI in FIG. 1 is preferably between 500 and 900 ° C. More preferably, it is performed at a temperature between 500 and 850 ° C, and even more preferably at a temperature of 550 to 750 ° C.

  In a preferred embodiment, the in-situ (HCl) pretreatment temperature described in steps (1), (1) ′ and (1) ″ corresponding to step VI in FIG. 1 prevents desorption of Cl-protected species. In order to do so, it should be lower than 900 ° C.

  In a preferred embodiment, the in situ (HCl) pretreatment described in steps (1), (1) ′ and (1) ″ corresponding to step VI in FIG. 1 has a duration of at least 30 seconds. 1 to 10 minutes, preferably 1 to 8 minutes, and more preferably 2 to 4 minutes.

  In another preferred embodiment, the minimum duration of the in situ (HCl) pretreatment described in steps (1), (1) ′ and (1) ″ corresponding to step VI in FIG. Seconds, preferably at least 1 minute.

  The etchant required during in-situ pretreatment is less than or equal to 0.5 to 2 inches of etching of the semiconductor material, which is also applicable to the most advanced process flows.

  Table 2 and FIG. 3 show that the 1 second HCl pretreatment (performed on the nitride surface treated with diluted HF) is the initial haze value of the surface (the nitride surface with a short deposition of dichlorosilane (DCS)) (As measured by the number of nuclei having a diameter smaller than 50 nm, formed on the surface). The haze value is further improved by increasing the pretreatment time, and the lowest value is obtained after 30 seconds. Increasing the HCl flow (during a given pretreatment time) also improves the haze value.

  The advantageous effects obtained are (1) the fact that Cl protects surface dangling bonds present on the nitride surface after removing a very thin oxide layer by diluted HF, or (2) in situ HCl. The process can be explained by any of the fact that the etch etches excess Si and restores surface stoichiometry, whereas diluted HF renders the Si-rich surface by preferential N etching.

堆積前後において、ＬＰＣＶＤ窒化物の上で測定された粒子数

Number of particles measured on LPCVD nitride before and after deposition

異なったＨＣｌその場前処理時間についてのヘイズの測定（５０ｎｍより小さい直径を有する核の反射数）

Haze measurements for different HCl in situ pretreatment times (number of reflections of nuclei with diameters smaller than 50 nm)

A process sequence with in situ (HCl) pretreatment prior to introducing the semiconductor source gas into the reaction chamber, steps III-V show the process sequence performed in the epireactor. 2 shows an overview of a time schedule for different embodiments of the present invention. The haze measurements for different HCl pre-treatments are shown.

Claims (9)

A method of manufacturing a semiconductor device using a selective epitaxial growth (SEG) process, comprising:
Supplying a semiconductor substrate;
Forming a pattern of insulating material on a semiconductor substrate, thereby forming a covered and uncovered surface;
Cleaning a covered and uncovered surface of a semiconductor substrate having a pattern of formed insulating material;
Placing a substrate having a pattern of insulating material into a reaction chamber of an epitaxial reactor;
Initiating selective epitaxial growth including introducing at least one semiconductor source gas with at least one first carrier gas into a reaction chamber of the epitaxial reactor;
Prior to the step of starting the selective epitaxial growth, in-situ pretreatment is performed on the surface of the substrate by introducing a halogen-containing etching gas together with the second carrier gas in the reaction chamber ,
The semiconductor substrate is selected from the group consisting of a single crystal silicon substrate, a single crystal germanium substrate, a single crystal silicon germanium substrate, a single crystal silicon germanium carbide substrate, a single crystal silicon carbide substrate, and a silicon on insulator (SOI) substrate,
The insulating material is a dielectric material, preferably made of silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ),
The cleaning process includes a wet cleaning process and / or a wet etching process,
The main semiconductor source gas is a group consisting of a silicon source gas, a germanium source gas, a silicon germanium source gas, a III / V source gas, a carbon source gas, and a source gas selected from the group consisting of a germanium silane gas and a mixed gas thereof. Selected from
The first and / or second carrier gas is H ₂ gas or inert gas;
The halogen-containing etching gas is selected from the group consisting of HCl gas, Cl ₂ gas, diluted HCl gas, and diluted Cl ₂ gas;
The diluted HCl gas is a mixed gas of HCl and H ₂ gas, or HCl and an inert gas,
The introduction of the halogen-containing etching gas is performed at least once prior to the introduction of the at least one semiconductor source gas, and the introduction of the halogen-containing etching gas continues without interruption during the introduction of the at least one semiconductor source gas. And
The introduction of at least one semiconductor source gas and the introduction of a halogen-containing etching gas are repeated,
A manufacturing method characterized in that the amount of etching required during in-situ pre-treatment using a halogen-containing etching gas is less than or equal to the etching of a semiconductor material of 0.5 to 10 mm . The manufacturing method according to claim 1 , wherein the diluted Cl ₂ gas is a mixed gas of Cl ₂ and H ₂ , or a mixed gas of Cl ₂ and an inert gas. The introduction of the halogen-containing etching gas is performed at least once prior to the introduction of the at least one semiconductor source gas,
The manufacturing method according to claim 1 or 2 , wherein the introduction of the halogen-containing etching gas is stopped and restarted with the introduction of at least one semiconductor source gas. The manufacturing method according to claim 1 , wherein the in-situ pretreatment using a halogen-containing etching gas prior to the selective epitaxial growth step is performed by in-situ H ₂ thermal annealing. The manufacturing method according to claim 4 , wherein the temperature of in-situ H ₂ thermal annealing is higher than the temperature of in-situ pretreatment using a halogen-containing etching gas. Situ pretreatment using a halogen-containing etching gas, prepared according to any one of claims 1 to 5 carried out at a temperature between 500 ° C. and a temperature of between 900 ° C., preferably at 550 ° C. and 750 ° C. Method. The production method according to claim 1, wherein the in-situ pretreatment using the halogen-containing etching gas is performed for at least 1 second. The manufacturing method according to any one of claims 1 to 7 , wherein the duration of the in-situ pretreatment using the halogen-containing etching gas is at least 30 seconds, preferably at least 1 minute. The manufacturing method according to claim 1 , wherein the in-situ pretreatment using the halogen-containing etching gas is performed for 1 to 10 minutes, preferably 1 to 8 minutes, more preferably 2 to 4 minutes.

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