JP5331998B2 - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having the small number of wiring layers. <P>SOLUTION: In this nonvolatile semiconductor storage device, a plurality of memory blocks MB which contain: a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns; a word line WL and a digit line DL provided corresponding to each row; and a bit line BL provided corresponding to each column are put in order in an extension direction of the word line WL, and a metal piling word line MWL is provided in common for the plurality of memory blocks MB corresponding to each word line WL, wherein a magnetic field application current I<SB>DL</SB>is caused to flow in the digit line DL corresponding to the metal piling word line MWL which is set to a selection level of the selected memory blocks MB. Accordingly, as a digit line driving circuit DD is controlled via the metal piling word line MWL, a main digit MDL line is not needed and the number of wiring layers becomes small. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a tunnel magnetoresistive element that stores data by changing a resistance value.

  The nonvolatile semiconductor memory device can hold stored data even when the power supply voltage is cut off, and does not need to supply the power supply voltage in a standby state. For this reason, it is widely used in portable devices that are required to have low power consumption.

  One such nonvolatile semiconductor memory device is an MRAM (Magnetic Random Access Memory) that stores data using the magnetoresistive effect. One of the MRAMs uses a tunnel magnetoresistive element having a magnetic tunnel junction (MTJ) (see, for example, Patent Document 1 and Non-Patent Document 1).

  In this MRAM, a memory cell including a tunnel magnetoresistive element and a transistor is arranged at an intersection of a word line and a digit line and a bit line. One electrode of the tunnel magnetoresistive element is connected to the bit line, the other electrode is grounded through the transistor, and the gate of the transistor is connected to the word line. In the write operation, a magnetic field application current is supplied to the digit line, and a write current having a polarity corresponding to the write data is supplied to the bit line to place the tunnel magnetoresistive element in a high resistance state or a low resistance state. During the read operation, the word line is set to the selected level to make the transistor conductive, and the current flowing out from the bit line through the tunnel magnetoresistive element and the transistor is detected to read the stored data.

There is also an MRAM that employs a so-called folded bit line configuration. In this MRAM, two word lines are provided corresponding to each row. One memory cell of two adjacent memory cells in the same row is arranged at the intersection of one of the corresponding two word lines and the corresponding bit line, and the other memory cell Is arranged at the intersection of the other word line and the corresponding bit line. In this MRAM, the common-mode noise generated in the two bit lines can be removed and data can be read accurately.
US Pat. No. 7,019,370 2004 Symposium on VLSI Circuits Digest of Technical Papers p.450-453 A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

  In such an MRAM, a metal piled word line is formed above the word line made of poly-silicon, and the word line and the metal piled word line are connected at a plurality of locations, thereby reducing the wiring resistance and the word line. The rise time of the potential is reduced to speed up the reading operation.

Further, since it is necessary to pass a predetermined write current I _DL through the digit line, the resistance value R _{DL of the} digit line becomes smaller than the value VDD / I _DL obtained by dividing the power supply voltage VDD by the write current I _DL. In addition, it is necessary to limit the length of the digit line. As a countermeasure, the memory array is divided into a plurality of memory blocks, digit lines are provided for each memory block, a common main digit line is provided for the plurality of memory blocks, and the digit lines are controlled by the main digit line and the block selection signal. There is a method, that is, a method of hierarchizing digit lines (see FIG. 9).

  However, when both the metal piled word line and the main digit line are employed, there are problems that the number of wiring layers increases, the number of processes increases, and the manufacturing cost increases.

  Therefore, a main object of the present invention is to provide a nonvolatile semiconductor memory device having a small number of wiring layers.

A nonvolatile semiconductor memory device according to an embodiment of the present invention includes a memory array divided into a plurality of memory blocks. Each memory block is arranged in a plurality of rows and a plurality of columns, each of which includes a plurality of memory cells including a tunnel magnetoresistive element that stores data by a change in resistance value, and a plurality of sets of 2 provided corresponding to a plurality of rows This includes a word line, a plurality of digit lines provided corresponding to a plurality of rows, and a plurality of bit lines provided corresponding to a plurality of columns, respectively. One memory cell of two adjacent memory cells in the same row is arranged at the intersection of one of the corresponding two word lines and the corresponding bit line, and the other memory cell Are arranged at the intersection of the other of the two corresponding word lines and the corresponding bit line. The plurality of memory blocks are arranged in the extending direction of the word lines. The nonvolatile semiconductor memory device further includes two piled word lines, a row decoder, a column decoder, a digit line driving circuit, and a bit line driving circuit. Two piling word line corresponding to each row is provided in common to a plurality of memory blocks are connected to two word lines of each set of corresponding. The row decoder selects one of the plurality of rows and one of the two piled word lines belonging to the row in accordance with the row address signal, and selects the selected piled- up Set the word line to the selected level. The column decoder selects one of the plurality of bit lines according to the column address signal. A digit line drive circuit is provided corresponding to each digit line, and at the time of a write operation, one of the two piled word lines in the corresponding row is set to the selected level. In response to this, a magnetic field application current is supplied to the corresponding digit line. The bit line driving circuit supplies a write current to the bit line selected by the column decoder during a write operation.

  In this nonvolatile semiconductor memory device, the digit line driving circuit is controlled via the piled word line, so that the main digit line becomes unnecessary and the number of wiring layers can be reduced.

  FIG. 1 is a block diagram showing the overall configuration of an MRAM device according to an embodiment of the present invention. In FIG. 1, the MRAM device includes a memory array 1, a row decoder 2, a drive circuit 3, a column decoder 4, read / write control circuits 5 and 6, and a control circuit 7.

  The memory array 1 is divided into a plurality of memory blocks MB. As shown in FIG. 2, each memory block MB includes a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns, a digit line DL and a pair of word lines WL provided corresponding to each row, Corresponding bit lines BL. A power supply voltage VDD is applied to one end of each digit line DL.

  The plurality of memory blocks MB are arranged in the extending direction of the word lines WL. A plurality of metal piled word lines MWL and a plurality of source lines SL are provided in common to the plurality of memory blocks MB. Each metal piled word line MWL is provided in common to a plurality of memory blocks MB corresponding to each word line WL, and is connected to each corresponding word line WL at a plurality of locations. Further, the plurality of source lines SL are arranged between the plurality of rows and on both sides, and each source line SL is grounded.

  Each memory cell MC includes a tunnel magnetoresistive element TMR and an access transistor (N channel MOS transistor) ATR. In each row, a plurality of tunneling magneto-resistance elements TMR are arranged along corresponding digit lines DL.

  In each odd row, the source of each odd-numbered access transistor ATR is connected to one of the corresponding two source lines SL (upper side in the figure), and its gate is a corresponding pair of word lines. One of the WLs (upper side in the figure) is connected to the word line WL, and the drain thereof is connected to the corresponding bit line BL via the corresponding tunnel magnetoresistive element TMR.

  In each odd-numbered row, the source of each access transistor ATR in each even-numbered column is connected to the other (lower side in the figure) of the corresponding two source lines SL, and its gate is a corresponding pair of words The other word line WL (the lower side in the figure) of the lines WL is connected, and the drain thereof is connected to the corresponding bit line BL via the corresponding tunnel magnetoresistive element TMR.

  In each even row, the source of each odd-numbered column access transistor ATR is connected to one of the corresponding two source lines SL (the lower side in the figure), and its gate is a corresponding pair of words. One of the lines WL (lower side in the figure) is connected to the word line WL, and its drain is connected to the corresponding bit line BL via the corresponding tunneling magneto-resistance element TMR.

  In each even row, the source of access transistor ATR in each even column is connected to the other (upper side in the figure) source line SL of the corresponding two source lines SL, and the gate thereof is a corresponding pair of word lines. The other word line WL (upper side in the figure) of WL is connected to the drain, and the drain thereof is connected to the corresponding bit line BL via the corresponding tunnel magnetoresistive element TMR.

  That is, in this memory block MB, one memory cell MC is arranged at the intersection of two adjacent bit lines BL and one word line WL, and approximately the same number of memory cells MC are connected to each bit line BL. Therefore, a folded bit line structure is realized.

  Tunneling magneto-resistance element TMR is an element whose electric resistance value changes according to the logic of stored data. That is, as shown in FIG. 3, tunnel magnetoresistive element TMR includes fixed magnetization film FL, tunnel insulating film TB, and free magnetization film VL stacked between electrode EL and bit line BL. Each of the fixed magnetization film FL and the free magnetization film VL is composed of a ferromagnetic film. The magnetization direction of the fixed magnetization film FL is fixed in one direction. The magnetization direction of free magnetic film VL is written in one of one direction and the other direction. When the magnetization directions of the fixed magnetization film FL and the free magnetization film VL are the same, the resistance value of the tunnel magnetoresistive element TMR becomes a relatively large value, and when the magnetization directions of the two are opposite, the tunnel magnetoresistive element TMR The electric resistance value is relatively small. The two-stage resistance values of tunneling magneto-resistance element TMR are associated with data “1” and data “0”, for example.

At the time of data writing, as shown in FIG. 3, the word line WL is set to the “L” level of the non-selection level, the access transistor ATR is made non-conductive, and the magnetic field application current I _DL is supplied to the digit line DL. write current _{I W} is caused to flow to the bit line BL with. The magnetization direction of free magnetic film VL is determined by a combination of the directions of magnetic field application current I _DL and write current I _W.

FIG. 4 is a diagram showing the relationship between the currents I _DL and I _W and the magnetic field during data writing. Referring to FIG. 4, a magnetic field Hx indicated by the horizontal axis indicates a magnetic field H (DL) generated by a magnetic field application current I _DL flowing through the digit line DL. On the other hand, the magnetic field Hy which is shown on the vertical axis indicates the magnetic field H (BL) generated by the write current I _W that flows through a bit line BL.

  The magnetic field direction stored in the free magnetic film VL is newly written only when the sum of the magnetic fields H (DL) and H (BL) reaches a region outside the asteroid characteristic line shown in the drawing. That is, when a magnetic field corresponding to the area inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic film VL is not updated. Therefore, in order to update the storage data of tunneling magneto-resistance element TMR by the write operation, it is necessary to pass a current through both digit line DL and bit line BL. The magnetic field direction once stored in tunneling magneto-resistance element TMR, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

At the time of data reading, as shown in FIG. 5, word line WL is set to the “H” level of the selection level, and access transistor ATR is rendered conductive, and source is connected from bit line BL through tunneling magneto-resistance element TMR and access transistor ATR. current flows _{I S} in line SL (the line of ground potential VSS). The value of the current I _S will vary depending on the resistance value of the tunneling magneto-resistance element TMR. Therefore, by detecting the value of the current I _S, it is possible to read data stored in the tunneling magneto-resistance element TMR.

  6A is a plan view showing the layout of the memory block MB shown in FIG. 2, and FIG. 6B is a cross-sectional view of the memory block MB. 6A and 6B, a plurality of word lines WL are formed on the surface of the semiconductor substrate 8 at a predetermined interval. Each word line WL is formed of poly-silicon in a band shape and extends in the Y direction in the drawing. The plurality of word lines WL are grouped by two, and the two word lines WL in each group correspond to two adjacent memory cell rows, respectively.

  Impurities are implanted into the surface of the semiconductor substrate 8 using the two word lines WL of each group as a mask to form a plurality of pairs of access transistors ATR. For example, in an odd-numbered word line group, a pair of access transistors ATR is formed corresponding to each odd-numbered memory cell column, and in an even-numbered word line group, corresponding to each even-numbered memory cell column. A pair of access transistors ATR are formed. The impurity region between the two word lines WL is the source S of the two access transistors ATR, and the impurity region on both sides of the two word lines WL is the drain D of the two access transistors ATR.

  In each memory cell row, a source line SL is formed using the first metal layer above the sources S of the plurality of access transistors ATR. Each source line SL has a predetermined width, is formed in a strip shape, and extends in the Y direction in the drawing. The source S of each access transistor ATR is connected to the upper source line SL via a contact hole (not shown).

  A metal piled word line MWL is formed above each word line WL using a second metal layer, and each metal piled word line MWL is connected to a corresponding word line WL by a contact hole (not shown).

  A digit line DL is formed using the third metal layer above each source line SL and the two metal piled word lines MWL. Above each digit line DL, a rectangular electrode EL is formed using a fourth metal layer corresponding to each memory cell column. One end of each electrode EL extends to above the drain D of the access transistor ATR on one side (left side in the figure) of the corresponding digit line DL, and is connected to the drain D through the contact hole CH.

  A tunnel magnetoresistive element TMR is formed above the corresponding digit line DL and on the surface of the other end of each electrode EL. A bit line BL is formed on the plurality of tunnel magnetoresistive elements TMR of each memory cell column using a fifth metal layer. An insulating layer 9 is filled between the substrate 8 and the bit line BL.

Returning to FIG. 1, in accordance with the row address signal RA included in the address signal ADD, the row decoder 2 and any one of the plurality of rows of the memory array 1 and the two metal piled word lines MWL in the row. Any one of the metal pile driving word lines MWL is selected, and the selected metal pile driving word line MWL is set to the “H” level of the selection level. The drive circuit 3 applies a magnetic field application current I _DL to the digit line DL of the row selected by the row decoder 2 at the time of data writing.

In accordance with a column address signal CA included in the address signal ADD, the column decoder 4 selects one of the plurality of memory blocks MB of the memory array 1 and the plurality of bit lines BL of the memory block MB. Any i bit lines (where i is a natural number) are selected. Read / write control circuits 5 and 6 write data to each of i bit lines BL selected by column decoder 4 in accordance with externally applied write data signals D1 to Di at the time of data writing. _IW is supplied, and a data signal is written to each of i memory cells MC. Read / write control circuits 5 and 6 detect current Is flowing in each of i bit lines BL selected by column decoder 4 during data read, and a logical data signal corresponding to the detection result. Q1 to Qi are output to the outside. The control circuit 7 controls the entire MRAM device according to the external command signal CMD.

  The data writing method that characterizes the present invention will be described below. FIG. 7 is a circuit block diagram showing a portion related to data writing of the MRAM. 7, the memory array 1 is divided into a plurality of memory blocks MB1, MB2,. The configuration of each of the memory blocks MB1, MB2,... Is as described with reference to FIG. In FIG. 7, only four memory cells MC1 to MC4 in each of the memory blocks MB1, MB2,... Are shown for simplification of explanation and drawing.

  The memory block MB1 includes four memory cells MC1 to MC4 arranged in 2 rows and 2 columns, a digit line DL1 and a pair of word lines WL1 and WL2 provided corresponding to the first memory cell row, a second memory Digit line DL2 and a pair of word lines WL3, WL4 provided corresponding to the cell row, bit line BL1 provided corresponding to the first memory cell column, and corresponding to the second memory cell column Bit line BL2. A power supply voltage VDD is applied to one end of each of the digit lines DL1 and DL2.

  Further, four metal piled word lines MWL1 to MWL4 and three source lines SL are provided in common to the plurality of memory blocks MB1, MB2,. The metal pile driving word lines MWL1 to MWL4 are provided corresponding to the word lines WL1 to WL4, respectively, and each metal pile driving word line MWL is connected to each corresponding word line WL at a plurality of locations. Three source lines SL are arranged between and on both sides of the two memory cell rows, and each source line SL is grounded.

  Each of memory cells MC1-MC4 includes tunneling magneto-resistance element TMR and access transistor ATR. In each memory cell row, two tunnel magnetoresistive elements TMR are arranged along corresponding digit lines DL.

  The source of access transistor ATR of memory cell MC1 is connected to one of the two corresponding source lines SL (upper side in the figure), its gate is connected to word line WL1, and its drain is connected to the corresponding one. The tunnel magnetoresistive element TMR is connected to the bit line BL1.

  The source of the access transistor ATR of the memory cell MC2 is connected to the other (lower side in the figure) of the corresponding two source lines SL, the gate thereof is connected to the word line WL2, and the drain thereof is corresponding. Are connected to the bit line BL2 through the tunnel magnetoresistive element TMR.

  The source of access transistor ATR of memory cell MC3 is connected to one of the corresponding two source lines SL (lower side in the figure), its gate is connected to word line WL4, and its drain is corresponding. Are connected to the bit line BL1 through the tunnel magnetoresistive element TMR.

  The source of the access transistor ATR of the memory cell MC4 is connected to the other source line SL (upper side in the figure) of the corresponding two source lines SL, the gate thereof is connected to the word line WL3, and the drain thereof is connected to the corresponding source line SL. The tunnel magnetoresistive element TMR is connected to the bit line BL2.

Digit line drive circuits DD1, DD2,... Are provided corresponding to the plurality of memory blocks MB1, MB2,. The digit line drive circuits DD1, DD2,... Are activated in response to the write block selection signals WEB1, WEB2,. The magnetic field application current I _{DL is} passed through the digit line DL.

  That is, digit line drive circuit DD1 includes an OR gate 10, an AND gate 11, and an N-channel MOS transistor 12 provided corresponding to each memory cell row. In the first memory cell row, two input nodes of the OR gate 10 are connected to metal piled word lines MWL1 and MWL2, respectively. Two input nodes of AND gate 11 receive write block select signal WEB1 and an output signal of OR gate 10, respectively. N-channel MOS transistor 12 is connected between the other end of digit line DL1 and a line of ground potential VSS, and its gate receives an output signal of AND gate 11.

The write block selection signal WEB1 is set to the activation level “H” level, and one of the two metal piled word lines MWL1 and MWL2 is set to the activation level “H”. "" Level, the output signal of the AND gate 11 becomes "H" level, the N-channel MOS transistor 12 becomes conductive, and the magnetic field application current I _DL flows through the digit line DL1.

In the second memory cell row, the write block selection signal WEB1 is set to the activation level “H” level, and one of the two metal piled word lines MWL3 and MWL4 is used. Is set to the “H” level of the activation level, the output signal of the AND gate 11 becomes the “H” level, the N-channel MOS transistor 12 becomes conductive, and the magnetic field application current I _DL flows through the digit line DL2.

  Digit line drive circuits DD2,... Are the same as digit line drive circuits DD1, except that write block selection signals WEB2,... Are applied instead of write block selection signal WEB1. The digit line drive circuits DD1, DD2,... Are included in the drive circuit 3 of FIG. Write block selection signals WEB1, WEB2,... Are generated by control circuit 7, column decoder 4, and read / write control circuits 5, 6 based on external command signal CMD and column address signal CA.

  Further, drivers D1a, D1b; D2a, D2b;... Are provided corresponding to the bit lines BL1, BL2,. Driver control signals φ1a, φ2a,... Are applied to the input nodes of the drivers D1a, D2a,..., Respectively, and their output nodes are connected to one ends of the bit lines BL1, BL2,. Driver control signals φ1b, φ2b,... Are applied to the input nodes of the drivers D1b, D2b,..., Respectively, and their output nodes are connected to the other ends of the bit lines BL1, BL2,.

For example, when data “0” is written to memory cell MC1 or MC3, driver control signals φ1a and φ1b are set to “H” level and “L” level, respectively, and the driver is output from the output node of driver D1a via bit line BL1. flowing a write current _{I W} to the output node of D1b. When data “1” is written to the memory cell MC1 or MC3, the driver control signals φ1a and φ1b are set to the “L” level and the “H” level, respectively, and the driver is output from the output node of the driver D1b via the bit line BL1. flowing a write current _{I W} to the output node of D1a. At this time, the control signals φ2a, φ2b,... Corresponding to the columns where data writing is not performed are both set to the “L” level, and the bit lines BL2, are set to the “L” level (ground potential VSS).

  The drivers D1a, D1b; D2a, D2b;... Are included in the read / write control circuits 5 and 6 in FIG. Driver control signals φ1a, φ2a,...; Φ1b, φ2b,... Are generated by control circuit 7, column decoder 4, and read / write control circuits 5 and 6 based on external command signal CMD and column address signal CA. Is done.

  The signal RA0 of the row address signals RA0 to RA8 and the write enable signal WE are input to the EX-OR gate 13, and the output signal of the EX-OR gate 13 is applied to the row decoder 2. Therefore, at the time of read operation in which signal WE is set to the inactive level “L” level, signal RA0 is input to row decoder 2 as it is, and at the time of write operation in which signal WE is set to the “H” level at the activation level. The signal RA0 is inverted and input to the row decoder 2.

  For example, when signal RA0 applied to row decoder 2 is at "H" level, odd-numbered metal piled word lines MWL1, MWL3,... Among a plurality of metal piled word lines MWL1, MWL2,. Any one of the odd-numbered metal piled word lines MWL1, MWL3,... Is selected by the remaining row address signals RA1 to RA8.

  When the signal RA0 applied to the row decoder 2 is at "L" level, the even-numbered metal piled word lines MWL2, MWL4,... Of the plurality of metal piled word lines MWL1, MWL2,. , Any one of the even-numbered metal piled word lines MWL2, MWL4,... Is selected by the remaining row address signals RA1 to RA8.

  Therefore, a metal piled word line (for example, MWL1) designated by external row address signals RA0-RA8 is selected as it is during a read operation, but is designated by external row address signals RA0-RA8 during a write operation. Of the two metal piled word lines (in this case, MWL1 and MWL2) corresponding to the row (for example, the first memory cell row), the metal piled word line (for example, MWL2) which is not designated by the external address signals RA0 to RA8 ) Is selected.

For example, when it is desired to read data from the memory cell MC1, it is necessary to set the metal piled word line MWL1 to the “H” level to make the access transistor ATR of the memory cell MC1 conductive. Is written, the metal piled word line MWL1 is set to “L” level to keep the access transistor ATR of the memory cell MC1 nonconductive, while the metal piled word line MWL2 is set to “H” level to set the digit line DL1. This is because a magnetic field application current _{IDL is} passed through the current.

  Next, the writing operation of this MRAM will be described. Assume that memory cell MC4 of memory block MB1 in FIG. 7 is designated by external row address signals RA0-RA8 and external column address signal CA. Write enable signal WE is set to the activation level “H” level, and signal RA 0 is inverted by EX-OR gate 13 and input to row decoder 2.

The external row address signals RA0 to RA8 themselves specify the metal piled word line MWL3 corresponding to the memory cell MC4. However, since the signal RA0 is inverted, the row decoder 2 sets the metal piled word line MWL4 to the selection level “ H ”level. Further, the write block selection signal WEB1 is set to the “H” level of the selection level. As a result, N channel MOS transistor 12 corresponding to the second memory cell row of digit line drive circuit DD1 is rendered conductive, and magnetic field application current I _DL flows through digit line DL2 of memory block MB1.

Further, according to the external column address signal CA and the write data signal D, for example, the driver control signal φ2a, φ2b are respectively "H" level and "L" level, the write current I _W is passed through the bit line BL2 memory Data signal D is written to cell MC4. At this time, since the access transistor ATR of the memory cell MC4 is turned off, current does not leak from the bit line BL2 to the source line SL via the memory cell MC4. On the other hand, although access transistor ATR of memory cell MC3 is rendered conductive, driver control circuits φ1a and φ1b are both set to “L” level and bit line BL1 is set to “L” level, so that memory cell MC3 is transferred from bit line BL1. No current flows through the source line SL.

  FIG. 8 is a time chart illustrating the operation of this MRAM. In FIG. 8, at time t0, write permission signal WE is raised to the “H” level of the activation level, and the write operation is started. At this time, it is assumed that memory cell MC2 of memory block MB1 in FIG. 7 is designated by external row address signals RA0-RA8 and external column address signal CA. Since write enable signal WE is at “H” level, signal RA 0 is inverted by EX-OR gate 13 and input to row decoder 2.

External row address signals RA0-RA8 themselves specify metal piled word line MWL2 corresponding to memory cell MC2, but since signal RA0 is inverted, row decoder 2 causes metal piled word line MWL1 (ie, word line WL1). ) Is set to the selection level “H” level. Further, the write block selection signal WEB1 is set to the “H” level of the selection level. N channel MOS transistor 12 corresponding to the first memory cell row of digit line drive circuit DD1 is rendered conductive, and magnetic field application current I _DL1 flows through digit line DL1 of memory block MB1.

Further, according to external column address signal CA and write data signal D, for example, driver control signals φ2a and φ2b are set to “H” level and “L” level, respectively, and write current + I _W is supplied to bit line BL2 to provide memory. Data “1” is written in the cell MC2. Driver control signal φ2a, φ2b are respectively "L" level and the "H" level, if the write current -I _W to the bit line BL2 is flowed, the data in the memory cell MC2 "0" is written.

  At this time, since the access transistor ATR of the memory cell MC2 is non-conductive, current does not leak from the bit line BL2 to the source line SL via the memory cell MC2. On the other hand, although access transistor ATR of memory cell MC1 is rendered conductive, driver control circuits φ1a and φ1b are both set to “L” level and bit line BL1 is set to “L” level, so that memory cell MC1 is transferred from bit line BL1. No current flows through the source line SL.

Next, at time t1, when only signal RA0 among external row address signals RA0-RA8 is inverted and falls to "L" level, external row address signals RA0-RA8 themselves correspond to memory cell MC1. Although the metal piled word line MWL1 is designated but the signal RA0 is inverted, the row decoder 2 sets the metal piled word line MWL2 (that is, the word line WL2) to the selected level of “H”. Further, the write block selection signal WEB1 is maintained at the “H” level of the selection level, and the magnetic field application current I _DL1 of the digit line DL1 of the memory block MB1 is maintained.

Further, according to the external column address signal CA and the write data signal D, for example, the driver control signal .phi.1a, .phi.1B are respectively "H" level and "L" level, the write current + I _W is passed through the bit line BL2 memory Data “1” is written in the cell MC1. Driver control signal .phi.1a, .phi.1B are respectively "L" level and the "H" level, if the write current -I _W to the bit line BL2 is flowed, the data in the memory cell MC1 "0" is written.

  At this time, since the access transistor ATR of the memory cell MC1 is turned off, current does not leak from the bit line BL1 to the source line SL via the memory cell MC1. On the other hand, although access transistor ATR of memory cell MC2 is turned on, driver control circuits φ2a and φ2b are both set to “L” level and bit line BL2 is set to “L” level, so that memory cell MC2 is transferred from bit line BL2. No current flows through the source line SL.

  Next, at time t2, write enable signal WE is raised to the “L” level of the inactivation level, and the read operation is started. When signal WE is set to “L” level, write block selection signal WEB1 is set to “L” level, digit line drive circuit DD1 is inactivated, and current of digit line DL1 is cut off. At time t2, only signal RA0 of external row address signals RA0-RA8 is inverted and raised to "H" level, but since signal WE has been set to "L" level, word line WL2 is " Maintained at the “H” level, access transistor ATR of memory cell MC2 is maintained in the conductive state.

Bit lines BL1 and BL2 are connected to a read circuit (not shown). Read circuit detects the current I _S flowing through the memory cell MC2 is given a predetermined read voltage to the bit line BL2. Further, the bit line BL1 is connected dummy memory cells (not shown), read circuit detects the reference current I _R flowing in the dummy memory cell by applying a predetermined read voltage to the bit line BL1. Read circuit compares the magnitude of the reference current I _R flowing in the current I _S and the dummy memory cell flowing through the memory cell MC2, and outputs a logic level read data signal corresponding to the comparison result.

  Next, at time t3, when only the signal RA0 of the external row address signals RA0 to RA8 is inverted and raised to the “L” level, the word line WL1 is raised to the “H” level, and the memory cell MC1 Access transistor ATR is rendered conductive.

The read circuit detects the current I _S flowing through the memory cell MC1 is given a predetermined read voltage to the bit line BL1. Further, the bit line BL2 is connected the dummy memory cells (not shown), read circuit detects the reference current I _R flowing in the dummy memory cell by applying a predetermined read voltage to the bit line BL2. Read circuit compares the magnitude of the reference current I _R flowing in the current I _S and the dummy memory cell flowing through the memory cell MC1, and outputs a logic level read data signal corresponding to the comparison result.

  FIG. 9 is a circuit block diagram showing a comparative example of this embodiment, which is compared with FIG. Referring to FIG. 9, this MRAM is different from the MRAM of FIG. 7 in that main digit lines MDL1, MDL2,... Are shared by a plurality of memory blocks MB1, MB2,. Are provided, and the OR gate 10 and the EX-OR gate 13 are removed. One input node of AND gate 11 is connected to main digit line MDL of the corresponding row instead of receiving the output signal of OR gate 10.

The signals RA0 and WE are directly input to the row decoder 2. Row decoder 2 sets the main digit line (for example, MDL1) of the row designated by row address signals RA0-RA8 to the selection level “H” level during the write operation. For example, when write block selection signal WEB1 is set to the selection level “H” level, magnetic field application current IDL flows through digit line DL1 of the first memory cell row of memory block MB1. In this state, when the write current I _W flows through the bit line BL1 of the first memory cell column, the data signal is written into the memory cell MC1.

In the read operation, row decoder 2 sets the metal piled word line (for example, MWL1) of the row designated by row address signals RA0-RA8 to the “H” level of the selection level. Thereby, the access transistor ATR of the memory cell MC becomes conductive. Readout circuit (not shown), compares the current I _S flowing through the source line SL via the memory cell MC1 from the bit line BL1, and a reference current I _R flowing from the bit line BL2 to the dummy memory cells (not shown) Then, a data signal having a logic level corresponding to the comparison result is output.

  FIGS. 10A and 10B are diagrams showing the layout and cross-sectional shape of the memory block MB of the MRAM shown in FIG. 9 and are compared with FIGS. 6A and 6B. Referring to FIGS. 10A and 10B, in this MRAM, main digit line MDL is added between two metal piled word lines MWL and digit line DL. Therefore, in the MRAM of the comparative example, the number of metal layers increases by the amount of the main digit line MDL as compared with the MRAM of the embodiment. Conversely, the MRAM of the embodiment requires fewer metal layers than the MRAM of the comparative example. Accordingly, the number of manufacturing steps is reduced, and the manufacturing cost can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of an MRAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory block shown in FIG. 1. FIG. 3 is a diagram showing a configuration and a write operation of the memory cell shown in FIG. It is a figure for demonstrating the characteristic of the tunnel magnetoresistive element shown in FIG. FIG. 4 is a diagram showing a read operation of the memory cell shown in FIG. 3. FIG. 3 is a diagram showing a layout and a cross-sectional shape of the memory block shown in FIG. 2. FIG. 7 is a circuit block diagram showing a portion related to data writing of the MRAM shown in FIGS. 8 is a time chart illustrating the operation of the MRAM illustrated in FIGS. It is a circuit block diagram which shows the comparative example of embodiment. It is a figure which shows the layout and cross-sectional shape of the memory block of MRAM shown in FIG.

Explanation of symbols

  1 memory array, 2 row decoder, 3 drive circuit, 4 column decoder, 5, 6 read / write control circuit, 7 control circuit, MB memory block, MC memory cell, TMR tunnel magnetoresistive element, ATR access transistor, S source , D drain, WL word line, MWL metal piled word line, DL digit line, MDL main digit line, SL source line, BL bit line, EL electrode, FL fixed magnetic film, TB tunnel insulating film, VL free magnetic film, 8 semiconductor substrate, 9 insulating layer, 10 OR gate, 11 AND gate, 12 N channel MOS transistor, 13 EX-OR gate, DD1, DD2 digit line drive circuit, D1a, D1b, D2a, D2b driver.

Claims (4)

A memory array divided into a plurality of memory blocks,
Each memory block is arranged in a plurality of rows and a plurality of columns, each of which includes a plurality of memory cells including a tunnel magnetoresistive element that stores data according to a change in resistance value, and a plurality of sets each provided corresponding to the plurality of rows Including two word lines, a plurality of digit lines provided corresponding to the plurality of rows, and a plurality of bit lines provided corresponding to the plurality of columns, respectively.
One memory cell of two adjacent memory cells in the same row is arranged at the intersection of one of the corresponding two word lines and the corresponding bit line, and the other memory cell Is arranged at the intersection of the other of the two corresponding word lines and the corresponding bit line,
The plurality of memory blocks are arranged in an extending direction of the word line,
Further, it provided in common to said plurality of memory blocks corresponding to each row, two and piling word lines respectively connected to each set of two word lines correspond,
In accordance with a row address signal, select one of the plurality of rows and one of the two piled word lines belonging to the row, and select the selected piled word line. A row decoder to select level,
A column decoder for selecting any one of the plurality of bit lines according to a column address signal;
It is provided corresponding to each digit line, and when a write operation is performed, one of the two piled word lines in the corresponding row is changed in response to the selection level being set. A digit line drive circuit for applying a magnetic field applied current to the digit line;
A nonvolatile semiconductor memory device comprising: a bit line driving circuit for supplying a write current to the bit line selected by the column decoder during the write operation. Each memory cell includes the tunnel magnetoresistive element and a transistor,
Each transistor is connected in series with a corresponding resistor memory element between a corresponding bit line and a reference potential line, and is turned on in response to the corresponding word line being set to the selection level.
The row address signal is used to select one of two word lines in the same row as the first sub-row address signal for selecting one of the plurality of rows. A second sub-row address signal of 1 bit,
Further, the row address signal is received, and the row address signal is directly passed to the row decoder during a read operation, and the first sub-row address signal is directly passed to the row decoder during a write operation. A gate circuit that inverts the logic level of the second sub-row address signal and applies it to the row decoder;
During the reading operation, via the bit line selected by the column decoder, and a read circuit for reading data stored in the memory cells corresponding to stake out the word line selected by the row decoder, according to claim 1 Nonvolatile semiconductor memory device. The bit line drive circuit, at the time of the write operation, by the row decoder providing the reference potential to each bit line connected to each transistor corresponding to stake out word lines in the selected level, to claim 2 The nonvolatile semiconductor memory device described. The column decoder selects one of the plurality of memory blocks and one of the plurality of bit lines belonging to the memory block according to the column address signal;
In the digit line driving circuit, the corresponding memory block is selected by the column decoder, and one of the two stake word lines in the corresponding row is set to the selection level. the flow field application current, non-volatile semiconductor memory device according to any one of claims 1 to 3 to a corresponding digit line in accordance with.

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